SN74GTLP1394 2-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE BUS TRANSCEIVER WITH SPLIT LVTTL PORT, FEEDBACK PATH, AND SELECTABLE POLARITY www.ti.com SCES286F – OCTOBER 1999 – REVISED APRIL 2005 FEATURES • • • • • • RGY PACKAGE (TOP VIEW) D, DGV, OR PW PACKAGE (TOP VIEW) OEBY Y1 Y2 VCC A1 A2 OEAB ERC 1 16 2 15 3 14 4 13 12 5 6 11 7 10 8 9 BIAS VCC GND B1 GND B2 GND VREF T/C Y1 Y2 VCC A1 A2 OEAB BIAS VCC • • 1 16 3 4 15 GND 14 B1 13 GND 5 6 12 B2 11 GND 2 10 VREF 7 8 9 T/C • • Data-Transfer Rate and Signal Integrity in Distributed Loads Ioff, Power-Up 3-State, and BIAS VCC Support Live Insertion Polarity Control Selects True or Complementary Outputs Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II ESD Protection Exceeds JESD 22 – 2000-V Human-Body Model (A114-A) – 200-V Machine Model (A115-A) – 1000-V Charged-Device Model (C101) OEBY • TI-OPC™ Circuitry Limits Ringing on Unevenly Loaded Backplanes OEC™ Circuitry Improves Signal Integrity and Reduces Electromagnetic Interference Bidirectional Interface Between GTLP Signal Levels and LVTTL Logic Levels Split LVTTL Port Provides a Feedback Path for Control and Diagnostics Monitoring LVTTL Interfaces Are 5-V Tolerant High-Drive GTLP Outputs (100 mA) LVTTL Outputs (–24 mA/24 mA) Variable Edge-Rate Control (ERC) Input Selects GTLP Rise and Fall Times for Optimal ERC • DESCRIPTION/ORDERING INFORMATION ORDERING INFORMATION PACKAGE (1) TA QFN – RGY –40°C to 85°C (1) ORDERABLE PART NUMBER TOP-SIDE MARKING Tape and reel SN74GTLP1394RGYR Tube SN74GTLP1394D Tape and reel SN74GTLP1394DR TSSOP – PW Tape and reel SN74GTLP1394PWR GP394 TVSOP – DGV Tape and reel SN74GTLP1394DGVR GP394 SOIC – D GP1394 GTLP1394 Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. TI-OPC, OEC, TI are trademarks of Texas Instruments. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 1999–2005, Texas Instruments Incorporated SN74GTLP1394 2-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE BUS TRANSCEIVER WITH SPLIT LVTTL PORT, FEEDBACK PATH, AND SELECTABLE POLARITY www.ti.com SCES286F – OCTOBER 1999 – REVISED APRIL 2005 DESCRIPTION/ORDERING INFORMATION (CONTINUED) The SN74GTLP1394 is a high-drive, 2-bit, 3-wire bus transceiver that provides LVTTL-to-GTLP and GTLP-to-LVTTL signal-level translation. It allows for transparent and inverted transparent modes of data transfer with separate LVTTL input and LVTTL output pins, which provides a feedback path for control and diagnostics monitoring. The device provides a high-speed interface between cards operating at LVTTL logic levels and a backplane operating at GTLP signal levels, and is especially designed to work with the Texas Instruments (TI™) 1394 backplane physical-layer controllers. High-speed (about three times faster than standard LVTTL or TTL) backplane operation is a direct result of GTLP reduced output swing (<1 V), reduced input threshold levels, improved differential input, OEC™ circuitry, and TI-OPC™ circuitry. Improved GTLP OEC and TI-OPC circuitry minimizes bus-settling time and have been designed and tested using several backplane models. The high drive allows incident-wave switching in heavily loaded backplanes with equivalent load impedance down to 11 Ω. GTLP is the TI derivative of the Gunning Transceiver Logic (GTL) JEDEC standard JESD 8-3. The ac specification of the SN74GTLP1394 is given only at the preferred higher noise margin GTLP, but the user has the flexibility of using this device at either GTL (VTT = 1.2 V and VREF = 0.8 V) or GTLP (VTT = 1.5 V and VREF = 1 V) signal levels. Normally, the B port operates at GTLP signal levels. The A-port and control inputs operate at LVTTL logic levels, but are 5-V tolerant and are compatible with TTL and 5-V CMOS inputs. VREF is the B-port differential input reference voltage. This device is fully specified for live-insertion applications using Ioff, power-up 3-state, and BIAS VCC. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down. The power-up 3-state circuitry places the outputs in the high-impedance state during power up and power down, which prevents driver conflict. The BIAS VCC circuitry precharges and preconditions the B-port input/output connections, preventing disturbance of active data on the backplane during card insertion or removal and permits true live-insertion capability. This GTLP device features TI-OPC circuitry, which actively limits the overshoot caused by improperly terminated backplanes, unevenly distributed cards, or empty slots during low-to-high signal transitions. This improves signal integrity, which allows adequate noise margin to be maintained at higher frequencies. High-drive GTLP backplane interface devices feature adjustable edge-rate control (ERC). Changing the ERC input voltage between GND and VCC adjusts the B-port output rise and fall times. This allows the designer to optimize system data-transfer rate and signal integrity to the backplane load. When VCC is between 0 and 1.5 V, the device is in the high-impedance state during power up or power down. However, to ensure the high-impedance state above 1.5 V, the output-enable (OE) input should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. FUNCTIONAL DESCRIPTION The output-enable (OEAB) input controls the activity of the B port. When OEAB is low, the B-port outputs are active. When OEAB is high, the B-port outputs are disabled. Separate LVTTL input and output pins provide a feedback path for control and diagnostics monitoring. The OEBY input controls the Y outputs. When OEBY is low, the Y outputs are active. When OEBY is high, the Y outputs are disabled. The polarity-control (T/C) input is provided to select polarity of data transmission in both directions. When T/C is high, data transmission is true, and A data goes to the B bus and B data goes to the Y bus. When T/C is low, data transmission is complementary, and inverted A data goes to the B bus and inverted B data goes to the Y bus. 2 SN74GTLP1394 2-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE BUS TRANSCEIVER WITH SPLIT LVTTL PORT, FEEDBACK PATH, AND SELECTABLE POLARITY www.ti.com SCES286F – OCTOBER 1999 – REVISED APRIL 2005 FUNCTION TABLES OUTPUT CONTROL INPUTS T/C OEAB OEBY OUTPUT MODE Isolation X H H Z H L H A data to B bus H H L B data to Y bus H L L A data to B bus, B data to Y bus L L H Inverted A data to B bus L H L Inverted B data to Y bus L L L Inverted A data to B bus, Inverted B data to Y bus True transparent True transparent with feedback path Inverted transparent Inverted transparent with feedback path OUTPUT EDGE-RATE CONTROL (ERC) INPUT ERC LOGIC LEVEL NOMINAL VOLTAGE OUTPUT B-PORT EDGE RATE L GND Slow H VCC Fast LOGIC DIAGRAM (POSITIVE LOGIC) 10 VREF 8 ERC 7 OEAB T/C 9 1 OEBY A1 Y1 A2 Y2 5 14 B1 2 6 12 B2 3 3 SN74GTLP1394 2-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE BUS TRANSCEIVER WITH SPLIT LVTTL PORT, FEEDBACK PATH, AND SELECTABLE POLARITY www.ti.com SCES286F – OCTOBER 1999 – REVISED APRIL 2005 Absolute Maximum Ratings (1) over operating free-air temperature range (unless otherwise noted) VCC BIAS VCC Supply voltage range VI Input voltage range (2) VO Voltage range applied to any output in the high-impedance or power-off state (2) IO Current into any output in the low state IO Current into any output in the high state (3) MIN MAX –0.5 4.6 A inputs, ERC, and control inputs –0.5 7 B port and VREF –0.5 4.6 Y outputs –0.5 7 B port –0.5 4.6 Y outputs 48 B port 200 Continuous current through each VCC or GND UNIT V V V mA 48 mA ±100 mA IIK Input clamp current VI < 0 –50 mA IOK Output clamp current VO < 0 –50 mA package (4) 73 DGV package (4) 120 PW package (4) 108 D θJA Package thermal impedance RGY package (5) Tstg (1) (2) (3) (4) (5) 4 Storage temperature range °C/W 39 –65 150 °C Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed. This current flows only when the output is in the high state and VO > VCC. The package thermal impedance is calculated in accordance with JESD 51-7. The package thermal impedance is calculated in accordance with JESD 51-5. www.ti.com SN74GTLP1394 2-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE BUS TRANSCEIVER WITH SPLIT LVTTL PORT, FEEDBACK PATH, AND SELECTABLE POLARITY SCES286F – OCTOBER 1999 – REVISED APRIL 2005 Recommended Operating Conditions VCC, BIAS VCC Supply voltage VTT Termination voltage VREF Reference voltage VI Input voltage VIH High-level input voltage (1) (2) (3) (4) MIN NOM MAX UNIT 3.15 3.3 3.45 V GTL 1.14 1.2 1.26 GTLP 1.35 1.5 1.65 GTL 0.74 0.8 0.87 GTLP 0.87 1 1.1 B port VTT Except B port B port ERC Except B port and ERC VCC 5.5 VCC 5.5 Low-level input voltage IIK Input clamp current IOH High-level output current IOL Low-level output current ∆t/∆v Input transition rise or fall rate ∆t/∆VCC Power-up ramp rate TA Operating free-air temperature VCC – 0.6 (2) (3) (4) V V 2 VREF – 0.05 ERC GND Except B port and ERC (1) V VREF + 0.05 B port VIL V 0.6 V 0.8 Y outputs Y outputs –18 mA –24 mA 24 B port 100 Outputs enabled 10 ns/V µs/V 20 –40 mA 85 °C All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004. Proper connection sequence for use of the B-port I/O precharge feature is GND and BIAS VCC = 3.3 V first, I/O second, and VCC = 3.3 V last, because the BIAS VCC precharge circuitry is disabled when any VCC pin is connected. The control and VREF inputs can be connected anytime, but normally are connected during the I/O stage. If B-port precharge is not required, any connection sequence is acceptable, but generally, GND is connected first. VTT and RTT can be adjusted to accommodate backplane impedances if the dc recommended IOL ratings are not exceeded. VREF can be adjusted to optimize noise margins, but normally is two-thirds VTT. TI-OPC circuitry is enabled in the A-to-B direction and is activated when VTT > 0.7 V above VREF. If operated in the A-to-B direction, VREF should be set to within 0.6 V of VTT to minimize current drain. 5 SN74GTLP1394 2-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE BUS TRANSCEIVER WITH SPLIT LVTTL PORT, FEEDBACK PATH, AND SELECTABLE POLARITY www.ti.com SCES286F – OCTOBER 1999 – REVISED APRIL 2005 Electrical Characteristics over recommended operating free-air temperature range for GTLP (unless otherwise noted) PARAMETER VIK VOH Y outputs VCC = 3.15 V, II = –18 mA VCC = 3.15 V to 3.45 V, IOH = –100 µA VCC – 0.2 IOH = –12 mA 2.4 IOH = –24 mA 2 VCC = 3.15 V VCC = 3.15 V to 3.45 V, Y outputs VCC = 3.15 V VOL B port VCC = 3.15 V A-port and control inputs II IOZH (2) Y outputs VCC = 3.45 V, VCC = 3.45 V B port IOZL (2) Y outputs and B port VCC = 3.45 V, ICC Y outputs and B port VCC = 3.45 V, IO = 0, VI (A-port or control inputs) = VCC or GND, VI (B port) = VTT or GND A-port inputs Control inputs Y outputs VO = 3.15 V or 0 Cio B port VO = 1.5 V or 0 (1) (2) (3) V V IOL = 100 µA 0.2 IOL = 12 mA 0.4 IOL = 24 mA 0.5 IOL = 10 mA 0.2 IOL = 64 mA 0.4 IOL = 100 mA 0.55 VI = 0 to 5.5 V ±10 VO = VCC 10 VO = 1.5 V 10 VO = GND –10 Outputs high 20 Outputs low 20 Outputs disabled 20 V µA µA µA mA 1.5 VI = 3.15 V or 0 Co UNIT –1.2 VCC = 3.45 V, One A-port or control input at VCC – 0.6 V, Other A-port or control inputs at VCC or GND ∆ICC (3) Ci MIN TYP (1) MAX TEST CONDITIONS 3.5 4.5 4 5 mA pF 4.5 5 pF 9 10.5 pF All typical values are at VCC = 3.3 V, TA = 25°C. For I/O ports, the parameters IOZH and IOZL include the input leakage current. This is the increase in supply current for each input that is at the specified TTL voltage level, rather than VCC or GND. Hot-Insertion Specifications for A Inputs and Y Outputs over recommended operating free-air temperature range PARAMETER Ioff TEST CONDITIONS MIN MAX UNIT 10 µA OE = 0 ±30 µA OE = 0 ±30 µA MAX UNIT VCC = 0, BIAS VCC = 0, VI or VO = 0 to 5.5 V IOZPU VCC = 0 to 1.5 V, VO = 0.5 V to 3 V, IOZPD VCC = 1.5 V to 0, VO = 0.5 V to 3 V, Live-Insertion Specifications for B Port over recommended operating free-air temperature range PARAMETER Ioff MIN 10 µA VO = 0.5 V to 1.5 V, OE = 0 ±30 µA VO = 0.5 V to 1.5 V, OE = 0 ±30 µA 5 mA 10 µA 1.05 V BIAS VCC = 0, VI or VO = 0 to 1.5 V IOZPU VCC = 0 to 1.5 V, BIAS VCC = 0, IOZPD VCC = 1.5 V to 0, BIAS VCC = 0, ICC (BIAS VCC) 6 TEST CONDITIONS VCC = 0, VCC = 0 to 3.15 V VCC = 3.15 V to 3.45 V BIAS VCC = 3.15 V to 3.45 V, VO (B port) = 0 to 1.5 V VO VCC = 0, BIAS VCC = 3.3 V, IO = 0 IO VCC = 0, BIAS VCC = 3.15 V to 3.45 V, VO (B port) = 0.6 V 0.95 –1 µA www.ti.com SN74GTLP1394 2-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE BUS TRANSCEIVER WITH SPLIT LVTTL PORT, FEEDBACK PATH, AND SELECTABLE POLARITY SCES286F – OCTOBER 1999 – REVISED APRIL 2005 Switching Characteristics over recommended ranges of supply voltage and operating free-air temperature, VTT = 1.5 V and VREF = 1 V for GTLP (see Figure 1) PARAMETER tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL ten tdis ten tdis TO (OUTPUT) EDGE RATE (1) A B Slow A B Fast A Y Slow A Y Fast T/C B Slow T/C B Fast OEAB B Slow OEAB B Fast tr Rise time, B outputs (20% to 80%) tf Fall time, B outputs (80% to 20%) tPLH tPHL tPLH tPHL ten tdis (1) (2) FROM (INPUT) B Y T/C Y OEBY Y MIN TYP (2) MAX 3.3 5.9 3 6.6 2.5 5.2 1.9 4.8 5.4 9 4.9 8.6 4.3 7.9 3.9 7.5 3 6.5 3.1 6.6 2.3 5.6 1.7 4.9 3.2 6.2 3.2 6.4 1.9 5.3 2.4 5.7 Slow 2.7 Fast 1.5 Slow 3.2 Fast 2.1 UNIT ns ns ns ns ns ns ns ns ns ns 1.6 4.6 1.4 3.9 1 4.5 1.2 4.1 1 4.1 1.3 4.6 ns ns ns Slow (ERC = GND) and Fast (ERC = VCC) All typical values are at VCC = 3.3 V, TA = 25°C. 7 SN74GTLP1394 2-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE BUS TRANSCEIVER WITH SPLIT LVTTL PORT, FEEDBACK PATH, AND SELECTABLE POLARITY www.ti.com SCES286F – OCTOBER 1999 – REVISED APRIL 2005 PARAMETER MEASUREMENT INFORMATION 500 Ω From Output Under Test S1 1.5 V 6V Open 12.5 Ω From Output Under Test CL = 30 pF (see Note A) GND CL = 50 pF (see Note A) TEST tPLH/tPHL tPLZ/tPZL tPHZ/tPZH 500 Ω S1 Open 6V GND Test Point LOAD CIRCUIT FOR B OUTPUTS LOAD CIRCUIT FOR Y OUTPUTS 3V 1.5 V Input 1.5 V 0V tPLH tPHL VOH 1V Output 1V VOL VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES (A input to B port) 1V 0V tPLH VOH Output VOL VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES (B port to Y output) tPLZ 3V 1.5 V VOL + 0.3 V VOL tPZH 1.5 V 1.5 V 0V Output Waveform 1 S1 at 6 V (see Note B) tPHL 1.5 V 1.5 V tPZL 1.5 V 1V Input 3V Output Control Output Waveform 2 S1 at GND (see Note B) tPHZ VOH 1.5 V VOH − 0.3 V ≈0 V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES (A input) NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR ≈ 10 MHz, ZO = 50 Ω, tr ≈ 2 ns, tf ≈ 2 ns. D. The outputs are measured one at a time, with one transition per measurement. Figure 1. Load Circuits and Voltage Waveforms 8 www.ti.com SN74GTLP1394 2-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE BUS TRANSCEIVER WITH SPLIT LVTTL PORT, FEEDBACK PATH, AND SELECTABLE POLARITY SCES286F – OCTOBER 1999 – REVISED APRIL 2005 Distributed-Load Backplane Switching Characteristics The preceding switching characteristics table shows the switching characteristics of the device into a lumped load (Figure 1). However, the designer's backplane application probably is a distributed load. The physical representation is shown in Figure 2. This backplane, or distributed load, can be approximated closely to a resistor inductance capacitance (RLC) circuit, as shown in Figure 3. This device has been designed for optimum performance in this RLC circuit. The following switching characteristics table shows the switching characteristics of the device into the RLC load, to help the designer better understand the performance of the GTLP device in this typical backplane. See www.ti.com/sc/gtlp for more information. 22 Ω 0.25” ZO = 50 Ω 1” Conn. 1” Conn. 1” Conn. Conn. 1” 1” 0.25” 22 Ω 1.5 V 1.5 V 1” Rcvr Rcvr Rcvr Slot 2 Slot 19 Slot 20 Drvr Slot 1 Figure 2. High-Drive Test Backplane 1.5 V 11 Ω From Output Under Test LL = 14 nH Test Point CL = 18 pF Figure 3. High-Drive RLC Network 9 SN74GTLP1394 2-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE BUS TRANSCEIVER WITH SPLIT LVTTL PORT, FEEDBACK PATH, AND SELECTABLE POLARITY www.ti.com SCES286F – OCTOBER 1999 – REVISED APRIL 2005 Switching Characteristics over recommended ranges of supply voltage and operating free-air temperature, VTT = 1.5 V and VREF = 1 V for GTLP (see Figure 3) PARAMETER tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL ten tdis ten tdis (1) (2) 10 FROM (INPUT) TO (OUTPUT) EDGE RATE (1) A B Slow A B Fast A Y Slow A Y Fast T/C B Slow T/C B Fast OEAB B Slow OEAB B Fast tr Rise time, B outputs (20% to 80%) tf Fall time, B outputs (80% to 20%) Slow (ERC = GND) and Fast (ERC = VCC) All typical values are at VCC = 3.3 V, TA = 25°C. All values are derived from TI-SPICE models. TYP (2) 4.2 4.2 3.6 3.6 5.8 5.8 5.2 5.2 4.4 4.4 3.8 3.8 4.2 4.3 3.6 3.3 Slow 2 Fast 1.2 Slow 2.5 Fast 1.8 UNIT ns ns ns ns ns ns ns ns ns ns www.ti.com SN74GTLP1394 2-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE BUS TRANSCEIVER WITH SPLIT LVTTL PORT, FEEDBACK PATH, AND SELECTABLE POLARITY SCES286F – OCTOBER 1999 – REVISED APRIL 2005 APPLICATION INFORMATION Operational Description The GTLP1394 is designed specifically for use with the TI 1394 backplane layer controller family to transmit the 1394 backplane serial bus across parallel backplanes. But, it is a versatile 2-bit device that also is being used to provide multiple single-bit clocks or an ATM read and write clock in multislot parallel backplane applications. The 1394-1995 is an IEEE designation for a high-performance serial bus. This serial bus defines both a backplane (e.g., GTLP, VME, FB+, CPCI, etc.) physical layer and a point-to-point cable-connected virtual bus. The backplane version operates at 25, 50, or 100 Mbps, whereas the cable version supports data rates of 100, 200, and 400 Mbps. Both versions are compatible at the link layer and above. The interface standard defines the transmission method, media in the cable version, and protocol. The primary application of the cable version is the interconnection of digital A/V equipment and integration of I/O connectivity at the back panel of personal computers using a low-cost, scalable, high-speed serial interface. The primary application of the backplane version is to provide a robust control interface to each daughter card. The 1394 standard also provides new services, such as real-time I/O and live connect/disconnect capability for external devices. Electrical The 1394 standard is a transaction-based packet technology for cable- or backplane-based environments. Both chassis and peripheral devices can use this technology. The 1394 serial bus is organized as if it were memory space interconnected between devices, or as if devices resided in slots on the main backplane. Device addressing is 64 bits wide, partitioned as ten bits for bus ID, six bits for node ID, and 48 bits for memory addresses. The result is the capability to address up to 1023 buses, with each having up to 63 nodes, each with 281 terabytes of memory. Memory-based addressing, rather than channel addressing, views resources as registers or memory that can be accessed with processor-to-memory transactions. Each bus entity is termed a unit, to be individually addressed, reset, and identified. Multiple nodes can reside physically in a single module, and multiple ports can reside in a single node. Some key features of the 1394 topology are multimaster capabilities, live connect/disconnect (hot plugging) capability, genderless cabling connectors on interconnect cabling, and dynamic node address allocation as nodes are added to the bus. A maximum of 63 nodes can be connected to one network. The cable-based physical interface uses dc-level line states for signaling during initialization and arbitration. Both environments use dominant mode addresses for arbitration. The backplane environment does not have the initialization requirements of the cable environment because it is a physical bus and does not contain repeaters. Due to the differences, a backplane-to-cable bridge is required to connect these two environments. The signals transmitted on both the cable and backplane environments are NRZ with data-strobe (DS) encoding. DS encoding allows only one of the two signal lines to change each data bit-period, essentially doubling the jitter tolerance, with very little additional circuitry overhead in the hardware. 11 SN74GTLP1394 2-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE BUS TRANSCEIVER WITH SPLIT LVTTL PORT, FEEDBACK PATH, AND SELECTABLE POLARITY www.ti.com SCES286F – OCTOBER 1999 – REVISED APRIL 2005 APPLICATION INFORMATION Protocol Both asynchronous and isochronous data transfers are supported. The asynchronous format transfers data and transaction-layer information to an explicit address. The isochronous format broadcasts data based on channel numbers, rather than specific addressing. Isochronous packets are issued on the average of each 125 µs in support of time-sensitive applications. Providing both asynchronous and isochronous formats on the same interface allows both non-real-time and real-time critical applications on the same bus. The cable environment's tree topology is resolved during a sequence of events, triggered each time a new node is added or removed from the network. This sequence starts with a bus reset phase, where previous information about a topology is cleared. The tree ID sequence determines the actual tree structure, and a root node is dynamically assigned, or it is possible to force a particular node to become the root. After the tree is formed, a self-ID phase allows each node on the network to identify itself to all other nodes. During the self-ID process, each node is assigned an address. After all the information has been gathered on each node, the bus goes into an idle state, waiting for the beginning of the standard arbitration process. The backplane physical layer shares some commonality with the cable physical layer. Common functions include: bus state determination, bus access protocols, encoding and decoding functions, and synchronization of received data to a local clock. Backplane Features • • • • • 25-, 50-, and 100-Mbps data rates for backplane environments Live connection/disconnection possible without data loss or interruption. Configuration ROM and status registers supporting plug and play Multidrop or point-to-point topologies supported. Specified bandwidth assignments for real-time applications Applicability and Typical Application for IEEE Std 1394 Backplane The 1394 backplane serial bus (BPSB) plays a supportive role in backplane systems, specifically GTLP, FutureBus+, VME64, and proprietary backplane bus systems. This supportive role can be grouped into three categories: • Diagnostics – Alternate control path to the parallel backplane bus – Test, maintenance, and troubleshooting – Software debug and support interface • System enhancement – Fault tolerance – Live insertion – CSR access – Auxiliary 2-bit bus with a 64-bit address space to the parallel backplane bus • Peripheral monitoring – Monitoring of peripherals (disk drives, fans, power supplies, etc.) in conjunction with another externally wired monitor bus, such as defined by the Intelligent Platform Management Interface (IPMI) The 1394 backplane physical layer (PHY) and the SN74GTLP1394 provide a cost-effective way to add high-speed 1394 connections to every daughter card in almost any backplane. More information on the backplane physical layer devices and how to implement the 1394 standard in backplane and cable applications can be found at www.ti.com/sc/1394. 12 www.ti.com SN74GTLP1394 2-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE BUS TRANSCEIVER WITH SPLIT LVTTL PORT, FEEDBACK PATH, AND SELECTABLE POLARITY SCES286F – OCTOBER 1999 – REVISED APRIL 2005 APPLICATION INFORMATION SN74GTLP1394 Interface With the TSB14AA1 1394 Backplane PHY • • • • • • • • • A1, B1, and Y1 are used for the PHY data signals. A2, B2, and Y2 are used for the PHY strobe signals. PHY N_OEB_D or OCDOE connects to OEAB, which controls the PHY transmit signals. OEBY is connected to GND, since the transceiver always must be able to receive signals from the backplane and relay them to the PHY. T/C is connected to GND for inverted signals. VCC is nominal 3.3 V. BIAS VCC is connected to nominal 3.3 V to support live insertion. VREF normally is 2/3 of VTT. ERC normally is connected to GND for slow edge-rate operation because frequencies of only 50 MHz (S100) and 25 MHz (S50) are required. LOGICAL REPRESENTATION VCC TSB14AA1 3.3-V VCC Tdata D0 − D1 CTL0 − CTL1 2 1394 LinkLayer Controller LREQ SCLK A1 1394 Backplane PhysicalLayer Controller GND B1 2 Rdata Host Interface T/C 1 kΩ TDOE Y1 OCDOE Tstrb Rstrb GND BPdata OEAB A2 B2 BPstrb Y2 OEBY SN74GTLP1394 13 SN74GTLP1394 2-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE BUS TRANSCEIVER WITH SPLIT LVTTL PORT, FEEDBACK PATH, AND SELECTABLE POLARITY www.ti.com SCES286F – OCTOBER 1999 – REVISED APRIL 2005 APPLICATION INFORMATION PHYSICAL REPRESENTATION 64-Bit Data Bus 32- to 64-Bit Address Bus GTLP1394 Transceiver 1394 Backplane PHY 1394 Link-Layer Controller Host Microprocessor Terminators Backplane Trace Connectors VME/FB+/CPCI or GTLP Transceivers STRB A2 Module Module Module Node Node Node PHY PHY PHY Y2 A1 Y1 VTT RTT VTT B2 STRB B1 14 DATA DATA RTT PACKAGE OPTION ADDENDUM www.ti.com 24-May-2007 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Eco Plan (2) Qty 74GTLP1394DGVRE4 ACTIVE TVSOP DGV 16 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 74GTLP1394DGVRG4 ACTIVE TVSOP DGV 16 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 74GTLP1394RGYRG4 ACTIVE QFN RGY 16 1000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR SN74GTLP1394D ACTIVE SOIC D 16 40 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74GTLP1394DE4 ACTIVE SOIC D 16 40 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74GTLP1394DG4 ACTIVE SOIC D 16 40 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74GTLP1394DGVR ACTIVE TVSOP DGV 16 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74GTLP1394DR ACTIVE SOIC D 16 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74GTLP1394DRE4 ACTIVE SOIC D 16 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74GTLP1394DRG4 ACTIVE SOIC D 16 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74GTLP1394PW ACTIVE TSSOP PW 16 90 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74GTLP1394PWE4 ACTIVE TSSOP PW 16 90 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74GTLP1394PWG4 ACTIVE TSSOP PW 16 90 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74GTLP1394PWR ACTIVE TSSOP PW 16 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74GTLP1394PWRE4 ACTIVE TSSOP PW 16 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74GTLP1394PWRG4 ACTIVE TSSOP PW 16 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74GTLP1394RGYR ACTIVE QFN RGY 16 1000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR Lead/Ball Finish MSL Peak Temp (3) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame Addendum-Page 1 PACKAGE OPTION ADDENDUM www.ti.com 24-May-2007 retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 2 PACKAGE MATERIALS INFORMATION www.ti.com 4-Oct-2007 TAPE AND REEL BOX INFORMATION Device Package Pins Site Reel Diameter (mm) Reel Width (mm) A0 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant SN74GTLP1394DGVR DGV 16 SITE 41 330 12 6.8 4.0 1.6 8 16 Q1 SN74GTLP1394DR D 16 SITE 27 330 16 6.5 10.3 2.1 8 16 Q1 SN74GTLP1394PWR PW 16 SITE 41 330 12 7.0 5.6 1.6 8 12 Q1 SN74GTLP1394RGYR RGY 16 SITE 41 180 12 3.8 4.3 1.5 8 12 Q1 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 4-Oct-2007 Device Package Pins Site Length (mm) Width (mm) SN74GTLP1394DGVR DGV 16 SITE 41 346.0 346.0 29.0 SN74GTLP1394DR D 16 SITE 27 342.9 336.6 28.58 SN74GTLP1394PWR PW 16 SITE 41 346.0 346.0 29.0 SN74GTLP1394RGYR RGY 16 SITE 41 190.0 212.7 31.75 Pack Materials-Page 2 Height (mm) MECHANICAL DATA MPDS006C – FEBRUARY 1996 – REVISED AUGUST 2000 DGV (R-PDSO-G**) PLASTIC SMALL-OUTLINE 24 PINS SHOWN 0,40 0,23 0,13 24 13 0,07 M 0,16 NOM 4,50 4,30 6,60 6,20 Gage Plane 0,25 0°–8° 1 0,75 0,50 12 A Seating Plane 0,15 0,05 1,20 MAX PINS ** 0,08 14 16 20 24 38 48 56 A MAX 3,70 3,70 5,10 5,10 7,90 9,80 11,40 A MIN 3,50 3,50 4,90 4,90 7,70 9,60 11,20 DIM 4073251/E 08/00 NOTES: A. B. C. D. All linear dimensions are in millimeters. This drawing is subject to change without notice. Body dimensions do not include mold flash or protrusion, not to exceed 0,15 per side. Falls within JEDEC: 24/48 Pins – MO-153 14/16/20/56 Pins – MO-194 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 MECHANICAL DATA MTSS001C – JANUARY 1995 – REVISED FEBRUARY 1999 PW (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE 14 PINS SHOWN 0,30 0,19 0,65 14 0,10 M 8 0,15 NOM 4,50 4,30 6,60 6,20 Gage Plane 0,25 1 7 0°– 8° A 0,75 0,50 Seating Plane 0,15 0,05 1,20 MAX PINS ** 0,10 8 14 16 20 24 28 A MAX 3,10 5,10 5,10 6,60 7,90 9,80 A MIN 2,90 4,90 4,90 6,40 7,70 9,60 DIM 4040064/F 01/97 NOTES: A. B. C. D. All linear dimensions are in millimeters. This drawing is subject to change without notice. Body dimensions do not include mold flash or protrusion not to exceed 0,15. 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