TI SN74AUP1G97

SN74AUP1G97
LOW-POWER CONFIGURABLE MULTIPLE-FUNCTION GATE
www.ti.com
SCES505D – NOVEMBER 2003 – REVISED JUNE 2005
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FEATURES
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Available in the Texas Instruments
NanoStar™ and NanoFree™ Packages
Low Static-Power Consumption (ICC = 0.9 µA
Max)
Low Dynamic-Power Consumption
(Cpd = 4.8 pF Typ at 3.3 V)
Low Input Capacitance (Ci = 1.5 pF Typ)
Low Noise - Overshoot and Undershoot <10%
of VCC
Ioff Supports Partial-Power-Down Mode
Operation
Includes Schmitt-Trigger Inputs
Wide Operating VCC Range of 0.8 V to 3.6 V
DBV PACKAGE
(TOP VIEW)
B
1
6
Optimized for 3.3-V Operation
3.6-V I/O Tolerant to Support Mixed-Mode
Signal Operation
tpd = 5.6 ns Max at 3.3 V
Suitable for Point-to-Point Applications
Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
ESD Performance Tested Per JESD 22
– 2000-V Human-Body Model
(A114-B, Class II)
– 200-V Machine Model (A115-A)
– 1000-V Charged-Device Model (C101)
ESD Protection Exceeds ±5000 V With
Human-Body Model
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DCK PACKAGE
(TOP VIEW)
B
C
GND
2
5
VCC
A
3
4
Y
1
6
DRL PACKAGE
(TOP VIEW)
C
B
GND
2
5
VCC
A
3
4
Y
GND
A
1
2
3
6
5
4
YEP OR YZP PACKAGE
(BOTTOM VIEW)
C
VCC
Y
A
3 4
Y
GND
2 5
VCC
B
1 6
C
See mechanical drawings for dimensions.
DESCRIPTION/ORDERING INFORMATION
The AUP family is TI's premier solution to the industry's low-power needs in battery-powered portable
applications. This family ensures a very low static- and dynamic-power consumption across the entire VCC range
of 0.8 V to 3.6 V, resulting in increased battery life (see Figure 1). This product also maintains excellent signal
integrity (see the very low undershoot and overshoot characteristics shown in Figure 2).
Static-Power Consumption
Dynamic-Power Consumption
(µA)
(pF)
100%
100%
80%
80%
3.3-V
Logic†
60%
60%
3.3-V
Logic†
LVC
40%
40%
20%
20%
AUP
0%
†
0%
AUP
Single, dual, and triple gates
Figure 1. AUP – The Lowest-Power Family
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
NanoStar, NanoFree are trademarks of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2003–2005, Texas Instruments Incorporated
SN74AUP1G97
LOW-POWER CONFIGURABLE MULTIPLE-FUNCTION GATE
www.ti.com
SCES505D – NOVEMBER 2003 – REVISED JUNE 2005
DESCRIPTION/ORDERING INFORMATION (CONTINUED)
Switching Characteristics
at 25 MHz†
3.5
Voltage − V
3
2.5
Input
2
Output
1.5
1
0.5
0
−0.5
0
5
†
10
15
20 25 30
Time − ns
35
40
45
AUP1G08 data at CL = 15 pF
Figure 2. Excellent Signal Integrity
The SN74AUP1G97 features configurable multiple functions. The output state is determined by eight patterns of
3-bit input. The user can choose the logic functions MUX, AND, OR, NAND, NOR, inverter, and noninverter. All
inputs can be connected to VCC or GND.
The device functions as an independent gate with Schmitt-trigger inputs, which allows for slow input transition
and better switching-noise immunity at the input.
NanoStar™ and NanoFree™ package technology is a major breakthrough in IC packaging concepts, using the
die as the package.
This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs,
preventing damaging current backflow through the device when it is powered down.
ORDERING INFORMATION
PACKAGE (1)
TA
–40°C to 85°C
(1)
(2)
ORDERABLE PART NUMBER
NanoStar™ – WCSP (DSBGA)
0.23-mm Large Bump – YEP
Tape and reel
SN74AUP1G97YEPR
NanoFree™ – WCSP (DSBGA)
0.23-mm Large Bump – YZP (Pb-free)
Tape and reel
SN74AUP1G97YZPR
SOT (SOT-23) – DBV
Tape and reel
SN74AUP1G97DBVR
SOT (SC-70) – DCK
Tape and reel
SN74AUP1G97DCKR
SOT (SOT-553) – DRL
Reel of 4000
SN74AUP1G97DRLR
_ _ _HP_
H97_
HP_
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at
www.ti.com/sc/package.
DBV/DCK/DRL: The actual top-side marking has one additional character that designates the assembly/test site.
YEP/YZP: The actual top-side marking has three preceding characters to denote year, month, and sequence code, and one following
character to designate the assembly/test site. Pin 1 identifier indicates solder-bump composition (1 = SnPb, ⋅ = Pb-free).
FUNCTION TABLE
INPUTS
2
TOP-SIDE MARKING (2)
C
B
A
OUTPUT
Y
L
L
L
L
L
L
H
L
L
H
L
H
L
H
H
H
H
L
L
L
H
L
H
H
H
H
L
L
H
H
H
H
SN74AUP1G97
LOW-POWER CONFIGURABLE MULTIPLE-FUNCTION GATE
www.ti.com
SCES505D – NOVEMBER 2003 – REVISED JUNE 2005
LOGIC DIAGRAM (POSITIVE LOGIC)
A
3
4
B
C
1
Y
6
FUNCTION SELECTION TABLE
LOGIC FUNCTION
FIGURE NO.
2-to-1 data selector
3
2-input AND gate
4
2-input OR gate with one inverted input
5
2-input NAND gate with one inverted input
5
2-input AND gate with one inverted input
6
2-input NOR gate with one inverted input
6
2-input OR gate
7
Inverter
8
Noninverted buffer
9
LOGIC CONFIGURATIONS
VCC
C
B
B
Y
A
A
1
6
2
5
3
4
C
Y
GND
Figure 3. 2-to-1 Data Selector
When C is L, Y = B
When C is H, Y = A
VCC
C
Y
A
A
1
6
2
5
3
4
C
Y
GND
Figure 4. 2-Input AND Gate
3
SN74AUP1G97
LOW-POWER CONFIGURABLE MULTIPLE-FUNCTION GATE
www.ti.com
SCES505D – NOVEMBER 2003 – REVISED JUNE 2005
VCC
C
Y
A
C
Y
A
A
1
6
2
5
3
4
C
Y
GND
Figure 5. Input OR Gate With One Inverted Input
2-Input NAND Gate With One Inverted Input
VCC
C
Y
B
B
C
Y
B
1
6
2
5
3
4
C
Y
GND
Figure 6. 2-Input AND Gate With One Inverted Input
2-Input NOR Gate With One Inverted Input
VCC
C
B
Y
B
1
6
2
5
3
4
C
Y
GND
Figure 7. 2-Input OR Gate
VCC
C
Y
1
6
2
5
3
4
GND
Figure 8. Inverter
4
C
Y
SN74AUP1G97
LOW-POWER CONFIGURABLE MULTIPLE-FUNCTION GATE
www.ti.com
SCES505D – NOVEMBER 2003 – REVISED JUNE 2005
VCC
B
B
Y
1
6
2
5
3
4
Y
GND
Figure 9. Noninverted Buffer
5
SN74AUP1G97
LOW-POWER CONFIGURABLE MULTIPLE-FUNCTION GATE
www.ti.com
SCES505D – NOVEMBER 2003 – REVISED JUNE 2005
Absolute Maximum Ratings (1)
over operating free-air temperature range (unless otherwise noted)
MIN
MAX
VCC
Supply voltage range
–0.5
4.6
V
VI
Input voltage range (2)
–0.5
4.6
V
–0.5
4.6
V
–0.5
VCC + 0.5
state (2)
UNIT
VO
Voltage range applied to any output in the high-impedance or power-off
VO
Output voltage range in the high or low state (2)
IIK
Input clamp current
VI < 0
–50
mA
IOK
Output clamp current
VO < 0
–50
mA
IO
Continuous output current
±20
mA
Continuous current through VCC or GND
±50
mA
θJA
Package thermal impedance (3)
Tstg
(1)
(2)
(3)
DBV package
165
DCK package
259
DRL package
142
YEP/YZP package
123
Storage temperature range
–65
V
°C/W
150
°C
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed.
The package thermal impedance is calculated in accordance with JESD 51-7.
Recommended Operating Conditions (1)
MIN
MAX
0.8
3.6
V
Input voltage
0
3.6
V
Output voltage
0
VCC
V
VCC = 0.8 V
–20
µA
VCC = 1.1 V
–1.1
VCC = 1.4 V
–1.7
VCC = 1.65
–1.9
VCC = 2.3 V
–3.1
VCC
Supply voltage
VI
VO
IOH
High-level output current
VCC = 3 V
IOL
Low-level output current
Input transition rise or fall rate
TA
Operating free-air temperature
(1)
6
mA
–4
VCC = 0.8 V
20
VCC = 1.1 V
1.1
VCC = 1.4 V
1.7
VCC = 1.65 V
1.9
VCC = 2.3 V
3.1
VCC = 3 V
∆t/∆v
UNIT
µA
mA
4
VCC = 0.8 V to 3.6 V
–40
200
ns/V
85
°C
All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
SN74AUP1G97
LOW-POWER CONFIGURABLE MULTIPLE-FUNCTION GATE
www.ti.com
SCES505D – NOVEMBER 2003 – REVISED JUNE 2005
Electrical Characteristics
over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VT+
Positive-going
input threshold
voltage
VT–
Negative-going
input threshold
voltage
∆VT
Hysteresis
(VT+ – VT–)
VCC
TA = –40°C to 85°C
MAX
MIN
MAX
0.6
0.3
0.6
0.3
1.1 V
0.53
0.9
0.53
0.9
1.4 V
0.74
1.11
0.74
1.11
1.65 V
0.91
1.29
0.91
1.29
2.3 V
1.37
1.77
1.37
1.77
3V
1.88
2.29
1.88
2.29
0.8 V
0.1
0.6
0.1
0.6
1.1 V
0.26
0.65
0.26
0.65
1.4 V
0.39
0.75
0.39
0.75
1.65 V
0.47
0.84
0.47
0.84
2.3 V
0.69
1.04
0.69
1.04
1.24
3V
0.88
1.24
0.88
0.8 V
0.07
0.5
0.07
0.5
1.1 V
0.08
0.46
0.08
0.46
1.4 V
0.18
0.56
0.18
0.56
1.65 V
0.27
0.66
0.27
0.66
2.3 V
0.53
0.92
0.53
0.92
0.79
1.31
0.79
1.31
IOH = –20 µA
0.8 V to 3.6 V
VCC – 0.1
VCC – 0.1
IOH = –1.1 mA
1.1 V
0.75 × VCC
0.7 × VCC
IOH = –1.7 mA
1.4 V
1.11
1.03
IOH = –1.9 mA
1.65 V
1.32
1.3
2.05
1.97
1.9
1.85
2.72
2.67
IOH = –2.3 mA
2.3 V
IOH = –3.1 mA
IOH = –2.7 mA
3V
IOH = –4 mA
VOL
TYP
0.8 V
3V
VOH
TA = 25°C
MIN
IOL = 20 µA
0.8 V to 3.6 V
IOL = 1.1 mA
IOL = 1.7 mA
IOL = 1.9 mA
IOL = 2.3 mA
2.6
1.1 V
0.3 × VCC
0.3 × VCC
1.4 V
0.31
0.37
1.65 V
0.31
0.35
0.31
0.33
0.44
0.45
0.31
0.33
0.44
0.45
3V
IOL = 4 mA
V
V
2.55
0.1
IOL = 2.7 mA
V
V
0.1
2.3 V
IOL = 3.1 mA
UNIT
V
0 V to 3.6 V
0.1
0.5
µA
Ioff
VI or VO = 0 V to 3.6 V
0V
0.2
0.6
µA
∆Ioff
VI or VO = 0 V to 3.6 V
0 V to 0.2 V
0.2
0.6
µA
ICC
VI = GND or (VCC to 3.6 V),
IO = 0
0.8 V to 3.6 V
0.5
0.9
µA
3.3 V
40
50
µA
II
All inputs
VI = GND to 3.6 V
V (1),
∆ICC
VI = VCC – 0.6
IO = 0
Ci
VI = VCC or GND
Co
VO = GND
(1)
0V
1.5
3.6 V
1.5
0V
3
pF
pF
One input at VCC – 0.6 V, other inputs at VCC or GND
7
SN74AUP1G97
LOW-POWER CONFIGURABLE MULTIPLE-FUNCTION GATE
www.ti.com
SCES505D – NOVEMBER 2003 – REVISED JUNE 2005
Switching Characteristics
over recommended operating free-air temperature range, CL = 5 pF (unless otherwise noted) (see Figure 10 and Figure 11)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
VCC
TA = 25°C
MIN
0.8 V
tpd
A, B, or C
Y
TYP
TA = –40°C to 85°C
MAX
MIN
MAX
UNIT
23.1
1.2 V ± 0.1 V
3.1
9.1
13.9
2.6
17.6
1.5 V ± 0.1 V
2.1
6.4
9.4
1.6
11.4
1.8 V ± 0.15 V
1.6
5.1
7.5
1.1
9.2
2.5 V ± 0.2 V
1.1
3.6
5.7
0.6
6.8
3.3 V ± 0.3 V
1
2.8
4.7
0.5
5.6
ns
Switching Characteristics
over recommended operating free-air temperature range, CL = 10 pF (unless otherwise noted) (see Figure 10 and Figure 11)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
VCC
TA = 25°C
MIN
0.8 V
1.2 V ± 0.1 V
tpd
A, B, or C
Y
TA = –40°C to 85°C
TYP MAX
MIN
MAX
UNIT
26.2
5.2
10.4
15.4
4.7
19.2
1.5 V ± 0.1 V
4
7.4
10.7
3.5
12.7
1.8 V ± 0.15 V
3.1
6
8.6
2.6
10.5
2.5 V ± 0.2 V
2.7
4.3
6.5
2.2
7.8
3.3 V ± 0.3 V
2.5
3.4
5.4
2
6.4
ns
Switching Characteristics
over recommended operating free-air temperature range, CL = 15 pF (unless otherwise noted) (see Figure 10 and Figure 11)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
VCC
TA = 25°C
MIN
0.8 V
tpd
A, B, or C
Y
TYP
TA = –40°C to 85°C
MAX
MIN
MAX
UNIT
28.9
1.2 V ± 0.1 V
4.1
11.5
16.8
3.6
21.3
1.5 V ± 0.1 V
3
8.3
11.8
2.5
14.1
1.8 V ± 0.15 V
2.3
6.7
9.5
1.8
11.6
2.5 V ± 0.2 V
1.7
4.8
7.2
1.2
8.6
3.3 V ± 0.3 V
1.4
3.9
6
0.9
7.1
ns
Switching Characteristics
over recommended operating free-air temperature range, CL = 30 pF (unless otherwise noted) (see Figure 10 and Figure 11)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
VCC
TA = 25°C
MIN
0.8 V
tpd
8
A, B, or C
Y
TYP
TA = –40°C to 85°C
MAX
MIN
MAX
UNIT
36.7
1.2 V ± 0.1 V
5.5
14.6
21.4
5
26.7
1.5 V ± 0.1 V
4.1
10.5
14.8
3.6
17.7
1.8 V ± 0.15 V
3.3
8.6
11.8
2.8
14.5
2.5 V ± 0.2 V
2.5
6.3
8.8
2
10.6
3.3 V ± 0.3 V
2.1
5.1
7.3
1.6
8.8
ns
SN74AUP1G97
LOW-POWER CONFIGURABLE MULTIPLE-FUNCTION GATE
www.ti.com
SCES505D – NOVEMBER 2003 – REVISED JUNE 2005
Operating Characteristics
TA = 25°C
PARAMETER
Cpd
Power dissipation capacitance
TEST CONDITIONS
f = 10 MHz
VCC
TYP
0.8 V
4
1.2 V ± 0.1 V
4
1.5 V ± 0.1 V
4
1.8 V ± 0.15 V
4
2.5 V ± 0.2 V
4.4
3.3 V ± 0.3 V
4.8
UNIT
pF
9
SN74AUP1G97
LOW-POWER CONFIGURABLE MULTIPLE-FUNCTION GATE
www.ti.com
SCES505D – NOVEMBER 2003 – REVISED JUNE 2005
PARAMETER MEASUREMENT INFORMATION
(Propagation Delays, Setup and Hold Times, and Pulse Duration)
From Output
Under Test
CL
(see Note A)
1 MΩ
LOAD CIRCUIT
CL
VM
VI
VCC = 0.8 V
VCC = 1.2 V
± 0.1 V
VCC = 1.5 V
± 0.1 V
VCC = 1.8 V
± 0.15 V
VCC = 2.5 V
± 0.2 V
VCC = 3.3 V
± 0.3 V
5, 10, 15, 30 pF
VCC/2
VCC
5, 10, 15, 30 pF
VCC/2
VCC
5, 10, 15, 30 pF
VCC/2
VCC
5, 10, 15, 30 pF
VCC/2
VCC
5, 10, 15, 30 pF
VCC/2
VCC
5, 10, 15, 30 pF
VCC/2
VCC
tw
VCC
Input
VCC/2
VCC/2
VI
VM
Input
0V
VM
VOLTAGE WAVEFORMS
PULSE DURATION
0V
tPHL
tPLH
VOH
VM
Output
VM
VOL
tPHL
VCC
Timing Input
0V
tPLH
tsu
VOH
VM
Output
VCC
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
Data Input
VCC/2
VCC/2
0V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
CL includes probe and jig capacitance.
All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, slew rate ≥ 1 V/ns.
The outputs are measured one at a time, with one transition per measurement.
tPLH and tPHL are the same as tpd.
All parameters and waveforms are not applicable to all devices.
Figure 10. Load Circuit and Voltage Waveforms
10
th
VM
VOL
NOTES: A.
B.
C.
D.
E.
VCC/2
SN74AUP1G97
LOW-POWER CONFIGURABLE MULTIPLE-FUNCTION GATE
www.ti.com
SCES505D – NOVEMBER 2003 – REVISED JUNE 2005
PARAMETER MEASUREMENT INFORMATION
(Enable and Disable Times)
2 × VCC
S1
5 kΩ
From Output
Under Test
GND
CL
(see Note A)
5 kΩ
TEST
S1
tPLZ/tPZL
tPHZ/tPZH
2 × VCC
GND
LOAD CIRCUIT
CL
VM
VI
V∆
VCC = 0.8 V
VCC = 1.2 V
± 0.1 V
VCC = 1.5 V
± 0.1 V
VCC = 1.8 V
± 0.15 V
VCC = 2.5 V
± 0.2 V
VCC = 3.3 V
± 0.3 V
5, 10, 15, 30 pF
VCC/2
VCC
0.1 V
5, 10, 15, 30 pF
VCC/2
VCC
0.1 V
5, 10, 15, 30 pF
VCC/2
VCC
0.1 V
5, 10, 15, 30 pF
VCC/2
VCC
0.15 V
5, 10, 15, 30 pF
VCC/2
VCC
0.15 V
5, 10, 15, 30 pF
VCC/2
VCC
0.3 V
VCC
Output
Control
Output
Waveform 1
S1 at 2 × VCC
(see Note B)
VCC/2
0V
tPZL
tPLZ
VCC
VCC/2
tPZH
Output
Waveform 2
S1 at GND
(see Note B)
VCC/2
VOL + V∆
VOL
tPHZ
VCC/2
VOH - V∆
VOH
≈0 V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, slew rate ≥ 1 V/ns.
D. The outputs are measured one at a time, with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. tPZL and tPZH are the same as ten.
G. All parameters and waveforms are not applicable to all devices.
Figure 11. Load Circuit and Voltage Waveforms
11
PACKAGE OPTION ADDENDUM
www.ti.com
13-Jun-2005
PACKAGING INFORMATION
Orderable Device
Status (1)
Package
Type
Package
Drawing
Pins Package Eco Plan (2)
Qty
SN74AUP1G97DBVR
ACTIVE
SOT-23
DBV
6
3000
Pb-Free
(RoHS)
CU NIPDAU
Level-1-260C-UNLIM
SN74AUP1G97DBVRE4
ACTIVE
SOT-23
DBV
6
3000
Pb-Free
(RoHS)
CU NIPDAU
Level-1-260C-UNLIM
SN74AUP1G97DBVT
ACTIVE
SOT-23
DBV
6
250
Pb-Free
(RoHS)
CU NIPDAU
Level-1-260C-UNLIM
SN74AUP1G97DBVTE4
ACTIVE
SOT-23
DBV
6
250
Pb-Free
(RoHS)
CU NIPDAU
Level-1-260C-UNLIM
SN74AUP1G97DCKR
ACTIVE
SC70
DCK
6
3000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74AUP1G97DCKRE4
ACTIVE
SC70
DCK
6
3000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74AUP1G97DCKT
ACTIVE
SC70
DCK
6
250
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74AUP1G97DCKTE4
ACTIVE
SC70
DCK
6
250
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74AUP1G97DRLR
ACTIVE
SOP
DRL
6
4000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74AUP1G97YEPR
ACTIVE
WCSP
YEP
6
3000
TBD
SNPB
Level-1-260C-UNLIM
SN74AUP1G97YZPR
ACTIVE
WCSP
YZP
6
3000
Pb-Free
(RoHS)
SNAGCU
Level-1-260C-UNLIM
Lead/Ball Finish
MSL Peak Temp (3)
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS) or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 1
MECHANICAL DATA
MPDS114 – FEBRUARY 2002
DCK (R-PDSO-G6)
PLASTIC SMALL-OUTLINE PACKAGE
0,30
0,15
0,65
6
0,10 M
4
1,40
1,10
1
0,13 NOM
2,40
1,80
3
Gage Plane
2,15
1,85
0,15
0°–8°
0,46
0,26
Seating Plane
1,10
0,80
0,10
0,00
0,10
4093553-3/D 01/02
NOTES: A.
B.
C.
D.
All linear dimensions are in millimeters.
This drawing is subject to change without notice.
Body dimensions do not include mold flash or protrusion.
Falls within JEDEC MO-203
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
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