INTEGRATED CIRCUITS DATA SHEET PCF8531 34 × 128 pixel matrix driver Product specification Supersedes data of 1999 Aug 10 File under Integrated Circuits, IC12 2000 Feb 11 Philips Semiconductors Product specification 34 × 128 pixel matrix driver PCF8531 CONTENTS 9 I2C-BUS INTERFACE Characteristics of the I2C-bus Bit transfer START and STOP conditions System configuration Acknowledge I2C-bus protocol Command decoder 1 FEATURES 2 APPLICATIONS 3 GENERAL DESCRIPTION 4 PACKAGES 5 ORDERING INFORMATION 9.1 9.1.1 9.1.2 9.1.3 9.1.4 9.2 9.3 6 BLOCK DIAGRAM 10 LIMITING VALUES 7 PINNING 11 HANDLING 8 FUNCTIONAL DESCRIPTION 12 DC CHARACTERISTICS 8.1 8.2 8.3 8.4 8.5 8.6 8.7 8.8 8.9 8.10 8.11 8.12 8.13 8.14 8.15 8.16 8.17 8.18 8.18.1 8.18.2 8.18.3 8.18.4 8.18.5 8.18.6 8.18.7 8.18.8 8.18.9 8.18.10 8.18.11 Oscillator Power-on reset I2C-bus controller Input filters Display data RAM Timing generator Address counter Display address counter Command decoder Bias voltage generator VLCD generator Reset Power-down Column driver outputs Row driver outputs LCD waveforms and DDRAM to data mapping Addressing Instructions Reset Function set Set Y address Set X address Set multiplex rate Display control (D, E and IM) Set bias system LCD bias voltage Set VOP value: Voltage multiplier control S[1:0] Temperature compensation 13 AC CHARACTERISTICS 14 APPLICATION INFORMATION 15 BONDING PAD LOCATIONS 16 DEVICE PROTECTION DIAGRAM 17 TRAY INFORMATION 18 DEFINITIONS 19 LIFE SUPPORT APPLICATIONS 20 PURCHASE OF PHILIPS I2C COMPONENTS 2000 Feb 11 2 Philips Semiconductors Product specification 34 × 128 pixel matrix driver 1 PCF8531 FEATURES • Single-chip LCD controller/driver • 34 row and 128 column outputs • Display data RAM 34 × 128 bits • 128 icons (last row is used for icons) • Fast mode I2C-bus interface (400 kbit/s) 2 • Software selectable multiplex rates: 1 : 17, 1 : 26 and 1 : 34 • Telecommunication systems APPLICATIONS • Automotive information systems • Icon mode with Mux rate 1 : 2: • Point-of-sale terminals – Featuring reduced current consumption while displaying icons only. • Instrumentation. • On-chip: 3 – Generation of VLCD (external supply also possible) GENERAL DESCRIPTION The PCF8531 is a low power CMOS LCD row/column driver, designed to drive dot matrix graphic displays at multiplex rates of 1 : 17, 1 : 26 and 1 : 34. Furthermore, it can drive up to 128 icons. All necessary functions for the display are provided in a single chip, including on-chip generation of VLCD and the LCD bias voltages, resulting in a minimum of external components and low power consumption. The PCF8531 is compatible with most microcontrollers and communicates via a two-line bidirectional bus (I2C-bus). All inputs are CMOS compatible. – Selectable linear temperature compensation – Oscillator requires no external components (external clock also possible) – Generation of intermediate LCD bias voltages – Power-on reset. • No external components required • Software selectable bias configuration • Logic supply voltage range VDD1 to VSS1 1.8 to 5.5 V • Supply voltage range for on-chip voltage generator VDD2 and VDD3 to VSS1 and VSS2 2.5 to 4.5 V Remark: The icon mode is used to save current. When only icons are displayed, a much lower operating voltage (VLCD) can be used and the switching frequency of the LCD outputs is reduced. In most applications it is possible to use VDD as VLCD. • Display supply voltage range VLCD to VSS: – Normal mode 4 to 9 V – Icon mode 3 to 9 V. • Low power consumption, suitable for battery operated systems 4 • CMOS compatible inputs The PCF8531 is available as chip with bumps in tray. • Manufactured in silicon gate CMOS process. 5 PACKAGES ORDERING INFORMATION TYPE NUMBER PCF8531U/2 2000 Feb 11 PACKAGE NAME − DESCRIPTION VERSION − chip with bumps in tray 3 Philips Semiconductors Product specification 34 × 128 pixel matrix driver 6 PCF8531 BLOCK DIAGRAM 34 VSS1 VDD2 VDD3 128 ROW DRIVERS VSS2 VDD1 C0 to C127 R0 to R33 handbook, full pagewidth COLUMN DRIVERS POWER-ON RESET ENR INTERNAL RESET RES T1 T2 PCF8531 T3 T4 DATA LATCHES VLCDIN BIAS VOLTAGE GENERATOR OSCILLATOR MATRIX LATCHES TIMING GENERATOR VLCDSENSE VLCDOUT DISPLAY DATA RAM VLCD GENERATOR SCL SDA SDACK INPUT FILTERS MATRIX DATA RAM I2C-BUS CONTROL COMMAND DECODER DISPLAY ADDRESS COUNTER ADDRESS COUNTER MGS465 SA0 Fig.1 Block diagram. 2000 Feb 11 4 OSC Philips Semiconductors Product specification 34 × 128 pixel matrix driver 7 PCF8531 PINNING SYMBOL PAD 1 to 14 DESCRIPTION dummy pads OSC 15 oscillator input; note 1 VLCDSENSE 16 voltage multiplier regulation input (VLCD); note 2 VLCDOUT 17 to 23 voltage multiplier output (VLCD); note 3 VLCDIN 24 to 30 LCD supply voltage (VLCD); note 2 RES 31 VDD3 32 to 34 supply voltage 3; note 5 VDD2 35 to 42 supply voltage 2; note 5 VDD1 43 to 49 supply voltage 1; note 5 SDA 50 and 51 SDACK external reset input (active LOW); note 4 serial data line input of the I2C-bus 52 serial data acknowledge output; note 6 53 dummy pad SA0 54 I2C-bus slave address input; bit 0 ENR 55 enable internal Power-on reset input; note 7 T4 56 test 4 input; note 8 VSS2 57 to 63 ground 2; note 9 VSS1 64 to 70 ground 1; note 9 T3 71 test 3 input; note 8 T1 72 test 1 input; note 8 SCL 73 and 74 75 to 77 T2 78 79 to 86 serial clock line input of the I2C-bus dummy pads test 2 output; note 10 dummy pads R0 87 LCD row driver output R2 88 LCD row driver output R4 89 LCD row driver output R6 90 LCD row driver output R8 91 LCD row driver output R10 92 LCD row driver output R12 93 LCD row driver output R14 94 LCD row driver output R16 95 LCD row driver output R18 96 LCD row driver output R20 97 LCD row driver output R22 98 LCD row driver output R24 99 LCD row driver output R26 100 LCD row driver output R28 101 LCD row driver output R30 102 LCD row driver output R32 103 LCD row driver output 2000 Feb 11 5 Philips Semiconductors Product specification 34 × 128 pixel matrix driver SYMBOL C0 to C127 PCF8531 PAD 104 to 231 DESCRIPTION LCD column driver outputs R33 232 LCD row driver output; icon row R31 233 LCD row driver output R29 234 LCD row driver output R27 235 LCD row driver output R25 236 LCD row driver output R23 237 LCD row driver output R21 238 LCD row driver output R19 239 LCD row driver output R17 240 LCD row driver output R15 241 LCD row driver output R13 242 LCD row driver output R11 243 LCD row driver output R9 244 LCD row driver output R7 245 LCD row driver output R5 246 LCD row driver output R3 247 LCD row driver output R1 248 LCD row driver output Notes 1. If the on-chip oscillator is used, this input must be connected to VDD1. 2. If the internal VLCD generation is used, VLCDOUT, VLCDIN and VLCDSENSE must be connected together. 3. If an external VLCD is used in the application, then pin VLCDOUT must be left open circuit, otherwise the chip will be damaged. 4. If only the internal Power-on reset is used, this input must be connected to VDD1. 5. VDD1 is for the logic supply, VDD2, and VDD3 are for the voltage multiplier. For split power supplies, VDD2 and VDD3 must be connected together. If only one supply voltage is available, VDD1, VDD2 and VDD3 must be connected together. 6. Serial data acknowledge for the I2C-bus. By connecting SDACK to SDA externally, the SDA line becomes fully I2C-bus compatible. Having the acknowledge output separated from the serial data line is advantageous in Chip-On-Glass (COG) applications. In COG applications where the track resistance from the SDACK pad to the system SDA line can be significant, a potential divider is generated by the bus pull-up resistor and the Indium Tin Oxide (ITO) track resistance. It is possible that the PCF8531 will not be able to create a valid logic 0 level during the acknowledge cycle. By splitting the SDA input from the SDACK output, the device could be used in a mode that ignores the acknowledge bit. In COG applications where the acknowledge cycle is required, it is necessary to minimize the track resistance from the SDACK pad to the system SDA line to guarantee a valid LOW level. 7. If ENR is connected to VSS, Power-on reset is disabled; to enable Power-on reset ENR should be connected to VDD1. 8. In the application, this input must be connected to VSS. 9. VSS1 and VSS2 must be connected together. 10. In the application, T2 must be left open circuit. 2000 Feb 11 6 Philips Semiconductors Product specification 34 × 128 pixel matrix driver 8 8.1 PCF8531 8.10 FUNCTIONAL DESCRIPTION Bias voltage generator The bias voltage generator generates four buffered intermediate bias voltages. This block contains the generator for the reference voltages and the four buffers. This block can operate in two voltage ranges: Oscillator The on-chip oscillator provides the clock signal for the display system. No external components are required and the OSC input must be connected to VDD. An external clock signal, if used, is connected to this input. • Normal mode; 4.0 to 9.0 V • Power save mode; 3.0 to 9.0 V. 8.2 Power-on reset 8.11 The on-chip Power-on reset initializes the chip after Power-on or power failure. 8.3 The VLCD voltage generator contains a configurable 2 to 5 times voltage multiplier; this is software programmable. I2C-bus controller The I2C-bus controller receives and executes the commands. The PCF8531 acts as an I2C-bus slave receiver and therefore cannot control bus communication. 8.4 8.12 Input filters • All row and column outputs are set to VSS (display off) • RAM data is undefined • Power-down mode. Display data RAM The PCF8531 contains a 34 × 128 bits static RAM, which stores the display data. The RAM is divided into 6 banks of 128 bytes (6 × 8 × 128 bits). Bank 6 is used for icon data. During RAM access, data is transferred to the RAM via the I2C-bus interface. There is a direct correspondence between the X address and column output number. 8.6 8.13 8.14 Timing generator Address counter 8.15 Display address counter Command decoder The command decoder identifies command words that arrive on the I2C-bus and determines the destination for the following data bytes. 2000 Feb 11 Row driver outputs The LCD drive section includes 34 row outputs (R0 to R33), which should be connected directly to the LCD. The row output signals are generated in accordance with the selected LCD drive mode. If less than 34 rows or lower Mux rates are required, the unused outputs must be left open circuit. The row signals are interlaced i.e. the selection order is R0, R2, ..., R1, R3 etc. The display address counter generates the addresses for read out of the display data. 8.9 Column driver outputs The LCD drive section includes 128 column outputs (C0 to C127) which should be connected directly to the LCD. The column output signals are generated in accordance with the multiplexed row signals and with the data in the display latch. When less than 128 columns are required, the unused column outputs should be left open circuit. The address counter sets the addresses of the display data RAM for writing. 8.8 Power-down During power-down, all static currents are switched off (no internal oscillator, no timing and no LCD segment drive system), and all LCD outputs are internally connected to VSS. The I2C-bus function remains operational. The timing generator produces the various signals required to drive the internal circuitry. Internal chip operation is not disturbed by operations on the data buses. 8.7 Reset The PCF8531 has the possibility of two reset modes, internal Power-on reset or external reset (RES). The reset mode is selected using the ENR signal. After a reset, the chip has the following state: To enhance noise immunity in electrically adverse environments, RC low-pass filters are provided on the SDA and SCL lines. 8.5 VLCD generator 7 Philips Semiconductors Product specification 34 × 128 pixel matrix driver 8.16 PCF8531 LCD waveforms and DDRAM to data mapping The LCD waveforms and the DDRAM to display data mapping are shown in Figs 2, 3 and 4. frame n + 1 frame n ROW 0 R0 (t) ROW 2 R2 (t) COL 0 C0 (t) COL 1 C1 (t) Vstate1(t) Vstate2 (t) VLCD V2 V3 V4 V5 VSS VLCD V2 V3 V4 V5 VSS VLCD V2 V3 V4 V5 VSS VLCD V2 V3 V4 V5 VSS VLCD V3 − VSS Vstate1(t) VLCD − V2 0V V3 − V2 V4 − V5 0V VSS − V5 V4 − VLCD −VLCD VLCD V3 − VSS Vstate2 (t) VLCD − V2 0V V3 − V2 V4 − V5 0V VSS − V5 V4 − VLCD −VLCD 0 2 4 6 8... ... 32 1 3 5 7... ... 33 0 2 4 6 8... ... 32 1 3 5 7... Vstate1(t) = C1(t) − R0(t). Vstate2(t) = C1(t) − R2(t). Fig.2 Typical LCD driver waveforms. 2000 Feb 11 8 ... 33 MGS466 Philips Semiconductors Product specification 34 × 128 pixel matrix driver PCF8531 frame n + 1 frame n only icons are driven VLCD V2 V3 ROW 0 to 32 V4 V5 VSS VLCD V2 V3 ROW 33 V4 V5 VSS VLCD V2 V3 COL 1 on/off V4 V5 VSS VLCD V2 V3 COL 2 off/on V4 V5 VSS VLCD V2 V3 COL 3 on/on V4 V5 VSS VLCD V2 V3 COL 4 off/off V4 V5 VSS MGS467 Fig.3 Icon mode; Mux 1 : 2 LCD waveforms. 2000 Feb 11 9 Philips Semiconductors Product specification 34 × 128 pixel matrix driver PCF8531 DDRAM bank 0 top of LCD R0 bank 1 R8 bank 2 R16 LCD bank 3 R24 bank 4 R32 R33 (icon row) bank 5 MGS468 Fig.4 DDRAM to display mapping. 2000 Feb 11 10 Philips Semiconductors Product specification 34 × 128 pixel matrix driver 8.17 PCF8531 Addressing column. In horizontal addressing mode (V = 0), the X address increments after each byte (see Fig.7). After the last X address (X = 127), X wraps around to 0 and Y increments to address the next row. After the very last address (X = 127 and Y = 4), the address pointers wrap around to address (X = 0 and Y = 0). It should be noted that in bank 4 only the LSB (DB0) of the data will be written into the RAM. The Y address 5 is reserved for icon data and is not affected by the addressing mode; it should be noted that in bank 5 only the 5th data bit (DB4) will be written into the RAM. Data is written in bytes into the RAM matrix of the PCF8531 as illustrated in Figs 5, 6 and 7. The display RAM has a matrix of 34 × 128 bits. The columns are addressed by the address pointer. The address ranges are X 0 to X 127 (7FH) and Y 0 to Y 5 (5H). Addresses outside of these ranges are not allowed. In vertical addressing mode (V = 1), the Y address increments after each byte (see Fig.6). After the last Y address (Y = 4), Y wraps around to 0 and X increments to address the next LSB handbook, full pagewidth 0 MSB 1 LSB 2 Y address 3 MSB LSB 4 5 icon data 0 X address MGS469 127 MSB Fig.5 RAM format and addressing. handbook, full pagewidth 0 5 1 6 2 638 3 639 4 0 0 1 0 1 2 Y address 3 4 5 icon data X address 127 MGS470 Fig.6 Sequence of writing data bytes into RAM with vertical addressing (V = 1). 2000 Feb 11 11 Philips Semiconductors Product specification 34 × 128 pixel matrix driver PCF8531 handbook, full pagewidth 0 1 2 127 0 128 129 130 255 1 256 257 258 383 2 384 385 386 511 3 512 513 514 639 4 0 1 0 Y address 5 icon data X address 127 MGS471 Fig.7 Sequence of writing data bytes into RAM with horizontal addressing (V = 0). 8.18 Instructions 8.18.1 RESET Only two PCF8531 registers, the Instruction Register (IR) and the Data Register (DR) can be directly controlled by the MPU. Before internal operation, control information is stored temporarily in these registers to allow interfacing to various types of MPUs which operate at different speeds or to allow interfacing to peripheral control ICs. The PCF8531 operation is controlled by the instructions given in Table 1. Details are explained in subsequent sections. After reset or internal Power-on reset (depending on application), the LCD driver will be set to the following state: Instructions are of four types: • Multiplex rate M[1:0] = 0 (Mux rate 1 : 17) 1. Those that define PCF8531 functions such as display configuration, etc. • Temperature control mode TC[2:0] = 0 • Power-down mode (PD = 1) • Horizontal addressing (V = 0) • Display blank (D = 0; E = 0), no icon mode (IM = 0) • Address counter X[6:0] = 0; Y[2:0] = 0 • Bias system BS[2:0] = 0 2. Those that set internal RAM addresses • HV-gen control, HVE = 0 the HV generator is switched off, PRS = 0 and S[1:0] = 0 3. Those that perform data transfer with internal RAM • VLCD = 0 V 4. Others. • RAM data is undefined In normal use, category 3 instructions are used most frequently. Automatic incrementing by 1 of internal RAM addresses after each data write reduces the MPU program load. • Command page definition H[1:0] = 0. 2000 Feb 11 12 Philips Semiconductors Product specification 34 × 128 pixel matrix driver 8.18.2 PCF8531 8.18.4 FUNCTION SET 8.18.2.1 PD SET X ADDRESS The X address points to the columns. The range of X is 0 to 127 (7FH). When PD = 1, the Power-down mode of the LCD driver is active: 8.18.5 • All LCD outputs at VSS (display off) SET MULTIPLEX RATE • Power-on reset detection active, oscillator off M[1:0] selects the multiplex rate (see Table 8). • VLCD can be disconnected 8.18.6 • I2C-bus is operational, commands can be executed Bits D and E select the display mode (see Table 6). Bit IM sets the display to icon mode. • RAM contents not cleared; RAM data can be written • Register settings remain unchanged. 8.18.2.2 DISPLAY CONTROL (D, E AND IM) 8.18.7 V SET BIAS SYSTEM Different multiplex rates require different bias settings. These are programmed by BS[2:0], which sets the binary number n. The optimum value for n is given by When V = 0 the horizontal addressing is selected. The data is written into the DDRAM as shown in Fig.7. When V = 1 the vertical addressing is selected. The data is written into the DDRAM as shown in Fig.6. Icon data is written independently of V when Y address is 5. n = Mux rate – 3 Supported values of n are given in Table 2. Table 3 shows the intermediate bias voltages. SET Y ADDRESS 8.18.3 Bits Y2, Y1 and Y0 define the Y address vector of the display RAM. Table 1 Y address Y2 Y1 Y0 BANK 0 0 0 0 0 0 1 1 0 1 0 2 0 1 1 3 1 0 0 4 1 0 1 5 (icons) Table 2 Programming the required bias system BS[2] 0 BS[1] 0 BS[0] 0 n 7 1⁄ 1⁄ 0 0 1 6 0 1 0 5 0 1 1 4 1 0 0 3 1 0 1 2 1 1 0 1 1 1 1 0 2000 Feb 11 BIAS SYSTEM 11 10 1⁄ 9 1⁄ 8 1⁄ 7 1⁄ 6 1⁄ 5 1⁄ 4 13 COMMENT recommended for 1 : 34 recommended for 1 : 26 recommended for 1 : 17 recommended for icon mode Philips Semiconductors Product specification 34 × 128 pixel matrix driver 8.18.8 Table 3 The generated voltage is dependent on the temperature, programmed Temperature Coefficient (TC) and the programmed voltage at reference temperature (Tcut). VLCD = VLCD (Tcut) × [1 + TC × (T − Tcut)]. LCD BIAS VOLTAGE Intermediate LCD bias voltages BIAS VOLTAGES SYMBOL V1 VLCD V2 n+3 ------------- × V LCD n+4 V3 n+2 ------------- × V LCD n+4 V4 2 ------------- × V LCD n+4 V5 1 ------------- × V LCD n+4 V6 8.18.9 PCF8531 VSS EXAMPLE FOR 1⁄ BIAS 7 The parameter values are given in Table 4. Two overlapping VLCD ranges can be selected via the command ‘HV-gen control’ (see Table 4 and Fig.8). The maximum voltage that can be generated depends on the VDD2 and VDD3 voltages and the display load current. For Mux 1 : 34, the optimum operating voltage of the liquid can be calculated as: VLCD 6⁄ 7 × VLCD 5⁄ 7 × VLCD 2⁄ 1⁄ 7 7 1 + 34 V LCD = --------------------------------------- × V th = 5.30 × V th 1 2 × 1 – ---------- 34 × VLCD Where Vth is the threshold voltage of the liquid crystal material used. × VLCD The practical value for VOP is determined by equating Voff(rms) with a defined LCD threshold voltage (Vth), typically when the LCD exhibits approximately 10% contrast. VSS SET VOP VALUE: As the programming range for the internally generated VLCD allows values above the maximum allowed VLCD, the user has to ensure, while setting the VOP register and selecting the temperature compensation, that the VLCD limit of maximum 9 V will never be exceeded under all conditions and including all tolerances. The operating voltage VLCD can be set by software. The voltage at reference temperature [VLCD (T = Tcut)] can be calculated as: VLCD (Tcut) = (a + VOP × b). Table 4 Parameter values for the HV generator programming VALUE SYMBOL UNIT PRS = 0 PRS = 1 27 27 °C a 2.94 6.75 V b 0.03 0.03 V 2.94 to 6.75 6.75 to 10.56 V Tcut Programming range 2000 Feb 11 14 Philips Semiconductors Product specification 34 × 128 pixel matrix driver PCF8531 handbook, full pagewidth VLCD b a 00 01 02 03 04 05 06 . . . 7D 7E 7F 00 01 02 03 04 LOW 05 06 . . . 5F 6F 7F HIGH MGL935 VOP[6:0] (programmed) [00H to 7FH] programme range LOW and HIGH. Fig.8 VOP programming of PCF8531. 8.18.10 VOLTAGE MULTIPLIER CONTROL S[1:0] The PCF8531 incorporates a software configurable voltage multiplier. After reset (internal or external), the voltage multiplier is set to 2 × VDD2. The voltage multiplier factors are set via the command ‘HV-gen configuration’ (see Tables 4, 5 and 6). handbook, halfpage MGS473 VLCD 8.18.11 TEMPERATURE COMPENSATION Due to the temperature dependency of the liquid crystal’s viscosity, the LCD controlling voltage VLCD should usually be increased at lower temperatures to maintain optimum contrast. Figure 9 shows VLCD for high multiplex rates. Linear temperature compensation is supported in the PCF8531. The temperature coefficient of VLCD can be selected from eight values by setting bits TC[2:0] (see Tables 4, 5 and 6). 0 °C Fig.9 2000 Feb 11 15 VLCD as a function of liquid crystal temperature. T Philips Semiconductors Product specification 34 × 128 pixel matrix driver Table 5 PCF8531 Instruction set INSTRUCTION I2C-BUS COMMAND(1) RS R/W I2C-BUS COMMAND BYTE DESCRIPTION DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 H1 and H0 = don’t care (H independent command page) NOP 0 0 0 0 0 0 0 0 0 0 no operation Write data 1 0 D7 D6 D5 D4 D3 D2 D1 D0 write data to display RAM Set default H[1:0] 0 0 0 0 0 0 0 0 0 1 select H[1:0] = 0 H1 = 0 and H0 = 0 (function and RAM command page) Instruction set 0 0 0 0 0 0 1 0 H1 H0 select command page Function set 0 0 0 0 1 0 0 PD V 0 power-down control; entry mode Set Y address of RAM 0 0 0 1 0 0 0 Y2 Y1 Y0 set Y address of RAM; 0≤Y≤5 Set X address of RAM 0 0 1 X6 X5 X4 X3 X2 X1 X0 set X address part of RAM; 0 ≤ X ≤ 127 select multiplex rate H1 = 0 and H0 = 1 (display setting command page) Multiplex rate 0 0 0 0 0 0 0 1 M1 M0 Display control 0 0 0 0 0 0 1 D IM E Bias system 0 0 0 0 0 1 0 BS2 BS1 set display configuration BS0 set Bias System (BSx) H1 = 1 and H0 = 0 (HV-gen command page) PRS HVE set VLCD programming range HV-gen control 0 0 0 0 0 0 0 1 HV-gen configuration 0 0 0 0 0 0 1 0 S1 S0 Temperature control 0 0 0 0 1 0 0 TC2 TC1 TC0 set temperature coefficient Test modes 0 0 0 1 X X X X X VLCD control 0 0 1 do not use (reserved for test) VOP6 VOP5 VOP4 VOP3 VOP2 VOP1 VOP0 set VLCD register 0 ≤ VOP ≤ 127 Note 1. R/W is set in the slave address byte; Co and RS are set in the control byte. 2000 Feb 11 X set voltage multiplication factor 16 Philips Semiconductors Product specification 34 × 128 pixel matrix driver Table 6 PCF8531 Explanations for symbols in Table 5 BIT 0 1 PD chip is active chip is in Power-down mode V horizontal addressing vertical addressing IM normal mode; full display + icons icon mode; only icons are displayed H[1:0](1) see Table 7 D and E see Table 7 HVE voltage multiplier disabled voltage multiplier enabled PRS VLCD programming range LOW VLCD programming range HIGH TC[2:0] see Table 7 S[1:0] see Table 7 Note 1. The H-bits identify the command page (use set default H[1:0] command to set H[1:0] = 0. Table 7 BITS Description of bits H, D and E, TC and S VALUE Table 8 DESCRIPTION Multiplex rates MUX RATE M1 M0 Command page (H) 1 : 17 0 0 H[1:0] 00 function and RAM command page 1 : 26 1 0 01 display setting command page 1 : 34 0 1 10 HV-gen command page Display modes (D, E) D and E 00 display blank 10 normal mode 01 all display segments 11 inverse video mode Temperature coefficient (TC) TC[2:0] 000 temperature coefficient 0 001 temperature coefficient 1 010 temperature coefficient 2 011 temperature coefficient 3 100 temperature coefficient 4 101 temperature coefficient 5 110 temperature coefficient 6 111 temperature coefficient 7 Voltage multiplier factor (S) S[1:0] 00 2 × voltage multiplier 01 3 × voltage multiplier 10 4 × voltage multiplier 11 5 × voltage multiplier 2000 Feb 11 17 Philips Semiconductors Product specification 34 × 128 pixel matrix driver 9 PCF8531 • Slave: the device addressed by a master I2C-BUS INTERFACE 9.1 • Multi-Master: more than one master can attempt to control the bus at the same time without corrupting the message Characteristics of the I2C-bus The I2C-bus is for bi-directional, two-line communication between different ICs or modules. The two lines are a Serial Data line (SDA) and a Serial Clock line (SCL). Both lines must be connected to a positive supply via a pull-up resistor. Data transfer may be initiated only when the bus is not busy. 9.1.1 • Arbitration: procedure to ensure that, if more than one master simultaneously tries to control the bus, only one is allowed to do so and the message is not corrupted • Synchronization: procedure to synchronize the clock signals of two or more devices. BIT TRANSFER 9.1.4 One data bit is transferred during each clock pulse. The data on the SDA line must remain stable during the HIGH period of the clock pulse as changes in the data line at this time will be interpreted as a control signal (see Fig.10). 9.1.2 Acknowledge on the I2C-bus is illustrated in Fig.13. Each byte of eight bits is followed by an acknowledge bit. The acknowledge bit is a HIGH signal put on the bus by the transmitter, during which time the master generates an extra acknowledge related clock pulse. A slave receiver that is addressed must generate an acknowledge after the reception of each byte. START AND STOP CONDITIONS Both data and clock lines remain HIGH when the bus is not busy. A HIGH-to-LOW transition of the data line, while the clock is HIGH is defined as the START condition (S). A LOW-to-HIGH transition of the data line while the clock is HIGH is defined as the STOP condition (P). The START and STOP conditions are illustrated in Fig.11. 9.1.3 ACKNOWLEDGE Also, a master receiver must generate an acknowledge after the reception of each byte that has been clocked out of the slave transmitter. The device that acknowledges must pull-down the SDA line during the acknowledge clock pulse so that the SDA line is stable LOW during the HIGH period of the acknowledge- related clock pulse (set-up and hold times must be taken into consideration). A master receiver must signal an “end of data” to the transmitter by not generating an acknowledge on the last byte that has been clocked out of the slave. In this event, the transmitter must leave the data line HIGH to enable the master to generate a STOP condition. SYSTEM CONFIGURATION The system configuration is illustrated in Fig.12 • Transmitter: the device that sends the data to the bus • Receiver: the device that receives the data from the bus • Master: the device that initiates a transfer, generates clock signals and terminates a transfer handbook, full pagewidth SDA SCL data line stable; data valid change of data allowed Fig.10 Bit transfer. 2000 Feb 11 18 MBC621 Philips Semiconductors Product specification 34 × 128 pixel matrix driver PCF8531 handbook, full pagewidth SDA SDA SCL SCL S P START condition STOP condition MBC622 Fig.11 Definition of START and STOP conditions. MASTER TRANSMITTER/ RECEIVER SLAVE TRANSMITTER/ RECEIVER SLAVE RECEIVER MASTER TRANSMITTER/ RECEIVER MASTER TRANSMITTER SDA SCL MGA807 Fig.12 System configuration. handbook, full pagewidth DATA OUTPUT BY TRANSMITTER not acknowledge DATA OUTPUT BY RECEIVER acknowledge SCL FROM MASTER 1 2 8 9 S clock pulse for acknowledgement START condition MBC602 Fig.13 Acknowledge on the I2C-bus. 2000 Feb 11 19 Philips Semiconductors Product specification 34 × 128 pixel matrix driver 9.2 PCF8531 The data pointer is automatically updated and the data is directed to the intended PCF8531 device. If the RS bit of the last control byte was set to logic 0, these command bytes will be decoded and the setting of the device will be changed according to the received commands. The acknowledgement after each byte is made only by the addressed PCF8531. At the end of the transmission, the I2C-bus master issues a STOP condition (P). I2C-bus protocol This driver does not support ‘read’. The PCF8531 is a slave receiver. Therefore, it only responds when R/W = 0 in the slave address byte. Before any data is transmitted on the I2C-bus, the device that should respond is addressed first. Two 7-bit slave addresses (0111100 and 0111101) are reserved for the PCF8531. The least significant bit of the slave address is set by connecting the input SA0 to either logic 0 (VSS) or logic 1 (VDD). 9.3 Command decoder • Pairs of bytes; information in the second byte, the first byte determines whether information is display or instruction data The I2C-bus protocol is illustrated in Fig.14. The sequence is initiated with a START condition (S) from the I2C-bus master, and is followed by the slave address. All slaves with the corresponding address acknowledge in parallel, all others ignore the I2C-bus transfer. After acknowledgement, one or more command words follow, which define the status of the addressed slaves. A command word consists of a control byte, which defines Co and RS, plus a data byte (see Fig.14 and Table 1). • Stream of information bytes after Co = 0; display or instruction data, depending on last RS (Register Selection). The command decoder identifies command words that arrive on the I2C-bus. The most significant bit of a control byte is the continuation bit Co. If this bit is logic 1, it indicates that only one data byte (either command or RAM data) will follow. If this bit is logic 0, it indicates that a series of data bytes (either command or RAM data) may follow. The DB6 bit of a control byte is the RAM data/command bit RS. When this bit is at logic 1, it indicates that another RAM data byte will be transferred next. If the bit is at logic 0, it indicates that another command byte will be transferred next. The last control byte is tagged with a cleared most significant bit, the continuation bit Co. The control and data bytes are also acknowledged by all addressed slaves on the bus. After the last control byte, depending on the RS bit setting, either a series of display data bytes or command data bytes may follow. If the RS bit was set to logic 1, these display bytes are stored in the display RAM at the address specified by the data pointer. slave address handbook, full pagewidth S 0 1 1 1 1 control byte 0 SA0 R/W A Co RS X X X X X X MGS474 Fig.14 Slave address and control byte. 2000 Feb 11 20 Philips Semiconductors Product specification 34 × 128 pixel matrix driver acknowledge from PCF8531 handbook, full pagewidth S S 0 1 1 1 1 0 A 0 A 1 RS 0 slave address PCF8531 acknowledge from PCF8531 control byte A acknowledge from PCF8531 data byte 2n ≥ 0 bytes R/W Co A 0 RS Co acknowledge from PCF8531 control byte A acknowledge from PCF8531 data byte A P n ≥ 0 bytes MSB . . . . . . . . . . . LSB 1 byte MGS475 Fig.15 Master transmits to slave receiver; write mode. 10 LIMITING VALUES In accordance with the Absolute Maximum Rating System (IEC 134); note 1. SYMBOL PARAMETER MIN. MAX. UNIT VDD1 logic supply voltage −0.5 +5.5 V VDD2, VDD3 multiplier supply voltage −0.5 +4.5 V IDD supply current −50 +50 mA VLCD LCD supply voltage −0.5 +9.0 V ILCD LCD supply current −50 +50 mA ISS negative supply current −50 +50 mA VI/VO input/output voltage (any input/output) −0.5 VDD + 0.5 V II DC input current −10 +10 mA IO DC output current −10 +10 mA Ptot total power dissipation per package − 300 mW P/out power dissipation per output − 30 mW Tstg storage temperature −65 +150 °C Tj junction temperature − 150 °C Note 1. Parameters are valid over the operating temperature range unless otherwise specified. All voltages referenced to VSS unless otherwise noted. 11 HANDLING Inputs and outputs are protected against electrostatic discharge in normal handling. However, to be totally safe, it is recommended to take normal precautions appropriate to handling MOS devices (see “Handling MOS Devices”). 2000 Feb 11 21 Philips Semiconductors Product specification 34 × 128 pixel matrix driver PCF8531 12 DC CHARACTERISTICS VDD1 = 1.8 (1.9) to 5.5 V; VDD2 and VDD3 = 2.5 to 4.5 V; VSS1,2 = 0 V; VDD1 to VDD3 ≤ VLCD ≤ 9.0 V; Tamb = −40 to +85 °C; unless otherwise specified. SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT Supplies VLCD VDD1 LCD supply voltage note 1 4.0 − 9.0 V icon mode; note 1 3.0 − 9.0 V 1.9 − 5.5 V Tamb ≥ −25 °C 1.8 − 5.5 V logic supply voltage VDD2, VDD3 multiplier supply voltage LCD voltage internally generated 2.5 − 4.5 V IDD supply current Power-down mode; internal VLCD − 2 10 µA normal mode; internal VLCD; notes 2 and 3 − 170 350 µA normal mode; external VLCD; note 2 − 10 50 µA normal mode; external VLCD; notes 2 and 4 − 25 100 µA icon mode; external VLCD; notes 2 and 5 − 15 70 µA note 6 0.9 1.2 1.6 V VSS − 0.3VDD V ILCD VPOR LCD input current Power-on reset level Logic VIL LOW-level input voltage VIH HIGH-level input voltage VDD V IOL LOW-level output current (SDA) VOL = 0.4 V; VDD = 5 V 3.0 − − mA ILI input leakage current VI = VDD or VSS −1 − +1 µA 0.7VDD − Column and row outputs Ro(col) column output resistance C0 to C127 note 7 − 12 20 kΩ Ro(row) row output resistance R0 to R33 note 7 − 12 20 kΩ Vbias(col) bias tolerance C0 to C127 −100 0 +100 mV Vbias(row) bias tolerance R0 to R33 −100 0 +100 mV 2000 Feb 11 22 Philips Semiconductors Product specification 34 × 128 pixel matrix driver SYMBOL PCF8531 PARAMETER CONDITIONS MIN. TYP. MAX. UNIT VLCD generation VLCD(tol) LCD voltage tolerance, internal VLCD TC1 to TC7; note 8 − − ±3.9 % TC0 LCD voltage temperature coefficient 0 Tamb = −20 to +70 °C − 0 − %/°C TC1 LCD voltage temperature coefficient 1 Tamb = −20 to +70 °C − −0.026 − %/°C TC2 LCD voltage temperature coefficient 2 Tamb = −20 to +70 °C − −0.039 − %/°C TC3 LCD voltage temperature coefficient 3 Tamb = −20 to +70 °C − −0.052 − %/°C TC4 LCD voltage temperature coefficient 4 Tamb = −20 to +70 °C − −0.078 − %/°C TC5 LCD voltage temperature coefficient 5 Tamb = −20 to +70 °C − −0.13 − %/°C TC6 LCD voltage temperature coefficient 6 Tamb = −20 to +70 °C − −0.19 − %/°C TC7 LCD voltage temperature coefficient 7 Tamb = −20 to +70 °C − −0.26 − %/°C Tcut cut point temperature − 27 − °C Notes 1. As the programming range for the internally generated VLCD allows values above the maximum allowed VLCD, the user has to ensure, while setting the VOP register and selecting the temperature compensation, that the VLCD limit of maximum 9 V will never be exceeded under all conditions and including all tolerances. 2. LCD outputs are open circuit, inputs at VDD or VSS; bus inactive. 3. VDD1 to VDD3 = 2.85 V; VLCD = 7.0 V; voltage multiplier = 3 × VDD; fOSC = 34 kHz. 4. VDD1 to VDD3 = 2.75 V; VLCD = 9.0 V; fOSC = 34 kHz. 5. VDD1 to VDD3 = 2.75 V; VLCD = 3.5 V; fOSC = 34 kHz. 6. Resets all logic when VDD1 < VPOR. 7. ILOAD ≤ 50 µA; outputs tested one at a time. 8. VLCD ≤ 7.7 V. 2000 Feb 11 23 Philips Semiconductors Product specification 34 × 128 pixel matrix driver PCF8531 13 AC CHARACTERISTICS VDD1 = 1.8 to 5.5 V; VDD2 and VDD3 = 2.5 to 4.5 V; VSS1 and VSS2 = 0 V; VDD1 to VDD3 ≤ VLCD ≤ 9.0 V; Tamb = −40 to +85 °C; unless otherwise specified. SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT fframe LCD frame frequency (internal clock) VDD = 3.0 V; note 1 40 66 135 Hz fOSC oscillator frequency (not available at any pin) 20 34 65 kHz fclk(ext) external clock frequency 20 − 65 kHz tW(RESL) reset LOW pulse width 300 − − ns tSU;RESL reset LOW pulse set-up time after Power-on − − 30 µs note 2 Serial-bus interface; note 3 fSCL SCL clock frequency 0 − 400 kHz tSCLL SCL clock LOW period 1.3 − − µs tSCLH SCL clock HIGH period 0.6 − − µs tSU;DAT data set-up time 100 − − ns tHD;DAT data hold time 0 − 0.9 µs tr SCL, SDA rise time note 4 20 + 0.1Cb − 300 ns tf SCL, SDA fall time note 4 20 + 0.1Cb − 300 ns Cb capacitive load represented by each bus line − − 400 pF tSU;STA set-up time for a repeated START condition 0.6 − − µs tHD;STA start condition hold time 0.6 − − µs tSU;STO set-up time for STOP condition 0.6 − − µs tSW tolerable spike width on bus − − 50 ns tBUF bus free time between a STOP and START condition 1.3 − − µs Notes 1. fframe = fclk(ext)/480; fOSC/480. 2. For tW(RESL) > 3 ns a reset may be generated. 3. All timing values are valid within the operating supply voltage and ambient temperature range and are referenced to VIL and VIH with an input voltage swing of VSS to VDD. 4. Cb = total capacitance of one bus line in pF. handbook, full pagewidth VDD RES VIL t SU; RESL Fig.16 Reset timing. 2000 Feb 11 24 t W(RESL) MGS476 Philips Semiconductors Product specification 34 × 128 pixel matrix driver PCF8531 ndbook, full pagewidth SDA t BUF tf t LOW SCL t HD;STA t HD;DAT tr t HIGH t SU;DAT SDA t SU;STA MGA728 t SU;STO Fig.17 I2C-bus timing diagram. MGS477 MGS478 400 400 handbook, halfpage handbook, halfpage IDD (µA) IDD (µA) 300 2× 5× 300 4× 3× VLCD = 9 V 200 200 7.5 V 4V 100 2 3 100 4 5 VDD2 and VDD3 (V) 4 6 8 10 VLCD (V) VDD1 = 2 V; 4 × voltage multiplier; Tamb = 27 °C; TC = 0; BS = 100; no VLCD load. VDD1 = 1.8 V; VDD2 and VDD3 = 2.6 V; Tamb = 27 °C; fOSC = 34 kHz; no VLCD load. Fig.18 IDD, internal VLCD generation. 2000 Feb 11 2 Fig.19 IDD for different multiplication factors. 25 Philips Semiconductors Product specification 34 × 128 pixel matrix driver PCF8531 MGS480 MGS479 9 30 handbook, halfpage handbook, halfpage VLCD I (µA) (V) 20 8 ILCD TC0 TC1 10 7 IDD TC6 TC7 0 6 −50 0 50 T (°C) 2 100 4 6 8 10 VLCD (V) VDD1 = 1.8 V; VDD2 and VDD3 = 2.5 V; external VLCD; Tamb = 27 °C; TC = 0; BS = 100; no VLCD load. VLCD = 7.5 V; VDD1 to VDD3 = 2.7 V; Tamb = 27 °C; no VLCD load. Fig.20 Temperature coefficient. Fig.21 IDD and ILCD with external VLCD. MGS481 30 MGS482 86 handbook, halfpage handbook, halfpage I DD (µA) I (µA) I LCD 84 20 82 10 I DD 80 78 0 0 20 40 60 f (kHz) 80 3 3.4 3.6 3.8 4 VLCD (V) VDD1 = 1.8 V; VDD1 = 2.5 V; 2 × voltage multiplier; Tamb = 27 °C; TC = 0; BS = 111; no VLCD load. VDD1 = 2.5 V; VDD2 and VDD3 = 2.5 V; external VLCD; Tamb = 27 °C; TC = 0; BS = 100; no VLCD load. Fig.22 IDD and ILCD dependent from frequency. 2000 Feb 11 3.2 Fig.23 Internal VLCD, icon mode. 26 Philips Semiconductors Product specification 34 × 128 pixel matrix driver PCF8531 14 APPLICATION INFORMATION Table 9 Programming example for PCF8531 SERIAL BUS BYTE STEP DISPLAY OPERATION DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 1 0 1 1 1 1 0 SA0 0 start; slave address; R/W = 0 2 1 0 0 0 0 0 0 0 control byte; Co = 1; RS = 0 3 0 0 0 0 0 0 0 1 H[1:0] independent command; select function and RAM command page (H[1:0] = 00) 4 1 0 0 0 0 0 0 0 control byte; Co = 1; RS = 0 5 0 0 1 0 0 0 1 0 function and RAM command page PD = 0 and V = 1 6 1 0 0 0 0 0 0 0 control byte; Co = 1; RS = 0 7 0 0 0 0 1 0 0 1 function and RAM command page select display setting command page H[1:0] = 01 8 1 0 0 0 0 0 0 0 control byte; Co = 1; RS = 0 9 0 0 0 0 1 1 0 0 display setting command page; set normal mode (D = 1; IM = 0 and E = 0) 10 1 0 0 0 0 0 0 0 control byte; Co = 1; RS = 0 11 0 0 0 0 0 1 0 1 select Mux rate 1 : 34 12 1 0 0 0 0 0 0 0 control byte; Co = 1; RS = 0 13 0 0 0 0 0 0 0 1 H[2:0] independent command; select function and RAM command page H[1:0] = 00 14 1 0 0 0 0 0 0 0 control byte; Co = 1; RS = 0 15 0 0 0 0 1 0 1 0 function and RAM command page; select HV-gen command page H[1:0] = 10 16 1 0 0 0 0 0 0 0 control byte; Co = 1; RS = 0 17 0 0 0 0 1 0 1 1 HV-gen command page; select voltage multiplication factor 5 S[1:0] = 11 18 1 0 0 0 0 0 0 0 control byte; Co = 1; RS = 0 19 0 0 1 0 0 0 1 0 HV-gen command page; select temperature coefficient 2 TC[2:0] = 010 20 1 0 0 0 0 0 0 0 control byte; Co = 1; RS = 0 2000 Feb 11 27 Philips Semiconductors Product specification 34 × 128 pixel matrix driver PCF8531 SERIAL BUS BYTE STEP DISPLAY OPERATION DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 21 0 0 0 0 0 1 1 1 HV-gen command page; select high VLCD programming range (PRS = 1); voltage multiplier off (HVE = 1) 22 1 0 0 0 0 0 0 0 control byte; Co = 1; RS = 0 23 1 0 1 0 0 0 0 0 HV-gen command page; set VLCD = 7.71 V; VOP[6:0] = 0100000 24 0 1 0 0 0 0 0 0 control byte; Co = 0; RS = 1 25 0 0 0 1 1 1 1 1 data write; Y and X are initialized to 0 by default, so they are not set here MGS405 26 0 0 0 0 0 1 0 1 data write MGS406 27 0 0 0 0 0 1 1 1 data write MGS407 28 0 0 0 0 0 0 0 0 data write MGS407 29 0 0 0 1 1 1 1 1 data write MGS409 30 0 0 0 0 0 1 0 0 data write MGS410 2000 Feb 11 28 Philips Semiconductors Product specification 34 × 128 pixel matrix driver PCF8531 SERIAL BUS BYTE STEP 31 DISPLAY DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 0 1 1 1 1 1 OPERATION data write; last data and stop transmission MGS411 32 0 1 1 1 1 0 SA0 0 repeated start; slave address; R/W = 0 MGS411 33 1 0 0 0 0 0 0 0 control byte; Co = 1; RS = 0 MGS411 34 0 0 0 0 0 0 0 1 H[1:0] independent command; select function and RAM command page H[1:0] = 00 MGS411 35 1 0 0 0 0 0 0 0 control byte; Co = 1; RS = 0 MGS411 36 0 0 0 0 1 0 0 1 function and RAM command page; select display setting command page H[1:0] = 01 MGS411 37 1 0 0 0 0 0 0 0 control byte; Co = 1; RS = 0 MGS411 38 0 0 0 0 0 0 0 1 H[1:0] independent command; select function and RAM command page H[1:0] = 00 MGS411 2000 Feb 11 29 Philips Semiconductors Product specification 34 × 128 pixel matrix driver PCF8531 SERIAL BUS BYTE STEP 39 DISPLAY DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 1 0 0 0 0 0 0 0 OPERATION control byte; Co = 1; RS = 0 MGS411 40 0 0 0 0 1 1 0 1 display control; set inverse video mode (D = 1; E = 1 and IM = 0) MGS412 41 1 0 0 0 0 0 0 0 control byte; Co = 1; RS = 0 MGS412 42 1 0 0 0 0 0 0 0 set X address of RAM; set address to ‘0000000’ MGS412 43 0 1 0 0 0 0 0 0 control byte; Co = 0; RS = 1 MGS412 44 0 0 0 0 0 0 0 0 data write MGS414 The pinning of the PCF8531 is optimized for single plane wiring e.g. for chip-on-glass display modules. Display size: 34 × 128 pixels. 2000 Feb 11 30 Philips Semiconductors Product specification 34 × 128 pixel matrix driver PCF8531 VLCD handbook, full pagewidth VDD1 to VDD3 VDD(I2C) 128 column drivers 34 row drivers VSS RES LCD PANEL ENR SA0 SCL SDA Rpu PCF8531 SDACK Rpu HOST MICROPROCESSOR/ MICROCONTROLLER VSS1, VSS2 RES SCL SDA VSS1, VSS2 MGS483 Fig.24 Typical system configuration. The host microprocessor/microcontroller and the PCF8531 are both connected to the I2C-bus. The SDA and SCL lines must be connected to the positive power supply via pull-up resistors. The internal oscillator requires no external components. The appropriate intermediate biasing voltage for the multiplexed LCD waveforms are generated on-chip. The only other connections required to complete the system are to the power supplies (VDD, VSS and VLCD) and suitable capacitors for decoupling VLCD and VDD. 2000 Feb 11 31 Philips Semiconductors Product specification 34 × 128 pixel matrix driver PCF8531 handbook, full pagewidth DISPLAY 34 × 128 PIXELS 17 128 17 PCF8531 R I/O Rsupply Cext 3 VSS1 I/O VDD1 VSS2 VLCD MGS484 to VDD3 Fig.25 Chip-on-glass application. The required minimum values for the external capacitors in an application with the PCF8531 are as follows: • Cext = 100 nF for VLCD and VSS1 and VSS2, and Cext = 470 nF for VDD1 to VDD3 and VSS1 and VSS2 • Higher capacitor values are recommended for ripple reduction • For COG applications, the recommended ITO track resistance is to be minimized for the I/O and supply connections. Optimized values for these tracks are below 50 Ω for the supply (Rsupply) and below 100 Ω for the I/O connections (RI/O). • To reduce the sensitivity of the reset to ESD/EMC disturbances for a chip-on-glass application, it is strongly recommended to implement a series input resistance in the reset line (recommended minimum value 8 kΩ) on the glass (ITO). If the reset input is not used, it should be connected to VDD1 using a short connection. 2000 Feb 11 32 Philips Semiconductors Product specification 34 × 128 pixel matrix driver PCF8531 15 BONDING PAD LOCATIONS SYMBOL Table 10 Bonding pad locations All x and y coordinates are referenced to the centre of the chip (dimensions in µm; see Fig.28). SYMBOL PAD x y VDD2 38 +1069.5 +823.4 VDD2 39 +999.5 +823.4 VDD2 40 +929.5 +823.4 VDD2 41 +859.5 +823.4 PAD x y dummy 1 +5973.6 −821.7 VDD2 42 +789.5 +823.4 dummy 2 +5969.5 +823.4 VDD1 43 +649.5 +823.4 dummy 3 +5899.5 +823.4 VDD1 44 +579.5 +823.4 dummy 4 +5829.5 +823.4 VDD1 45 +509.5 +823.4 dummy 5 +5479.5 +823.4 VDD1 46 +439.5 +823.4 dummy 6 +5409.5 +823.4 VDD1 47 +369.5 +823.4 dummy 7 +5059.5 +823.4 VDD1 48 +299.5 +823.4 dummy 8 +4989.5 +823.4 VDD1 49 +229.5 +823.4 dummy 9 +4639.5 +823.4 SDA 50 +19.5 +823.4 dummy 10 +4569.5 +823.4 SDA 51 −50.5 +823.4 dummy 11 +4219.5 +823.4 SDACK 52 −400.5 +823.4 dummy 12 +4149.5 +823.4 dummy 53 −750.5 +823.4 dummy 13 +3799.5 +823.4 SA0 54 −820.5 +823.4 dummy 14 +3729.5 +823.4 ENR 55 −1100.5 +823.4 OSC 15 +3449.5 +823.4 T4 56 −1380.5 +823.4 VLCDSENSE 16 +3169.5 +823.4 VSS2 57 −1660.5 +823.4 VLCDOUT 17 +3099.5 +823.4 VSS2 58 −1730.5 +823.4 VLCDOUT 18 +3029.5 +823.4 VSS2 59 −1800.5 +823.4 VLCDOUT 19 +2959.5 +823.4 VSS2 60 −1870.5 +823.4 VLCDOUT 20 +2889.5 +823.4 VSS2 61 −1940.5 +823.4 VLCDOUT 21 +2819.5 +823.4 VSS2 62 −2010.5 +823.4 VLCDOUT 22 +2749.5 +823.4 VSS2 63 −2080.5 +823.4 VLCDOUT 23 +2679.5 +823.4 VSS1 64 −2220.5 +823.4 VLCDIN 24 +2539.5 +823.4 VSS1 65 −2290.5 +823.4 VLCDIN 25 +2469.5 +823.4 VSS1 66 −2360.5 +823.4 VLCDIN 26 +2399.5 +823.4 VSS1 67 −2430.5 +823.4 VLCDIN 27 +2329.5 +823.4 VSS1 68 −2500.5 +823.4 VLCDIN 28 +2259.5 +823.4 VSS1 69 −2570.5 +823.4 VLCDIN 29 +2189.5 +823.4 VSS1 70 −2640.5 +823.4 VLCDIN 30 +2119.5 +823.4 T3 71 −2780.5 +823.4 RES 31 +1979.5 +823.4 T1 72 −3060.5 +823.4 VDD3 32 +1699.5 +823.4 SCL 73 −3410.5 +823.4 VDD3 33 +1629.5 +823.4 SCL 74 −3480.5 +823.4 VDD3 34 +1559.5 +823.4 dummy 75 −3830.5 +823.4 VDD2 35 +1279.5 +823.4 dummy 76 −4180.5 +823.4 VDD2 36 +1209.5 +823.4 dummy 77 −4530.5 +823.4 VDD2 37 +1139.5 +823.4 T2 78 −4600.5 +823.4 2000 Feb 11 33 Philips Semiconductors Product specification 34 × 128 pixel matrix driver SYMBOL dummy PCF8531 PAD x y 79 −4880.5 +823.4 SYMBOL PAD x y C16 120 −3406.4 −821.7 dummy 80 −4950.5 +823.4 C17 121 −3336.4 −821.7 dummy 81 −5230.5 +823.4 C18 122 −3266.4 −821.7 dummy 82 −5300.5 +823.4 C19 123 −3196.4 −821.7 dummy 83 −5650.5 +823.4 C20 124 −3126.4 −821.7 dummy 84 −5720.5 +823.4 C21 125 −3056.4 −821.7 dummy 85 −5930.5 +823.4 C22 126 −2986.4 −821.7 dummy 86 −5926.4 −821.7 C23 127 −2916.4 −821.7 R0 87 −5786.4 −821.7 C24 128 −2846.4 −821.7 R2 88 −5716.4 −821.7 C25 129 −2776.4 −821.7 R4 89 −5646.4 −821.7 C26 130 −2706.4 −821.7 R6 90 −5576.4 −821.7 C27 131 −2636.4 −821.7 R8 91 −5506.4 −821.7 C28 132 −2566.4 −821.7 R10 92 −5436.4 −821.7 C29 133 −2496.4 −821.7 R12 93 −5366.4 −821.7 C30 134 −2426.4 −821.7 R14 94 −5296.4 −821.7 C31 135 −2356.4 −821.7 R16 95 −5226.4 −821.7 C32 136 −2216.4 −821.7 R18 96 −5156.4 −821.7 C33 137 −2146.4 −821.7 R20 97 −5086.4 −821.7 C34 138 −2076.4 −821.7 R22 98 −5016.4 −821.7 C35 139 −2006.4 −821.7 R24 99 −4946.4 −821.7 C36 140 −1936.4 −821.7 R26 100 −4876.4 −821.7 C37 141 −1866.4 −821.7 R28 101 −4806.4 −821.7 C38 142 −1796.4 −821.7 R30 102 −4736.4 −821.7 C39 143 −1726.4 −821.7 R32 103 −4666.4 −821.7 C40 144 −1656.4 −821.7 C0 104 −4526.4 −821.7 C41 145 −1586.4 −821.7 C1 105 −4456.4 −821.7 C42 146 −1516.4 −821.7 C2 106 −4386.4 −821.7 C43 147 −1446.4 −821.7 C3 107 −4316.4 −821.7 C44 148 −1376.4 −821.7 C4 108 −4246.4 −821.7 C45 149 −1306.4 −821.7 C5 109 −4176.4 −821.7 C46 150 −1236.4 −821.7 C6 110 −4106.4 −821.7 C47 151 −1166.4 −821.7 C7 111 −4036.4 −821.7 C48 152 −1096.4 −821.7 C8 112 −3966.4 −821.7 C49 153 −1026.4 −821.7 C9 113 −3896.4 −821.7 C50 154 −956.4 −821.7 C10 114 −3826.4 −821.7 C51 155 −886.4 −821.7 C11 115 −3756.4 −821.7 C52 156 −816.4 −821.7 C12 116 −3686.4 −821.7 C53 157 −746.4 −821.7 C13 117 −3616.4 −821.7 C54 158 −676.4 −821.7 C14 118 −3546.4 −821.7 C55 159 −606.4 −821.7 C15 119 −3476.4 −821.7 C56 160 −536.4 −821.7 2000 Feb 11 34 Philips Semiconductors Product specification 34 × 128 pixel matrix driver SYMBOL PCF8531 PAD x y C57 161 −466.4 −821.7 C58 162 −396.4 C59 163 −326.4 C60 164 C61 C62 PAD x y C98 202 +2543.6 −821.7 −821.7 C99 203 +2613.6 −821.7 −821.7 C100 204 +2683.6 −821.7 −256.4 −821.7 C101 205 +2753.6 −821.7 165 −186.4 −821.7 C102 206 +2823.6 −821.7 166 −116.4 −821.7 C103 207 +2893.6 −821.7 C63 167 −46.4 −821.7 C104 208 +2963.6 −821.7 C64 168 +93.6 −821.7 C105 209 +3033.6 −821.7 C65 169 +163.6 −821.7 C106 210 +3103.6 −821.7 C66 170 +233.6 −821.7 C107 211 +3173.6 −821.7 C67 171 +303.6 −821.7 C108 212 +3243.6 −821.7 C68 172 +373.6 −821.7 C109 213 +3313.6 −821.7 C69 173 +443.6 −821.7 C110 214 +3383.6 −821.7 C70 174 +513.6 −821.7 C111 215 +3453.6 −821.7 C71 175 +583.6 −821.7 C112 216 +3523.6 −821.7 C72 176 +653.6 −821.7 C113 217 +3593.6 −821.7 C73 177 +723.6 −821.7 C114 218 +3663.6 −821.7 C74 178 +793.6 −821.7 C115 219 +3733.6 −821.7 C75 179 +863.6 −821.7 C116 220 +3803.6 −821.7 C76 180 +933.6 −821.7 C117 221 +3873.6 −821.7 C77 181 +1003.6 −821.7 C118 222 +3943.6 −821.7 C78 182 +1073.6 −821.7 C119 223 +4013.6 −821.7 C79 183 +1143.6 −821.7 C120 224 +4083.6 −821.7 C80 184 +1213.6 −821.7 C121 225 +4153.6 −821.7 C81 185 +1283.6 −821.7 C122 226 +4223.6 −821.7 C82 186 +1353.6 −821.7 C123 227 +4293.6 −821.7 C83 187 +1423.6 −821.7 C124 228 +4363.6 −821.7 C84 188 +1493.6 −821.7 C125 229 +4433.6 −821.7 C85 189 +1563.6 −821.7 C126 230 +4503.6 −821.7 C86 190 +1633.6 −821.7 C127 231 +4573.6 −821.7 C87 191 +1703.6 −821.7 R33 232 +4713.6 −821.7 C88 192 +1773.6 −821.7 R31 233 +4783.6 −821.7 C89 193 +1843.6 −821.7 R29 234 +4853.6 −821.7 C90 194 +1913.6 −821.7 R27 235 +4923.6 −821.7 C91 195 +1983.6 −821.7 R25 236 +4993.6 −821.7 C92 196 +2053.6 −821.7 R23 237 +5063.6 −821.7 C93 197 +2123.6 −821.7 R21 238 +5133.6 −821.7 C94 198 +2193.6 −821.7 R19 239 +5203.6 −821.7 C95 199 +2263.6 −821.7 R17 240 +5343.6 −821.7 C96 200 +2403.6 −821.7 R15 241 +5413.6 −821.7 C97 201 +2473.6 −821.7 R13 242 +5483.6 −821.7 2000 Feb 11 SYMBOL 35 Philips Semiconductors Product specification 34 × 128 pixel matrix driver SYMBOL PCF8531 PAD x y R11 243 +5553.6 −821.7 R9 244 +5623.6 −821.7 R7 245 +5693.6 −821.7 R5 246 +5763.6 −821.7 R3 247 +5833.6 −821.7 R1 248 +5903.6 −821.7 handbook, halfpage 12.23 mm 1.96 mm PCF8531 Table 11 Bonding pads PAD SIZE UNIT Pad pitch min. 70 µm Pad size; Al 62 × 100 µm Bump dimensions 50 × 90 × 17.5 (±5) µm pitch y x µm Wafer thickness (excluding 381 bumps) MGS487 Table 12 Alignment marks MARKS x y C1 −5402.0 +823.1 C2 +5292.4 +823.4 F +5890.3 +401.9 Circle 1 −5543.0 +798.4 Circle 2 +5637.4 +798.4 Fig.26 Bonding pads. 100 µm handbook, full pagewidth 100 µm y center 80 µm 100 µm y center 100 µm y center x center x center x center circle C F MGS490 Fig.27 Shapes of recognition pattern. 2000 Feb 11 36 This text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here in _white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here inThis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader. white to force landscape pages to be ... VLCDOUT VLCDSENSE OSC VLCDIN RES VDD3 VDD2 VDD1 SDA SDACK SA0 ENR T4 VSS2 VSS1 T3 T1 SCL T2 Philips Semiconductors 34 × 128 pixel matrix driver handbook, full pagewidth 2000 Feb 11 PC8531-1 y R1 pad1 C127 R33 C63 C64 C31 C32 R32 C0 R0 . .. . .. ... . .. . .. . .. . .. . .. . .. . .. . .. . .. C95 C96 37 x 0,0 MGS486 Product specification Fig.28 Bonding pad location. PCF8531 The positioning of the bonding pads is not to scale. Philips Semiconductors Product specification 34 × 128 pixel matrix driver PCF8531 16 DEVICE PROTECTION DIAGRAM For all diagrams: the maximum forward current is 5 mA and the maximum reverse voltage is 5 V. handbook, full pagewidth PADS 43 to 49 PADS 35 to 42 PADS 32 to 34 VDD1 VDD2 VDD3 VSS1 VSS1 VSS1 VSS2 PADS 64 to 70 PADS 57 to 63 PADS 57 to 63 PADS 16, 24 to 30 PADS 17 to 23 VLCDIN (SUPPLY), VLCDSENSE VSS2 VSS1 VSS1 VLCDOUT VSS1 VLCDIN VDD1 PADS 73, 74, 50, 51, 52 PADS 87 to 248 SCL, SDA, SDACK VSS1 VSS1 VDD1 VDD1 PADS 15, 54, 71, 72, 56, 31, 55 PAD 78 T2 OSC, SA0, T3, T1, T4, RES, ENR VSS1 MGS485 Fig.29 Device protection diagrams. 2000 Feb 11 38 VSS1 Philips Semiconductors Product specification 34 × 128 pixel matrix driver PCF8531 17 TRAY INFORMATION x handbook, full pagewidth A C y D B F E MGS488 The dimensions are given in Table 13. Fig.30 Tray details. Table 13 Dimensions DIM. handbook, halfpage PC8531-1 MGS489 The orientation of the IC in a pocket is indicated by the position of the IC type name on the die surface with respect to the chamfer on the upper left corner of the tray. Refer to the bonding pad location diagram for the orientating and position of the type name on the die surface. Fig.31 Tray alignment. 2000 Feb 11 39 DESCRIPTION VALUE A pocket pitch; x direction 13.72 mm B pocket pitch; y direction 4.17 mm C pocket width; x direction 12.34 mm D pocket width; y direction 2.05 mm E tray width; x direction 50.8 mm F tray width; y direction 50.8 mm x number of pockets in x direction 3 y number of pockets in y direction 10 Philips Semiconductors Product specification 34 × 128 pixel matrix driver PCF8531 18 DEFINITIONS Data sheet status Objective specification This data sheet contains target or goal specifications for product development. Preliminary specification This data sheet contains preliminary data; supplementary data may be published later. Product specification This data sheet contains final product specifications. Limiting values Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Where application information is given, it is advisory and does not form part of the specification. 19 LIFE SUPPORT APPLICATIONS These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such improper use or sale. 20 PURCHASE OF PHILIPS I2C COMPONENTS Purchase of Philips I2C components conveys a license under the Philips’ I2C patent to use the components in the I2C system provided the system conforms to the I2C specification defined by Philips. This specification can be ordered using the code 9398 393 40011. 2000 Feb 11 40 Philips Semiconductors Product specification 34 × 128 pixel matrix driver PCF8531 NOTES 2000 Feb 11 41 Philips Semiconductors Product specification 34 × 128 pixel matrix driver PCF8531 NOTES 2000 Feb 11 42 Philips Semiconductors Product specification 34 × 128 pixel matrix driver PCF8531 NOTES 2000 Feb 11 43 Philips Semiconductors – a worldwide company Argentina: see South America Australia: 3 Figtree Drive, HOMEBUSH, NSW 2140, Tel. +61 2 9704 8141, Fax. +61 2 9704 8139 Austria: Computerstr. 6, A-1101 WIEN, P.O. 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Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights. Printed in The Netherlands 465006/03/pp44 Date of release: 2000 Feb 11 Document order number: 9397 750 06616