Holtek 32-bit Microcontroller with ARM® Cortex™-M3 Core
HT32F1251/51B/52/53 Series
Datasheet
Revision: V1.00
Date: May 27, 2011
32-bit ARM Cortex™-M3 MCU
HT32F1251/51B/52/53
Table of Contents
1 General Description................................................................................................. 6
2 Features.................................................................................................................... 7
Core........................................................................................................................................ 7
Flash Memory Controller........................................................................................................ 8
Reset Control Unit.................................................................................................................. 8
Clock Control Unit................................................................................................................... 8
Power Management................................................................................................................ 9
Analog to Digital Converter..................................................................................................... 9
Analog Operational Amplifier/Comparator.............................................................................. 9
I/O Ports................................................................................................................................ 10
PWM Generation and Capture Timers.................................................................................. 10
Watchdog Timer.................................................................................................................... 11
Real Time Clock.................................................................................................................... 11
Inter-integrated Circuit (I2C).................................................................................................. 12
Serial Peripheral Interface (SPI)........................................................................................... 12
Universal Synchronous Asynchronous Receiver Transmitter (USART)............................... 13
Debug Support...................................................................................................................... 13
Package and Operation Temperature................................................................................... 13
3 Overview................................................................................................................. 14
Device Information................................................................................................................ 14
Block Diagram...................................................................................................................... 15
Memory Map......................................................................................................................... 16
Clock Structure..................................................................................................................... 17
Pin Assignment..................................................................................................................... 18
4 Electrical Characteristics...................................................................................... 22
Absolute Maximum Ratings.................................................................................................. 22
DC Characteristics................................................................................................................ 22
On-Chip LDO Voltage Regulator Characteristics.................................................................. 22
Power Consumption............................................................................................................. 23
Reset and Supply Monitor Characteristics............................................................................ 23
External Clock Characteristics.............................................................................................. 24
Internal Clock Characteristics............................................................................................... 25
PLL Characteristics............................................................................................................... 26
Memory Characteristics........................................................................................................ 26
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Table of Contents
On-chip Memory..................................................................................................................... 7
32-bit ARM Cortex™-M3 MCU
HT32F1251/51B/52/53
I/O Port Characteristics......................................................................................................... 26
ADC Characteristics............................................................................................................. 28
Operation Amplifier/Comparator Characteristics.................................................................. 29
GPTM Characteristics........................................................................................................... 29
I2C Characteristics................................................................................................................ 30
5 Package Information............................................................................................. 33
48-pin LQFP (7mmx7mm) Outline Dimensions.................................................................... 33
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Table of Contents
SPI Characteristics............................................................................................................... 31
32-bit ARM Cortex™-M3 MCU
HT32F1251/51B/52/53
List of Tables
Rev. 1.00
1. HT32F125x Series Features and Peripheral List...................................................................... 14
2. HT32F125x Pin Descriptions.................................................................................................... 20
3. Absolute Maximum Ratings....................................................................................................... 22
4. DC Operating Conditions.......................................................................................................... 22
5. LDO Characteristics.................................................................................................................. 22
6. Power Consumption Characteristics......................................................................................... 23
7. LVD/BOD Characteristics.......................................................................................................... 23
8. High Speed External Clock (HSE) Characteristics.................................................................... 24
9. Low Speed External Clock (LSE) Characteristics..................................................................... 24
10. High Speed Internal Clock (HSI) Characteristics.................................................................... 25
11. Low Speed Internal Clock (LSI) Characteristics...................................................................... 25
12. PLL Characteristics................................................................................................................. 26
13. Flash Memory Characteristics................................................................................................. 26
14. I/O Port Characteristics........................................................................................................... 26
15. ADC Characteristics................................................................................................................ 28
16. OPA/CMP Characteristics....................................................................................................... 29
17. GPTM Characteristics............................................................................................................. 29
18. I2C Characteristics................................................................................................................... 30
19. SPI Characteristics.................................................................................................................. 31
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List of Tables
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
32-bit ARM Cortex™-M3 MCU
HT32F1251/51B/52/53
List of Figures
Rev. 1.00
HT32F125x Block Diagram...................................................................................................... 15
HT32F125x Memory Map......................................................................................................... 16
HT32F125x Clock Structure Diagram....................................................................................... 17
HT32F1251B 48LQFP Pin Assignment.................................................................................... 18
HT32F1251/52/53 48LQFP Pin Assignment............................................................................ 19
I2C Timing Diagram................................................................................................................... 30
SPI Timing Diagram – SPI Master Mode.................................................................................. 31
SPI Timing Diagram – SPI Slave Mode and CPHA=1.............................................................. 32
5 of 35
May 27, 2011
List of Figures
Figure 1.
Figure 2.
Figure 3.
Figure 4.
Figure 5.
Figure 6.
Figure 7.
Figure 8.
32-bit ARM Cortex™-M3 MCU
HT32F1251/51B/52/53
1
General Description
The Holtek HT32F125x series of devices are high performance, low power consumption 32-bit
microcontrollers based on the ARM® Cortex™-M3 processor core. The Cortex™-M3 is a nextgeneration processor core which is tightly coupled with a Nested Vectored Interrupt Controller
(NVIC), SysTick timer and advanced debug support.
The above features make the HT32F125x device suitable for a wide range of applications, especially
in areas such as white goods and application control, power monitor and alarm systems, consumer
and handheld equipment, data logging applications and so on.
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General Description
The HT32F125x device operates at a frequency of up to 72 MHz with a Flash accelerator to obtain
maximum efficiency. It provides up to 32 KB of embedded Flash memory for code/data storage
and up to 8 KB of embedded SRAM memory for system operation and application program usage.
A variety of peripherals, such as ADC, I2C, USART, SPI, SW-DP (Serial Wire Debug Port), etc.,
are also implemented in this device series. Several power saving modes provide the flexibility for
maximum optimisation between wakeup latency and power consumption, an especially important
consideration in low power applications.
32-bit ARM Cortex™-M3 MCU
HT32F1251/51B/52/53
2
Core
Features
▄▄ 32-bit ARM® Cortex™-M3 processor core
▄▄ Up to 72 MHz operation frequency
Features
▄▄ 1.25 DMIPS/MHz (Dhrystone 2.1)
▄▄ Single-cycle multiplication and hardware division
▄▄ Integrated Nested Vectored Interrupt Controller (NVIC)
▄▄ 24-bit SysTick timer
The Cortex™-M3 processor is a general-purpose 32-bit processor core especially suitable for
products requiring high performance and low power consumption microcontrollers. It offers many
new features such as a Thumb-2 instruction set, hardware divider, low latency interrupt respond
time, atomic bit-banding access and multiple buses for simultaneous accesses. The Cortex™-M3
processor is based on the ARMv7 architecture and supports both Thumb and Thumb-2 instruction
sets. Some system peripherals listed below are also provided by Cortex™-M3:
▄▄ Internal Bus Matrix connected with ICode bus, DCode bus, System bus, Private Peripheral Bus
(PPB) and debug accesses (AHB-AP)
▄▄ Nested Vectored Interrupt Controller (NVIC)
▄▄ Flash Patch and Breakpoint (FPB)
▄▄ Data Watchpoint and Trace (DWT)
▄▄ Instrument Trace Macrocell (ITM)
▄▄ Memory Protection Unit (MPU)
▄▄ Serial Wire JTAG Debug Port (SWJ-DP)
▄▄ Embedded Trace Macrocell (ETM)
▄▄ Trace Port Interface Unit (TPIU)
On-chip Memory
▄▄ 9 to 32 KB on-chip Flash memory for instruction/data and option storage
▄▄ 2 to 8 KB on-chip SRAM
▄▄ Supports several boot modes
The ARM® Cortex™-M3 processor is structured in Harvard architecture which can use separate
buses to fetch instructions and load/store data. The instruction code and data are both located in the
same memory address space but in different address ranges. The maximum address range of the
Cortex™-M3 is 4 GB since it has a 32-bit bus address width. Additionally, a pre-defined memory
map is provided by the Cortex™-M3 processor to reduce the software complexity of repeated
implementation of different device vendors. However, some regions are used by the ARM®
Cortex™-M3 system peripherals. Refer to the ARM® Cortex™-M3 Technical Reference Manual
for more information. The Figure 2. HT32F125x Memory Map shows the memory map of the
HT32F125x series of devices, including Code, SRAM, peripheral, and other pre-defined regions.
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32-bit ARM Cortex™-M3 MCU
HT32F1251/51B/52/53
Flash Memory Controller
▄▄ Flash accelerator for maximum efficiency
▄▄ 32-bit word programming (ISP and IAP)
▄▄ Flash protection capability to prevent illegal access
Reset Control Unit
▄▄ Supply supervisor:
●● Power On Reset (POR)
●● Brown Out Detector (BOD)
●● Programmable Low Voltage Detector (LVD)
The Reset Control Unit (RSTCU) has three kinds of reset, the power on reset, system reset and
APB unit reset. The power on reset, known as a cold reset, resets the full system during power up.
A system reset resets the processor core and peripheral IP components with the exception of the
SW-DP controller. The resets can be triggered by an external signal, internal events and the reset
generators.
Clock Control Unit
▄▄ External 4 to 16 MHz crystal oscillator
▄▄ External 32,768 Hz crystal oscillator
▄▄ Internal 8MHz RC oscillator trimmed to 1% accuracy at 3.3V operating voltage and 25°C
operating temperature
▄▄ Internal 32 kHz RC oscillator
▄▄ Integrated system clock PLL
▄▄ Independent clock gating bits for peripheral clock sources
The Clock Control unit, CKCU, provides a range of oscillator and clock functions. These include
a High Speed Internal RC oscillator (HSI), a High Speed External crystal oscillator (HSE), a Low
Speed Internal RC oscillator (LSI), a Low Speed External crystal oscillator (LSE), a Phase Lock
Loop (PLL), a HSE clock monitor, clock prescalers, clock multiplexers and clock gating circuitry.
The clocks of the AHB, APB and CortexTM-M3 are derived from the system clock (CK_SYS)
which can come from the HSI, HSE or PLL. The Watchdog Timer and Real Time Clock (RTC) use
either the LSI or LSE as their clock source. The maximum operating frequency of the system core
clock (CK_AHB) can be up to 72 MHz. (NOTE: LSE is not supported by HT32F1251B).
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Features
The Flash Memory Controller, FMC, provides all the necessary functions and pre-fetch buffer for
the embedded on-chip Flash Memory. Since the access speed of the Flash Memory is slower than
the CPU, a wide access interface with a pre-fetch buffer is provided for the Flash Memory in order
to reduce the CPU waiting time which will cause CPU instruction execution delays. Flash Memory
word program/page erase functions are also provided.
32-bit ARM Cortex™-M3 MCU
HT32F1251/51B/52/53
Power Management
▄▄ Single 3.3 V power supply: 2.7 V to 3.6 V
▄▄ Integrated 1.8 V LDO regulator for core and peripheral power supply
▄▄ VBAT battery power supply for RTC and backup registers
▄▄ Three power domains: 3.3V, 1.8V and Backup
▄▄ Four power saving modes: Sleep, Deep-Sleep1, Deep-Sleep2, Power-Down
Analog to Digital Converter
▄▄ 12-bit SAR ADC engine
▄▄ Up to 1 Msps conversion rate - 1 μs at 56 MHz, 1.17 μs at 72 MHz
▄▄ 8 external analog input channels
▄▄ Supply voltage range: 2.7 V ~ 3.6 V
▄▄ Conversion range: VSSA ~ VDDA
A 12-bit multi-channel ADC is integrated in the device. There are a total of 10 multiplexed
channels, which include 8 external channels on which the external analog signals can be supplied,
and 2 internal channels. If the input voltage is required to remain within a specific threshold
window, the Analog Watchdog function will monitor and detect the signal. An interrupt will then
be generated to inform that the input voltage is higher or lower than the set thresholds. There are
three conversion modes to convert an analog signal to digital data. The ADC can be operated in
one shot, continuous and discontinuous conversion modes.
Analog Operational Amplifier/Comparator
▄▄ 2 Operational Amplifiers or 2 Comparator functions which are software configurable
▄▄ Supply voltage range: 2.7 V ~ 3.6 V
Two Operational Amplifiers/Comparators (OPA/CMP) are implemented within the devices. They
can be configured either as Operational Amplifiers or as Analog Comparators. When configured as
comparators, they are capable of asserting interrupts to the NVIC.
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Features
The Power consumption can be regarded as one of the most important issues for many embedded
system applications. Accordingly the Power Control Unit, PWRCU, in these devices provides many
types of power saving modes such as Sleep, Deep-Sleep1, Deep-Sleep2 and Power-Down mode.
These operating modes reduce the power consumption and allow the application to achieve the best
trade-off between the conflicting demands of CPU operating time, speed and power consumption.
(NOTE: HT32F1251B does not support V BAT battery power supply).
32-bit ARM Cortex™-M3 MCU
HT32F1251/51B/52/53
I/O Ports
▄▄ Up to 32 GPIOs
▄▄ Port A and Port B are mapped as 16 external interrupts (EXTI)
▄▄ Almost all I/O pins are 5 V-tolerant except for pins shared with analog inputs
The GPIO ports are pin-shared with other alternative functions (AFs) to obtain maximum flexibility
on the package pins. The GPIO pins can be used as alternative functional pins by configuring the
corresponding registers regardless of the AF input or output pins.
The external interrupts on the GPIO pins of the device have related control and configuration
registers in the External Interrupt Control Unit (EXTI).
PWM Generation and Capture Timers
▄▄ Two 16-bit General-Purpose Timers (GPTM)
▄▄ Up to 4CHs PWM compare output or input capture for each GPTM
▄▄ External trigger input
The General-Purpose Timers, known as GPTM0 and GPTM1, consist of one 16-bit up/downcounter, four 16-bit Capture/Compare Registers (CCRs), one 16-bit Counter-Reload Register (CRR)
and several control/status registers. They can be used for a variety of purposes including general
time, input signal pulse width measurement or output waveform generation such as single pulse
generation or PWM output. The GPTM supports an Encoder Interface using a decoder with two
inputs.
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Features
There are up to 32 General Purpose I/O pins, (GPIO), named PA0 ~ PA15 and PB0 ~ PB15 for the
device to implement logic input/output functions. Each of the GPIO ports has related control and
configuration registers to satisfy the requirements of specific applications.
32-bit ARM Cortex™-M3 MCU
HT32F1251/51B/52/53
Watchdog Timer
▄▄ 12-bit down counter with 3-bit prescaler
▄▄ Interrupt or reset event for the system
▄▄ Programmable watchdog timer window function
▄▄ Write protection function
Real Time Clock
▄▄ 32-bit up-counter with a programmable prescaler
▄▄ Alarm function
▄▄ Interrupt and Wake-up event
The Real Time Clock, RTC, circuitry includes the APB interface, a 32-bit up-counter, a control
register, a prescaler, a compare register and a status register. Most of the RTC circuits are located
in the Backup Domain except for the APB interface. The APB interface is located in the V DD18
domain. Therefore, it is necessary to be isolated from the ISO signal that comes from the power
control unit when the V DD18 domain is powered off, i.e., when the device enters the Power-Down
mode. The RTC counter is used as a wakeup timer to generate a system resume from the PowerDown mode.
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Features
The Watchdog Timer is a hardware timing circuitry that can be used to detect system failures due
to software malfunctions. It includes a 12-bit down-counting counter, a prescaler, a WDT counter
value register, a WDT delta value register, interrupt related circuits, WDT operation control
circuitry and the WDT protection mechanism. The Watchdog Timer can be operated in an interrupt
mode or a reset mode. The Watchdog Timer will generate an interrupt or a reset when the counter
counts down and reaches a zero value. If the software does not reload the counter value before
the Watchdog Timer underflow occurs, an interrupt or a reset will be generated when the counter
underflows. In addition, an interrupt or reset is also generated if the software reloads the counter
when the counter value is greater than or equal to the WDT delta value. That means the counter
must be reloaded within a limited timing window using a specific method. The Watchdog Timer
counter can be stopped while the processor is in the debug mode. The register write protection
function can be enabled to prevent it from changing the configuration of the Watchdog Timer
unexpectedly.
32-bit ARM Cortex™-M3 MCU
HT32F1251/51B/52/53
Inter-integrated Circuit (I2C)
▄▄ Support both master and slave mode with a frequency of up to 400 kHz
▄▄ Provide arbitration function
▄▄ Supports 7-bit and 10-bit addressing mode and general call addressing
The SDA line which is connected to the whole I 2C bus is a bi-directional data line between the
master and slave devices used for the transmission and reception of data. The I 2C module also
has an arbitration detect function to prevent the situation where more than one master attempts to
transmit data to the I2C bus at the same time.
Serial Peripheral Interface (SPI)
▄▄ SPI interfaces with a frequency of up to 18 MHz
▄▄ Support both master and slave mode
▄▄ FIFO Depth: 8 levels
▄▄ Multi-master and multi-slave operation
The Serial Peripheral Interface, SPI, provides an SPI protocol data transmit and receive function in
both master and slave mode. The SPI interface uses 4 pins, among which are the serial data input
and output lines MISO and MOSI, the clock line, SCK, and the slave select line, SEL. One SPI
device acts as a master which controls the data flow using the SEL and SCK signals to indicate the
start of the data communication and the data sampling rate. To receive a data byte, the streamed
data bits are latched on a specific clock edge and stored in the data register or in the RX FIFO.
Data transmission is carried in a similar way but with a reverse sequence. The mode fault detection
provides a capability for multi-master applications.
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Features
The I2C Module is an internal circuit allowing communication with an external I2C interface which
is an industry standard two line serial interface used for connection to external hardware. These
two serial lines are known as a serial data line, SDA, and a serial clock line, SCL. The I2C module
provides two data transfer rates: (1) 100 kHz in the Standard mode or (2) 400 kHz in the Fast mode.
The SCL period generation register is used to setup different kinds of duty cycle implementation
for the SCL pulse.
32-bit ARM Cortex™-M3 MCU
HT32F1251/51B/52/53
Universal Synchronous Asynchronous Receiver Transmitter (USART)
▄▄ Operating frequency: up to 4.5 MHz
▄▄ Supports both asynchronous and clocked synchronous serial communication modes
▄▄ IrDA SIR encoder and decoder
▄▄ RS485 mode with output enable control
▄▄ Full Modem function
The Universal Synchronous Asynchronous Receiver Transceiver, USART, provides a flexible
full duplex data exchange using synchronous or asynchronous transfer. The USART is used to
translate data between parallel and serial interfaces, and is also commonly used for RS232 standard
communication. The USART peripheral function supports five-types of interrupt including Line
Status Interrupt, Transmitter FIFO Empty Interrupt, Receiver Threshold Level Reaching Interrupt,
Time Out Interrupt and MODEM Status Interrupt. The USART module includes a 16-byte
transmitter FIFO, (TX_FIFO) and a 16-byte receiver FIFO (RX_FIFO).
Software can detect a USART error status by reading the Line Status Register, LSR. The status
includes the type and the condition of transfer operations as well as several error conditions
resulting from Parity, Overrun, Framing and Break events.
The USART includes a programmable baud rate generator which is capable of dividing the CK_
AHB to produce a clock for the USART transmitter and receiver.
Debug Support
▄▄ Serial Wire Debug Port - SW-DP
▄▄ 6 instruction comparators and 2 literal comparators for hardware breakpoint or code / literal
patch
▄▄ 4 comparators for hardware watchpoint
▄▄ 1-bit asynchronous trace - TRACESWO
Package and Operation Temperature
▄▄ 48-pin LQFP package
▄▄ Operation temperature range: -40°C to +85°C
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Features
▄▄ FIFO Depth: 16 x 9 bits for both receiver and transmitter
32-bit ARM Cortex™-M3 MCU
HT32F1251/51B/52/53
3
Overview
Device Information
Most features are common to all devices while the main features distinguishing them are Flash
memory and SRAM memory capacities.
Peripherals
HT32F1252
HT32F1251
HT32F1251B
31
16
8
8
Option Bytes Flash (KB)
1
1
1
1
SRAM (KB)
8
4
2
2
Timers
Communication
Rev. 1.00
HT32F1253
Main Flash (KB)
GPTM
2
RTC
1
WDT
1
USART
1
SPI
1
I2C
1
GPIO
32
30
EXTI
16
12-bit ADC
Number of channels
1
8 Channels
OPA/Comparator
2
CPU frequency
Up to 72 MHz
Operating voltage
2.7 V ~ 3.6 V
Operating temperature
-40 ℃ ~ +85 ℃
Package
LQFP48
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Overview
Table 1. HT32F125x Series Features and Peripheral List
32-bit ARM Cortex™-M3 MCU
HT32F1251/51B/52/53
Block Diagram
SWDIO
SWCLK
TRACESWO
AF
BOOT0
BOOT1
AF
TPIU
AF
SW-DP
1.8 V
DCode
NVIC
System
VLDOIN
VSSLDO
HSI
8 MHz
HSE
XTALIN
XTALOUT
I2C_SDA
I2C_SCL
4 ~ 16 MHz
BOD
LVD
AHB to APB
Bridge
Powered by 3.3 V
I2C
SPI
WDT
12-bit
SAR ADC
ADC
GPTM0
Analog
OPA/CMP
OPA/CMP
GPTM1
Powered by VDDA
GPIOA
GT0_CH0
AF
...
USART
Power control
AF
GT0_CH3
GT0_ETI
GT1_CH0
...
AF
AF
GT1_CH3
GT1_ETI
APB1
APB0
RTC
AF
VDDA
VSSA
SRAM
1.8 V
AF
Bus Matrix
SRAM
Controller
Slave
VLDOOUT
LDO
AF
Interrupt request
Slave
AF
...
ADC_IN7
CN0, CP0
AOUT0
CN1, CP1
AOUT1
CKCU/RSTCU
Control Registers
AF
SPI_MOSI
SPI_MISO
SPI_SCK
SPI_SEL
ADC_IN0
VDD18
AHB Peripherals
Slave
UR_TX, UR_RX
UR_DCD
UR_DSR
UR_DTR
UR_RI
UR_RTS/TXE
UR_CTS/SCK
fMax: 144 MHz
Powered by 1.8 V
FMC Control
Registers
Master
PLL
Flash
Memory
Clock and reset control
fMax: 72 MHz
Flash
Memory
Controller
RTCOUT
PWRSW
PA [15:0]
VLDOIN
PWRCU
AFIO
PORB
LSI
VBAK 3.3 V
EXTI
Control signal:
Alternate function:
AF
32 kHz
LSE
BREG
WAKEUP
32,768 Hz
nRST
Powered by VBAK
Powered by 1.8 V
AF
Power supply:
Bus:
VBAT
VBAK
GPIOB
PB [15:0]
AF
XTAL32KIN
XTAL32KOUT
NOTE: HT32F1251B does not include the VBAT, XTAL32KIN and XTAL32KOUT pins.
Figure 1. HT32F125x Block Diagram
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Overview
ICode
CortexTM-M3
Processor
POR
32-bit ARM Cortex™-M3 MCU
HT32F1251/51B/52/53
Memory Map
0xFFFF_FFFF
Reserved
0xE010_0000
0x4010_0000
0x4008_A000
Reserved
0x4008_8000
0x4400_0000
APB/AHB bit band alias
0x4008_2000
32 MB
0x4008_0000
0x4200_0000
Peripherals
0x4010_0000
0x4008_0000
0x4000_0000
0x4007_0000
Reserved
AHB peripherals
APB peripherals
512 KB
512 KB
0x2000_2000
0x2000_1000
0x4006_8000
0x2000_0000
0x1FF0_0400
0x1FF0_0000
0x1F00_0800
0x1F00_0000
Code
SRAM bit band alias
256 KB
4 KB on-chip SRAM
2 KB on-chip SRAM
2 KB on-chip SRAM
HT32F1253
HT32F1252
HT32F1251(B)
Reserved
Option Bytes Flash
1 KB
8 KB on-chip Flash
0x4001_C000
0x4001_1000
0x4001_0000
0x4000_5000
HT32F1253
8 KB
16 KB
31 KB
0x0000_0000
0x4002_2000
0x4001_8000
2 KB
15 KB on-chip Flash
8 KB on-chip Flash
0x4002_3000
0x4001_9000
0x0000_7C00
0x0000_2000
0x4002_4000
0x4001_A000
Reserved
0x0000_4000
0x4002_5000
0x4001_B000
Reserved
Boot Loader
0x4004_9000
0x4004_8000
Reserved
2 KB
4 KB
8 KB
0x2000_0800
0x4006_B000
0x4006_9000
0x2204_0000
SRAM
0x4006_E000
0x4006_A000
Reserved
0x2200_0000
0x4006_F000
HT32F1252
HT32F1251(B)
0x4000_4000
0x4000_1000
0x4000_0000
Reserved
CKCU/RSTCU
Reserved
FMC
Reserved
GPTM1
GPTM0
Reserved
RTC/PWRCU
Reserved
WDT
Reserved
I2C
Reserved
EXTI
Reserved
AFIO
Reserved
GPIO B
GPIO A
Reserved
OPA/CMP
Reserved
ADC
Reserved
SPI
Reserved
USART
APB Peripherals
NOTES: 1. For HT32F1251(B), the Flash memory space at 0x0000_2000 to 0x0000_7BFF and the SRAM
memory space at 0x2000_0800 to 0x2000_1FFF are reserved.
2. For HT32F1252, the Flash memory space at 0x0000_4000 to 0x0000_7BFF and the SRAM memory
space at 0x2000_1000 to 0x2000_1FFF are reserved.
Figure 2. HT32F125x Memory Map
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Overview
0xE000_0000
AHB Peripherals
Private peripheral bus
32-bit ARM Cortex™-M3 MCU
HT32F1251/51B/52/53
Clock Structure
Prescaler
÷1, 2
PLLSRC
8 MHz
HSI RC
PLLEN
PLL
0
CK_PLL
4-16 MHz
HSE XTAL
fCK_SYS,max = 144MHz
0x
CK_HSI
HSEEN
11
CK_HSE
CK_SYS
AHB
Prescaler
÷ 1,2,4,8
fCK_AHB,max = 72MHz
CK_AHB
1
0
HCLKF
( to Flash)
CK_WDT
CM3EN
FMCEN
CK_LSI
WDTEN
RTCSRC
1
0
SRAMEN
CK_RTC
14
CKOUTSRC[2:0]
OPA0EN
14
WDTEN
(APB peripherals clock gating)
RTCEN
000
CK_PLL/16
001
010
CK_AHB/16
CK_SYS/16
011
CK_HSE/16
100
CK_HSI/16
101
CK_LSE
110
CK_LSI
HCLKS
( to SRAM)
CM3EN
LSIEN
CKOUT
HCLKC
( to Cortex-M3)
CM3EN
(control by HW)
WDTSRC
LSEEN
32 kHz
LSI RC
FCLK
( free running clock)
10
Clock
Monitor
32.768 kHz CK_LSE
LSE OSC
STCLK
(to SysTick)
÷8
SW[1:0]
ADC
Prescaler
÷ 1,2,4,6,8...
PCLK
( to OPA,
AFIO
GPIO Port,
ADC,
SPI,
USART,
I2C,
GPTIM,
EXTI,
RTC,
WDT)
CK_ADC
ADCEN
Legend: HSE = High Speed External clock
HSI = High Speed Internal clock
LSE = Low Speed External clock
LSI = Low Speed Internal clock
NOTE: 1. Control bits LSIEN & LSEEN are located at RTC Control Register (RTCCR).
2. HT32F1251B does not include the VBAT, XTAL32KIN and XTAL32KOUT pins.
Figure 3. HT32F125x Clock Structure Diagram
Rev. 1.00
17 of 35
May 27, 2011
Overview
f CK_PLL,max = 144MHz
1
HSIEN
CK_USART
UREN
32-bit ARM Cortex™-M3 MCU
HT32F1251/51B/52/53
Pin Assignment
AF3
GT1_CH0
AF2
-
AF1
CN0
CP0
AOUT0
CN1
CP1
AOUT1
Overview
UR_RTS
/TXE
-
GT1_CH2
-
GT1_CH1
GT1_CH3
-
42
41
40
39
38
33V
33V
33V
33V
33V
AF0
(Default)
43
33V
VDD18
PB2
44
P33
PB3
45
P33
PB4
46
AP
PB5
47
AP
PB6
48
PB7
N.C.
VDD33_1
AF0
(Default)
GT1_ETI
GT0_ET1
UR_CTS
/SCK
AF1
VSS33_1
AF2
VDDA
AF3
VSSA_1
Holtek HT32F1251B
LQFP48
AF0
(Default)
37
P18
AF1
AF2
AF3
-
VSSA_2
1
AP
33V
36
XTALOUT
PB1
-
GT0_Ch3
GT1_ETI
ADC_IN0
PA0
2
33V
33V
35
XTALIN
PB0
-
-
GT0_CH2
-
ADC_IN1
PA1
3
33V
5VT
34
PB15
SPI_MOSI
UR_RI
GT1_CH0
GT0_CH1
UR_DCD
ADC_IN2
PA2
4
33V
5VT
33
PB14
SPI_MISO
UR_DTR
GT1_CH1
GT0_CH0
UR_DSR
ADC_IN3
PA3
5
33V
5VT
32
PB13
SPI_SCK
UR_DSR
GT1_CH2
SPI_MOSI
UR_DTR
ADC_IN4
PA4
6
33V
5VT
31
PB12
SPI_SEL
UR_DCD
GT1_CH3
UR_RI
ADC_IN5
PA5
7
33V
P33
30
VSS33_3
ADC_IN6
PA6
8
33V
P33
29
VSS33_2
ADC_IN7
PA7
9
33V
-
PA8
10
5VT
11
5VT
12
5VT
SPI_MISO
SPI_SCK
SPI_SEL
-
UR_RTS
/TXE
UR_CTS
/SCK
UR_RX
-
UR_TX
-
-
-
-
PA9BOOT0
PA10BOOT1
AP
3.3 V Analog Power Pad
P18
1.8 V Power Pad
33V
3.3 V I/O Pad
5VT
5 V Tolerance I/O Pad
P33
28
VDD33_2
5VT
5VT
High Current Output
5 V Tolerance I/O Pad
27
TRACE
SWO
PA15
-
GT0_CH0
5VT
26
SWCLK
PA14
-
GT0_CH1
5VT
25
SWDIO
PA13
-
GT0_CH2
PA12
AF0
(Default)
I2C_SDA
AF1
-
-
AF2
GT0_CH3
-
-
AF3
24
-
23
CKOUT
22
I2C_SCL
21
PB11
20
PA11
19
GT0_ETI
nRST
18
5VT
-
17
5VT
PB10WAKEUP
16
5VT
N.C.
15
5VT
RTCOUT
14
N.C.
5VT
N.C.
P33
VSSLDO
VLDOOUT
P33
N.C.
13
3.3 V Digital Power Pad
VLDOIN
P18
P33
Figure 4. HT32F1251B 48LQFP Pin Assignment
Rev. 1.00
18 of 35
May 27, 2011
32-bit ARM Cortex™-M3 MCU
HT32F1251/51B/52/53
AF3
GT1_CH0
GT1_CH1
AF2
-
-
AF0
(Default)
VDD18
PB2
N.C.
PB3
Overview
AF1
CN0
CP0
PB4
AF3
PB1
-
-
36
XTALOUT
33V
35
XTALIN
PB0
-
-
5VT
34
PB15
SPI_MOSI
UR_RI
GT1_CH0
5VT
33
PB14
SPI_MISO
UR_DTR
GT1_CH1
5VT
32
PB13
SPI_SCK
UR_DSR
GT1_CH2
5VT
31
PB12
SPI_SEL
UR_DCD
GT1_CH3
P33
30
VSS33_3
P33
29
VSS33_2
GT0_CH1
UR_DCD
ADC_IN2
PA2
4
33V
GT0_CH0
UR_DSR
ADC_IN3
PA3
5
33V
SPI_MOSI
UR_DTR
ADC_IN4
PA4
6
33V
UR_RI
ADC_IN5
PA5
7
33V
ADC_IN6
PA6
8
33V
ADC_IN7
PA7
9
33V
PA8
10
5VT
11
5VT
12
5VT
-
AF2
33V
33V
-
AF1
AP
3
-
AF0
(Default)
1
2
-
37
P18
VSSA_2
PA1
UR_TX
AOUT0
38
33V
PA0
-
GT1_CH2
39
33V
ADC_IN1
-
UR_RTS
/TXE
40
33V
PB5
41
33V
ADC_IN0
UR_RX
CN1
42
33V
-
-
-
43
33V
GT1_ETI
SPI_SEL
GT1_CH3
44
P33
PB6
45
P33
PB7
46
AP
GT0_Ch3
SPI_SCK
CP1
AOUT1
47
AP
GT0_CH2
UR_RTS
/TXE
UR_CTS
/SCK
-
48
33V
SPI_MISO
VDD33_1
AF0
(Default)
GT1_ETI
GT0_ET1
UR_CTS
/SCK
AF1
VSS33_1
AF2
VDDA
AF3
VSSA_1
Holtek HT32F1251/52/53
LQFP48
PA9BOOT0
PA10BOOT1
AP
3.3 V Analog Power Pad
P18
1.8 V Power Pad
33V
3.3 V I/O Pad
5VT
5 V Tolerance I/O Pad
P33
28
VDD33_2
High Current Output
5 V Tolerance I/O Pad
5VT
5VT
27
TRACE
SWO
PA15
-
GT0_CH0
5VT
26
SWCLK
PA14
-
GT0_CH1
5VT
25
SWDIO
PA13
-
GT0_CH2
P33
33V
33V
5VT
5VT
5VT
5VT
14
15
16
17
18
19
20
21
22
23
24
nRST
VBAT
PB11
PA11
PA12
AF0
(Default)
PB10WAKEUP
CKOUT
I2C_SCL
I2C_SDA
AF1
-
-
-
-
-
-
AF2
-
GT0_ETI
GT0_CH3
-
-
AF3
-
PB8
PB9
RTCOUT
5VT
XTAL32K
OUT
XTAL32K
IN
P33
VSSLDO
VLDOOUT
P33
N.C.
13
3.3 V Digital Power Pad
VLDOIN
P18
P33
Figure 5. HT32F1251/52/53 48LQFP Pin Assignment
Rev. 1.00
19 of 35
May 27, 2011
32-bit ARM Cortex™-M3 MCU
HT32F1251/51B/52/53
Table 2. HT32F125x Pin Descriptions
Pin
Name
Pins
Type
48
LQFP
(Note1)
IO
Level
(Note2)
Description
Default function
(AF0)
AF1
AF2
AF3
VSSA_2
1
P
Ground reference for ADC and OPA/Comparator
PA0
2
I/O
GPIO PA0
ADC_IN0
PA1
3
I/O
GPIO PA1
ADC_IN1
PA2
4
I/O
GPIO PA2
ADC_IN2
UR_DCD
GT0_CH1
PA3
5
I/O
GPIO PA3
ADC_IN3
UR_DSR
GT0_CH0
PA4
6
I/O
GPIO PA4
ADC_IN4
UR_DTR
SPI_MOSI
PA5
7
I/O
GPIO PA5
ADC_IN5
UR_RI
SPI_MISO
PA6
8
I/O
GPIO PA6
ADC_IN6
UR_RTS/TXE
SPI_SCK
PA7
9
I/O
GPIO PA7
ADC_IN7
UR_CTS/SCK
SPI_SEL
PA8
10
I/O
5V-T
GPIO PA8
UR_RX
PA9
11
I/O
5V-T
GPIO PA9-BOOT0
UR_TX
PA10
12
I/O
5V-T
GT1_ETI
GT0_CH3
GPIO PA10-BOOT1
P
LDO 1.8 V output. Please put a 10μF capacitor to GND in those pins
as close as possible.
15
P
LDO 3.3 V power source, also connected to the power switch of the
backup domain.
16
P
LDO ground reference
17
I
(Backup 5V-T
domain)
External reset pin and external wakeup pin in Power-Down mode
VBAT(note3) 18
P
VDD 3.3 V for backup domain
PB8(note3) 19
I/O
(Backup
domain)
XTAL32KIN
PB8
PB9(note3) 20
I/O
(Backup
domain)
XTAL32KOUT
PB9
PB10
21
I/O
(Backup 5V-T
domain)
RTCOUT
PB10WAKEUP
GT0_ETI
PB11
22
I/O
5V-T
GPIO PB11
CKOUT
GT0_CH3
PA11
23
I/O
5V-T
GPIO PA11
I2C_SCL
PA12
24
I/O
5V-T
GPIO PA12
I2C_SDA
PA13
25
I/O
5V-T
SWDIO
PA13
GT0_CH2
PA14
26
I/O
5V-T
SWCLK
PA14
GT0_CH1
5V-T
TRACESWO
PA15
GT0_CH0
VLDOOUT
13
N.C
14
VLDOIN
VSSLDO
nRST
PA15
27
I/O
VDD33_2
28
P
3.3 V voltage for digital I/O
VSS33_2
29
P
Ground reference for digital I/O
VSS33_3
30
P
PB12
31
I/O
Rev. 1.00
Ground reference for digital core
5V-T
GPIO PB12
20 of 35
SPI_SEL
UR_DCD
GT1_CH3
May 27, 2011
Overview
GT0_CH2
32-bit ARM Cortex™-M3 MCU
HT32F1251/51B/52/53
Pins
Pin
Name
Type
48
LQFP
(Note1)
IO
Level
(Note2)
Description
Default function
(AF0)
AF1
AF2
AF3
32
I/O
5V-T
GPIO PB13
SPI_SCK
UR_DSR
GT1_CH2
PB14
33
I/O
5V-T
GPIO PB14
SPI_MISO
UR_DTR
GT1_CH1
PB15
34
I/O
5V-T
GPIO PB15
SPI_MOSI
UR_RI
GT1_CH0
PB0
35
I/O
XTALIN
PB0
PB1
Overview
PB13
PB1
36
I/O
XTALOUT
VDD18
37
P
1.8 V voltage for core
N.C
38
PB2
39
I/O
GPIO PB2
CN0
GT1_CH0
PB3
40
I/O
GPIO PB3
CP0
GT1_CH1
PB4
41
I/O
GPIO PB4
AOUT0
PB5
42
I/O
GPIO PB5
CN1
GT1_CH3
PB6
43
I/O
GPIO PB6
CP1
GT1_ETI
PB7
44
I/O
GPIO PB7
AOUT1
VDD33_1
45
P
3.3 V voltage for digital I/O
VSS33_1
46
P
Ground reference for digital I/O
VDDA
47
P
3.3 V analog voltage for ADC and OPA/Comparator
VSSA_1
48
P
Ground reference for ADC and OPA/Comparator
UR_RTS/TXE
UR_CTS/SCK
GT1_CH2
GT0_ETI
NOTES: 1. I = input, O = output, P = power supply.
2. 5V-T = 5 V tolerant.
3. HT32F1251B does not include the VBAT, XTAL32KIN and XTAL32KOUT pins.
4. The GPIOs are in AF0 state after VDD18 power on reset (POR) except the RTCOUT pin of Backup
Domain I/O. The RTCOUT pin is reset by the Backup Domain power-on-reset (PORB) or Backup
Domain software reset (BAK_RST bit in BAK_CR register).
5. The backup domain of I/O pins has driving current capability limitation (< 1mA @ VBAT = 3.3 V).
Rev. 1.00
21 of 35
May 27, 2011
32-bit ARM Cortex™-M3 MCU
HT32F1251/51B/52/53
4
Electrical Characteristics
Absolute Maximum Ratings
Table 3. Absolute Maximum Ratings
Symbol
Parameter
Min
Max
Unit
VDD33
External main supply voltage
VSS - 0.3
VSS + 3.6
V
VDDA
External analog supply voltage
VSSA - 0.3
VSSA + 3.6
V
VBAT
External battery supply voltage
VSS - 0.3
VSS + 3.6
V
VIN
Input voltage on 5 V-tolerant I/O
VSS - 0.3
VSS + 5.5
V
Input voltage on other I/O
VSS - 0.3
VDD33 + 0.3
V
TA
Operating temperature range
-40
+85
°C
TSTG
Storage temperature range
-55
+150
°C
TJ
Maximum junction temperature
—
125
°C
PD
Total power dissipation
—
500
mW
VESD
Electrostatic discharge voltage (human body mode)
-4000
+4000
V
DC Characteristics
Table 4. DC Operating Conditions
Symbol
TA = 25°C, unless otherwise specified.
Parameter
Conditions
Min
Typ
Max
Unit
VDD33
Operating voltage of I/O
—
2.7
3.3
3.6
V
VDDA
Analog operating voltage
—
2.7
3.3
3.6
V
VBAT
Operating voltage of Battery supply —
2.7
3.3
3.6
V
VDD18
Operating voltage of core power
1.62
1.8
1.98
V
—
On-Chip LDO Voltage Regulator Characteristics
Table 5. LDO Characteristics
Symbol
Parameter
TA = 25°C, unless otherwise specified.
Conditions
Min
Typ
Max
Unit
VLDOOUT
Internal regulator output
voltage
VLDOIN = 3.3 V Regulator input
1.71
1.8
1.89
V
IDD18
Output current
VLDOIN = 2.4 V Regulator input
—
—
200
mA
CLDO
External filter capacitor
value for internal core
power supply
The capacitor value is
dependent on the core power
current consumption
2.2
—
10
μF
Rev. 1.00
22 of 35
May 27, 2011
Electrical Characteristics
The following table shows the absolute maximum ratings of the device. These are stress ratings
only. Stresses beyond absolute maximum ratings may cause permanent damage to the device. Note
that the device is not guaranteed to operate properly at the maximum ratings. Exposure to the
absolute maximum rating conditions for extended periods may affect device reliability.
32-bit ARM Cortex™-M3 MCU
HT32F1251/51B/52/53
Power Consumption
Table 6. Power Consumption Characteristics
Symbol
Parameter
Min
Typ
VDD33 = VBAT = 3.3 V, HSE = 8MHz, PLL = 144 MHz,
fHCLK = 72 MHz, fPCLK = 72 MHz, All peripherals enabled
—
47
—
mA
VDD33 = VBAT = 3.3 V, HSE = 8MHz, PLL = 144 MHz,
fHCLK = 72 MHz, fPCLK = 72 MHz, All peripherals disabled
—
28
—
mA
VDD = VBAT = 3.3 V, HSE = 8MHz, PLL = 144 MHz,
fHCLK = 0 MHz, fPCLK = 72 MHz, All peripherals enabled
—
30
—
mA
VDD33 = VBAT = 3.3 V, HSE = 8MHz, PLL = 144 MHz,
fHCLK = 0 MHz, fPCLK = 72 MHz, All peripherals disabled
—
7
—
mA
Supply current
(Deep-Sleep1
mode)
VDD33 = VBAT = 3.3 V, All clock off (HSE/PLL/fHCLK), LDO
in low power mode, LSI on, RTC on
—
66
—
μA
Supply current
(Deep-Sleep2
mode)
VDD33 = VBAT = 3.3 V, All clock off (HSE/PLL/fHCLK), LDO
off (DMOS on), LSI on, RTC on
—
11
—
μA
VDD33 = VBAT = 3.3 V, LDO off, LSE on, LSI off, RTC on
—
4.2
—
μA
VDD33 = VBAT = 3.3 V, LDO off, LSE on, LSI off, RTC off
—
4.1
—
μA
VDD33 = VBAT = 3.3 V, LDO off, LSE off, LSI on, RTC on
—
4.3
—
μA
VDD33 = VBAT = 3.3 V, LDO off, LSE off, LSI on, RTC off
—
4.2
—
μA
—
4
—
μA
—
3.9
—
μA
Supply current
(Sleep mode)
Supply current
(Power-Down
mode)
VDD33 not present, VBAT = 3.3 V, LDO off, LSE off, LSI
Battery supply
on, RTC on
current (PowerV
DD33 not present, VBAT = 3.3 V, LDO off, LSE off, LSI
Down mode)
on, RTC off
IBAT
Max Unit
NOTES: 1. HSE is the high speed external oscillator while HSI is the 8MHz high speed internal oscillator.
2. LSE is the low speed external oscillator while LSI is the 32 KHz low speed internal oscillator.
3. RTC means real time clock.
4. Code = while (1) { NOP x n } executed in Flash (n > 200).
Reset and Supply Monitor Characteristics
Table 7. LVD/BOD Characteristics
Symbol
VBOD
TA = 25°C, unless otherwise specified.
Parameter
Voltage of Brown Out Detector
Conditions
—
LVDS
VLVD
VPOR
Voltage of Low Voltage Detector
Voltage of Power On Reset
Min
Typ
Max
Unit
—
2.5
—
V
= ‘00’
—
2.7
—
V
LVDS (Note1) = ‘01’
—
2.8
—
V
LVDS
(Note1)
= ‘10’
—
2.9
—
V
LVDS
(Note1)
= ‘11’
(Note1)
—
—
3.0
—
V
—
1.36
—
V
NOTE: LVDS field is in PWRCU LVDCSR register
Rev. 1.00
23 of 35
May 27, 2011
Electrical Characteristics
Conditions
Supply current
(Run mode)
IDD
TA = 25°C, unless otherwise specified.
32-bit ARM Cortex™-M3 MCU
HT32F1251/51B/52/53
External Clock Characteristics
Table 8. High Speed External Clock (HSE) Characteristics
Symbol
Parameter
Conditions
TA = 25°C, unless otherwise specified.
Min
Typ
Max
Unit
4
—
16
MHz
High Speed External oscillator
frequency (HSE)
CHSE
Recommended load capacitance on
XTALIN and XTALOUT
—
TBD
—
pF
RFHSE
Recommended external feedback
resistor between XTALIN and
XTALOUT
—
1.0
—
MΩ
DHSE
HSE Oscillator Duty cycle
40
—
60
%
IDDHSE
HSE Oscillator Operating Current
VDD33 = 3.3 V, TA = 25°C
—
0.96
—
mA
ISTBHSE
HSE Oscillator Standby current
VDD33 = 3.3 V, TA = 25°C
—
—
0.1
μA
tSUHSE
HSE Oscillator Startup time
VDD33 = 3.3 V, TA = 25°C
—
—
4
ms
VDD33 = 3.3 V
Table 9. Low Speed External Clock (LSE) Characteristics
Symbol
Parameter
Conditions
TA = 25°C, unless otherwise specified.
Min
Typ
Max
Unit
—
32.768
—
kHz
fLSE
Low Speed External oscillator
frequency (LSE)
CLSE
Recommended load capacitance on
—
XTAL32IN and XTAL32OUT
—
TBD
—
pF
RFLSE
Recommended external feedback
resistor between XTAL32IN and
XTAL32OUT
—
—
10
—
MΩ
DLSE
LSE Oscillator Duty cycle
—
40
—
60
%
IDDLSE
LSE Oscillator Operating Current
VDD33 = VBAT = 3.3 V,
LSESM = 0 (Normal
startup mode)
—
1.7
—
μA
ISTBLSE
LSE Oscillator Standby current
VDD33 = VBAT = 3.3 V,
LSESM = 1 (Fast startup
mode)
—
3
8
μA
tSULSE
LSE Oscillator Startup time
VDD33 = VBAT = 3.3 V,
LSESM = 1 (Fast startup
mode)
—
200
—
ms
Rev. 1.00
VDD33 = VBAT = 3.3 V
24 of 35
May 27, 2011
Electrical Characteristics
fHSE
32-bit ARM Cortex™-M3 MCU
HT32F1251/51B/52/53
Internal Clock Characteristics
Table 10. High Speed Internal Clock (HSI) Characteristics
Symbol
Parameter
TA = 25°C, unless otherwise specified.
Conditions
Min
Typ
Max
Unit
TBD
8
TBD
MHz
High Speed Internal
VDD33 = 3.3 V,
Oscillator Frequency (HSI ) TA = -40°C ~ +85°C
ACCHSI
HSI Oscillator Frequency
accuracy
Factory-trimmed,
VDD33 = 3.3 V, TA = 25°C
-1
—
+1
%
DHSI
HSI Oscillator Duty cycle
VDD33 = 3.3 V, fHSI = 8 MHz
35
—
65
%
IDDHSI
HSI Oscillator Operating
Current
VDD33 = 3.3 V, fHSI = 8 MHz
—
0.92
—
mA
tSUHSI
HSI Oscillator Startup time
VDD33 = 3.3 V,
fHSI = 8 MHz, HSIRCBL = 0 (HSI
Ready Counter Bits Length 7 Bits )
—
17
—
μs
NOTE: HSIRCBL field is in PWRCU HSIRCR register
Table 11. Low Speed Internal Clock (LSI) Characteristics
Symbol
Parameter
Conditions
TA = 25°C, unless otherwise specified.
Min
Typ
Max
Unit
fLSI
Low Speed Internal Oscillator VDD33 = VBAT = 3.3 V,
Frequency(LSI)
TA = -40°C ~ +85°C
25
32
43
kHz
IDDLSI
LSI Oscillator Operating
Current
VDD33 = VBAT = 3.3 V,
TA = 25°C
—
1.0
2
μA
tSULSI
LSI Oscillator Startup time
VDD33 = VBAT = 3.3 V,
TA = 25°C
—
35
—
ms
Rev. 1.00
25 of 35
May 27, 2011
Electrical Characteristics
fHSI
32-bit ARM Cortex™-M3 MCU
HT32F1251/51B/52/53
PLL Characteristics
Table 12. PLL Characteristics
Symbol
TA = 25°C, unless otherwise specified.
Parameter
Conditions
Min
Typ
Max
Unit
PLL input clock frequency
PLLVDD18 = 1.8 V
4
—
16
MHz
PLL output clock frequency
PLLVDD18 = 1.8 V
8
—
144
MHz
tLOCK
PLL lock time
PLLVDD18 = 1.8 V
—
TBD
—
ms
Memory Characteristics
Table 13. Flash Memory Characteristics
Symbol
Parameter
TA = 25°C, unless otherwise specified.
Conditions
Min
Typ
Max
Unit
1
—
—
kcycles
NENDU
Number of guaranteed
VDD18 =1.8 V,
program /erase cycles before
TA= -40°C ~ +85°C
failure. (Endurance)
TRET
Data retention time
TA = 25°C
100
—
—
Years
tPROG
Word programming time
VDD18 = 1.8 V,
TA = -40°C ~ +85°C
40
—
—
μs
tERASE
Page erase time
VDD18 = 1.8 V,
TA = -40°C ~ +85°C
20
—
40
ms
tMERASE
Mass erase time
VDD18 = 1.8 V,
TA = -40°C ~ +85°C
20
—
40
ms
I/O Port Characteristics
Table 14. I/O Port Characteristics
Symbol
Parameter
TA = 25°C, unless otherwise specified.
Conditions
Min
Typ
Max
Unit
VI = 0 V, On-chip
pull-up resister
disabled.
—
—
3
μA
—
—
3
μA
—
—
3
μA
VI = VDD33, On-chip
pull-down resister
disabled.
—
—
3
μA
—
—
3
μA
—
—
3
μA
3.3 V IO
-0.3
—
0.8
V
5 V-tolerant IO
-0.3
—
0.8
V
Reset pin
-0.3
—
0.8
V
3.3 V IO
2
—
3.6
V
2
—
5.5
V
2
—
5.5
V
3.3 V IO
IIL
Low level input current
5 V-tolerant IO
Reset pin
3.3 V IO
IIH
High level input current
5 V-tolerant IO
Reset pin
VIL
VIH
Low level input voltage
High level input voltage 5 V-tolerant IO
Reset pin
Rev. 1.00
26 of 35
May 27, 2011
Electrical Characteristics
fPLLIN
fPLL
32-bit ARM Cortex™-M3 MCU
HT32F1251/51B/52/53
Symbol
VHYS
IOH
VOL
Schmitt Trigger Input
Voltage Hysteresis
Conditions
3.3 V IO
Low level output voltage
VOH
RPU
Internal pull-up resistor
RPD
Internal pull-down
resistor
Rev. 1.00
Max
Unit
—
400
—
mV
5 V-tolerant IO
—
400
—
mV
—
400
—
mV
3.3 V 4 mA drive IO, VOL = 0.4 V
4
—
—
mA
3.3 V 8 mA drive IO, VOL = 0.4 V
8
—
—
mA
8
—
—
mA
12
—
—
mA
Backup Domain IO drive @ VBAT =3.3V,
VOL = 0.4 V, PB8, PB9, PB10.
—
—
1
mA
3.3V I/O 4 mA drive, VOH=VDD33-0.4V
4
—
—
mA
3.3V I/O 8 mA drive, VOH=VDD33-0.4V
8
—
—
mA
5 V-tolerant I/O 8 mA drive,
VOH = VDD33 - 0.4 V
8
—
—
mA
5 V-tolerant I/O 12 mA drive,
VOH = VDD33 - 0.4 V
12
—
—
mA
Backup Domain IO drive@VBAT=3.3V,
VOH = VDD33 - 0.4 V, PB8, PB9, PB10.
—
—
1
mA
3.3 V 4 mA drive IO, IOL = 4 mA
—
—
0.4
V
3.3 V 8 mA drive IO, IOL = 8 mA
—
—
0.4
V
5 V-tolerant 8 mA drive IO, IOL=8mA
—
—
0.4
V
5 V-tolerant 12 mA drive IO, IOL=12mA
High level output
voltage
Typ
Reset pin
Low level output current 5 V-tolerant 8 mA drive IO, VOL=0.4V
(GPO Sink current)
5 V-tolerant 12 mA drive IO, VOL=0.4V
High level output
current
(GPO Source current)
Min
—
—
0.4
V
3.3 V 4 mA drive IO, IOH = 4 mA
VDD33 0.4 V
—
—
V
3.3 V 8 mA drive IO, IOH = 8 mA
VDD33 0.4 V
—
—
V
5 V-tolerant 8 mA drive IO,
IOH=8mA
VDD33 0.4 V
—
—
V
5 V-tolerant 12 mA drive IO,
IOH=12mA
VDD33 0.4 V
—
—
V
3.3 V I/O
34
—
74
kΩ
5 V-tolerant I/O
38
—
89
kΩ
3.3 V I/O
29
—
86
kΩ
5 V-tolerant I/O
35
—
107
kΩ
27 of 35
May 27, 2011
Electrical Characteristics
IOL
Parameter
32-bit ARM Cortex™-M3 MCU
HT32F1251/51B/52/53
ADC Characteristics
Table 15. ADC Characteristics
Symbol
Parameter
TA = 25°C, unless otherwise specified.
Conditions
Min
Typ
Max
Unit
2.7
3.3
3.6
V
0
—
VDDA
V
Operating voltage
VADCIN
A/D Converter input
voltage range
IADC
Current consumption
VDDA = 3.3 V
—
1
TBD
mA
IADC_DN
Power down current
consumption
VDDA = 3.3 V
—
1
10
uA
fADC
A/D Converter clock
0.7
—
14
MHz
fS
Sampling rate
0.05
—
1
MHz
fADCCONV
A/D Converter
conversion time
—
14
—
tADC
RI
Input sampling switch
resistance
—
—
1
kΩ
CI
Input sampling
capacitance
—
—
5
pF
tSU
Startup time
—
—
1
us
N
A/D Converter
Resolution
—
12
—
bits
INL
Integral Non-linearity
error
fS = 1 MHz, VDDA = 3.3 V
-—
±2
±5
LSB
DNL
Differential Non-linearity
fS = 1 MHz, VDDA = 3.3 V
error
—
—
±1
LSB
EO
Offset error
—
—
±10
LSB
EG
Gain error
—
—
±10
LSB
No pin/pad capacitance included
NOTES: 1. tADC = 1/fADC.
2. Guaranteed by design, not tested in production.
Rev. 1.00
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May 27, 2011
Electrical Characteristics
VDDA
32-bit ARM Cortex™-M3 MCU
HT32F1251/51B/52/53
Operation Amplifier/Comparator Characteristics
Table 16. OPA/CMP Characteristics
Symbol
TA = 25°C, unless otherwise specified.
Parameter
Conditions
Min
Typ
Max
Unit
Operating voltage
2.7
3.3
3.6
V
Typical operating current
—
230
—
uA
Assign registers OPAEN = 0
and EN_OPAOP = 0
—
—
0.1
uA
VDDA = 3.3 V,
AnOF[5:0] = ‘100000’
-15
—
15
mV
-1
—
1
mV
60
100
IOPA/CMP_DN Power down supply current
VIOS
Input offset voltage
GV
Voltage Gain
Ut
Unit-Gain Bandwidth
VCM
Common mode voltage range VDDA = 3.3 V
tRT
Comparator response time
VDDA = 3.3 V;
Input Overdrive = ±10mV
SR
Slew Rate
VDDA = 3.3 V;
Output capacitor load
CL=100pF
VDDA = 3.3 V, After calibration
RL=100KΩ
1,3
RL=100KΩ, CL=100pF
1.24
dB
MHz
VSSA
—
VDDA –
0.6
V
—
1
—
us
1.6
V/us
NOTE: Guaranteed by design, not tested in production.
GPTM Characteristics
Table 17. GPTM Characteristics
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
fGPTM
Timer clock source
—
—
—
72
MHz
tRES
Timer resolution time
—
1
—
—
1/fGPTM
fEXT
External signal frequency on
channel 1 ~ 4
—
—
—
1/2
fGPTM
RES
Timer resolution
—
—
—
16
bits
Rev. 1.00
29 of 35
May 27, 2011
Electrical Characteristics
VDDA
IOPA/CMP
32-bit ARM Cortex™-M3 MCU
HT32F1251/51B/52/53
I2C Characteristics
Table 18. I2C Characteristics
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
fSCL
SCL clock frequency
—
—
—
400
kHz
tSCL(H)
SCL clock high time
—
600
—
—
ns
tSCL(L)
SCL clock low time
—
1300
—
—
ns
SCL and SDA fall time
—
—
—
300
ns
SCL and SDA rise time
—
—
—
300
ns
tSU(STA)
START condition setup time
—
600
—
—
ns
tH(STA)
START condition hold time
—
600
—
—
ns
tSU(SDA)
SDA data setup time
—
100
—
—
ns
tH(SDA)
SDA data hold time
—
0
—
—
ns
tSU(STO)
STOP condition setup time
—
600
—
—
ns
tRISE
tFALL
SCL
tSCL(L)
tH(STA)
tSCL(H)
tH(SDA)
tSU(SDA)
tSU(STO)
SDA
tSU(STA)
Figure 6. I2C Timing Diagram
Rev. 1.00
30 of 35
May 27, 2011
Electrical Characteristics
tFALL
tRISE
32-bit ARM Cortex™-M3 MCU
HT32F1251/51B/52/53
SPI Characteristics
Table 19. SPI Characteristics
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
fSCK
SCK clock frequency
—
—
—
fPCLK/4
MHz
tSCK(H)
SCK clock high time
—
fPCLK/8
—
—
ns
tSCK(L)
SCK clock low time
—
fPCLK/8
—
—
ns
tV(MO)
Data output valid time
—
—
—
5
ns
tH(MO)
Data output hold time
—
2
—
—
ns
tSU(MI)
Data input setup time
—
5
—
—
ns
tH(MI)
Data input hold time
—
5
—
—
ns
SPI Slave mode
tSU(SEL)
SEL enable setup time
—
4 tPCLK
—
—
ns
tH(SEL)
SEL enable hold time
—
2 tPCLK
—
—
ns
tA(SO)
Data output access time
—
—
—
3 tPCLK
ns
tDIS(SO)
Data output disable time
—
—
—
10
ns
tV(SO)
Data output valid time
—
—
—
25
ns
tH(SO)
Data output hold time
—
15
—
—
ns
tSU(SI)
Data input setup time
—
5
—
—
ns
tH(SI)
Data input hold time
—
4
—
—
ns
tSCK
SCK (CPOL = 0)
tSCK(H)
tSCK(L)
SCK (CPOL = 1)
tV(MO)
MOSI
DATA VALID
tSU(MI)
MISO
MOSI
MISO
DATA VALID
DATA VALID
tH(MI)
CPHA = 1
DATA VALID
DATA VALID
tV(MO)
tH(MO)
DATA VALID
tSU(MI)
tH(MO)
DATA VALID
DATA VALID
DATA VALID
tH(MI)
DATA VALID
CPHA = 0
DATA VALID
DATA VALID
Figure 7. SPI Timing Diagram – SPI Master Mode
Rev. 1.00
31 of 35
May 27, 2011
Electrical Characteristics
SPI Master mode
32-bit ARM Cortex™-M3 MCU
HT32F1251/51B/52/53
SEL
tSU(SEL)
tH(SEL)
tSCK
SCK
(CPOL=0)
tSCK(L)
SCK
(CPOL=1)
tSU(SI)
MOSI
LSB/MSB IN
MSB/LSB IN
tA(SO)
MISO
tH(SI)
tV(SO)
tDIS(SO)
tH(SO)
MSB/LSB OUT
LSB/MSB OUT
Figure 8. SPI Timing Diagram – SPI Slave Mode and CPHA=1
Rev. 1.00
32 of 35
May 27, 2011
Electrical Characteristics
tSCK(H)
32-bit ARM Cortex™-M3 MCU
HT32F1251/51B/52/53
5
Package Information
Package Information
48-pin
LQFP (7mmx7mm) Outline Dimensions
48-pin LQFP (7mm7mm) Outline Dimensions
Package Information
Symbol
Dimensions in inch
Min.
Nom.
Max.
A
0.350
0.272
Dimensions in inch
0.358
SymbolB
0.280
A
B
C
D
E
C
D
E
F
G
0.350
Nom.
0.350
0.358
0.272
0.280
0.020
―
0.008
―
0.057
―
0.272
―
0.350
0.272
0.053
Max.
0.358
0.280
0.358
0.280
H
―
0.020
F
I
―
0.008
0.004
―
G
J
0.053
0.018
―
0.057
0.030
H
K
―
0.004
―
0.063
0.008
― 0
0.004
7 —
I
J
0.018
K Symbol
0.004
α
A
B
Rev. 1.00
Min.
―
Dimensions in mm
―
―
0.063
0.030
0.008
Min.
Nom.
Max.
8.90
9.10
6.90
7.10
0°
―
7°
C
8.90
9.10
D
6.90
7.10
E
0.50
F
0.20
G
1.35
1.45
H
1.60
I
0.10
J
0.45
0.75
K
0.10
0.20
0
7
33 of 35
May 27, 2011
32-bit ARM Cortex™-M3 MCU
HT32F1251/51B/52/53
Symbol
A
Min.
Nom.
Max.
8.90
―
9.10
B
6.90
―
7.10
C
8.90
―
9.10
D
6.90
―
7.10
E
―
0.50
―
F
―
0.20
―
G
1.35
―
1.45
H
―
―
1.60
I
—
0.10
—
J
0.45
―
0.75
K
0.10
―
0.20
α
0°
―
7°
34 of 35
May 27, 2011
Package Information
Rev. 1.00
Dimensions in mm
32-bit ARM Cortex™-M3 MCU
HT32F1251/51B/52/53
Package Information
Holtek Semiconductor Inc. (Headquarters)
No.3, Creation Rd. II, Science Park, Hsinchu, Taiwan
Tel: 886-3-563-1999
Fax: 886-3-563-1189
http://www.holtek.com.tw
Holtek Semiconductor Inc. (Taipei Sales Office)
4F-2, No. 3-2, YuanQu St., Nankang Software Park, Taipei 115, Taiwan
Tel: 886-2-2655-7070
Fax: 886-2-2655-7373
Fax: 886-2-2655-7383 (International sales hotline)
Holtek Semiconductor Inc. (Shenzhen Sales Office)
5F, Unit A, Productivity Building, No.5 Gaoxin M 2nd Road, Nanshan District, Shenzhen, China 518057
Tel: 86-755-8616-9908, 86-755-8616-9308
Fax: 86-755-8616-9722
Holtek Semiconductor (USA), Inc. (North America Sales Office)
46729 Fremont Blvd., Fremont, CA 94538, USA
Tel: 1-510-252-9880
Fax: 1-510-252-9885
http://www.holtek.com
Copyright© 2011 by HOLTEK SEMICONDUCTOR INC.
The information appearing in this Data Sheet is believed to be accurate at the time of publication. However,
Holtek assumes no responsibility arising from the use of the specifications described. The applications
mentioned herein are used solely for the purpose of illustration and Holtek makes no warranty or
representation that such applications will be suitable without further modification, nor recommends the use
of its products for application that may present a risk to human life due to malfunction or otherwise. Holtek's
products are not authorized for use as critical components in life support devices or systems. Holtek reserves
the right to alter its products without prior notification. For the most up-to-date information, please visit our
web site at http://www.holtek.com.tw.
Rev. 1.00
35 of 35
May 27, 2011