PRELIMINARY Integrated Circuit Systems, Inc. ICS83056I-01 6-BIT, 2:1, SINGLE-ENDED MULTIPLEXER GENERAL DESCRIPTION FEATURES The ICS83056I-01 is a 6-bit, 2:1, Single-ended Multiplexer and a member of the HiPerClockS™famHiPerClockS™ ily of High Performance Clock Solutions from ICS. The ICS83056I-01 has two selectable single-ended clock inputs and six single-ended clock outputs. The output has a VDDO pin which may be set at 3.3V, 2.5V, or 1.8V, making the device ideal for use in voltage translation applications. An output enable pin places the output in a high impedance state which may be useful for testing or debug. Possible applications include systems with up to 6 transceivers which need to be independently set for different rates. For example, a board may have six transceivers, each of which need to be independently configured for 1 Gigabit Ethernet or 1 Gigabit Fibre Channel rates. Another possible application may require the ports to be independently set for FEC (Forward Error Correction) or non-FEC rates. The device operates up to 250MHz and is packaged in a 20 TSSOP. • 6-bit, 2:1 single-ended multiplexer ICS • Nominal output impedance: 15Ω (VDDO =3 .3V) • Maximum output frequency: 250MHz • Propagation delay: 2.5ns (typical) • Input skew: 45ps (typical) • Part-to-part skew: TBD • Additive phase jitter, RMS (12KHz - 20MHz): 0.07ps (typical) • Operating supply modes: VDD/VDDO 3.3V/3.3V 3.3V/2.5V 3.3V/1.8V 2.5V/2.5V 2.5V/1.8V • -40°C to 85°C ambient operating temperature BLOCK DIAGRAM PIN ASSIGNMENT SEL5 Q5 VDDO GND Q4 SEL4 CLK1 VDD Q3 SEL3 SEL0 Pulldown Pulldown CLK0 0 Q0 Pulldown CLK1 1 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 SEL0 Q0 VDDO GND Q1 SEL1 CLK0 OE Q2 SEL2 ICS83056I-01 0 20-Lead TSSOP 6.5mm x 4.4mm x 0.92mm package body G Package Top View Q5 1 SEL5 Pulldown OE Pullup The Preliminary Information presented herein represents a product in prototyping or pre-production. The noted characteristics are based on initial product characterization. Integrated Circuit Systems, Incorporated (ICS) reserves the right to change any circuitry or specifications without notice. 83056AGI-01 www.icst.com/products/hiperclocks.html 1 REV. A FEBRUARY 7, 2005 PRELIMINARY Integrated Circuit Systems, Inc. ICS83056I-01 6-BIT, 2:1, SINGLE-ENDED MULTIPLEXER TABLE 1. PIN DESCRIPTIONS Number 1, 6 10, 11 15, 20 2, 5, 9, 12, 16, 19 3, 18 Name SEL5, SEL4, SEL3, SEL2, SEL1, SEL0 Q5, Q4, Q3, Q2, Q1, Q0 VDDO Type Power Output supply pin. 4, 17 GND Power Power supply ground. 7, 14 CLK1, CLK0 Input Input Description Pulldown Clock select input. See Control Input Function Table. LVCMOS / LVTTL interface levels. Single-ended clock output. LVCMOS/LVTTL interface levels. Output Pulldown Single-ended clock inputs. LVCMOS/LVTTL interface levels. Core supply pin. Output enable. When LOW, outputs are in HIGH impedance state. 13 OE Input Pullup When HIGH, outputs are active. LVCMOS / LVTTL interface levels. NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values. 8 Power VDD TABLE 2. PIN CHARACTERISTICS Symbol Parameter Test Conditions Minimum Typical Maximum Units CIN Input Capacitance 4 pF RPULLUP Input Pullup Resistor 51 KΩ RPULLDOWN Input Pulldown Resistor Power Dissipation Capacitance (per output) Output Impedance 51 KΩ 11 pF 15 Ω C PD ROUT TABLE 3. CONTROL INPUT FUNCTION TABLE Control Inputs SEL3 SEL2 0 0 SEL5 0 SEL4 0 0 0 0 0 0 0 SEL1 0 S E L0 0 Q5 CLK0 Q4 CLK0 Outputs Q3 Q2 CLK0 CLK0 0 0 1 CLK0 CLK0 CLK0 CLK0 CLK0 CLK1 0 1 0 CLK0 CLK0 CLK0 CLK0 CLK1 CLK0 • • • Q1 CLK0 Q0 CLK0 • • • 1 1 1 1 0 1 CLK1 CLK1 CLK1 CLK1 CLK0 CLK1 1 1 1 1 1 0 CLK1 CLK1 CLK1 CLK1 CLK1 CLK0 1 1 1 1 1 1 CLK1 CLK1 CLK1 CLK1 CLK1 CLK1 83056AGI-01 www.icst.com/products/hiperclocks.html 2 REV. A FEBRUARY 7, 2005 PRELIMINARY Integrated Circuit Systems, Inc. ICS83056I-01 6-BIT, 2:1, SINGLE-ENDED MULTIPLEXER ABSOLUTE MAXIMUM RATINGS Supply Voltage, VDD 4.6V Inputs, VI -0.5V to VDD + 0.5 V Outputs, VO -0.5V to VDDO + 0.5V Package Thermal Impedance, θJA 73.2°C/W (0 lfpm) Storage Temperature, TSTG -65°C to 150°C NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VDD = 3.3V±5%, VDDO = 3.3V±5%, OR 2.5V±5%, OR 1.8V±0.2V, TA = -40°C TO 85°C Symbol Parameter VDD Core Supply Voltage VDDO Test Conditions Output Supply Voltage Minimum Typical Maximum Units 3.135 3.3 3.465 V 3.135 3.3 3.465 V 2.375 2.5 2.625 V 1.6 1.8 2.0 V IDD Power Supply Current 32 mA IDDO Output Supply Current 4 mA TABLE 4B. POWER SUPPLY DC CHARACTERISTICS, VDD = 2.5V±5%, VDDO = 2.5V±5%, OR 1.8V±0.2V, TA = -40°C TO 85°C Symbol Parameter VDD Core Supply Voltage VDDO Output Supply Voltage IDD Power Supply Current 30 mA IDDO Output Supply Current 4 mA 83056AGI-01 Test Conditions www.icst.com/products/hiperclocks.html 3 Minimum Typical Maximum Units 2.375 2.5 2.625 V 2.375 2.5 2.625 V 1.6 1.8 2.0 V REV. A FEBRUARY 7, 2005 PRELIMINARY Integrated Circuit Systems, Inc. ICS83056I-01 6-BIT, 2:1, SINGLE-ENDED MULTIPLEXER TABLE 4C. LVCMOS/LVTTL DC CHARACTERISTICS, TA = -40°C TO 85°C Symbol Parameter CLK0, CLK1 VIH Input High Voltage OE, SEL0:SEL5 CLK0, CLK1 VIL IIH IIL VOH VOL Input Low Voltage OE, SEL0:SEL5 Input High Current Input Low Current CLK0, CLK1, SEL0:SEL5 OE CLK0, CLK1, SEL0:SEL5 OE Output HighVoltage Output Low Voltage Test Conditions Minimum Maximum Units VDD = 3.3V ± 5% 2 Typical VDD + 0.3 V VDD = 2.5V ± 5% 1.7 VDD + 0.3 V VDD = 3.3V ± 5% 2 VDD + 0.3 V VDD = 2.5V ± 5% 1.7 VDD + 0.3 V VDD = 3.3V ± 5% -0.3 1.3 V VDD = 2.5V ± 5% -0.3 0.7 V VDD = 3.3V ± 5% -0.3 1.3 V VDD = 2.5V ± 5% -0.3 0.7 V VDD = 3.3V or 2.5V ± 5% 150 µA VDD = 3.3V or 2.5V ± 5% 5 µA VDD = 3.3V or 2.5V ± 5% -5 µA VDD = 3.3V or 2.5V ± 5% -150 µA VDDO = 3.3V ± 5%; NOTE 1 2.6 V VDDO = 2.5V ± 5%; NOTE 1 1.8 V VDDO = 1.8V ± 0.2V; NOTE 1 VDD - 0.3 V VDDO = 3.3V ± 5%; NOTE 1 0.5 V VDDO = 2.5V ± 5%; NOTE 1 0.45 V VDDO = 1.8V ± 0.2V; NOTE 1 0.35 V NOTE 1: Outputs terminated with 50Ω to VDDO/2. See Parameter Measurement section, "Load Test Circuit" diagrams. TABLE 5A. AC CHARACTERISTICS, VDD = VDDO = 3.3V ± 5%, TA = -40°C TO 85°C Symbol Parameter fMAX tpLH tpHL t sk(i) t sk(pp) Test Conditions Output Frequency Propagation Delay, Low to High; NOTE 1 Propagation Delay, High to Low; NOTE 1 Input Skew; NOTE 5 Minimum Typical Maximum Units 250 MHz 2.5 ns 2.65 ns 45 ps TBD ps Integration Range: 12KHz - 20MHz 0.07 ps 20% to 80% 535 ps 50 % tR / tF Par t-to-Par t Skew; NOTE 2, 5 Buffer Additive Phase Jitter, RMS; refer to Additive Phase Jitter section, NOTE 4 Output Rise/Fall Time odc Output Duty Cycle t EN Output Enable Time; NOTE 3 5 ns tDIS Output Disable Time; NOTE 3 5 ns tjit @100MHz 45 MUXISOL MUX Isolation NOTE 1A: Measured from VDD/2 of the input to VDDO/2 of the output. NOTE 2: Defined as skew between outputs on different devices operating a the same supply voltages and with equal load conditions. Using the same type of input on each device, the output is measured at VDDO/2. NOTE 3: These parameters are guaranteed by characterization. Not tested in production. NOTE 4: Driving only one input clock. NOTE 5: This parameter is defined in accordance with JEDEC Standard 65. 83056AGI-01 www.icst.com/products/hiperclocks.html 4 dB REV. A FEBRUARY 7, 2005 PRELIMINARY Integrated Circuit Systems, Inc. ICS83056I-01 6-BIT, 2:1, SINGLE-ENDED MULTIPLEXER TABLE 5B. AC CHARACTERISTICS, VDD = 3.3V ± 5%, VDDO = 2.5V ± 5%, TA = -40°C TO 85°C Symbol Parameter fMAX tpLH tpHL t sk(i) t sk(pp) Test Conditions Minimum Output Frequency Propagation Delay, Low to High; NOTE 1 Propagation Delay, High to Low; NOTE 1 Input Skew; NOTE 5 Typical Maximum Units 250 MHz 2.7 ns 2.7 ns 38 ps TBD ps Integration Range: 12KHz - 20MHz 0.04 ps 20% to 80% 550 ps 50 % tR / tF Par t-to-Par t Skew; NOTE 2, 5 Buffer Additive Phase Jitter, RMS; refer to Additive Phase Jitter section, NOTE 4 Output Rise/Fall Time odc Output Duty Cycle tEN Output Enable Time; NOTE 3 5 ns tDIS Output Disable Time; NOTE 3 5 ns tjit @100MHz 45 MUXISOL MUX Isolation NOTE 1A: Measured from VDD/2 of the input to VDDO/2 of the output. NOTE 2: Defined as skew between outputs on different devices operating a the same supply voltages and with equal load conditions. Using the same type of input on each device, the output is measured at VDDO/2. NOTE 3: These parameters are guaranteed by characterization. Not tested in production. NOTE 4: Driving only one input clock. NOTE 5: This parameter is defined in accordance with JEDEC Standard 65. dB TABLE 5C. AC CHARACTERISTICS, VDD = 3.3V ± 5%, VDDO = 1.8V ± 0.2V, TA = -40°C TO 85°C Symbol Parameter fMAX tpLH tpHL t sk(i) t sk(pp) tjit tR / tF Test Conditions Output Frequency Propagation Delay, Low to High; NOTE 1 Propagation Delay, High to Low; NOTE 1 Input Skew; NOTE 5 Par t-to-Par t Skew; NOTE 2, 5 Buffer Additive Phase Jitter, RMS; refer to Additive Phase Jitter section, NOTE 4 Output Rise/Fall Time Minimum Typical Maximum Units 250 MHz 3 ns 3 ns 38 ps TBD ps Integration Range: 12KHz - 20MHz 0.05 ps 20% to 80% 595 ps odc Output Duty Cycle t EN Output Enable Time; NOTE 3 50 5 % tDIS Output Disable Time; NOTE 3 5 @100MHz 45 MUXISOL MUX Isolation NOTE 1A: Measured from VDD/2 of the input to VDDO/2 of the output. NOTE 2: Defined as skew between outputs on different devices operating a the same supply voltages and with equal load conditions. Using the same type of input on each device, the output is measured at VDDO/2. NOTE 3: These parameters are guaranteed by characterization. Not tested in production. NOTE 4: Driving only one input clock. NOTE 5: This parameter is defined in accordance with JEDEC Standard 65. 83056AGI-01 www.icst.com/products/hiperclocks.html 5 ns ns dB REV. A FEBRUARY 7, 2005 PRELIMINARY Integrated Circuit Systems, Inc. ICS83056I-01 6-BIT, 2:1, SINGLE-ENDED MULTIPLEXER TABLE 5D. AC CHARACTERISTICS, VDD = VDDO = 2.5V ± 5%, TA = -40°C TO 85°C Symbol Parameter fMAX tpLH tpHL t sk(i) t sk(pp) Test Conditions Minimum Output Frequency Propagation Delay, Low to High; NOTE 1 Propagation Delay, High to Low; NOTE 1 Input Skew; NOTE 5 Typical Maximum Units 250 MHz 2.7 ns 2.9 ns 45 ps TBD ps Integration Range: 12KHz - 20MHz 0.10 ps 20% to 80% 540 ps 50 % tR / tF Par t-to-Par t Skew; NOTE 2, 5 Buffer Additive Phase Jitter, RMS; refer to Additive Phase Jitter section, NOTE 4 Output Rise/Fall Time odc Output Duty Cycle tEN Output Enable Time; NOTE 3 5 ns tDIS Output Disable Time; NOTE 3 5 ns tjit @100MHz 45 MUXISOL MUX Isolation NOTE 1A: Measured from VDD/2 of the input to VDDO/2 of the output. NOTE 2: Defined as skew between outputs on different devices operating a the same supply voltages and with equal load conditions. Using the same type of input on each device, the output is measured at VDDO/2. NOTE 3: These parameters are guaranteed by characterization. Not tested in production. NOTE 4: Driving only one input clock. NOTE 5: This parameter is defined in accordance with JEDEC Standard 65. dB TABLE 5E. AC CHARACTERISTICS, VDD = 2.5V ± 5%, VDDO = 1.8V ± -0.2V, TA = -40°C TO 85°C Symbol Parameter fMAX tpLH tpHL t sk(i) t sk(pp) tjit tR / tF Test Conditions Output Frequency Propagation Delay, Low to High; NOTE 1 Propagation Delay, High to Low; NOTE 1 Input Skew; NOTE 5 Par t-to-Par t Skew; NOTE 2, 5 Buffer Additive Phase Jitter, RMS; refer to Additive Phase Jitter section, NOTE 4 Output Rise/Fall Time Minimum Typical Maximum Units 250 MHz 2.9 ns 3 ns 43 ps TBD ps Integration Range: 12KHz - 20MHz 0.07 ps 20% to 80% 590 ps odc Output Duty Cycle tEN Output Enable Time; NOTE 3 50 5 % tDIS Output Disable Time; NOTE 3 5 MUXISOL MUX Isolation @100MHz 45 NOTE 1A: Measured from VDD/2 of the input to VDDO/2 of the output. NOTE 2: Defined as skew between outputs on different devices operating a the same supply voltages and with equal load conditions. Using the same type of input on each device, the output is measured at VDDO/2. NOTE 3: These parameters are guaranteed by characterization. Not tested in production. NOTE 4: Driving only one input clock. NOTE 5: This parameter is defined in accordance with JEDEC Standard 65. 83056AGI-01 www.icst.com/products/hiperclocks.html 6 ns ns dB REV. A FEBRUARY 7, 2005 PRELIMINARY Integrated Circuit Systems, Inc. ICS83056I-01 6-BIT, 2:1, SINGLE-ENDED MULTIPLEXER ADDITIVE PHASE JITTER the 1Hz band to the power in the fundamental. When the required offset is specified, the phase noise is called a dBc value, which simply means dBm at a specified offset from the fundamental. By investigating jitter in the frequency domain, we get a better understanding of its effects on the desired application over the entire time record of the signal. It is mathematically possible to calculate an expected bit error rate given a phase noise plot. The spectral purity in a band at a specific offset from the fundamental compared to the power of the fundamental is called the dBc Phase Noise. This value is normally expressed using a Phase noise plot and is most often the specified plot in many applications. Phase noise is defined as the ratio of the noise power present in a 1Hz band at a specified offset from the fundamental frequency to the power value of the fundamental. This ratio is expressed in decibels (dBm) or a ratio of the power in 0 -10 Additive Phase Jitter (Random) -20 at 155.52MHz (12KHz - 20MHz) = 0.07ps (typical) -30 -40 -50 SSB PHASE NOISE dBc/HZ -60 -70 -80 -90 -100 -110 -120 -130 -140 -150 -160 -170 -180 -190 1k 10k 100k 1M 10M 100M OFFSET FROM CARRIER FREQUENCY (HZ) As with most timing specifications, phase noise measurements have issues. The primary issue relates to the limitations of the equipment. Often the noise floor of the equipment is higher than the noise floor of the device. This is illustrated 83056AGI-01 above. The device meets the noise floor of what is shown, but can actually be lower. The phase noise is dependant on the input source and measurement equipment. www.icst.com/products/hiperclocks.html 7 REV. A FEBRUARY 7, 2005 PRELIMINARY ICS83056I-01 Integrated Circuit Systems, Inc. 6-BIT, 2:1, SINGLE-ENDED MULTIPLEXER PARAMETER MEASUREMENT INFORMATION 1.65V±5% 1.25V±5% SCOPE VDD, VDDO LVCMOS SCOPE VDD, VDDO Qx Qx LVCMOS GND GND -1.65V±5% -1.25V±5% 3.3V CORE/3.3V OUTPUT LOAD AC TEST CIRCUIT 2.5V CORE/2.5V OUTPUT LOAD AC TEST CIRCUIT 2.05V±5% 2.4±0.065V 0.9V±0.1V 1.25V±5% SCOPE V DD VDDO LVCMOS SCOPE V DD VDDO Qx Qx LVCMOS GND GND -0.9V±0.1V -1.25V±5% 3.3V CORE/2.5V OUTPUT LOAD AC TEST CIRCUIT 3.3V CORE/1.8V OUTPUT LOAD AC TEST CIRCUIT 1.6V±0.025V 0.9V±0.1V Part 1 SCOPE VDD VDDO LVCMOS Qx V DDO 2 Qx Part 2 GND Qy V DDO 2 t sk(pp) -0.9V±0.1V 2.5 CORE/1.8V OUTPUT LOAD AC TEST CIRCUIT 83056AGI-01 PART-TO-PART SKEW www.icst.com/products/hiperclocks.html 8 REV. A FEBRUARY 7, 2005 PRELIMINARY Integrated Circuit Systems, Inc. 6-BIT, 2:1, SINGLE-ENDED MULTIPLEXER VDD CLK0, CLK1 ICS83056I-01 80% 80% tR tF 2 VDDO Clock Outputs 2 tpLH Q0:Q5 PROPAGATION DELAY 20% 20% OUTPUT RISE/FALL TIME CLKx V DDO 2 Q0:Q5 Q0:Q5 Pulse Width tPD1 t odc = PERIOD t PW t PERIOD CLKy Q0:Q5 tPD2 INPUT SKEW 83056AGI-01 OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD www.icst.com/products/hiperclocks.html 9 REV. A FEBRUARY 7, 2005 PRELIMINARY ICS83056I-01 Integrated Circuit Systems, Inc. 6-BIT, 2:1, SINGLE-ENDED MULTIPLEXER RELIABILITY INFORMATION TABLE 5. θJAVS. AIR FLOW TABLE FOR 20 LEAD TSSOP θJA by Velocity (Linear Feet per Minute) Single-Layer PCB, JEDEC Standard Test Boards Multi-Layer PCB, JEDEC Standard Test Boards 0 200 500 114.5°C/W 73.2°C/W 98.0°C/W 66.6°C/W 88.0°C/W 63.5°C/W NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs. TRANSISTOR COUNT The transistor count for ICS83056I-01 is: 967 83056AGI-01 www.icst.com/products/hiperclocks.html 10 REV. A FEBRUARY 7, 2005 PRELIMINARY Integrated Circuit Systems, Inc. PACKAGE OUTLINE - G SUFFIX ICS83056I-01 6-BIT, 2:1, SINGLE-ENDED MULTIPLEXER FOR 20 LEAD TSSOP TABLE 6. PACKAGE DIMENSIONS Millimeters SYMBOL MIN MAX N 20 A -- 1.20 A1 0.05 0.15 A2 0.80 1.05 b 0.19 0.30 c 0.09 0.20 D 6.40 E E1 6.60 6.40 BASIC 4.30 e 4.50 0.65 BASIC L 0.45 0.75 α 0° 8° aaa -- 0.10 Reference Document: JEDEC Publication 95, MO-153 83056AGI-01 www.icst.com/products/hiperclocks.html 11 REV. A FEBRUARY 7, 2005 PRELIMINARY Integrated Circuit Systems, Inc. ICS83056I-01 6-BIT, 2:1, SINGLE-ENDED MULTIPLEXER TABLE 7. ORDERING INFORMATION Part/Order Number ICS83056AGI-01 ICS83056AGI-01 Marking ICS83056AI01 ICS83056AI01 Package 20 Lead TSSOP 20 Lead TSSOP Shipping Packaging tube 2500 tape & reel Temperature -40°C to 85°C -40°C to 85°C The aforementioned trademark, HiPerClockS™ is a trademark of Integrated Circuit Systems, Inc. or its subsidiaries in the United States and/or other countries. While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial and industrial applications. Any other applications such as those requiring high reliability or other extraordinary environmental requirements are not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life support devices or critical medical instruments. 83056AGI-01 www.icst.com/products/hiperclocks.html 12 REV. A FEBRUARY 7, 2005