INTEL 243658-020

Intel® Celeron® Processor
up to 1.10 GHz
Datasheet
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Available at 1.10 GHz, 1 GHz, 950 MHz,
900 MHz, 850 MHz, 800 MHz, 766 MHz,
733 MHz, 700 MHz, 667 MHz, 633 MHz,
600 MHz, 566 MHz, 533 MHz,
533A MHz, 500 MHz, 466 MHz,
433 MHz, 400 MHz, 366 MHz, 333 MHz,
and 300A MHz core frequencies with
128 KB level-two cache (on die); 300 MHz
and 266 MHz core frequencies without
level-two cache.
Intel’s latest Celeron® processors in the
FC-PGA/FC-PGA2 package are
manufactured using the advanced 0.18
micron technology.
Binary compatible with applications
running on previous members of the Intel
microprocessor line.
Dynamic execution microarchitecture.
Operates on a 100/66 MHz, transactionoriented system bus.
Specifically designed for uni-processor
based Value PC systems, with the
capabilities of MMX™ technology.
Power Management capabilities.
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Optimized for 32-bit applications running
on advanced 32-bit operating systems.
Uses cost-effective packaging technology.
— Single Edge Processor (S.E.P.) Package
to maintain compatibility with SC242
(processor core frequencies (MHz):
266, 300, 300A, 333, 366, 400, 433).
— Plastic Pin Grid Array (PPGA) Package
(processor core frequencies (MHz):
300A, 333, 366, 400, 433, 466, 500,
533).
— Flip-Chip Pin Grid Array (FC-PGA /
FC-PGA2) Package (processor core
frequencies (MHz); 533A, 566, 600,
633, 667, 700, 733, 766, 800, 850, 900,
950); (GHz); 1, 1.10
Integrated high-performance 32 KB
instruction and data, nonblocking, levelone cache: separate 16 KB instruction and
16 KB data caches.
Integrated thermal diode.
The Intel® Celeron® processor is designed for uni-processor based Value PC desktops and is
binary compatible with previous generation Intel architecture processors. The Celeron processor
provides good performance for applications running on advanced operating systems such as
Microsoft* Windows*98, Windows NT*, Windows* 2000, Windows XP* and Linux*. This is
achieved by integrating the best attributes of Intel processors—the dynamic execution
performance of the P6 microarchitecture plus the capabilities of MMX™ technology—bringing
a balanced level of performance to the Value PC market segment. The Celeron processor offers
the dependability you would expect from Intel at an exceptional value. Systems based on
Celeron processors also include the latest features to simplify system management and lower the
cost of ownership for small business and home environments.
FC-PGA2 Package
FC-PGA Package
PPGA Package
S.E.P. Package
Document Number: 243658-020
January 2002
Information in this document is provided in connection with Intel® products. No license, express or implied, by estoppel or otherwise, to any intellectual
property rights is granted by this document. Except as provided in Intel’s Terms and Conditions of Sale for such products, Intel assumes no liability
whatsoever, and Intel disclaims any express or implied warranty, relating to sale and/or use of Intel products including liability or warranties relating to
fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. Intel products are not
intended for use in medical, life saving, or life sustaining applications.
Intel may make changes to specifications and product descriptions at any time, without notice.
Designers must not rely on the absence or characteristics of any features or instructions marked "reserved" or "undefined." Intel reserves these for
future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them.
The Intel® Celeron® processor may contain design defects or errors known as errata which may cause the product to deviate from published specifications. Current characterized errata are available on request.
Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order.
Copies of documents which have an ordering number and are referenced in this document, or other Intel literature, may be obtained by calling
1-800-548-4725 or by visiting Intel’s website at http://www.intel.com.
Intel, Celeron, Pentium, MMX and the Intel logo are trademarks or registered trademarks of Intel Corporation or its subsidiaries in the United States
and other countries.
*Other names and brands may be claimed as the property of others.
Copyright© 1996–2002, Intel Corporation
Datasheet
Intel® Celeron® Processor up to 1.10 GHz
Contents
1.0
Introduction.......................................................................................................................11
1.1
1.2
2.0
Electrical Specifications....................................................................................................15
2.1
2.2
2.3
2.4
2.5
2.6
2.7
2.8
2.9
2.10
2.11
2.12
3.0
System Bus and Vref...........................................................................................15
Clock Control and Low Power States..................................................................15
2.2.1 Normal State—State 1 ...........................................................................16
2.2.2 AutoHALT Power Down State—State 2 .................................................16
2.2.3 Stop-Grant State—State 3 .....................................................................17
2.2.4 HALT/Grant Snoop State—State 4 ........................................................17
2.2.5 Sleep State—State 5..............................................................................17
2.2.6 Deep Sleep State—State 6 ....................................................................18
2.2.7 Clock Control..........................................................................................18
Power and Ground Pins ......................................................................................18
2.3.1 Phase Lock Loop (PLL) Power...............................................................19
Processor Decoupling .........................................................................................19
2.4.1 System Bus AGTL+ Decoupling.............................................................19
Voltage Identification ...........................................................................................20
System Bus Unused Pins....................................................................................21
Processor System Bus Signal Groups ................................................................21
2.7.1 Asynchronous Vs. Synchronous for System Bus Signals ......................23
2.7.2 System Bus Frequency Select Signal (BSEL[1:0]).................................23
Test Access Port (TAP) Connection....................................................................23
Maximum Ratings................................................................................................23
Processor DC Specifications...............................................................................24
AGTL+ System Bus Specifications .....................................................................33
System Bus AC Specifications ............................................................................34
System Bus Signal Simulations........................................................................................52
3.1
3.2
3.3
3.4
Datasheet
Terminology.........................................................................................................11
1.1.1 Package Terminology.............................................................................12
1.1.2 Processor Naming Convention...............................................................13
References ..........................................................................................................14
System Bus Clock (BCLK) Signal Quality Specifications and
Measurement Guidelines ....................................................................................52
AGTL+ Signal Quality Specifications and Measurement Guidelines ..................55
Non-AGTL+ Signal Quality Specifications and Measurement Guidelines...........57
3.3.1 Overshoot/Undershoot Guidelines .........................................................57
3.3.2 Ringback Specification ...........................................................................58
3.3.3 Settling Limit Guideline...........................................................................59
AGTL+ Signal Quality Specifications and Measurement Guidelines
(FC-PGA/FC-PGA2 Packages) ...........................................................................59
3.4.1 Overshoot/Undershoot Guidelines (FC-PGA/FC-PGA2 Packages) .......59
3.4.2 Overshoot/Undershoot Magnitude (FC-PGA/FC-PGA2 Packages) .......59
3.4.3 Overshoot/Undershoot Pulse Duration (FC-PGA/FC-PGA2
Packages) ..............................................................................................60
3.4.4 Activity Factor (FC-PGA/FC-PGA2 Packages) ......................................60
3
Intel® Celeron® Processor up to 1.10 GHz
3.4.5
3.5
4.0
Thermal Specifications and Design Considerations......................................................... 65
4.1
5.0
5.2
5.3
5.4
5.5
6.2
6.3
Mechanical Specifications for the Boxed Intel® Celeron® Processor ................ 110
6.1.1 Mechanical Specifications for the S.E.P. Package............................... 110
6.1.1.1 Boxed Processor Heatsink Weight.......................................... 112
6.1.1.2 Boxed Processor Retention Mechanism ................................. 112
6.1.2 Mechanical Specifications for the PPGA Package............................... 113
6.1.2.1 Boxed Processor Heatsink Weight.......................................... 114
6.1.3 Mechanical Specifications for the FC-PGA/FC-PGA2 Packages......... 114
6.1.3.1 Boxed Processor Heatsink Weight.......................................... 115
Thermal Specifications...................................................................................... 115
6.2.1 Thermal Requirements for the Boxed Intel® Celeron® Processor........ 115
6.2.1.1 Boxed Processor Cooling Requirements ................................ 115
6.2.1.2 Boxed Processor Thermal Cooling Solution Clip .................... 117
Electrical Requirements for the Boxed Intel® Celeron® Processor ................... 117
6.3.1 Electrical Requirements ....................................................................... 117
Processor Signal Description ......................................................................................... 120
7.1
4
S.E.P. Package ................................................................................................... 69
5.1.1 Materials Information.............................................................................. 69
5.1.2
Signal Listing (S.E.P. Package) ............................................................ 70
PPGA Package ................................................................................................... 79
5.2.1 PPGA Package Materials Information.................................................... 79
5.2.2 PPGA Package Signal Listing ................................................................ 81
FC-PGA/FC-PGA2 Packages ............................................................................. 92
5.3.1 FC-PGA Mechanical Specifications ....................................................... 92
5.3.2 Mechanical Specifications (FC-PGA2 Package) .................................... 94
5.3.2.1 Recommended Mechanical Keep-Out Zones
(FC-PGA2 Package) ................................................................. 96
5.3.3 FC-PGA/FC-PGA2 Package Signal List................................................. 97
Processor Markings (PPGA/FC-PGA/FC-PGA2 Packages) ............................. 108
Heatsink Volumetric Keepout Zone Guidelines................................................. 109
Boxed Processor Specifications..................................................................................... 110
6.1
7.0
Thermal Specifications........................................................................................ 65
4.1.1 Thermal Diode........................................................................................ 68
Mechanical Specifications................................................................................................ 69
5.1
6.0
Reading Overshoot/Undershoot Specification Tables
(FC-PGA/FC-PGA2 Packages) .............................................................. 61
3.4.6 Determining if a System meets the Overshoot/Undershoot
Specifications (FC-PGA/FC-PGA2 Packages)....................................... 62
Non-AGTL+ Signal Quality Specifications and Measurement Guidelines........... 64
Signal Summaries ............................................................................................. 126
Datasheet
Intel® Celeron® Processor up to 1.10 GHz
Figures
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Datasheet
Clock Control State Machine...............................................................................16
BCLK to Core Logic Offset ..................................................................................48
BCLK*, PICCLK, and TCK Generic Clock Waveform .........................................49
System Bus Valid Delay Timings ........................................................................49
System Bus Setup and Hold Timings..................................................................49
System Bus Reset and Configuration Timings (For the S.E.P. and
PPGA Packages) ................................................................................................50
System Bus Reset and Configuration Timings (For the
FC-PGA/FC-PGA2 Package) ..............................................................................50
Power-On Reset and Configuration Timings.......................................................51
Test Timings (TAP Connection) ..........................................................................51
Test Reset Timings .............................................................................................51
BCLK, TCK, PICCLK Generic Clock Waveform at the Processor Core Pins .....53
BCLK, TCK, PICCLK Generic Clock Waveform at the Processor
Edge Fingers .......................................................................................................54
Low to High AGTL+ Receiver Ringback Tolerance.............................................56
Non-AGTL+ Overshoot/Undershoot, Settling Limit, and Ringback .....................57
Maximum Acceptable AGTL+ Overshoot/Undershoot Waveform
(FC-PGA/FC-PGA2 Packages) ...........................................................................63
Non-AGTL+ Overshoot/Undershoot, Settling Limit, and Ringback ....................64
Processor Functional Die Layout (CPUID 0686h)...............................................67
Processor Functional Die Layout (up to CPUID 0683h)......................................67
Processor Substrate Dimensions (S.E.P. Package) ...........................................70
Processor Substrate Primary/Secondary Side Dimensions (S.E.P. Package)....70
Package Dimensions (PPGA Package) ..............................................................79
PPGA Package (Pin Side View)..........................................................................81
Package Dimensions (FC-PGA Package)...........................................................92
Package Dimensions (FC-PGA2 Package).........................................................94
Volumetric Keep-Out ...........................................................................................96
Component Keep-Out .........................................................................................96
Package Dimensions (FC-PGA/FC-PGA2 Packages) ........................................97
Top Side Processor Markings (PPGA Package)...............................................108
Top Side Processor Markings (FC-PGA Package) ...........................................108
Top Side Processor Markings (FC-PGA2 Package) .........................................108
Retention Mechanism for the Boxed Intel® Celeron® Processor in the
S.E.P. Package .................................................................................................111
Side View Space Requirements for the Boxed Processor in the S.E.P.
Package ............................................................................................................111
Front View Space Requirements for the Boxed Processor in the S.E.P.
Package ............................................................................................................112
Boxed Intel® Celeron® Processor in the PPGA Package..................................113
Side View Space Requirements for the Boxed Processor in the PPGA
Package ............................................................................................................113
Conceptual Drawing of the Boxed Intel® Celeron® Processor in the
370-Pin Socket (FC-PGA/FC-PGA2 Packages)................................................114
Dimensions of Mechanical Step Feature in Heatsink Base for the
FC-PGA/FC-PGA2 Packages ...........................................................................114
Top View Airspace Requirements for the Boxed Processor in the
S.E.P. Package .................................................................................................115
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Intel® Celeron® Processor up to 1.10 GHz
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Side View Airspace Requirements for the Boxed Intel® Celeron®
Processor in the FC-PGA/FC-PGA2 and PPGA Packages .............................. 116
Volumetric Keepout Requirements for The Boxed Fan Heatsink...................... 116
Clip Keepout Requirements for the 370-Pin (Top View) ................................... 117
Boxed Processor Fan Heatsink Power Cable Connector Description .............. 118
Motherboard Power Header Placement for the S.E.P. Package ...................... 119
Motherboard Power Header Placement Relative to the 370-pin Socket........... 119
Datasheet
Intel® Celeron® Processor up to 1.10 GHz
Tables
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Datasheet
Processor Identification .......................................................................................13
Voltage Identification Definition ...........................................................................20
Intel® Celeron® Processor System Bus Signal Groups.......................................22
Absolute Maximum Ratings................................................................................24
Voltage and Current Specifications .....................................................................25
AGTL+ Signal Groups DC Specifications............................................................31
Non-AGTL+ Signal Group DC Specifications......................................................32
Processor AGTL+ Bus Specifications .................................................................33
System Bus AC Specifications (Clock) at the Processor Edge Fingers
(for S.E.P. Package)............................................................................................35
System Bus AC Specifications (Clock) at the Processor
Core Pins (for Both S.E.P. and PGA Packages) .................................................36
System Bus AC Specifications (SET Clock)........................................................37
Valid Intel® Celeron® Processor System Bus, Core Frequency..........................38
System Bus AC Specifications (AGTL+ Signal Group) at the Processor
Edge Fingers (for S.E.P. Package) .....................................................................39
System Bus AC Specifications (AGTL+ Signal Group) at the Processor
Core Pins (for S.E.P. Package)...........................................................................39
Processor System Bus AC Specifications (AGTL+ Signal Group) at the
Processor Core Pins (for PPGA Package)..........................................................40
System Bus AC Specifications (AGTL+ Signal Group) at the Processor
Core Pins (for FC-PGA/FC-PGA2 Packages) .....................................................40
System Bus AC Specifications (CMOS Signal Group) at the Processor
Edge Fingers (for S.E.P. Package) .....................................................................41
System Bus AC Specifications (CMOS Signal Group) at the Processor
Core Pins (for Both S.E.P., PGA, and FC-PGA/FC-PGA2 Packages)................41
System Bus AC Specifications (CMOS Signal Group) .......................................42
System Bus AC Specifications (Reset Conditions)
(for Both S.E.P. and PPGA Packages) ...............................................................42
System Bus AC Specifications (Reset Conditions) (for the
FC-PGA/FC-PGA2 Packages) ............................................................................42
System Bus AC Specifications (APIC Clock and APIC I/O) at the
Processor Edge Fingers (for S.E.P. Package) ....................................................43
System Bus AC Specifications (APIC Clock and APIC I/O) at the
Processor Core Pins (For S.E.P. and PGA Packages) .......................................44
System Bus AC Specifications (APIC Clock and APIC I/O) ................................45
System Bus AC Specifications (TAP Connection) at the Processor
Edge Fingers (For S.E.P. Package) ....................................................................45
System Bus AC Specifications (TAP Connection) at the Processor
Core Pins (for Both S.E.P. and PPGA Packages)...............................................46
System Bus AC Specifications (TAP Connection) ..............................................47
BCLK Signal Quality Specifications for Simulation at the Processor Core
(for Both S.E.P. and PPGA Packages) ...............................................................52
BCLK/PICCLK Signal Quality Specifications for Simulation at the
Processor Pins (for the FC-PGA/FC-PGA2 Packages).......................................53
BCLK Signal Quality Guidelines for Edge Finger Measurement
(for the S.E.P. Package)......................................................................................54
AGTL+ Signal Groups Ringback Tolerance Specifications at the
Processor Core (For Both the S.E.P. and PPGA Packages) ..............................55
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Intel® Celeron® Processor up to 1.10 GHz
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AGTL+ Signal Groups Ringback Tolerance Specifications at the
Processor Pins (For FC-PGA/FC-PGA2 Packages) ........................................... 55
AGTL+ Signal Groups Ringback Tolerance Guidelines for Edge Finger
Measurement on the S.E.P. Package ................................................................. 56
Signal Ringback Specifications for Non-AGTL+ Signal Simulation at the
Processor Core (S.E.P. and PPGA Packages)................................................... 58
Signal Ringback Guidelines for Non-AGTL+ Signal Edge Finger
Measurement (S.E.P. Package).......................................................................... 58
Signal Ringback Specifications for Non-AGTL+ Signal Simulation at the
Processor Pins (FC-PGA/FC-PGA2 Packages).................................................. 58
Example Platform Information............................................................................. 61
66 MHz AGTL+ Signal Group Overshoot/Undershoot Tolerance at
Processor Pins (FC-PGA/FC-PGA2 Packages).................................................. 62
33 MHz CMOS Signal Group Overshoot/Undershoot Tolerance at
Processor Pins (FC-PGA/FC-PGA2 Packages).................................................. 63
Processor Power for the PPGA and FC-PGA Packages .................................... 66
Intel® Celeron® Processor for the FC-PGA2 Package Thermal Design Power . 67
Thermal Diode Parameters (S.E.P. and PPGA Packages)................................. 68
Thermal Diode Parameters (FC-PGA/FC-PGA2 Packages)............................... 68
Thermal Diode Interface...................................................................................... 68
S.E.P. Package Signal Listing by Pin Number.................................................... 71
S.E.P. Package Signal Listing by Signal Name .................................................. 75
Package Dimensions (PPGA Package) .............................................................. 80
Information Summary (PPGA Package) ............................................................. 80
PPGA Package Signal Listing by Pin Number .................................................... 82
PPGA Package Signal Listing in Order by Signal Name .................................... 87
Package Dimensions (FC-PGA Package) .......................................................... 93
Processor Die Loading Parameters (FC-PGA Package) .................................... 93
Package Dimensions (FC-PGA2 Package) ........................................................ 95
Processor Case Loading Parameters (FC-PGA2 Package) ............................... 95
FC-PGA/FC-PGA2 Signal Listing in Order by Signal Name ............................... 98
FC-PGA/FC-PGA2 Signal Listing in Order by Pin Number ............................... 103
Boxed Processor Fan Heatsink Spatial Dimensions for the S.E.P. Package ... 112
Fan Heatsink Power and Signal Specifications................................................. 118
Alphabetical Signal Reference .......................................................................... 120
Output Signals................................................................................................... 126
Input Signals ..................................................................................................... 127
Input/Output Signals (Single Driver).................................................................. 128
Input/Output Signals (Multiple Driver) ............................................................... 128
Datasheet
Intel® Celeron® Processor up to 1.10 GHz
Revision History
Datasheet
Revision
Date
-020
January 2002
Description
• Added IHS specifications for 900 MHz, 950 MHz, and 1 GHz.
• Added 566 MHz specification for CPUID of 068Ah.
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Intel® Celeron® Processor up to 1.10 GHz
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Datasheet
Intel® Celeron® Processor up to 1.10 GHz
1.0
Introduction
The Intel® Celeron® processor is based on the P6 microarchitecture and is optimized for the Value
PC market segment. The Intel Celeron processor, like the Pentium ® II processor, features a
Dynamic Execution microarchitecture and executes MMX™ technology instructions for enhanced
media and communication performance. The Intel Celeron processor also utilizes multiple lowpower states such as AutoHALT, Stop-Grant, Sleep, and Deep Sleep to conserve power during idle
times.
The Intel Celeron processor is capable of running today’s most common PC applications with up to
4 GB of cacheable memory space. As this processor is intended for Value PC systems, it does not
provide multiprocessor support. The Pentium II and Pentium ® III processors should be used for
multiprocessor system designs.
To be cost-effective at both the processor and system level, the Intel Celeron processor utilizes
cost-effective packaging technologies. They are the S.E.P. (Single-Edge Processor) package, the
PPGA (Plastic Pin Grid Array) package, the FC-PGA (Flip-Chip Pin Grid Array) package, and the
FC-PGA2 (Flip-Chip Pin Grid Array) package. Refer to the Intel® Celeron® Processor
Specification Update for the latest packaging and frequency support information (Order Number
243337).
Note:
1.1
This datasheet describes the Intel Celeron processor for the PPGA package, FC-PGA/FC-PGA2
packages, and the S.E.P. Package versions. Unless otherwise specified, the information in this
document applies to all versions and information on PGA packages, refer to both PPGA and
FC-PGA packages.
Terminology
In this document, a ‘#’ symbol after a signal name refers to an active low signal. This means that a
signal is in the active state (based on the name of the signal) when driven to a low level. For
example, when FLUSH# is low, a flush has been requested. When NMI is high, a nonmaskable
interrupt has occurred. In the case of signals where the name does not imply an active state but
describes part of a binary sequence (such as address or data), the ‘#’ symbol implies that the signal
is inverted. For example, D[3:0] = ‘HLHL’ refers to a hex ‘A’, and D[3:0]# = ‘LHLH’ also refers to
a hex ‘A’ (H= High logic level, L= Low logic level).
The term “system bus” refers to the interface between the processor, system core logic (a.k.a. the
AGPset components), and other bus agents. The system bus is an interface to the processor,
memory, and I/O.
Datasheet
11
Intel® Celeron® Processor up to 1.10 GHz
1.1.1
Package Terminology
The following terms are used often in this document and are explained here for clarification:
• Processor substrate—The structure on which passive components (resistors and capacitors)
are mounted.
• Processor core—The processor’s execution engine.
• S.E.P. Package—Single-Edge Processor Package, which consists of a processor substrate,
processor core, and passive components. This package differs from the S.E.C. Cartridge as this
processor has no external plastic cover, thermal plate, or latch arms.
• PPGA package—Plastic Pin Grid Array package. The package is a pinned laminated printed
circuit board structure.
• FC-PGA — Flip-Chip Pin Grid Array. The FC-PGA uses the same 370-pin zero insertion
force socket (PGA370) as the PPGA. Thermal solutions are attached directly to the back of the
processor core package without the use of a thermal plate or heat spreader.
• FC-PGA2 — Flip Chip Pin Grid Array 2. The FC-PG2A uses the same 370-pin zero insertion
force socket (PGA370) as the PPGA. The FC-PGA2 package contains an Integrated Heat
Spreader that covers the processor die.
• Keepout zone - The area on or near a FC-PGA/FC-PGA2 packaged processor that system
designs can not utilize.
• Keep-in zone - The area of a FC-PGA packaged processor that thermal solutions may utilize.
Additional terms referred to in this and other related documentation:
• SC242—242-contact slot connector. A processor in the S.E.P. Package uses this connector to
interface with a system board.
• 370-pin socket (PGA370)—The zero insertion force (ZIF) socket in which a processor in the
PPGA package will use to interface with a system board.
• Retention mechanism—A mechanical assembly which holds the package in the SC242
connector.
12
Datasheet
Intel® Celeron® Processor up to 1.10 GHz
1.1.2
Processor Naming Convention
A letter(s) is added to certain processors (e.g., 533A MHz) when the core frequency alone may not
uniquely identify the processor. Below is a summary of what each letter means as well as a table
listing all the FC-PGA/FC-PGA2 processors for the PGA370 socket.
Table 1.
Processor Identification
Processor
Core Frequency
System Bus Frequency
(MHz)
CPUID1
300 MHz
300 MHz
66
065xh
300A MHz
300 MHz
66
066xh
366 MHz
366 MHz
66
066xh
400 MHz
400 MHz
66
066xh
433 MHz
433 MHz
66
066xh
466 MHz
466 MHz
66
066xh
500 MHz
500 MHz
66
066xh
533 MHz
533 MHz
66
066xh
533A MHz
533 MHz
66
068xh
566 MHz
566 MHz
66
068xh
600 MHz
600 MHz
66
068xh
633 MHz
633 MHz
66
068xh
667 MHz
667 MHz
66
068xh
700 MHz
700 MHz
66
068xh
733 MHz
733 MHz
66
068xh
766 MHz
766 MHz
66
068xh
800 MHz
800 MHz
100
068xh
850 MHz
850 MHz
100
068xh
900 MHz
900 MHz
100
068xh
950 MHz
950 MHz
100
068xh
1 GHz
1 GHz
100
068xh
1.10 GHz
1.10 MHz
100
068xh
NOTES:
®
1. Refer to the Intel® Celeron Processor Specification Update for the exact CPUID for each processor.
Datasheet
13
Intel® Celeron® Processor up to 1.10 GHz
1.2
References
The reader of this specification should also be familiar with material and concepts presented in the
following documents:
• AP-485, Intel® Processor Identification and the CPUID Instruction (Order Number 241618)1
• AP-589, Design for EMI (Order Number 243334)1
• AP-900, Identifying Support for Streaming SIMD Extensions in the Processor and Operating
System1
• AP-905, Pentium® III Processor Thermal Design Guidelines1
• AP-907, Pentium® III Processor Power Distribution Guidelines1
• Intel® Pentium® III Processor for the PGA370 Socket at 500 MHz to 933 MHz Datasheet
(Order Number 245264)
•
•
•
•
•
Intel® Pentium® III Processor Thermal Metrology for CPUID 068h Family1
Intel® Pentium® III Processor Software Application Development Application Notes1
Intel® Celeron® Processor Specification Update (Order Number 243748)
370-Pin Socket (PGA370) Design Guidelines (Order Number 244410)
Intel® Architecture Software Developer's Manual (Order Number 243193)
— Volume I: Basic Architecture (Order Number 243190)
— Volume II: Instruction Set Reference (Order Number 243191)
— Volume III: System Programming Guide (Order Number 243192)
• Intel® 440EX AGPset Design Guide (Order Number 290637)
• Intel® Celeron® Processor with the Intel® 440LX AGPset Design Guide
(Order Number 245088)
• Intel® 440BX AGPset Design Guide (Order Number 290634)
• Intel® Celeron® Processor with the Intel® 440ZX-66 AGPset Design Guide
(Order Number 245126)
• Intel® Celeron® Processor (PPGA) at 466 MHz Thermal Solutions Guidelines
(Order Number 245156)
Notes:
1. This reference material can be found on the Intel Developer’s Web site located at
http://developer.intel.com.
2. For a complete listing of the Intel® Celeron® processor reference material, refer to the Intel
Developer’s Web site when this processor is formally launched. The Web site is located at
http://developer.intel.com/design/celeron/.
14
Datasheet
Intel® Celeron® Processor up to 1.10 GHz
2.0
Electrical Specifications
2.1
System Bus and VREF
Celeron processor signals use a variation of the low voltage Gunning Transceiver Logic (GTL)
signaling technology. The Intel Celeron processor system bus specification is similar to the GTL
specification, but has been enhanced to provide larger noise margins and reduced ringing. The
improvements are accomplished by increasing the termination voltage level and controlling the
edge rates. Because this specification is different from the standard GTL specification, it is referred
to as Assisted Gunning Transceiver Logic (AGTL+) in this document.
The Celeron processor varies from the Pentium Pro processor in its output buffer implementation.
The buffers that drive the system bus signals on the Celeron processor are actively driven to
VCCCORE for one clock cycle during the low-to-high transition. This improves rise times and
reduces overshoot. These signals should still be considered open-drain and require termination to a
supply that provides the logic-high signal level.
The AGTL+ inputs use differential receivers which require a reference signal (VREF). VREF is used
by the receivers to determine if a signal is a logic-high or a logic-low, and is provided to the
processor core by either the processor substrate (S.E.P. Package) or the motherboard (PGA370
socket). Local VREF copies should be generated on the motherboard for all other devices on the
AGTL+ system bus.
Termination is used to pull the bus up to the high voltage level and to control reflections on the
transmission line. The processor may contain termination resistors (S.E.P. Package, FC-PGA
Package, and FC-PGA2 Package) that provide termination for one end of the Intel Celeron
processor system bus. Otherwise, this termination must exist on the motherboard.
Solutions exist for single-ended termination as well, though this implementation changes system
design and eliminate backwards compatibility for Celeron processors in the PPGA package.
Single-ended termination designs must still provide an AGTL+ termination resistor on the
motherboard for the RESET# signal.
The AGTL+ bus depends on incident wave switching. Therefore timing calculations for AGTL+
signals are based on motherboard flight time as opposed to capacitive deratings. Analog signal
simulation of the Intel Celeron processor system bus, including trace lengths, is highly
recommended when designing a system. See the Pentium® II Processor AGTL+ Layout Guidelines
and the Pentium® II Processor I/O Buffer Models, Quad Format (Electronic Form) for details.
2.2
Clock Control and Low Power States
Celeron processors allow the use of AutoHALT, Stop-Grant, Sleep, and Deep Sleep states to reduce
power consumption by stopping the clock to internal sections of the processor, depending on each
particular state. See Figure 1 for a visual representation of the Intel Celeron processor low power
states.
For the processor to fully realize the low current consumption of the Stop-Grant, Sleep, and Deep
Sleep states, a Model Specific Register (MSR) bit must be set. For the MSR at 02Ah (hex), bit 26
must be set to a ‘1’ (this is the power on default setting) for the processor to stop all internal clocks
during these modes. For more information, see the Pentium® II Processor Developer's Manual
(Order Number 243502).
Datasheet
15
Intel® Celeron® Processor up to 1.10 GHz
2.2.1
Normal State—State 1
This is the normal operating state for the processor.
2.2.2
AutoHALT Power Down State—State 2
AutoHALT is a low power state entered when the processor executes the HALT instruction. The
processor will transition to the Normal state upon the occurrence of SMI#, BINIT#, INIT#, or
LINT[1:0] (NMI, INTR). RESET# will cause the processor to immediately initialize itself.
The return from a System Management Interrupt (SMI) handler can be to either Normal Mode or
the AutoHALT Power Down state. See the Intel Architecture Software Developer's Manual,
Volume III: System Programmer's Guide (Order Number 243192) for more information.
FLUSH# will be serviced during the AutoHALT state, and the processor will return to the
AutoHALT state.
The system can generate a STPCLK# while the processor is in the AutoHALT Power Down state.
When the system deasserts the STPCLK# interrupt, the processor will return execution to the
HALT state.
Figure 1. Clock Control State Machine
2. Auto HALT Power Down State
BCLK running.
Snoops and interrupts allowed.
Snoop
Event
Occurs
Snoop
Event
Serviced
4. Auto HALT Power Down State
BCLK running.
Snoops and interrupts allowed.
HALT Instruction and
HALT Bus Cycle generated
INIT#, BINIT#, INTR, SMI#,
RESET#
STPCLK# Deasserted
and Stop Grant entered
from Auto HALT.
Snoop event occurs
Snoop event serviced
1. Normal State
Normal execution.
STPCLK#
asserted
STPCLK#
deasserted
3. Stop Grant State
BCLK running.
Snoops and interrupts allowed.
SLP#
asserted
SLP#
deasserted
5. Sleep State
BCLK running.
Snoops and interrupts allowed.
BCLK
input
stopped
BCLK
input
restarted
6. Deep Sleep State
BCLK stopped.
No Snoops and interrupts allowed.
16
Datasheet
Intel® Celeron® Processor up to 1.10 GHz
2.2.3
Stop-Grant State—State 3
The Stop-Grant state on the processor is entered when the STPCLK# signal is asserted.
Since the AGTL+ signal pins receive power from the system bus, these pins should not be driven
(allowing the level to return to VTT) for minimum power drawn by the termination resistors in this
state. In addition, all other input pins on the system bus should be driven to the inactive state.
BINIT# will not be serviced while the processor is in Stop-Grant state. The event will be latched
and can be serviced by software upon exit from Stop-Grant state.
FLUSH# will not be serviced during Stop-Grant state.
RESET# will cause the processor to immediately initialize itself, but the processor will stay in
Stop-Grant state. A transition back to the Normal state will occur with the deassertion of the
STPCLK# signal.
A transition to the HALT/Grant Snoop state will occur when the processor detects a snoop on the
system bus (see Section 2.2.4). A transition to the Sleep state (see Section 2.2.5) will occur with the
assertion of the SLP# signal.
While in the Stop-Grant State, SMI#, INIT#, and LINT[1:0] will be latched by the processor, and
only serviced when the processor returns to the Normal State. Only one occurrence of each event
will be recognized upon return to the Normal state.
2.2.4
HALT/Grant Snoop State—State 4
The processor will respond to snoop transactions on the Celeron processor system bus while in
Stop-Grant state or in AutoHALT Power Down state. During a snoop transaction, the processor
enters the HALT/Grant Snoop state. The processor will stay in this state until the snoop on the Intel
Celeron processor system bus has been serviced (whether by the processor or another agent on the
Intel Celeron processor system bus). After the snoop is serviced, the processor will return to the
Stop-Grant state or AutoHALT Power Down state, as appropriate.
2.2.5
Sleep State—State 5
The Sleep state is a very low power state in which the processor maintains its context, maintains
the phase-locked loop (PLL), and has stopped all internal clocks. The Sleep state can only be
entered from Stop-Grant state. Once in the Stop-Grant state, the SLP# pin can be asserted, causing
the processor to enter the Sleep state. The SLP# pin is not recognized in the Normal or AutoHALT
states.
Snoop events that occur while in Sleep State or during a transition into or out of Sleep state will
cause unpredictable behavior.
In the Sleep state, the processor is incapable of responding to snoop transactions or latching
interrupt signals. No transitions or assertions of signals (with the exception of SLP# or RESET#)
are allowed on the system bus while the processor is in Sleep state. Any transition on an input
signal before the processor has returned to Stop-Grant state will result in unpredictable behavior.
If RESET# is driven active while the processor is in the Sleep state, and held active as specified in
the RESET# pin specification, then the processor will reset itself, ignoring the transition through
Stop-Grant State. If RESET# is driven active while the processor is in the Sleep State, the SLP#
and STPCLK# signals should be deasserted immediately after RESET# is asserted to ensure the
processor correctly executes the Reset sequence.
Datasheet
17
Intel® Celeron® Processor up to 1.10 GHz
While in the Sleep state, the processor is capable of entering its lowest power state, the Deep Sleep
state, by stopping the BCLK input. (See Section 2.2.6.) Once in the Sleep state, the SLP# pin can
be deasserted if another asynchronous system bus event occurs. The SLP# pin has a minimum
assertion of one BCLK period.
2.2.6
Deep Sleep State—State 6
The Deep Sleep state is the lowest power state the processor can enter while maintaining context.
The Deep Sleep state is entered by stopping the BCLK input (after the Sleep state was entered from
the assertion of the SLP# pin). The processor is in Deep Sleep state immediately after BLCK is
stopped. It is recommended that the BLCK input be held low during the Deep Sleep State. Stopping
of the BCLK input lowers the overall current consumption to leakage levels.
To re-enter the Sleep state, the BCLK input must be restarted. A period of 1 ms (to allow for PLL
stabilization) must occur before the processor can be considered to be in the Sleep State. Once in
the Sleep state, the SLP# pin can be deasserted to re-enter the Stop-Grant state.
While in Deep Sleep state, the processor is incapable of responding to snoop transactions or
latching interrupt signals. No transitions or assertions of signals are allowed on the system bus
while the processor is in Deep Sleep state. Any transition on an input signal before the processor
has returned to Stop-Grant state will result in unpredictable behavior.
2.2.7
Clock Control
BCLK provides the clock signal for the processor and on die L2 cache. During AutoHALT Power
Down and Stop-Grant states, the processor processes a system bus snoop. The processor does not
stop the clock to the L2 cache during AutoHALT Power Down or Stop-Grant states. Entrance into
the Halt/Grant Snoop state allows the L2 cache to be snooped, similar to the Normal state.
When the processor is in the Sleep or Deep Sleep states, it does not respond to interrupts or snoop
transactions. During the Sleep state, the internal clock to the L2 cache is not stopped. During the
Deep Sleep state, the internal clock to the L2 cache is stopped. The internal clock to the L2 cache
will be restarted only after the internal clocking mechanism for the processor is stable (i.e., the
processor has re-entered Sleep state).
PICCLK should not be removed during the AutoHALT Power Down or Stop-Grant states.
PICCLK can be removed during the Sleep or Deep Sleep states. When transitioning from the Deep
Sleep state to the Sleep state, PICCLK must be restarted with BCLK.
2.3
Power and Ground Pins
There are five pins defined on the S.E.P. Package for voltage identification (VID) and four pins on
the PPGA, FC-PGA, and FC-PGA2 packages. These pins specify the voltage required by the
processor core. These have been added to cleanly support voltage specification variations on
current and future Celeron processors.
For clean on-chip power distribution, Intel Celeron processors in the S.E.P. Package have 27 VCC
(power) and 30 VSS (ground) inputs. The 27 VCC pins are further divided to provide the different
voltage levels to the components. VCCCORE inputs for the processor core account for 19 of the VCC
pins, while 4 VTT inputs (1.5 V) are used to provide a AGTL+ termination voltage to the processor.
For only the S.E.P. Package, one VCC5 pin is provided for Voltage Transient Tools. VCC5 and
VCCCORE must remain electrically separated from each other.
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Intel® Celeron® Processor up to 1.10 GHz
The PPGA package has more power (88) and ground (80) pins than the S.E.P. Package. Of the
power pins, 77 are used for the processor core (VCCCORE) and 8 are used as a AGTL+ reference
voltage (VREF). The other 3 power pins are VCC1.5, VCC2.5 and VCCCMOS and are used for future
processor compatibility.
FC-PGA/FC-PGA2 packages have 77 VCCCORE, 77 ground pins, eight VREF, one VCC1.5, one
VCC2.5, and one VCCCMOS. VCCCORE inputs supply the processor core, including the on-die L2
cache. The VREF inputs are used as the AGTL+ reference voltage for the processor.
The VCCCMOS pin is provided as a feature for future processor support in a flexible design. In such
a design, the VCCCMOS pin is used to provide the CMOS voltage for use by the platform.
Additionally, 2.5 V must be provided to the VCC2.5 input and 1.5 V must be provided to the Vcc1.5
input. The processor routes the CMOS voltage level through the package that it is compatible with.
For example, processors requiring 1.5 V CMOS voltage levels route 1.5 V to the VCCCMOS output.
Each power signal, regardless of package, must meet the specifications stated in Table 4. In
addition, all VCCCORE pins must be connected to a voltage island while all VSS pins have to
connect to a system ground plane. In addition, the motherboard must implement the VTT pins as a
voltage island or large trace. Similarly, all VSS pins must be connected to a system ground plane.
2.3.1
Phase Lock Loop (PLL) Power
It is highly critical that phase lock loop power delivery to the processor meets Intel’s requirements.
A low pass filter is required for power delivery to pins PLL1 and PLL2. This serves as an isolated,
decoupled power source for the internal PLL.
2.4
Processor Decoupling
Due to the large number of transistors and high internal clock speeds, the processor is capable of
generating large average current swings between low and full power states. This causes voltages on
power planes to sag below their nominal values if bulk decoupling is not adequate. Care must be
taken in the board design to ensure that the voltage provided to the processor remains within the
specifications listed in Table 5. Failure to do so can result in timing violations or a reduced lifetime
of the component.
2.4.1
System Bus AGTL+ Decoupling
The S.E.P. Package and FC-PGA/FC-PGA2 packages contain high frequency decoupling
capacitance on the processor substrate, where the PPGA package does not. Therefore, Celeron
processors in the PGA packages require high frequency decoupling on the system motherboard.
Bulk decoupling must be provided on the motherboard for proper AGTL+ bus operation for all
packages. See AP-585, Pentium® II Processor AGTL+ Guidelines (Order Number 243330), AP587, Pentium® II Processor Power Distribution Guidelines (Order Number 243332), and the
Pentium® II Processor Developer's Manual (Order Number 243502) for more information.
Datasheet
19
Intel® Celeron® Processor up to 1.10 GHz
2.5
Voltage Identification
The processor’s voltage identification (VID) pins can be used to automatically select the VCCCORE
voltage from a compatible voltage regulator. There are five VID pins (VID[4:0]) on the S.E.P.
Package, while there are only four (VID[3:0]) on the PGA packages. This is because there are no
Celeron processors in the PGA package that require more than 2.05 V (see Table 2).
VID pins are not signals, but rather are an open or short circuit to VSS on the processor. The
combination of opens and shorts defines the processor core’s required voltage. The VID pins also
allow for compatibility with current and future Intel Celeron processors.
Note that the ‘11111’ (all opens) ID can be used to detect the absence of a processor core in a given
slot (S.E.P. Package only), as long as the power supply used does not affect the VID signals.
Detection logic and pull-ups should not affect VID inputs at the power source (see Section 7.0).
External logic monitoring the VID signals or the voltage regulator may require the VID pins to be
pulled-up. If this is the case, the VID pins should be pulled up to a TTL-compatible level with
external resistors to the power source of the regulator.
The power source chosen must be guaranteed to be stable whenever the voltage regulator’s supply
is stable. This will prevent the possibility of the processor supply going above the specified
VCCCORE in the event of a failure in the supply for the VID lines. In the case of a DC-to-DC
converter, this can be accomplished by using the input voltage to the converter for the VID line
pull-ups. In addition, the power supply must supply the requested voltage or disable itself.
Table 2.
Voltage Identification Definition
VID4
(S.E.P.P. only)
VID3
VID2
VID1
VID0
VCCCORE
0
1
1
1
1
1.30
0
1
1
1
0
1.35
0
1
1
0
1
1.40
0
1
1
0
0
1.45
0
1
0
1
1
1.50
0
1
0
1
0
1.55
0
1
0
0
1
1.60
0
1
0
0
0
1.65
0
0
1
1
1
1.70
0
0
1
1
0
1.75
0
0
1
0
1
1.80
0
0
1
0
0
1.85
0
0
0
1
1
1.90
0
0
0
1
0
1.95
0
0
0
0
1
2.00
0
0
0
0
0
2.05
1
1
1
1
1
No Core4
1
1
1
1
0
2.14
NOTES:
1. 0 = Processor pin connected to VSS.
2. 1 = Open on processor; may be pulled up to TTL VIH on motherboard.
3. The Celeron processor core uses a 2.0 V power source.
4. VID4 applies only to the S.E.P. Package. VID[3:0] applies to both S.E.P. and PGA packages.
20
Datasheet
Intel® Celeron® Processor up to 1.10 GHz
2.6
System Bus Unused Pins
All RESERVED pins must remain unconnected. Connection of these pins to VCCCORE, VSS, or to
any other signal (including each other) can result in component malfunction or incompatibility
with future Celeron processor products. See Section 5.0 for a pin listing of the processor and the
location of each RESERVED pin.
For Intel Celeron processors in the S.E.P. Package, the TESTHI pin must be at a logic-high level
when the core power supply comes up. For more information, please refer to erratum C26 of the
Intel® Celeron® Processor Specification Update (Order Number 243748). Also note that the
TESTHI signal is not available on Intel Celeron processors in the PGA package.
PICCLK must be driven with a valid clock input and the PICD[1:0] lines must be pulled-up to
2.5 V even when the APIC will not be used. A separate pull-up resistor must be provided for each
PICD line.
For reliable operation, always connect unused inputs or bi-directional signals to their deasserted
signal level. The pull-up or pull-down resistor value is system dependent and should be chosen
such that the logic-high (VIH) and logic-low (VIL) requirements are met.
For the S.E.P. Package, unused AGTL+ inputs should not be connected as the package substrate has
termination resistors. On the other hand, the PGA packages do not have AGTL+ termination in
their package and must have any unused AGTL+ inputs terminated through a pull-up resistor. For
designs that intend to only support the FC-PGA/FC-PGA2 processors, unused AGTL+ inputs will
be terminated by the processor’s on-die termination resistors and, thus, do not need to be
terminated on the motherboard. However, the reset pin should always be terminated on the
motherboard.
For unused CMOS inputs, active-low signals should be connected through a pull-up resistor to
meet VIH requirements and active-high signals should be connected through a pull-down resistor to
meet VIL requirements. Unused CMOS outputs can be left unconnected. A resistor must be used
when tying bi-directional signals to power or ground. For any signal pulled to either power or
ground, a resistor will allow for system testability.
2.7
Processor System Bus Signal Groups
To simplify the following discussion, the Celeron processor system bus signals have been
combined into groups by buffer type. All Celeron processor system bus outputs are open drain
and require a high-level source provided externally by the termination or pull-up resistor.
AGTL+ input signals have differential input buffers, which use VREF as a reference signal. AGTL+
output signals require termination to 1.5 V. In this document, the term "AGTL+ Input" refers to the
AGTL+ input group as well as the AGTL+ I/O group when receiving. Similarly, "AGTL+ Output"
refers to the AGTL+ output group as well as the AGTL+ I/O group when driving.
EMI pins (S.E.P. Package only) should be connected to motherboard ground and/or to chassis
ground through zero ohm (0 Ω) resistors. The zero ohm resistors should be placed in close
proximity to the SC242 connector. The path to chassis ground should be short in length and have a
low impedance.
The PWRGOOD, BCLK, and PICCLK inputs can each be driven from ground to 2.5 V. Other
CMOS inputs (A20M#, IGNNE#, INIT#, LINT0/INTR, LINT1/NMI, PREQ#, SMI, SLP#, and
STPCLK#) must be pulled up to VCCCMOS. In addition, the CMOS, APIC, and TAP outputs are
Datasheet
21
Intel® Celeron® Processor up to 1.10 GHz
open drain and should be pulled high to VCCCMOS. This ensures not only correct operation for
current Intel Celeron processors, but compatibility for future Intel Celeron processor products as
well.
The groups and the signals contained within each group are shown in Table 3. Refer to Section 7.0
for descriptions of these signals.
Table 3.
Intel® Celeron® Processor System Bus Signal Groups
Group Name
Signals
AGTL+ Input
BPRI#, DEFER#, RESET#11, RS[2:0]#, TRDY#
AGTL+ Output
PRDY#
AGTL+ I/O
A[31:3]#, ADS#, BNR#, BP[3:2]#, BPM[1:0]#, BR0#8, D[63:0]#, DBSY#, DRDY#, HIT#,
HITM#, LOCK#, REQ[4:0]#,
CMOS Input4
A20M#, FLUSH#, IGNNE#, INIT#, LINT0/INTR, LINT1/NMI, PREQ#, SMI#, SLP#2,
STPCLK#
CMOS Input
PWRGOOD1,9
CMOS Output4
FERR#, IERR#, THERMTRIP#3
System Bus Clock
BCLK9
APIC Clock
PICCLK9
APIC I/O
4
PICD[1:0]
4
TAP Input
TAP Output
TCK, TDI, TMS, TRST#
4
Power/Other5
TDO
CPUPRES#7, EDGCTRL7, EMI6, PLL[2:1]7, SLOTOCC#6, THERMDP, THERMDN,
VCC1.57, VCC2.57, VCCL25, VCC56, VCCCMOS7, VCCCORE, VCOREDET7, VID[3:0]7,
VID[4:0]6, VREF[7:0]7, VSS, VTT14, RTTCTRL12, BSEL[1:0]10, SLEWCTRL13
NOTES:
1. See Section 7.0 for information on the PWRGOOD signal.
2. See Section 7.0 for information on the SLP# signal.
3. See Section 7.0 for information on the THERMTRIP# signal.
4. These signals are specified for 2.5 V operation for S.E.P.P. and PPGA packages; they are specified at 1.5V
operation for the FC-PGA/FC-PGA2 packages.
5. VCCCORE is the power supply for the processor core.
VID[4:0] and VID[3:0] are described in Section 2.0.
VTT is used to terminate the system bus and generate VREF on the processor substrate.
VSS is system ground.
VCC5 is not connected to the Celeron processor. This supply is used for Voltage Transient Tools.
SLOTOCC# is described in Section 7.0.
BSEL is described in Section 2.7.2 and Section 7.0.
EMI pins are described in Section 7.0.
VCCL2 is a Pentium® II processor reserved signal provided to maintain compatibility with the Pentium® II
processor and may be left as a no-connect for “Intel Celeron processor-only” designs.
6. Only applies to Intel Celeron processors in the S.E.P. Package.
7. Only applies to Intel Celeron processors in the PPGA and FC-PGA/FC-PGA2 packages.
8. The BR0# pin is the only BREQ# signal that is bidirectional. See Section 7.0 for more information.
9. These signals are specified for 2.5 V operation.
10.BSEL1 is not used in Celeron processors.
11. RESET# must always be terminated to VTT on the motherboard for PGA packages. On-die termination is not
provided for this signal on FC-PGA/FC-PGA2 packages.
12.For the FC-PGA/FC-PGA2 packages, this signal is used to control the value of the processor on-die
termination resistance. Refer to the specific platform design guide for the recommended pull-down resistor
value.
13.Only applies to Intel Celeron processors in the FC-PGA/FC-PGA2 packages.
14.S.E.P. Package and FC-PGA/FC-PGA2 packages.
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Intel® Celeron® Processor up to 1.10 GHz
2.7.1
Asynchronous Vs. Synchronous for System Bus Signals
All AGTL+ signals are synchronous to BCLK. All of the CMOS, APIC, and TAP signals can be
applied asynchronously to BCLK. All APIC signals are synchronous to PICCLK. All TAP signals
are synchronous to TCK.
2.7.2
System Bus Frequency Select Signal (BSEL[1:0])
The BSEL pins have two functions. First, they can act as outputs and can be used by an external
clock generator to select the proper system bus frequency. Second, they can act as an inputs and
can be used by a system BIOS to detect and report the processor core frequency. See the Intel®
Celeron® Processor with the Intel® 440ZX-66 AGPset Design Guide (Order Number 245126) for
an example implementation of BSEL.
BSEL0 is 3.3 V tolerant for the S.E.P. Package, while it is 2.5 V tolerant on the PPGA package. A
logic-low on BSEL0 is defined as 66 MHz. On the FC-PGA/FC-PGA2 packages a logic low on
both BSEL0 and BSEL1 are defined as 66 MHz and are 3.3V tolerant.
2.8
Test Access Port (TAP) Connection
Due to the voltage levels supported by other components in the Test Access Port (TAP) logic, it is
recommended that the Celeron processor be first in the TAP chain and followed by any other
components within the system. A translation buffer should be used to connect to the rest of the
chain unless one of the other components is capable of accepting a VccCMOS (1.5V or 2.5 V) input.
Similar considerations must be made for TCK, TMS, and TRST#. Two copies of each signal may
be required with each driving a different voltage level.
A Debug Port may be placed at the start and end of the TAP chain with the TDI of the first
component coming from the Debug Port and the TDO from the last component going to the Debug
Port.
2.9
Maximum Ratings
Table 4 contains the Celeron processor stress ratings only. Functional operation at the absolute
maximum and minimum is not implied nor guaranteed. The processor should not receive a clock
while subjected to these conditions. Functional operating conditions are given in the AC and DC
tables. Extended exposure to the maximum ratings may affect device reliability. Furthermore,
although the processor contains protective circuitry to resist damage from static electric discharge,
one should always take precautions to avoid high static voltages or electric fields.
Datasheet
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Intel® Celeron® Processor up to 1.10 GHz
Table 4.
Absolute Maximum Ratings
Symbol
TSTORAGE
Parameter
Min
Max
Unit
–40
85
°C
• PPGA and S.E.P.P.
–0.5
Operating
voltage + 1.0
V
• FC-PGA/FC-PGA2
–0.5
2.1
V
• PPGA and S.E.P.P.
–0.3
VCCCORE + 0.7
V
• FC-PGA/FC-PGA2
VTT - 2.18
2.18
V
7, 8
• PPGA and S.E.P.P.
-0.3
3.3
V
3
• FC-PGA/FC-PGA2
VTT - 2.18
-0.58
2.18
3.18
V
V
7, 8, 9
10
Processor storage temperature
Notes
Any processor supply voltage with
respect to VSS
VCC(All)
1, 2
AGTL+ buffer DC input voltage with
respect to VSS
VinAGTL+
CMOS buffer DC input voltage with
respect to VSS
VinCMOS
IVID
Max VID pin current
5
mA
ISLOTOCC#
Max SLOTOCC# pin current
5
mA
5
ICPUPRES#
Max CPUPRES# pin current
5
mA
6
Mech Max
Edge Fingers5
Mechanical integrity of processor
edge fingers
50
Insertions/
Extractions
4, 5
NOTES:
1. Operating voltage is the voltage to which the component is designed to operate. See Table 5.
2. This rating applies to the VCCCORE, VCC5, and any input (except as noted below) to the processor.
3. Parameter applies to CMOS, APIC, and TAP bus signal groups only.
4. The electrical and mechanical integrity of the processor edge fingers are specified to last for 50 insertion/
extraction cycles.
5. S.E.P. Package Only
6. PGA Packages Only
7. Input voltage can never exceed VSS + 2.8 volts.
8. Input voltage can never go below VTT - 2.18 volts.
9. Parameter applies to CMOS (except BCLK, PICCLK, and PWRGOOD), APIC, and TAP bus signal groups
only for VinCMOS on the FC-PGA/FC-PGA2 Packages only.
10.Parameter applies to CMOS signals BCLK, PICCLK, and PWRGOOD for VinCMOS1.5 on FC-PGA/
FC-PGA2 Package only.
2.10
Processor DC Specifications
The processor DC specifications in this section are defined for the Celeron processor. See
Section 7.0 for signal definitions and Section 5.0 for signal listings.
Most of the signals on the Intel Celeron processor system bus are in the AGTL+ signal group.
These signals are specified to be terminated to 1.5 V. The DC specifications for these signals are
listed in Table 6.
To allow connection with other devices, the Clock, CMOS, APIC, and TAP signals are designed to
interface at non-AGTL+ levels. The DC specifications for these pins are listed in Table 7.
Table 5 through Table 8 list the DC specifications for Intel Celeron processors operating at 66 MHz
Intel Celeron processor system bus frequencies. Specifications are valid only while meeting
specifications for case temperature, clock frequency, and input voltages. Care should be taken to
read all notes associated with each parameter.
24
Datasheet
Intel® Celeron® Processor up to 1.10 GHz
Table 5.
Voltage and Current Specifications (Sheet 1 of 5)
Processor
Symbol
Parameter
Min
Core Freq
Notes
2.00
2, 3, 4
2.00
2, 3, 4
0650h
2.00
2, 3, 4
0651h
2.00
2, 3, 4
0660h
2.00
2, 3, 4
0665h
2.00
2, 3, 4
0660h
2.00
2, 3, 4
0665h
2.00
2, 3, 4
0660h
2.00
2, 3, 4
0665h
2.00
2, 3, 4
0660h
2.00
2, 3, 4
0665h
2.00
2, 3, 4
0660h
2.00
2, 3, 4
0665h
2.00
2, 3, 4
466 MHz
0665h
2.00
2, 3, 4
500 MHz
0665h
2.00
2, 3, 4
533 MHz
0665h
2.00
2, 3, 4
0683h
1.50
2, 3, 4
0686h
1.70
2, 3, 4
0683h
1.50
300A MHz
333 MHz
366 MHz
400 MHz
433 MHz
533A MHz
566 MHz
600 MHz
633 MHz
667 MHz
700 MHz
733 MHz
766 MHz
Datasheet
Unit
0651h
300 MHz
VCC for processor
core
Max
0650h
266 MHz
VCCCORE
Typ
CPUID
0686h
—
1.70
2, 3, 4
—
V
2, 3, 4
068Ah
1.75
2, 3, 20,
25
0683h
1.50
2, 3, 4
0686h
1.70
2, 3, 4
068Ah
1.75
2, 3, 20,
25
0683h
1.65
2, 3, 20
0686h
1.70
2, 3, 20
068Ah
1.75
2, 3, 20
0683h
1.65
2, 3, 20
0686h
1.70
2, 3, 20
068Ah
1.75
2, 3, 20
0683h
1.65
2, 3, 20
2, 3, 20
0686h
1.70
068Ah
1.75
2, 3, 20
0683h
1.65
2, 3, 20
2, 3, 20
0686h
1.70
068Ah
1.75
2, 3, 20
0683h
1.65
2, 3, 20
0686h
1.70
2, 3, 20
068Ah
1.75
2, 3, 20
25
Intel® Celeron® Processor up to 1.10 GHz
Table 5.
Voltage and Current Specifications (Sheet 2 of 5)
Processor
Symbol
Parameter
Min
Core Freq
800 MHz
850 MHz
900 MHz
VCCCORE
VCC for processor
core
1 GHz
1.10 GHz
Notes
1.65
2, 3, 20
1.70
2, 3, 20
068Ah
1.75
2, 3, 20
—
—
0686h
1.70
2, 3, 20
068Ah
1.75
2, 3, 20
—
—
—
—
068Ah
1.75
—
—
—
—
—
—
V
2, 3, 20
—
—
—
—
068Ah
1.75
2, 3, 20
—
—
—
—
—
—
068Ah
1.75
2, 3, 20
—
—
—
—
—
—
068Ah
1.75
2, 3, 20
—
—
Static AGTL+ bus
termination voltage
—
—
1.455
1.50
Transient AGTL+
bus termination
voltage
—
—
1.365
VCC2.518
VCC for VCCCMOS
—
—
VTT
AGTL+ bus
termination voltage
—
Baseboard
Tolerance, Static
Processor core
voltage static
tolerance level at
SC242 pins
Baseboard
Tolerance,
Transient
Processor core
voltage transient
tolerance level at
SC242 pins
VCC1.516
Unit
0686h
AGTL+ input
reference voltage
VREF19
Max
0683h
—
950 MHz
Typ
CPUID
2/ VTT –
3
2/
2%
3VTT
+ 2%
V
± 2%, 11
1.545
V
1.5 ± 3%
1.50
1.365
V
1.5 ± 3%
2.375
2.5
2.625
V
2.5 ± 5%
—
1.365
1.50
1.635
V
1.5 ± 9%5
—
—
–0.070
—
0.100
V
6
—
—
–0.120
—
0.120
V
6
• SC242 edge
fingers
—
—
–0.085
—
0.100
V
7
• PPGA
processor pins
—
—
-0.089
—
0.100
V
8
• FC-PGA/
FC-PGA2
processor pins
—
—
-0.080
—
0.040
V
17
Processor core
voltage static
tolerance level at:
VCCCORE
Tolerance, Static
26
Datasheet
Intel® Celeron® Processor up to 1.10 GHz
Table 5.
Voltage and Current Specifications (Sheet 3 of 5)
Processor
Symbol
Parameter
Min
Typ
Max
Unit
—
–0.140
—
0.140
V
7
—
—
-0.144
—
0.144
V
8
—
—
-0.130
—
—
-0.110
266 MHz
—
8.2
300 MHz
—
9.3
9, 10
300A MHz
—
9.3
9, 10
333 MHz
—
10.1
9, 10
Core Freq
CPUID
• SC242 edge
fingers
—
• PPGA
processor pins
Notes
Processor core
voltage transient
tolerance level at:
VCCCORE
Tolerance,
Transient
• FC-PGA/
FC-PGA2
processor pins
17
24
9, 10
—
11.2
9, 10
12.2
9, 10
433 MHz
—
12.6
9, 10
466 MHz
—
13.4
9, 10
500 MHz
—
14.2
9, 10
533 MHz
—
14.9
9, 10
533A MHz
—
11.4
9, 10
9, 10
633 MHz
667 MHz
700 MHz
733 MHz
766 MHz
800 MHz
850 MHz
Datasheet
V
—
ICC for processor core
Termination voltage
supply current
0.080
400 MHz
600 MHz
IVTT
0.080
366 MHz
566 MHz
ICCCORE
—
—
11.9
068Ah
12.1
9, 10, 25
0686h
12.0
9, 10
068Ah
12.6
9, 10, 25
0686h
12.7
9, 10
068Ah
13.0
—
0686h
A
13.3
9, 10
9, 10
068Ah
13.9
9, 10
0686h
14.0
9, 10
068Ah
14.8
9, 10
0686h
14.6
9, 10
068Ah
15.4
9, 10
0686h
15.5
9, 10
068Ah
16.0
9, 10
0686h
16.0
9, 10
068Ah
16.6
9, 10
0686h
16.2
9, 10
9, 10
068Ah
17.3
900 MHz
068Ah
18.4
9, 10
950 MHz
068Ah
19.4
9, 10
1 GHz
068Ah
20.2
9, 10
1.10 GHz
068Ah
22.6
9, 10
—
—
—
—
2.7
A
11
27
Intel® Celeron® Processor up to 1.10 GHz
Table 5.
Voltage and Current Specifications (Sheet 4 of 5)
Processor
Symbol
Parameter
Min
Core Freq
Typ
266 MHz
1.12
300 MHz
1.15
300A MHz
1.15
333 MHz
1.18
366 MHz
1.21
400 MHz
1.25
433 MHz
1.30
466 MHz
1.35
500 MHz
1.43
533 MHz
1.52
533A MHz
ISGNT
28
ICC Stop-Grant for
processor core
Max
566 MHz
600 MHz
Unit
Notes
CPUID
2.5
—
—
—
6.921
6.921
633 MHz
6.921
667 MHz
6.921
700 MHz
6.921
733 MHz
6.921
766 MHz
6.921
800 MHz
6.921
850 MHz
6.921
900 MHz
6.921
950 MHz
6.921
1 GHz
6.921
1.10 GHz
6.921
A
12
Datasheet
Intel® Celeron® Processor up to 1.10 GHz
Table 5.
Voltage and Current Specifications (Sheet 5 of 5)
Processor
Symbol
Parameter
Min
Core Freq
Typ
266 MHz
ISLP
ICC Sleep for
processor core
Max
0.94
300A MHz
0.94
333 MHz
0.96
366 MHz
0.97
400 MHz
0.99
433 MHz
1.01
466 MHz
1.03
500 MHz
1.09
533 MHz
1.16
533A MHz
2.5
600 MHz
Notes
0.90
300 MHz
566 MHz
Unit
CPUID
—
—
—
6.622
6.922
633 MHz
6.922
667 MHz
6.922
700 MHz
6.922
733 MHz
6.922
766 MHz
6.922
800 MHz
6.922
850 MHz
6.922
900 MHz
6.922
950 MHz
6.922
1 GHz
6.922
1.10 GHz
6.922
A
ICC Deep Sleep for
processor core:
IDSLP
• S.E.P.P and
PPGA
—
—
—
—
0.90
• FC-PGA/
FC-PGA2
—
—
—
—
6.623
• S.E.P.P and
PPGA
—
—
—
—
500
mA
• FC-PGA/
FC-PGA2
—
—
—
—
250
mA
• S.E.P.P
—
—
—
—
20
A/µs
13, 14, 15
• PPGA and
FC-PGA/
FC-PGA2
—
—
—
—
240
A/µs
13, 14
—
—
—
—
8
A/µs
See
Table 8,
Table 20,
Table 22
A
ICC for VCCCMOS
ICCCMOS
Power supply
current slew rate
dICCCORE/dt
dICCVTT/dt
Datasheet
Termination current
slew rate
29
Intel® Celeron® Processor up to 1.10 GHz
NOTES:
1. Unless otherwise noted, all specifications in this table apply to all processor frequencies.
2. VCCCORE and ICCCORE supply the processor core.
3. These voltages are targets only. A variable voltage source should exist on systems in the event that a
different voltage is required.
4. Use the Typical Voltage specification with the Tolerance specifications to provide correct voltage regulation to
the processor.
5. VTT must be held to 1.5 V ± 9%. It is recommended that V TT be held to 1.5 V ± 3% while the Celeron®
processor system bus is idle. This is measured at the processor edge fingers.
6. These are the tolerance requirements, across a 20 MHz bandwidth, at the SC242 connector pin on the
bottom side of the baseboard. The requirements at the SC242 connector pins account for voltage drops
(and impedance discontinuities) across the connector, processor edge fingers, and to the processor core.
VCCCORE must return to within the static voltage specification within 100 µs after a transient event.
7. These are the tolerance requirements, across a 20 MHz bandwidth, at the processor edge fingers. The
requirements at the processor edge fingers account for voltage drops (and impedance discontinuities) at the
processor edge fingers and to the processor core. VCCCORE must return to within the static voltage
specification within 100 µs after a transient event.
8. These are the tolerance requirements, across a 20 MHz bandwidth, at the top of the PPGA package.
VCCCORE must return to within the static voltage specification within 100 µs after a transient event.
9. Max ICCCORE measurements are measured at VCCCORE max voltage (VCCCORE_TYP + maximum static
tolerance), under maximum signal loading conditions.
10.Voltage regulators may be designed with a minimum equivalent internal resistance to ensure that the output
voltage, at maximum current output, is no greater than the nominal (i.e., typical) voltage level of VCCCORE
(VCCCORE_TYP). In this case, the maximum current level for the regulator, ICCCORE_REG, can be reduced from
the specified maximum current ICCCORE_MAX and is calculated by the equation:
ICCCORE_REG = ICCCORE_MAX × VCCCORE_TYP/(VCCCORE_TYP + VCCCORE Tolerance, Transient)
11. The current specified is the current required for a single Intel Celeron processor. A similar amount of current
is drawn through the termination resistors on the opposite end of the AGTL+ bus, unless single-ended
termination is used (see Section 2.1).
12.The current specified is also for AutoHALT state.
13.Maximum values are specified by design/characterization at nominal VCCCORE.
14.Based on simulation and averaged over the duration of any change in current. Use to compute the maximum
inductance tolerable and reaction time of the voltage regulator. This parameter is not tested.
15.dICC/dt specifications are measured and specified at the SC242 connector pins.
16.FC-PGA/FC-PGA2 packages only
17.These are the tolerance requirements across a 20 MHz bandwidth at the FC-PGA/FC-PGA2 socket pins on
the solder side of the motherboard. VCCCORE must return to within the static voltage specification within
100 µs after a transient event.
18.PGA only
19.S.E.P Package and FC-PGA/FC-PGA2 Packages only
20.These processors implement independent VTT and VCCCORE power planes.
21.For processors with CPUID of 0686h, the ISGNT is 2.5 A.
22.For processors with CPUID of 0686h, the ISLP is 2.5 A.
23.For processors with CPUID of 0686h, the IDSLP is 2.2 A.
24.This specification is applicable only for processor frequencies of 933 MHz and above.
25.This Intel® Celeron® processor is a Telecommunications and Embedded Group (TSEG) and Embedded Intel
Architecture Division (EID) product only.
30
Datasheet
Intel® Celeron® Processor up to 1.10 GHz
Table 6.
AGTL+ Signal Groups DC Specifications
Symbol
Parameter
Min
Max
Unit
Notes
• S.E.P.P and PPGA
–0.3
0.82
V
• FC-PGA/FC-PGA2
–0.150
VREF – 0.200
V
9
• S.E.P.P and PPGA
1.22
VTT
V
2, 3
• FC-PGA/FC-PGA2
VREF + 0.200
VTT
V
2, 3
Input Low Voltage
VIL
Input High Voltage
VIH
RON
Buffer On Resistance
16.67
Ω
8
IL
Leakage Current for
inputs, outputs, and I/O
±100
µA
6, 7
NOTES:
1. Unless otherwise noted, all specifications in this table apply to all Celeron processor frequencies and cache
sizes.
2. VIH and VOH for the Intel Celeron processor may experience excursions of up to 200 mV above VTT for a
single system bus clock. However, input signal drivers must comply with the signal quality specifications in
Section 3.0.
3. Minimum and maximum VTT are given in Table 8.
4. Parameter correlated to measurement into a 25 Ω resistor terminated to 1.5 V.
5. IOH for the Intel Celeron processor may experience excursions of up to 12 mA for a single system bus clock.
6. (0 ≤ VIN ≤ 2.0 V +5%) for S.E.P Package and PPGA Package; (0 ≤ VIN ≤ 1.5V +3%) for FC-PGA/FC-PGA2
packages.
7. (0 ≤ VOUT ≤ 2.0 V +5%) for S.E.P Package and PPGA Package; (0 ≤ VOUT ≤ 1.5V +3%) for FC-PGA/
FC-PGA2 packages.
8. Refer to the I/O Buffer Models for IV characteristics.
9. Steady state input voltage must not be above VSS + 1.65 V or below VTT - 1.65 V.
Datasheet
31
Intel® Celeron® Processor up to 1.10 GHz
Table 7.
Non-AGTL+ Signal Group DC Specifications
Symbol
Parameter
Min
Max
Unit
Notes
VIL
Input Low Voltage
–0.3
0.7
V
10
VIH
Input High Voltage
1.7
2.625
V
2.5 V +5% maximum,
Note 10
VIL1.5
Input Low Voltage
–0.150
VREF - 0.200
V
8, 9
VIL2.5
Input Low Voltage
-0.58
0.700
V
7, 9
VIH1.5
Input High Voltage
VREF + 0.200
VTT
V
5, 8, 9
VIH2.5
Input High Voltage
2.0
3.18
V
7, 9
VOL
Output Low Voltage
0.4
V
2
2.625
V
All outputs are opendrain to 2.5 V +5%
VTT
V
6, 8, 9
Output High Voltage
VOH
• S.E.P.P and PPGA
N/A
• FC-PGA/FC-PGA2
Output Low Current
IOL
IL
• S.E.P.P and PPGA
14
mA
• FC-PGA/FC-PGA2
9
mA
9
µA
3, 4, 5, 6
Leakage Current for
Inputs, Outputs, and I/O
±100
NOTES:
1. Unless otherwise noted, all specifications in this table apply to all Celeron processor frequencies.
2. Parameter measured at 14 mA (for use with TTL inputs) for S.E.P Package and PPGA Package. It is 9 mA
for FC-PGA/FC-PGA2 packages.
3. (0 ≤ VIN ≤ 2.5 V +5%) for PPGA package and S.E.P package only.
4. (0 ≤ VOUT ≤ 2.5 V +5%) for PPGA package and S.E.P package only.
5. (0≤ VIN ≤ 1.5V +3%) for FC-PGA/FC-PGA2 packages only.
6. (0≤ VOUT ≤ 1.5V +3%) for FC-PGA/FC-PGA2 packages only.
7. Applies to non-AGTL+ signals BCLK, PICCLK, and PWRGOOD for FC-PGA/FC-PGA2 Packages only.
8. Applies to non-AGTL+ signals except BCLK, PICCLK, and PWRGOOD for FC-PGA/FC-PGA2 packages
only.
9. These values are specified at the processor pins for FC-PGA/FC-PGA2 packages only.
10.S.E.P. package and PPGA package only.
32
Datasheet
Intel® Celeron® Processor up to 1.10 GHz
2.11
AGTL+ System Bus Specifications
It is recommended that the AGTL+ bus be routed in a daisy-chain fashion with termination
resistors to VTT at each end of the signal trace. These termination resistors are placed electrically
between the ends of the signal traces and the VTT voltage supply and generally are chosen to
approximate the substrate impedance. The valid high and low levels are determined by the input
buffers using a reference voltage called VREF. Single ended termination may be possible if trace
lengths are tightly controlled, see the Intel® 440EX AGPset Design Guide (Order Number 290637)
or the Intel® Celeron ® Processor (PPGA) with the Intel® 440LX AGPset Design Guide (Order
Number 245088) for more information.
Table 8 below lists the nominal specification for the AGTL+ termination voltage (VTT). The
AGTL+ reference voltage (VREF) is generated on the processor substrate (S.E.P. Package only) for
the processor core, but should be set to 2/3 VTT for other AGTL+ logic using a voltage divider on
the motherboard. It is important that the motherboard impedance be specified and held to:
• ±20% tolerance (S.E.E.P. and PPGA)
• ±15% tolerance (FC-PGA/FC-PGA2)
It is also important that the intrinsic trace capacitance for the AGTL+ signal group traces is known
and well-controlled. For more details on AGTL+, see the Pentium® II Processor Developer's
Manual (Order Number 243502) and AP-585, Pentium® II Processor AGTL+ Guidelines (Order
Number 243330).
Table 8.
Processor AGTL+ Bus Specifications
Symbol
Parameter
Min
Typ
Max
Units
Notes
1.365
1.50
1.635
V
1.5 V ± 9% 2
1.50
V
4
56
Ω
± 5%
Ω
5
V
± 2% 3
V
6
Bus Termination Voltage
VTT
• S.E.P.P and PPGA
• FC-PGA/FC-PGA2
Termination Resistor
RTT
• S.E.P.P and PPGA
• FC-PGA/FC-PGA2
(on die RTT)
40
130
Bus Reference Voltage
VREF
2
• S.E.P.P and PPGA
• FC-PGA/FC-PGA2
0.950
/3 VTT
2/3 VTT
1.05
NOTES:
1. Unless otherwise noted, all specifications in this table apply to all Celeron processor frequencies.
2. VTT must be held to 1.5 V ± 9%; dICCVTT/dt is specified in Table 5. It is recommended that VTT be held to
1.5 V ± 3% while the Intel Celeron processor system bus is idle. This is measured at the processor edge
fingers.
3. VREF is generated on the processor substrate to be 2/3 VTT nominally with the S.E.P. package. It must be
created on the motherboard for processors in the PPGA package.
4. VTT and Vcc1.5 must be held to 1.5V ±9%. It is required that VTT and Vcc1.5 be held to 1.5 V ±3% while the
processor system bus is idle (static condition). This is measured at the PGA370 socket pins on the bottom
side of the baseboard.
5. The value of the on-die RTT is determined by the resistor value measured by the RTTCTRL signal pin. The
on-die RTT tolerance is ±15% based on the RTTCTRL resistor pull-down of ±1%. See Section 7.0 for more
details on the RTTCTRL signal. Refer to the recommendation guidelines for the specific chipset/processor
combination.
6. VREF is generated on the motherboard and should be 2/3 VTT ±2% nominally. Insure that there is adequate
VREF decoupling on the motherboard.
Datasheet
33
Intel® Celeron® Processor up to 1.10 GHz
2.12
System Bus AC Specifications
The Celeron processor system bus timings specified in this section are defined at the Intel Celeron
processor edge fingers and the processor core pins. Timings specified at the processor edge fingers
only apply to the S.E.P. Package and timings given at the processor core pins apply to all S.E.P.
Package and PGA packages. Unless otherwise specified, timings are tested at the processor core
during manufacturing. Timings at the processor edge fingers are specified by design
characterization. See Section 7.0 for the Intel Celeron processor signal definitions. Note that at
66 MHz system bus operation, the Intel Celeron processor timings at the processor edge
fingers are identical to the Pentium II processor timings at the edge fingers. See the Pentium®
II Processor at 233, 266, 300, and 333 MHz (Order Number 243335) for more detail.
Table 9 through Table 26 list the AC specifications associated with the Intel Celeron processor
system bus. These specifications are broken into the following categories: Table 9 through Table 12
contain the system bus clock specifications, Table 13 and Table 14 contain the AGTL+
specifications, Table 17 and Table 18 are the CMOS signal group specifications, Table 20 contains
timings for the Reset conditions, Table 22 and Table 23 cover APIC bus timing, and Table 25 and
Table 26 cover TAP timing. For each pair of tables, the first table contains timing specifications for
measurement or simulation at the processor edge fingers. The second table contains specifications
for simulation at the processor core pads.
All Intel Celeron processor system bus AC specifications for the AGTL+ signal group are relative
to the rising edge of the BCLK input. All AGTL+ timings are referenced to VREF for both ‘0’ and
‘1’ logic levels unless otherwise specified.
The timings specified in this section should be used in conjunction with the I/O buffer models
provided by Intel. These I/O buffer models, which include package information, are available in
Quad format as the Intel Celeron® Processor I/O Buffer Models, Quad XTK Format (Electronic
Form). AGTL+ layout guidelines are also available in AP-585, Pentium® II Processor AGTL+
Guidelines (Order Number 243330).
Care should be taken to read all notes associated with a particular timing parameter.
34
Datasheet
Intel® Celeron® Processor up to 1.10 GHz
Table 9.
System Bus AC Specifications (Clock) at the Processor Edge Fingers
(for S.E.P. Package)
T# Parameter
Min
System Bus Frequency
T1’: BCLK Period
Nom
Max
66.67
0.78
T2’: BCLK Period Stability
Figure
Notes
MHz
15.0
T1B’: SC242 to Core Logic BCLK Offset
Unit
± 300
ns
3
4, 5, 6
ns
3
Absolute Value 7,8
ps
See Table 10
T3’: BCLK High Time
4.44
ns
3
@>2.0 V 6
T4’: BCLK Low Time
4.44
ns
3
@<0.5 V 6
T5’: BCLK Rise Time
0.84
2.31
ns
3
(0.5 V–2.0 V) 6, 9
T6’: BCLK Fall Time
0.84
2.31
ns
3
(2.0 V–0.5 V) 6, 9
NOTES:
1. Unless otherwise noted, all specifications in this table apply to all Celeron processor frequencies.
2. All AC timings for the AGTL+ signals are referenced to the BCLK rising edge at 0.70 V at the processor edge
fingers. This reference is to account for trace length and capacitance on the processor substrate, allowing the
processor core to receive the signal with a reference at 1.25 V. All AGTL+ signal timings (address bus, data
bus, etc.) are referenced at 1.00 V at the processor edge fingers.
3. All AC timings for the CMOS signals are referenced to the BCLK rising edge at 0.70 V at the processor edge
fingers. This reference is to account for trace length and capacitance on the processor substrate, allowing the
processor core to receive the signal with a reference at 1.25 V. All CMOS signal timings (compatibility
signals, etc.) are referenced at 1.25 V at the processor edge fingers.
4. The internal core clock frequency is derived from the Intel Celeron processor system bus clock. The system
bus clock to core clock ratio is determined during initialization. Table 12 shows the supported ratios for each
processor.
5. The BCLK period allows a +0.5 ns tolerance for clock driver variation.
6. This specification applies to Intel Celeron processors when operating at a system bus frequency of 66 MHz.
7. The BCLK offset time is the absolute difference needed between the BCLK signal arriving at the Intel Celeron
processor edge finger at 0.5 V vs. arriving at the core logic at 1.25 V. The positive offset is needed to account
for the delay between the SC242 connector and processor core. The positive offset ensures both the
processor core and the core logic receive the BCLK edge concurrently.
8. See Section 3.1 for Intel Celeron processor system bus clock signal quality specifications.
9. Not 100% tested. Specified by design characterization as a clock driver requirement.
Datasheet
35
Intel® Celeron® Processor up to 1.10 GHz
Table 10. System Bus AC Specifications (Clock) at the Processor
Core Pins (for Both S.E.P. and PGA Packages)
T# Parameter
Min
System Bus Frequency
T1: BCLK Period
Nom
Max
66.67
Figure
Notes
MHz
15.0
T2: BCLK Period Stability
Unit
± 300
ns
3
4, 5, 6
ps
3
6, 8, 9
T3: BCLK High Time
4.94
ns
3
@>2.0 V 6
T4: BCLK Low Time
4.94
ns
3
@<0.5 V 6
T5: BCLK Rise Time
• S.E.P.P. and PPGA
0.34
1.36
ns
3
(0.5 V–2.0 V) 6, 10
• FC-PGA/FC-PGA2
0.40
1.6
ns
3
10, 11
• S.E.P.P. and PPGA
0.34
1.36
ns
3
(2.0 V–0.5 V) 6, 10
• FC-PGA/FC-PGA2
0.40
1.6
ns
3
10, 11
T6: BCLK Fall Time
NOTES:
1. Unless otherwise noted, all specifications in this table apply to all Celeron processor frequencies.
2. All AC timings for the AGTL+ signals are referenced to the BCLK rising edge at 1.25 V at the processor core
pin. All AGTL+ signal timings (address bus, data bus, etc.) are referenced at 1.00 V at the processor core
pins.
3. All AC timings for the CMOS signals are referenced to the BCLK rising edge at 1.25 V at the processor core
pin. All CMOS signal timings (compatibility signals, etc.) are referenced at 1.25 V at the processor core pins.
4. The internal core clock frequency is derived from the Intel Celeron processor system bus clock. The system
bus clock to core clock ratio is determined during initialization. Table 12 shows the supported ratios for each
processor.
5. The BCLK period allows a +0.5 ns tolerance for clock driver variation.
6. This specification applies to the Intel Celeron processor when operating at a system bus frequency of
66 MHz.
7. See Section 3.1 for Intel Celeron processor system bus clock signal quality specifications.
8. Due to the difficulty of accurately measuring clock jitter in a system, it is recommended that a clock driver be
used that is designed to meet the period stability specification into a test load of 10 to 20 pF. This should be
measured on the rising edges of adjacent BCLKs crossing 1.25 V at the processor core pin. The jitter
present must be accounted for as a component of BCLK timing skew between devices.
9. The clock driver’s closed loop jitter bandwidth must be set low to allow any PLL-based device to track the
jitter created by the clock driver. The –20 dB attenuation point, as measured into a 10 to 20 pF load, should
be less than 500 kHz. This specification may be ensured by design characterization and/or measured with a
spectrum analyzer.
10.Not 100% tested. Specified by design characterization as a clock driver requirement.
11. BCLK Rise time is measure between 0.5V–2.0V. BCLK fall time is measured between 2.0 V–0.5 V.
36
Datasheet
Intel® Celeron® Processor up to 1.10 GHz
Table 11. System Bus AC Specifications (SET Clock)1, 2
T# Parameter
Min
T4: BCLK Low Time
Unit
Figure
MHz
100.00
10.0
ns
10.0
±250
T2: BCLK Period Stability
T3: BCLK High Time
Max
66.67
System Bus Frequency
T1: BCLK Period
Nom
±250
2.5
2.5
2.4
2.4
Notes
4
3
4, 5, 10
4, 5, 11
6, 7, 10
ps
6, 7, 11
ns
3
ns
3
9, 10
9, 11
9, 10
9, 11
T5: BCLK Rise Time
0.4
1.6
ns
3
3, 8
T6: BCLK Fall Time
0.4
1.6
ns
3
3, 8
NOTES:
1. Unless otherwise noted, all specifications in this table apply to Celeron processors at all frequencies.
2. All AC timings for the AGTL+ signals are referenced to the BCLK rising edge at 1.25 V at the processor pin.
All AGTL+ signal timings (address bus, data bus, etc.) are referenced at 1.00 V at the processor pins.
3. Not 100% tested. Specified by design characterization as a clock driver requirement.
4. The internal core clock frequency is derived from the processor system bus clock. The system bus clock to
core clock ratio is determined during initialization. Individual processors will only operate at their specified
system bus frequency, either 66 MHz or 100 MHz, not both. Table 12 shows the supported ratios for each
processor.
5. The BCLK period allows a +0.5 ns tolerance for clock driver variation. See the appropriate clock synthesizer/
driver specification for details.
6. Due to the difficulty of accurately measuring clock jitter in a system, it is recommended that a clock driver be
used that is designed to meet the period stability specification into a test load of 10 to 20 pF. This should be
measured on the rising edges of adjacent BCLKs crossing 1.25 V at the processor pin. The jitter present
must be accounted for as a component of BCLK timing skew between devices.
7. The clock driver’s closed loop jitter bandwidth must be set low to allow any PLL-based device to track the
jitter created by the clock driver. The –20 dB attenuation point, as measured into a 10 to 20 pF load, should
be less than 500 kHz. This specification may be ensured by design characterization and/or measured with a
spectrum analyzer. See the appropriate clock synthesizer/driver specification for details
8. BCLK Rise time is measure between 0.5 V–2.0 V. BCLK fall time is measured between 2.0 V–0.5 V.
9. BCLK high time is measured as the period of time above 2.0 V. BCLK low time is measured as the period of
time below 0.5 V.
10.This specification applies to Pentium III processors operating at a system bus frequency of 66 MHz.
11. This specification applies to Pentium III processors operating at a system bus frequency of 100 MHz
Datasheet
37
Intel® Celeron® Processor up to 1.10 GHz
Table 12. Valid Intel® Celeron® Processor System Bus, Core Frequency
Core Frequency (MHz)
BCLK Frequency (MHz)
Frequency Multiplier
266
66
4
300
66
4.5
333
66
5
366
66
5.5
400
66
6
433
66
6.5
466
66
7
500
66
7.5
533
66
8
566
66
8.5
600
66
9
633
66
9.5
667
66
10
700
66
10.5
733
66
11
766
66
11.5
800
100
8
850
100
8.5
900
100
9
950
100
9.5
1,000
100
10
1,100
100
11
NOTES:
1. Contact your local Intel representative for the latest information on processor frequencies and/or frequency
multipliers.
2. While other bus ratios are defined, operation at frequencies other than those listed are not supported.
38
Datasheet
Intel® Celeron® Processor up to 1.10 GHz
Table 13. System Bus AC Specifications (AGTL+ Signal Group) at the Processor Edge
Fingers (for S.E.P. Package)
T# Parameter
Min
Max
Unit
Figure
Notes
T7’: AGTL+ Output Valid Delay
1.07
6.37
ns
4
4, 5
T8’: AGTL+ Input Setup Time
1.96
ns
5
4, 6, 7, 8
T9’: AGTL+ Input Hold Time
1.53
ns
5
4, 9
T10’: RESET# Pulse Width
1.00
ms
6
10
NOTES:
1. Unless otherwise noted, all specifications in this table apply to all Celeron processor frequencies.
2. Not 100% tested. Specified by design characterization.
3. All AC timings for the AGTL+ signals are referenced to the BCLK rising edge at 0.50 V at the processor edge
fingers. All AGTL+ signal timings (compatibility signals, etc.) are referenced at 1.00 V at the processor edge
fingers.
4. This specification applies to Intel Celeron processors operating with a 66 MHz Intel Celeron processor
system bus only.
5. Valid delay timings for these signals are specified into 50 Ω to 1.5 V and with VREF at 1.0 V.
6. A minimum of 3 clocks must be guaranteed between two active-to-inactive transitions of TRDY#.
7. RESET# can be asserted (active) asynchronously, but must be deasserted synchronously.
8. Specification is for a minimum 0.40 V swing.
9. Specification is for a maximum 1.0 V swing.
10.After VCCCORE, and BCLK become stable.
Table 14. System Bus AC Specifications (AGTL+ Signal Group) at the Processor Core Pins
(for S.E.P. Package)
T# Parameter
Min
Max
Unit
Figure
Notes
T7: AGTL+ Output Valid Delay
0.17
5.16
ns
4
5
T8: AGTL+ Input Setup Time
2.10
ns
5
5, 6, 7, 8
T9: AGTL+ Input Hold Time
0.77
ns
5
9
T10: RESET# Pulse Width
1.00
ms
6
7, 10
NOTES:
1. Unless otherwise noted, all specifications in this table apply to all Intel ®Celeron® processor frequencies.
2. These specifications are tested during manufacturing.
3. All AC timings for the AGTL+ signals are referenced to the BCLK rising edge at 1.25 V at the processor core
pin. All AGTL+ signal timings (compatibility signals, etc.) are referenced at 1.00 V at the processor core pins.
4. This specification applies to the Intel Celeron processor operating with a 66 MHz Intel Celeron processor
system bus only.
5. Valid delay timings for these signals are specified into 25 Ω to 1.5 V and with VREF at 1.0 V.
6. A minimum of 3 clocks must be guaranteed between two active-to-inactive transitions of TRDY#.
7. RESET# can be asserted (active) asynchronously, but must be deasserted synchronously.
8. Specification is for a minimum 0.40 V swing.
9. Specification is for a maximum 1.0 V swing.
10.After VCCCORE and BCLK become stable.
Datasheet
39
Intel® Celeron® Processor up to 1.10 GHz
Table 15. Processor System Bus AC Specifications (AGTL+ Signal Group) at the Processor
Core Pins (for PPGA Package)
T# Parameter
Min
Max
Unit
Figure
Notes
T7: AGTL+ Output Valid Delay
0.30
4.43
ns
4
5
T8: AGTL+ Input Setup Time
2.10
ns
5
5, 6, 7
T9: AGTL+ Input Hold Time
0.85
ns
5
T10: RESET# Pulse Width
1.00
ms
6
7, 8
NOTES:
1. Unless otherwise noted, all specifications in this table apply to all processor frequencies.
2. These specifications are tested during manufacturing.
3. All AC timings for the AGTL+ signals are REFerenced to the BCLK rising edge at 1.25 V at the processor pin.
All GTL+ signal timings (compatibility signals, etc.) are referenced at 1.00 V at the processor pins.
4. This specification applies to the processor operating with a 66 MHz system bus only.
5. Valid delay timings for these signals are specified into 25 Ω to 1.5 V and with VREF at 1.0 V.
6. A minimum of 3 clocks must be guaranteed between two active-to-inactive transitions of TRDY#.
7. RESET# can be asserted (active) asynchronously, but must be deasserted synchronously.
8. After VCCCORE and BCLK become stable.
Table 16. System Bus AC Specifications (AGTL+ Signal Group) at the Processor Core Pins
(for FC-PGA/FC-PGA2 Packages)
T# Parameter
Min
Max
Unit
Figure
Notes
T7: AGTL+ Output Valid Delay
0.40
3.25
ns
4
4, 10, 11
T8: AGTL+ Input Setup Time
1.20
ns
5
5, 6, 7, 10, 11
T9: AGTL+ Input Hold Time
1.00
ns
5
8, 10, 11
T10: RESET# Pulse Width
1.00
ms
7
6, 9, 10, 11
NOTES:
1. Unless otherwise noted, all specifications in this table apply to all Celeron processors at all frequencies and
cache sizes.
2. These specifications are tested during manufacturing.
3. All AC timings for the AGTL+ signals are referenced to the BCLK rising edge at 1.25 V at the processor pin.
All AGTL+ signal timings (compatibility signals, etc.) are referenced at 1.00V at the processor pins.
4. Valid delay timings for these signals are specified into 50 Ω to 1.5 V and with VREF at 1.0 V.
5. A minimum of 3 clocks must be guaranteed between two active-to-inactive transitions of TRDY#.
6. RESET# can be asserted (active) asynchronously, but must be deasserted synchronously.
7. Specification is for a minimum 0.40 V swing from VREF - 200 mV to VREF + 200 mV. This assumes an edge
rate of 0.3 V/ns.
8. Specification is for a maximum 1.0 V swing from VTT – 1V to VTT. This assumes an edge rate of 3 V/ns.
9. This should be measured after VCCCORE, VCCCMOS, and BCLK become stable.
10.This specification applies to the FC-PGA/FC-PGA2 packages running at 66 MHz system bus frequency.
11. This specification applies to the FC-PGA/FC-PGA2 packages running at 100 MHz system bus frequency.
40
Datasheet
Intel® Celeron® Processor up to 1.10 GHz
Table 17. System Bus AC Specifications (CMOS Signal Group) at the Processor Edge Fingers
(for S.E.P. Package)
T# Parameter
Min
Max
Unit
Figure
Notes
T14’: CMOS Input Pulse Width, except
PWRGOOD
2
BCLKs
8
Active and
Inactive states
T14B: LINT[1:0] Input Pulse Width
6
BCLKs
8
5
T15’: PWRGOOD Inactive Pulse Width
10
BCLKs
8
6, 7
NOTES:
1. Unless otherwise noted, all specifications in this table apply to all Celeron processor frequencies.
2. Not 100% tested. Specified by design characterization.
3. All AC timings for the CMOS signals are referenced to the BCLK rising edge at 0.50 V at the processor edge
fingers. All CMOS signal timings (address bus, data bus, etc.) are referenced at 1.25 V.
4. These signals may be driven asynchronously.
5. This specification only applies when the APIC is enabled and the LINT1 or LINT0 pin is configured as an
edge-triggered interrupt with fixed delivery; otherwise, specification T14 applies.
PWRGOOD must remain below VIL,max (Table 6) until all the voltage planes meet the voltage tolerance
specifications in Table 5 and BCLK has met the BCLK AC specifications in Table 10 for at least 10 clock
cycles. PWRGOOD must rise glitch-free and monotonically to 2.5 V.
6. When driven inactive or after VCCCORE, and BCLK become stable.
7. If the BCLK signal meets its AC specification within 150 ns of turning on, then the PWRGOOD inactive pulse
width specification (T15) is waived and BCLK may start after PWRGOOD is asserted. PWRGOOD must still
remain below VIL,max until all the voltage planes meet the voltage tolerance specifications.
Table 18. System Bus AC Specifications (CMOS Signal Group) at the Processor Core Pins
(for Both S.E.P., PGA, and FC-PGA/FC-PGA2 Packages)
T# Parameter
Min
Max
Unit
Figure
Notes
T14: CMOS Input Pulse Width, except
PWRGOOD
2
BCLKs
8
Active and
Inactive states
T14B: LINT[1:0] Input Pulse Width
(S.E.P.P. Only)
6
BCLKs
8
5
T15: PWRGOOD Inactive Pulse Width
10
BCLKs
8
6, 7
NOTES:
1. Unless otherwise noted, all specifications in this table apply to all Celeron processor frequencies.
2. These specifications are tested during manufacturing.
3. All AC timings for the CMOS signals are referenced to the BCLK rising edge at 1.25 V at the processor core
pins. All CMOS signal timings (address bus, data bus, etc.) are referenced at 1.25 V.
4. These signals may be driven asynchronously.
5. This specification only applies when the APIC is enabled and the LINT1 or LINT0 pin is configured as an
edge-triggered interrupt with fixed delivery; otherwise, specification T14 applies.
6. When driven inactive or after VCCCORE, and BCLK become stable.
7. If the BCLK signal meets its AC specification within 150 ns of turning on, then the PWRGOOD inactive pulse
width specification (T15) is waived and BCLK may start after PWRGOOD is asserted. PWRGOOD must still
remain below VIL,max until all the voltage planes meet the voltage tolerance specifications.
PWRGOOD must remain below VIL,max (Table 6) until all the voltage planes meet the voltage tolerance
specifications in Table 5 and BCLK has met the BCLK AC specifications in Table 10 for at least 10 clock
cycles. PWRGOOD must rise glitch-free and monotonically to 2.5 V.
Datasheet
41
Intel® Celeron® Processor up to 1.10 GHz
Table 19. System Bus AC Specifications (CMOS Signal Group) 1, 2, 3, 4
T# Parameter
Min
Max
Unit
Figure
T14: CMOS Input Pulse Width, except
PWRGOOD
2
BCLKs
4
T15: PWRGOOD Inactive Pulse Width
10
BCLKs
4, 8
Notes
Active and
Inactive states
5
NOTES:
1. Unless otherwise noted, all specifications in this table apply to Celeron processors at all frequencies
2. These specifications are tested during manufacturing.
3. These signals may be driven asynchronously.
4. All CMOS outputs shall be asserted for at least 2 BCLKs.
5. When driven inactive or after VCCCORE, VTT, VCCCMOS, and BCLK become stable.
Table 20. System Bus AC Specifications (Reset Conditions)
(for Both S.E.P. and PPGA Packages)
T# Parameter
Min
T16: Reset Configuration Signals (A[14:5]#,
BR0#, FLUSH#, INIT#) Setup Time
4
T17: Reset Configuration Signals (A[14:5]#,
BR0#, FLUSH#, INIT#) Hold Time
2
Max
20
Unit
Figure
Notes
BCLKs
6
Before deassertion
of RESET#
BCLKs
6
After clock that
deasserts RESET#
NOTES:
1. Unless otherwise noted, all specifications in this table apply to all Intel ® Celeron® processor frequencies.
Table 21. System Bus AC Specifications (Reset Conditions) (for the FC-PGA/FC-PGA2
Packages)
T# Parameter
Min
T16: Reset Configuration Signals
(A[14:5]#, BR0#, INIT#)
Setup Time
4
T17: Reset Configuration Signals
(A[14:5]#, BR0#, INIT#) Hold
Time
2
T18: Reset Configuration Signals
(A20M#, IGNNE#, LINT[1:0])
Setup Time
1
T19: Reset Configuration Signals
(A20M#, IGNNE#, LINT[1:0])
Delay Time
T20: Reset Configuration Signals
(A20M#, IGNNE#, LINT[1:0])
Hold Time
2
Max
Unit
Figure
Notes
BCLKs
7
Before deassertion of
RESET#
BCLKs
7
After clock that
deasserts RESET#
ms
7
Before deassertion of
RESET#, 3
5
BCLKs
7
After assertion of
RESET#, 2, 3
20
BCLKs
7
After clock that
deasserts RESET#, 3
20
NOTES:
1. Unless otherwise noted, all specifications in this table apply to Celeron FC-PGA/FC-PGA2 processors at all
frequencies and cache sizes.
2. For a reset, the clock ratio defined by these signals must be a safe value (their final or a lower-multiplier)
within this delay unless PWRGOOD is being driven inactive.
3. These parameters apply to processor engineering samples only. For production units, the processor core
frequency will be determined through the processor internal logic.
42
Datasheet
Intel® Celeron® Processor up to 1.10 GHz
44
Table 22. System Bus AC Specifications (APIC Clock and APIC I/O) at the Processor Edge
Fingers (for S.E.P. Package)
T# Parameter
Min
Max
Unit
Figure
T21’: PICCLK Frequency
2.0
33.3
MHz
T22’: PICCLK Period
30.0
500.0
ns
3
T23’: PICCLK High Time
12.0
ns
3
Notes
T24’: PICCLK Low Time
12.0
ns
3
T25’: PICCLK Rise Time
0.25
3.0
ns
3
T26’: PICCLK Fall Time
0.25
3.0
ns
3
T27’: PICD[1:0] Setup Time
8.5
ns
5
5
ns
5
5
ns
4
5, 6, 7
T28’: PICD[1:0] Hold Time
3.0
T29’: PICD[1:0] Valid Delay
3.0
12.0
NOTES:
1. Unless otherwise noted, all specifications in this table apply to all Celeron processor frequencies.
2. Not 100% tested. Specified by design characterization.
3. All AC timings for the APIC I/O signals are referenced to the PICCLK rising edge at 0.7 V at the processor
edge fingers. All APIC I/O signal timings are referenced at 1.25 V at the processor edge fingers.
4. This specification applies to Intel Celeron processors operating with a 66 MHz Intel Celeron processor
system bus only.
5. Referenced to PICCLK rising edge.
6. For open drain signals, valid delay is synonymous with float delay.
7. Valid delay timings for these signals are specified to 2.5 V +5%.
Datasheet
43
Intel® Celeron® Processor up to 1.10 GHz
Table 23. System Bus AC Specifications (APIC Clock and APIC I/O) at the Processor Core
Pins (For S.E.P. and PGA Packages)
T# Parameter
Min
Max
Unit
Figure
T21: PICCLK Frequency
2.0
33.3
MHz
T22: PICCLK Period
30.0
500.0
ns
3
Notes
T23: PICCLK High Time
• S.E.P.P and PPGA
11.0
ns
3
@>2.0 V
• FC-PGA/FC-PGA2
10.5
ns
3
@>1.7 V
• S.E.P.P and PPGA
11.0
ns
3
@<0.5 V
• FC-PGA/FC-PGA2
10.5
ns
3
@<0.7 V
T25: PICCLK Rise Time
0.25
3.0
ns
3
(0.5 V–2.0 V)
T26: PICCLK Fall Time
0.25
3.0
ns
3
(2.0 V–0.5 V)
T24: PICCLK Low Time
T27: PICD[1:0] Setup Time
• S.E.P.P and PPGA
8.0
ns
5
5
• FC-PGA/FC-PGA2
5.0
ns
5
5
T28: PICD[1:0] Hold Time
2.5
ns
5
5
T29: PICD[1:0] Valid Delay (S.E.P.P
and PPGA only)
1.5
10.0
ns
4
5, 6, 7
T29a: PICD[1:0] Valid Delay (Rising
Edge) (FC-PGA/FC-PGA2
only)
1.5
8.7
ns
4
5, 6, 8
T29b: PICD[1:0] Valid Delay (Falling
Edge) (FC-PGA/FC-PGA2
only)
1.5
12.0
ns
4
5, 6, 8
NOTES:
1. Unless otherwise noted, all specifications in this table apply to all Celeron processor frequencies.
2. These specifications are tested during manufacturing.
3. All AC timings for the APIC I/O signals are referenced to the PICCLK rising edge at 1.25 V at the processor
core pins. All APIC I/O signal timings are referenced at 1.25 V at the processor core pins.
4. This specification applies to Intel Celeron processors operating with a 66 MHz Intel Celeron processor
system bus only.
5. Referenced to PICCLK rising edge.
6. For open drain signals, valid delay is synonymous with float delay.
7. Valid delay timings for these signals are specified to 2.5 V +5%.
8. Valid delay timings for these signals are specified to 1.5 V +5%.
44
Datasheet
Intel® Celeron® Processor up to 1.10 GHz
Table 24. System Bus AC Specifications (APIC Clock and APIC I/O)1, 2, 3
T# Parameter
Min
Max
Unit
MHz
T21: PICCLK Frequency
2.0
33.3
T22: PICCLK Period
30.0
500.0
T23: PICCLK High Time
10.5
T24: PICCLK Low Time
10.5
T25: PICCLK Rise Time
0.25
3.0
T26: PICCLK Fall Time
0.25
3.0
T27: PICD[1:0] Setup Time
5.0
Figure
Notes
ns
3
ns
3
ns
3
@ < 0.7 V
ns
3
(0.7 V–1.7 V)
ns
3
(1.7 V–0.7 V)
ns
5
4
@ > 1.7 V
T28: PICD[1:0] Hold Time
2.5
ns
5
4
T29a: PICD[1:0] Valid Delay (Rising Edge)
1.5
8.7
ns
3, 4
4, 5, 6
T29b: PICD[1:0] Valid Delay (Falling Edge)
1.5
12.0
ns
3, 4
4, 5, 6
NOTES:
1. Unless otherwise noted, all specifications in this table apply to Celeron processors at all frequencies.
2. These specifications are tested during manufacturing.
3. All AC timings for the APIC I/O signals are referenced to the PICCLK rising edge at 1.25 V at the processor
pins. All APIC I/O signal timings are referenced at 0.75 V at the processor pins.
4. Referenced to PICCLK rising edge.
5. For open drain signals, valid delay is synonymous with float delay.
6. Valid delay timings for these signals are specified into 150 Ω load pulled up to 1.5 V.
Table 25. System Bus AC Specifications (TAP Connection) at the Processor Edge Fingers
(For S.E.P. Package)
T# Parameter
Min
T30’: TCK Frequency
T31’: TCK Period
Max
Unit
16.667
MHz
60.0
Figure
ns
3
Notes
T32’: TCK High Time
25.0
ns
3
@1.7 V
T33’: TCK Low Time
25.0
ns
3
@0.7 V
T34’: TCK Rise Time
5.0
ns
3
(0.7 V–1.7 V) 4
T35’: TCK Fall Time
5.0
ns
3
(1.7 V–0.7 V) 4
T36’: TRST# Pulse Width
40.0
ns
6
Asynchronous
T37’: TDI, TMS Setup Time
5.5
ns
9
5
T38’: TDI, TMS Hold Time
14.5
ns
9
5
T39’: TDO Valid Delay
2.0
13.5
ns
9
6, 7
28.5
ns
9
6, 7
2.0
27.5
ns
9
6, 8, 9
27.5
ns
9
6, 8, 9
T40’: TDO Float Delay
T41’: All Non-Test Outputs Valid Delay
T42’: All Non-Test Inputs Setup Time
T43’: All Non-Test Inputs Setup Time
5.5
ns
9
5, 8, 9
T44’: All Non-Test Inputs Hold Time
14.5
ns
9
5, 8, 9
NOTES:
1. Unless otherwise noted, all specifications in this table apply to all Intel ® Celeron® processor frequencies.
2. All AC timings for the TAP signals are referenced to the TCK rising edge at 0.70 V at the processor edge
fingers. All TAP signal timings (TMS, TDI, etc.) are referenced at 1.25 V at the processor edge fingers.
3. Not 100% tested. Specified by design characterization.
4. 1 ns can be added to the maximum TCK rise and fall times for every 1 MHz below 16.667 MHz.
5. Referenced to TCK rising edge.
6. Referenced to TCK falling edge.
7. Valid delay timing for this signal is specified to 2.5 V +5%.
8. Non-Test Outputs and Inputs are the normal output or input signals (besides TCK, TRST#, TDI, TDO, and
TMS). These timings correspond to the response of these signals due to TAP operations.
9. During Debug Port operation, use the normal specified timings rather than the TAP signal timings.
Datasheet
45
Intel® Celeron® Processor up to 1.10 GHz
Table 26. System Bus AC Specifications (TAP Connection) at the Processor Core Pins
(for Both S.E.P. and PPGA Packages)
T# Parameter
Min
T30: TCK Frequency
Max
Unit
16.667
MHz
Figure
Notes
T31: TCK Period
60.0
ns
3
T32: TCK High Time
25.0
ns
3
@1.7 V; 10
T33: TCK Low Time
25.0
ns
3
@0.7 V; 10
T34: TCK Rise Time
5.0
ns
3
(0.7 V–1.7 V); 4, 10
T35: TCK Fall Time
5.0
ns
3
(1.7 V–0.7 V); 4, 10
ns
6
Asynchronous; 10
T36: TRST# Pulse Width
40.0
T37: TDI, TMS Setup Time
5.0
ns
9
5
T38: TDI, TMS Hold Time
14.0
ns
9
5
T39: TDO Valid Delay
1.0
10.0
ns
9
6, 7
25.0
ns
9
6, 7, 10
25.0
ns
9
6, 8, 9
25.0
ns
9
6, 8, 9, 10
T40: TDO Float Delay
T41: All Non-Test Outputs Valid Delay
2.0
T42: All Non-Test Inputs Setup Time
T43: All Non-Test Inputs Setup Time
5.0
ns
9
5, 8, 9
T44: All Non-Test Inputs Hold Time
13.0
ns
9
5, 8, 9
NOTES:
1. Unless otherwise noted, all specifications in this table apply to all Celeron processor frequencies.
2. For the S.E.P. and PPGA packages: All AC timings for the TAP signals are referenced to the TCK rising edge
at 1.25 V at the processor core pins. All TAP signal timings (TMS, TDI, etc.) are referenced at 1.25 V at the
processor core pins.
For the FC-PGA/FC-PGA2 packages: All AC timings for the TAP signals are referenced to the TCK rising
edge at 0.75 V at the processor pins. All TAP signal timings (TMS, TDI, etc.) are referenced at 0.75 V at the
processor pins.
3. These specifications are tested during manufacturing, unless otherwise noted.
4. 1 ns can be added to the maximum TCK rise and fall times for every 1 MHz below 16.667 MHz.
5. Referenced to TCK rising edge.
6. Referenced to TCK falling edge.
7. For the S.E.P. and PPGA packages: Valid delay timing for this signal is specified to 2.5 V +5%.
For the FC-PGA/FC-PGA2 packages: Valid delay timing for this signal is specified to 1.5 V +3%.
8. Non-Test Outputs and Inputs are the normal output or input signals (besides TCK, TRST#, TDI, TDO, and
TMS). These timings correspond to the response of these signals due to TAP operations.
9. During Debug Port operation, use the normal specified timings rather than the TAP signal timings.
10.Not 100% tested. Specified by design characterization.
46
Datasheet
Intel® Celeron® Processor up to 1.10 GHz
Table 27. System Bus AC Specifications (TAP Connection)1, 2, 3
T# Parameter
Min
T30: TCK Frequency
Max
Unit
16.667
MHz
Figure
Notes
T31: TCK Period
60.0
ns
3
T32: TCK High Time
25.0
ns
3
VREF + 0.200 V, 10
T33: TCK Low Time
25.0
ns
3
VREF – 0.200 V, 10
ns
3
(VREF – 0.200 V) –
(VREF + 0.200 V),
T34: TCK Rise Time
5.0
4, 10
T35: TCK Fall Time
5.0
ns
3
(VREF + 0.200 V) –
(VREF – 0.200 V),
4, 10
T36: TRST# Pulse Width
40.0
ns
10
T37: TDI, TMS Setup Time
5.0
ns
9
5
T38: TDI, TMS Hold Time
14.0
ns
9
5
T39: TDO Valid Delay
1.0
10.0
ns
9
6, 7
25.0
ns
9
6, 7, 10
2.0
25.0
ns
9
6, 8, 9
25.0
ns
9
6, 8, 9, 10
T40: TDO Float Delay
T41: All Non-Test Outputs Valid Delay
T42: All Non-Test Inputs Setup Time
Asynchronous, 10
T43: All Non-Test Inputs Setup Time
5.0
ns
9
5, 8, 9
T44: All Non-Test Inputs Hold Time
13.0
ns
9
5, 8, 9
NOTES:
1. Unless otherwise noted, all specifications in this table apply to all Celeron processors frequencies.
2. All AC timings for the TAP signals are referenced to the TCK rising edge at 0.75 V at the processor pins. All
TAP signal timings (TMS, TDI, etc.) are referenced at 0.75 V at the processor pins.
3. These specifications are tested during manufacturing, unless otherwise noted.
4. 1 ns can be added to the maximum TCK rise and fall times for every 1 MHz below 16.667 MHz.
5. Referenced to TCK rising edge.
6. Referenced to TCK falling edge.
7. Valid delay timing for this signal is specified to 1.5 V (1.25 V for AGTL platforms).
8. Non-Test Outputs and Inputs are the normal output or input signals (besides TCK, TRST#, TDI, TDO, and
TMS). These timings correspond to the response of these signals due to TAP operations.
9. During Debug Port operation, use the normal specified timings rather than the TAP signal timings.
10.Not 100% tested. Specified by design characterization.
Datasheet
47
Intel® Celeron® Processor up to 1.10 GHz
Note:
For Figure 3 through Figure 10, the following apply:
1. Figure 3 through Figure 10 are to be used in conjunction with Table 9 through Table 26.
2. All AC timings for the AGTL+ signals at the processor edge fingers are referenced to the
BCLK rising edge at 0.50 V. This reference is to account for trace length and capacitance on
the processor substrate, allowing the processor core to receive the signal with a reference at
1.25 V. All AGTL+ signal timings (address bus, data bus, etc.) are referenced at 1.00 V at the
processor edge fingers.
3. All AC timings for the AGTL+ signals at the processor core pins are referenced to the BCLK
rising edge at 1.25 V. All AGTL+ signal timings (address bus, data bus, etc.) are referenced at
1.00 V at the processor core pins.
4. All AC timings for the CMOS signals at the processor edge fingers are referenced to the
BCLK rising edge at 0.50 V. This reference is to account for trace length and capacitance on
the processor substrate, allowing the processor core to receive the signal with a reference at
1.25 V. All CMOS signal timings (compatibility signals, etc.) are referenced at 1.25 V at the
processor edge fingers.
5. All AC timings for the APIC I/O signals at the processor edge fingers are referenced to the
PICCLK rising edge at: 0.7 V for S.E.P. and PPGA packages and 0.75 V for the FC-PGA/
FC-PGA2 packages. All APIC I/O signal timings are referenced at 1.25 V for S.E.P. and
PPGA packages and 0.75 V for the FC-PGA/FC-PGA2 packages at the processor edge
fingers.
6. All AC timings for the TAP signals at the processor edge fingers are referenced to the TCK
rising edge at 0.70 V for S.E.P. and PPGA packages and 0.75 V for the FC-PGA/FC-PGA2
packages. All TAP signal timings (TMS, TDI, etc.) are referenced at 1.25 V for S.E.P. and
PPGA packages and 0.75 V for the FC-PGA/FC-PGA2 packages at the processor edge
fingers.
Figure 2. BCLK to Core Logic Offset
BCLK at
Edge Fingers
0.5V
T1B'
BCLK at
Core Logic
48
1.25V
Datasheet
Intel® Celeron® Processor up to 1.10 GHz
Figure 3. BCLK*, PICCLK, and TCK Generic Clock Waveform
th
tr
1.7V (2.0V*)
1.25V
CLK
0.7V (0.5V*)
tf
tl
tp
Tr
Tf
Th
Tl
Tp
=
=
=
=
=
T5,
T6,
T3,
T4,
T1,
T25,
T26,
T23,
T24,
T22,
T34
T35
T32
T33
T31
(Rise Tim e)
(Fall Tim e)
(High Tim e)
(Low Time)
(BLCK, TCK, PICCLK Period)
Note: BCLK is referenced to 0.5 V and 2.0 V. PICCLK is referenced to 0.7 V and 1.7 V.
For S.E.P. and PPGA packages, TCK is referenced to 0.7 V and 1.7 V.
For the FC-PGA package, TCK is referenced to V REF ±200m V.
Figure 4. System Bus Valid Delay Timings
CLK
Tx
Tx
Signal
Valid
V
Valid
Tpw
Tx = T7, T11, T29a, T29b (Valid Delay)
Tpw = T14, T14B, T15 (Pulse Width)
V = 1.0V for AGTL+ signal group;
For S.E.P and PPGA packages, 1.25V for CMOS, APIC and JTAG signal groups
For FC-PGA package, 0.75V for CMOS, APIC and TAP signal groups
Figure 5. System Bus Setup and Hold Timings
CLK
Ts
Signal
V
Th
Valid
Ts = T8, T12, T27 (Setup Time)
Th = T9, T13, T28 (Hold Time)
V = 1.0V for AGTL+ signal group;
For S.E.P. and PPGA packages, 1.25V for APIC and JTAG signal groups
For the FC-PGA package, 0.75V for APIC and TAP signal groups
Datasheet
49
Intel® Celeron® Processor up to 1.10 GHz
Figure 6. System Bus Reset and Configuration Timings (For the S.E.P. and PPGA Packages)
BCLK
Tu
Tt
RESET#
Tv
Tw
Configuration
(A[14:5]#, BR0#,
FLUSH#, INT#)
Tx
Valid
Tt
Tu
Tv
Tw
Tx
= T9 (AGTL+ Input Hold Time)
= T8 (AGTL+ Input Setup Time)
= T10 (RESET# Pulse Width)
= T16 (Reset Configuration Signals (A[14:5]#, BR0#, FLUSH#, INIT#) Setup Time)
= T17 (Reset Configuration Signals (A[14:5]#, BR0#, FLUSH#, INIT#) Hold Time)
Figure 7. System Bus Reset and Configuration Timings (For the FC-PGA/FC-PGA2 Package)
BCLK
Tu
Tt
RESET#
Tv
Ty
Configuration
(A20M#, IGNNE#,
LINT[1:0])
Tx
Tz
Safe
Valid
Tw
Configuration
(A[14:5]#, BR0#,
FLUSH#, INT#)
Valid
= T9 (AGTL+ Input Hold Time)
= T8 (AGTL+ Input Setup Time)
= T10 (RESET# Pulse Width)
= T16 (Reset Configuration Signals (A[14:5]#, BR0#, FLUSH#, INIT#) Setup Time)
= T17 (Reset Configuration Signals (A[14:5]#, BR0#, FLUSH#, INIT#) Hold Time)
T20 (Reset Configuration Signals (A20M#, IGNNE#, LINT[1:0]) Hold Time)
Ty = T19 (Reset Configuration Signals (A20M#, IGNNE#, LINT[1:0]) Delay Time)
Tz = T18 (Reset Configuration Signals (A20M#, IGNNE#, LINT[1:0]) Setup Time)
Tt
Tu
Tv
Tw
Tx
50
Datasheet
Intel® Celeron® Processor up to 1.10 GHz
Figure 8. Power-On Reset and Configuration Timings
BCLK
VccCORE, VTT,
VREF
PWRGOOD
VIL, max
Ta
VIH, min
Tb
RESET#
TC
Configuration
(A20M#, IGNNE#,
INTR, NMI)
Valid Ratio
Ta
Tb
Tc
= T15 (PWRGOOD Inactive Pulse)
= T10 (RESET# Pulse Width)
= T20 (Reset Configuration Signals (A20M#, IGNNE#, LINT[1:0]) Hold Time) (FC-PGA)
Figure 9. Test Timings (TAP Connection)
1.25V
TCK
Tv
Tw
Tr
Ts
1.25V
TDI, TMS
Input
Signals
Tx
Tu
Ty
Tz
TDO
Output
Signals
Tr = T43 (All Non-Test Inputs Setup Time)
Ts = T44 (All Non-Test Inputs Hold Time)
Tu = T40 (TDO Float Delay)
Tv = T37 (TDI, TMS Setup Time)
Tw = T38 (TDI, TMS Hold Time)
Tx = T39 (TDO Valid Delay)
Ty = T41 (All Non-Test Outputs Valid Delay)
Tz = T42 (All Non-Test Outputs Float Delay)
Figure 10. Test Reset Timings
TRST#
1.25V
Tq
Tq = T37 (TRST# Pulse Width)
C
Datasheet
51
Intel® Celeron® Processor up to 1.10 GHz
3.0
System Bus Signal Simulations
Signals driven on the Celeron processor system bus should meet signal quality specifications to
ensure that the components read data properly and to ensure that incoming signals do not affect the
long term reliability of the component. Specifications are provided for simulation at the processor
core; guidelines are provided for correlation to the processor edge fingers. These edge finger
guidelines are intended for use during testing and measurement of system signal integrity.
Violations of these guidelines are permitted, but if they occur, simulation of signal quality at the
processor core should be performed to ensure that no violations of signal quality specifications
occur. Meeting the specifications at the processor core in Table 28, Table 31, and Table 34 ensures
that signal quality effects will not adversely affect processor operation, but does not necessarily
guarantee that the guidelines in Table 30, Table 33, and Table 35 will be met.
3.1
System Bus Clock (BCLK) Signal Quality Specifications
and Measurement Guidelines
Table 28 describes the BCLK signal quality specifications at the processor core for both S.E.P. and
PPGA Packages. Table 29 shows the BCLK and PICCLK signal quality specifications at the
processor core for the FC-PGA/FC-PGA2 packages. Table 30 describes guidelines for signal
quality measurement at the processor edge fingers. Figure 11 describes the signal quality waveform
for the system bus clock at the processor core pins; Figure 12 describes the signal quality
waveform for the system bus clock at the processor edge fingers.
Table 28. BCLK Signal Quality Specifications for Simulation at the Processor Core
(for Both S.E.P. and PPGA Packages)
T# Parameter
Min
V1: BCLK VIL
V2: BCLK VIH
2.0
V3: VIN Absolute Voltage Range
–0.7
V4: Rising Edge Ringback
1.7
V5: Falling Edge Ringback
Nom
Max
Unit
Figure
0.5
V
11
V
11
2
3.5
0.7
Notes
V
11
2
V
11
3
V
11
3
NOTES:
1. Unless otherwise noted, all specifications in this table apply to all Celeron processor frequencies.
2. This is the Intel Celeron processor system bus clock overshoot and undershoot specification for 66 MHz
system bus operation.
3. The rising and falling edge ringback voltage specified is the minimum (rising) or maximum (falling) absolute
voltage the BCLK signal can dip back to after passing the VIH (rising) or VIL (falling) voltage limits. This
specification is an absolute value.
52
Datasheet
Intel® Celeron® Processor up to 1.10 GHz
Table 29. BCLK/PICCLK Signal Quality Specifications for Simulation at the Processor Pins
(for the FC-PGA/FC-PGA2 Packages)
T# Parameter
Min
Max
Unit
Figure
V1: BCLK VIL
0.50
V
11
V1: PICCLK VIL
0.70
V
11
V
11
V2: BCLK VIH
Nom
2.00
V2: PICCLK VIH
2.00
V3: VIN Absolute Voltage Range
–0.58
V4: BCLK Rising Edge Ringback
V4: PICCLK Rising Edge Ringback
Notes
V
11
V
11
2.00
V
11
2
2.00
V
11
2
3.18
V5: BCLK Falling Edge Ringback
0.50
V
11
2
V5: PICCLK Falling Edge Ringback
0.70
V
11
2
NOTES:
1. Unless otherwise noted, all specifications in this table apply to FC-PGA/FC-PGA2 processors frequencies
and cache sizes.
2. The rising and falling edge ringback voltage specified is the minimum (rising) or maximum (falling) absolute
voltage the BCLK/PICCLK signal can dip back to after passing the VIH (rising) or VIL (falling) voltage limits.
This specification is an absolute value.
Figure 11. BCLK, TCK, PICCLK Generic Clock Waveform at the Processor Core Pins
T3
V3
V4
V2
V1
V5
T6
Datasheet
V3
T4
T5
53
Intel® Celeron® Processor up to 1.10 GHz
Table 30. BCLK Signal Quality Guidelines for Edge Finger Measurement
(for the S.E.P. Package)
T# Parameter
Min
Nom
V1’: BCLK VIL
V2’: BCLK VIH
2.0
V3’: VIN Absolute Voltage Range
–0.5
V4’: Rising Edge Ringback
2.0
Unit
Figure
0.5
V
12
V
12
V
12
2
3.3
V5’: Falling Edge Ringback
V6’: Tline Ledge Voltage
Max
1.0
V7’: Tline Ledge Oscillation
Notes
V
12
3
0.5
V
12
3
1.7
V
12
At Ledge Midpoint 4
0.2
V
12
Peak-to-Peak 5
NOTES:
1. Unless otherwise noted, all specifications in this table apply to all Celeron processor frequencies.
2. This is the Intel Celeron processor system bus clock overshoot and undershoot measurement guideline.
3. The rising and falling edge ringback voltage guideline is the minimum (rising) or maximum (falling) absolute
voltage the BCLK signal may dip back to after passing the VIH (rising) or VIL (falling) voltage limits. This
guideline is an absolute value.
4. The BCLK at the processor edge fingers may have a dip or ledge midway on the rising or falling edge. The
midpoint voltage level of this ledge should be within the range of the guideline.
5. The ledge (V7) is allowed to have peak-to-peak oscillation as given in the guideline.
Figure 12. BCLK, TCK, PICCLK Generic Clock Waveform at the Processor Edge Fingers
T3
V3
V4
V2
V7
V6
V1
V5
V3
T6
54
T4
T5
Datasheet
Intel® Celeron® Processor up to 1.10 GHz
3.2
AGTL+ Signal Quality Specifications and Measurement
Guidelines
Many scenarios have been simulated to generate a set of AGTL+ layout guidelines which are
available in AP-585, Pentium® II Processor AGTL+ Guidelines (Order Number 243330). Refer to
the Pentium® II Processor Developer's Manual (Order Number 243502) for the AGTL+ buffer
specification.
Table 31 provides the AGTL+ signal quality specifications (for both the S.E.P. and PPGA
Packages) for use in simulating signal quality at the processor core. Table 32 provides the AGTL+
signal quality specifications (for the FC-PGA/FC-PGA2 packages) for use in simulating signal
quality at the processor core. Table 33 provides AGTL+ signal quality guidelines for measuring and
testing signal quality at the processor edge fingers. Figure 13 describes the signal quality waveform
for AGTL+ signals at the processor core and edge fingers. For more information on the AGTL+
interface, see the Pentium® II Processor Developer's Manual (Order Number 243502).
Table 31. AGTL+ Signal Groups Ringback Tolerance Specifications at the Processor Core
(For Both the S.E.P. and PPGA Packages)
T# Parameter
α: Overshoot
Min
Unit
Figure
Notes
100
mV
13
4
τ: Minimum Time at High
1.00
ns
13
4
ρ: Amplitude of Ringback
–100
mV
13
4, 5
φ: Final Settling Voltage
100
mV
13
4
δ: Duration of Squarewave Ringback
N/A
ns
13
NOTES:
1. Unless otherwise noted, all specifications in this table apply to all Celeron processor frequencies.
2. Specifications are for the edge rate of 0.3 – 0.8 V/ns. See Figure 13 for the generic waveform.
3. All values specified by design characterization.
4. This specification applies to Intel Celeron processors operating with a 66 MHz Intel Celeron processor
system bus only.
5. Ringback below VREF + 20 mV is not supported.
Table 32. AGTL+ Signal Groups Ringback Tolerance Specifications at the Processor Pins
(For FC-PGA/FC-PGA2 Packages)
T# Parameter
α: Overshoot
Min
Unit
Figure
Notes
100
mV
13
4, 8, 9, 10
τ: Minimum Time at High
0.50
ns
13
9
ρ: Amplitude of Ringback
–200
mV
13
5, 6, 7, 8
φ: Final Settling Voltage
200
mV
13
8
δ: Duration of Squarewave Ringback
N/A
ns
13
NOTES:
1. Unless otherwise noted, all specifications in this table apply to all Celeron processor frequencies.
2. Specifications are for the edge rate of 0.3 – 0.8V/ns. See Figure 13 for the generic waveform.
3. All values specified by design characterization.
4. See Table 36 for maximum allowable overshoot.
5. Ringback between VREF + 100 mV and VREF + 200 mV or VREF – 200 mV and VREF – 100 mVs requires the
flight time measurements to be adjusted as described in the Intel AGTL+ Specifications (Intel®Pentium®II
Developers Manual). Ringback below VREF + 100 mV or above VREF – 100 mV is not supported.
6. Intel recommends simulations not exceed a ringback value of VREF ±200 mV to allow margin for other
sources of system noise.
7. A negative value for ρ indicates that the amplitude of ringback is above VREF. (i.e., φ = –100 mV specifies the
signal cannot ringback below VREF + 100 mV).
8. φ and ρ: are measured relative to VREF. α: is measured relative to VREF + 200 mV.
9. All Ringback entering the Overdrive Region must have flight time correction.
10.Overshoot specifications for Ringback do not correspond to Overshoot specifications in Section 3.4.
Datasheet
55
Intel® Celeron® Processor up to 1.10 GHz
Table 33. AGTL+ Signal Groups Ringback Tolerance Guidelines for Edge Finger
Measurement on the S.E.P. Package
T# Parameter
Min
Unit
Figure
Notes
α’: Overshoot
100
mV
13
τ’: Minimum Time at High
1.5
ns
13
4
ρ ’: Amplitude of Ringback
–250
mV
13
4, 5
φ’: Final Settling Voltage
250
mV
13
4
δ’: Duration of Squarewave Ringback
N/A
ns
13
NOTES:
1. Unless otherwise noted, all guidelines in this table apply to all Celeron processor frequencies.
2. Guidelines are for the edge rate of 0.3 – 0.8 V/ns. See Figure 13 for the generic waveform.
3. All values specified by design characterization.
4. This guideline applies to Intel Celeron processors operating with a 66 MHz system bus only.
5. Ringback below VREF + 250 mV is not supported.
Figure 13. Low to High AGTL+ Receiver Ringback Tolerance
τ
α
VREF +0.2
φ
VREF
ρ
VREF –0.2
δ
0.7V Clk Ref
Vstart
Clock
Time
Note: High to Low case is analogous.
56
Datasheet
Intel® Celeron® Processor up to 1.10 GHz
3.3
Non-AGTL+ Signal Quality Specifications and Measurement
Guidelines
There are three signal quality parameters defined for non-AGTL+ signals: overshoot/undershoot,
ringback, and settling limit. All three signal quality parameters are shown in Figure 14 for the nonAGTL+ signal group.
Figure 14. Non-AGTL+ Overshoot/Undershoot, Settling Limit, and Ringback
Settling Limit
Overshoot
V HI
Rising-Edge
Ringback
Falling-Edge
Ringback
Settling Limit
VLO
VSS
Time
Undershoot
NOTES:
1. For the FC-PGA/FC-PGA2 packages, VHI = 1.5 V for all non-AGTL+ signals except for BCLK, PICCLK, and
PWRGOOD. VHI = 2.5 V for BCLK, PICCLK, and PWRGOOD. BCLK and PICCLK signal quality is detailed in
Section 3.1.
3.3.1
Overshoot/Undershoot Guidelines
Overshoot (or undershoot) is the absolute value of the maximum voltage above the nominal high
voltage or below VSS. The overshoot/undershoot guideline limits transitions beyond VCC or VSS
due to the fast signal edge rates. (See Figure 14 for non-AGTL+ signals.) The processor can be
damaged by repeated overshoot events on the voltage tolerant buffers if the charge is large enough
(i.e., if the overshoot is great enough). The PPGA and S.E.P. packages have 2.5 V tolerant buffers
and the FC-PGA/FC-PGA2 packages has 1.5 V or 2.5 V tolerant buffers.
However, excessive ringback is the dominant detrimental system timing effect resulting from
overshoot/undershoot (i.e., violating the overshoot/undershoot guideline will make satisfying the
ringback specification difficult). The overshoot/undershoot guideline is 0.7 V for the PPGA
and S.E.P. packages and 0.3 V for the FC-PGA/FC-PGA2 packages and assumes the absence
of diodes on the input. These guidelines should be verified in simulations without the on-chip
ESD protection diodes present because the diodes will begin clamping the signals (2.5 V tolerant
signals for the S.E.P. and PPGA packages, and 2.5 V or 1.5 V tolerant signals for the FC-PGA/
FC-PGA2 packages) beginning at approximately 0.7 V above the appropriate supply and 0.7 V
below VSS. If signals are not reaching the clamping voltage, this will not be an issue. A system
should not rely on the diodes for overshoot/undershoot protection as this will negatively affect the
life of the components and make meeting the ringback specification very difficult.
Datasheet
57
Intel® Celeron® Processor up to 1.10 GHz
3.3.2
Ringback Specification
Ringback refers to the amount of reflection seen after a signal has switched. The ringback
specification is the voltage that the signal rings back to after achieving its maximum absolute
value. (See Figure 14 for an illustration of ringback.) Excessive ringback can cause false signal
detection or extend the propagation delay. The ringback specification applies to the input pin of
each receiving agent. Violations of the signal ringback specification are not allowed under any
circumstances for non-AGTL+ signals.
Ringback can be simulated with or without the input protection diodes that can be added to the
input buffer model. However, signals that reach the clamping voltage should be evaluated further.
See Table 34 for the signal ringback specifications for non-AGTL+ signals for simulations at the
processor core, and Table 35 for guidelines on measuring ringback at the edge fingers. Table 36
lists the ringback specifications for the FC-PGA/FC-PGA2 packages.
Table 34. Signal Ringback Specifications for Non-AGTL+ Signal Simulation at the Processor
Core (S.E.P. and PPGA Packages)
Transition
Maximum Ringback
(with Input Diodes Present)
Unit
Figure
Non-AGTL+ Signals
0→1
1.7
V
14
Non-AGTL+ Signals
1→0
0.7
V
14
Input Signal Group
Notes
NOTE:
1. Unless otherwise noted, all specifications in this table apply to all Celeron processor frequencies.
Table 35. Signal Ringback Guidelines for Non-AGTL+ Signal Edge Finger Measurement
(S.E.P. Package)
Transition
Maximum Ringback
(with Input Diodes Present)
Unit
Figure
Non-AGTL+ Signals
0→1
2.0
V
14
Non-AGTL+ Signals
1→0
0.7
V
14
Input Signal Group
Notes
NOTE:
1. Unless otherwise noted, all specifications in this table apply to all Celeron processor frequencies.
Table 36. Signal Ringback Specifications for Non-AGTL+ Signal Simulation at the Processor
Pins (FC-PGA/FC-PGA2 Packages)
Input Signal Group
Non-AGTL+ Signals
Transition
Maximum Ringback
(with Input Diodes Present)
Unit
Figure
0→1
VREF + 0.200
V
16
PWRGOOD
0→1
2.0
V
16
Non-AGTL+ Signals
1→0
VREF – 0.200
V
16
NOTES:
1. Unless otherwise noted, all specifications in this table apply to all FC-PGA/FC-PGA2 processor frequencies
and cache sizes.
58
Datasheet
Intel® Celeron® Processor up to 1.10 GHz
3.3.3
Settling Limit Guideline
Settling limit defines the maximum amount of ringing at the receiving pin that a signal must reach
before its next transition. The amount allowed is 10 percent of the total signal swing (VHI – VLO)
above and below its final value. A signal should be within the settling limits of its final value, when
either in its high state or low state, before it transitions again.
Signals that are not within their settling limit before transitioning are at risk of unwanted
oscillations which could jeopardize signal integrity. Simulations to verify settling limit may be
done either with or without the input protection diodes present. Violation of the settling limit
guideline is acceptable if simulations of 5 to 10 successive transitions do not show the amplitude of
the ringing increasing in the subsequent transitions.
3.4
AGTL+ Signal Quality Specifications and Measurement
Guidelines (FC-PGA/FC-PGA2 Packages)
3.4.1
Overshoot/Undershoot Guidelines (FC-PGA/FC-PGA2 Packages)
Overshoot (or undershoot) is the absolute value of the maximum voltage above the nominal high
voltage or below VSS. The overshoot guideline limits transitions beyond VCC or VSS due to the fast
signal edge rates. The processor can be damaged by repeated overshoot events on 1.5 V or 2.5 V
tolerant buffers if the charge is large enough (i.e., if the overshoot is great enough). Determining
the impact of an overshoot/undershoot condition requires knowledge of the magnitude, the pulse
direction and the activity factor (AF). Permanent damage to the processor is the likely result of
excessive overshoot/undershoot. Violating the overshoot/undershoot guideline will also make
satisfying the ringback specification difficult.
When performing simulations to determine impact of overshoot and overshoot, ESD diodes must
be properly characterized. ESD protection diodes do not act as voltage clamps and will not provide
overshoot or undershoot protection. ESD diodes modeled within Intel I/O Buffer models do not
clamp undershoot or overshoot and will yield correct simulation results. If other I/O buffer models
are being used to characterize the FC-PGA/FC-PGA2 processor performance, care must be taken
to ensure that ESD models do not clamp extreme voltage levels. Intel I/O Buffer models also
contain I/O capacitance characterization. Therefore, removing the ESD diodes from an I/O Buffer
model will impact results and may yield excessive overshoot/undershoot.
3.4.2
Overshoot/Undershoot Magnitude (FC-PGA/FC-PGA2 Packages)
Magnitude describes the maximum potential difference between a signal and its voltage reference
level, VSS (overshoot) and VTT (undershoot). While overshoot can be measured relative to VSS
using one probe (probe to signal and GND lead to VSS), undershoot must be measured relative to
VTT. This can be accomplished by simultaneously measuring the VTT plane while measuring the
signal undershoot. Today’s oscilloscopes can easily calculate the true undershoot waveform using a
Math function where the Signal waveform is subtracted from the VTT waveform. The true
undershoot waveform can also be obtained with the following oscilloscope data file analysis:
Converted Undershoot Waveform = VTT– Signal_measured
Note:
The converted undershoot waveform appears as a positive (overshoot) signal.
Note:
Overshoot (rising edge) and undershoot (falling edge) conditions are separate and their impact
must be determined independently.
Datasheet
59
Intel® Celeron® Processor up to 1.10 GHz
After the true waveform conversion, the undershoot/overshoot specifications shown in Table 38
and Table 39 can be applied to the converted undershoot waveform using the same magnitude and
pulse duration specifications used with an overshoot waveform.
Overshoot/undershoot magnitude levels must observe the Absolute Maximum Specifications listed
in Table 38 and Table 39. These specifications must not be violated at any time regardless of bus
activity or system state. Within these specifications are threshold levels that define different
allowed pulse durations. Provided that the magnitude of the overshoot/undershoot is within the
Absolute Maximum Specifications (2.18V), the pulse magnitude, duration and activity factor must
all be used to determine if the overshoot/undershoot pulse is within specifications.
3.4.3
Overshoot/Undershoot Pulse Duration (FC-PGA/FC-PGA2 Packages)
Pulse duration describes the total time an overshoot/undershoot event exceeds the overshoot/
undershoot reference voltage (Vos_ref = 1.635 V). The total time could encompass several
oscillations above the reference voltage. Multiple overshoot/undershoot pulses within a single
overshoot/undershoot event may need to be measured to determine the total pulse duration.
Note:
Oscillations below the reference voltage can not be subtracted from the total overshoot/undershoot
pulse duration.
Note:
Multiple Overshoot/Undershoot events occurring within the same clock cycle must be considered
together as one event. Using the worst case Overshoot/Undershoot Magnitude, sum together the
individual Pulse Durations to determine the total Overshoot/Undershoot Pulse Duration for that
total event.
3.4.4
Activity Factor (FC-PGA/FC-PGA2 Packages)
Activity Factor (AF) describes the frequency of overshoot (or undershoot) occurrence relative to a
clock. Since the highest frequency of assertion of an AGTL+ or a CMOS signal is every other
clock, an AF = 1 indicates that the specific overshoot (or undershoot) waveform occurs EVERY
OTHER clock cycle. Thus, an AF = 0.01 indicates that the specific overshoot (or undershoot)
waveform occurs one time in every 200 clock cycles.
The specifications provided in Table 38 and Table 39 show the Maximum Pulse Duration allowed
for a given Overshoot/Undershoot Magnitude at a specific Activity Factor. Each table entry is
independent of all others, meaning that the Pulse Duration reflects the existence of overshoot/
undershoot events of that magnitude ONLY. A platform with an overshoot/undershoot that just
meets the pulse duration for a specific magnitude where the AF < 1, means that there can be NO
other overshoot/undershoot events, even of lesser magnitude (note that if AF = 1, then the event
occurs at all times and no other events can occur).
60
Note:
Activity factor for AGTL+ signals is referenced to BCLK frequency.
Note:
Activity factor for CMOS signals is referenced to PICCLK frequency.
Datasheet
Intel® Celeron® Processor up to 1.10 GHz
3.4.5
Reading Overshoot/Undershoot Specification Tables (FC-PGA/
FC-PGA2 Packages)
The overshoot/undershoot specification for the FC-PGA/FC-PGA2 packages processor is not a
simple single value. Instead, many factors are needed to determine the over/undershoot
specification. In addition to the magnitude of the overshoot, the following parameters must also be
known: the junction temperature the processor will be operating, the width of the overshoot (as
measured above 1.635 V) and the Activity Factor (AF). To determine the allowed overshoot for a
particular overshoot event, the following must be done:
1. Determine the signal group that particular signal falls into. If the signal is an AGTL+ signal
operating with a 66 MHz system bus, use Table 38 (66 MHz AGTL+ signal group). If the
signal is a CMOS signal, use Table 39 (33 MHz CMOS signal group).
2. Determine the maximum junction temperature (Tj) for the range of processors that the system
will support (80oC or 90oC).
3. Determine the Magnitude of the overshoot (relative to VSS)
4. Determine the Activity Factor (how often does this overshoot occur?)
5. From the appropriate Specification table, read off the Maximum Pulse Duration (in ns)
allowed.
6. Compare the specified Maximum Pulse Duration to the signal being measured. If the Pulse
Duration measured is less than the Pulse Duration shown in the table, then the signal meets the
specifications.
The above procedure is similar for undershoots after the undershoot waveform has been converted
to look like an overshoot. Undershoot events must be analyzed separately from Overshoot events
as they are mutually exclusive.
Table 37 shows an example of how the maximum pulse duration is determined for a given
waveform.
Table 37. Example Platform Information
Required Information
FSB Signal Group
Maximum Platform Support
66 MHz AGTL+
Max Tj
90 °C
Overshoot Magnitude
2.13V
Activity Factor (AF)
Notes
0.1
Measured Value
Measured overshoot occurs on
average every 20 clocks
NOTES:
1. Corresponding Maximum Pulse Duration Specification – 3.2 ns
2. Pulse Duration (measured) – 2.0 ns
Given the above parameters, and using Table 38 (90oC/AF=0.1 column) the maximum allowed
pulse duration is 3.2 ns. Since the measured pulse duration is 2.0ns, this particular overshoot event
passes the overshoot specifications, although this doesn't guarantee that the combined overshoot/
undershoot events meet the specifications.
Datasheet
61
Intel® Celeron® Processor up to 1.10 GHz
3.4.6
Determining if a System meets the Overshoot/Undershoot
Specifications (FC-PGA/FC-PGA2 Packages)
The overshoot/undershoot specifications listed in the following tables specify the allowable
overshoot/undershoot for a single overshoot/undershoot event. However most systems will have
multiple overshoot and/or undershoot events that each have their own set of parameters (duration,
AF and magnitude). While each overshoot on its own may meet the overshoot specification, when
the total impact of all overshoot events is accounted for, the system may fail. A guideline to ensure
a system passes the overshoot and undershoot specifications is shown below. It is important to meet
these guidelines; otherwise, contact your Intel field representative.
1. Insure no signal (CMOS or AGTL+) ever exceed the 1.635 V; OR
2. If only one overshoot/undershoot event magnitude occurs, ensure it meets the over/undershoot
specifications in the following tables; OR
3. If multiple overshoots and/or multiple undershoots occur, measure the worst case pulse
duration for each magnitude and compare the results against the AF = 1 specifications. If all of
these worst case overshoot or undershoot events meet the specifications
(measured time < specifications) in the table (where AF=1), then the system passes.
The following notes apply to Table 38 and Table 39.
NOTES:
1. Overshoot/Undershoot Magnitude = 2.18 V is an Absolute value and should never be exceeded
2. Overshoot is measured relative to VSS
3. Undershoot is measured relative to VTT
4. Overshoot/Undershoot Pulse Duration is measured relative to 1.635 V.
5. Ringbacks below VTT can not be subtracted from Overshoots/Undershoots.
6. Lesser Undershoot does not allocate longer or larger Overshoot.
7. Consult the appropriate layout guidelines provided in the specific platform design guide.
8. All values specified by design characterization.
Table 38. 66 MHz AGTL+ Signal Group Overshoot/Undershoot Tolerance at Processor Pins
(FC-PGA/FC-PGA2 Packages)
Maximum Pulse Duration at Tj = 80 °C
(ns)
Maximum Pulse Duration at Tj = 90 °C
(ns)
AF = 0.01
AF = 0.1
AF = 1
AF = 0.01
AF = 0.1
AF = 1
2.18 V
30
3.8
0.38
18
1.8
0.18
2.13 V
30
7.4
0.74
30
3.2
0.32
2.08 V
30
13.6
1.36
30
6.4
0.64
2.03 V
30
25
2.5
30
12
1.1
1.98 V
30
30
4.56
30
22
2
1.93 V
30
30
8.2
30
30
3.8
1.88 V
30
30
15
30
30
6.8
Overshoot/
Undershoot
Magnitude
NOTES:
1. BCLK period is 30.0 ns.
2. Measurements taken at the processor socket pins on the solder-side of the motherboard.
62
Datasheet
Intel® Celeron® Processor up to 1.10 GHz
Table 39. 33 MHz CMOS Signal Group Overshoot/Undershoot Tolerance at Processor Pins
(FC-PGA/FC-PGA2 Packages)
Overshoot/
Undershoot
Magnitude
Maximum Pulse Duration at Tj = 80 °C
(ns)
Maximum Pulse Duration at Tj = 90 °C
(ns)
AF = 0.01
AF = 0.01
AF = 0.1
AF = 1
AF = 0.1
AF = 1
2.18 V
60
7.6
0.76
36
3.6
0.36
2.13 V
60
14.8
1.48
60
6.4
0.64
2.08 V
60
27.2
2.7
60
12.8
1.2
2.03 V
60
50
5
60
24
2.2
1.98 V
60
60
9.1
60
44
4
1.93 V
60
60
16.4
60
60
7.6
1.88 V
60
60
30
60
60
13.6
NOTES:
1. PICCLK period is 30 ns.
2. Measurements taken at the processor socket pins on the solder-side of the motherboard.
Figure 15. Maximum Acceptable AGTL+ Overshoot/Undershoot Waveform
(FC-PGA/FC-PGA2 Packages)
Time Dependent
Overshoot
2.18V
2.08V
1.98V
1.88V
1.635V
VTT
Converted Undershoot
Waveform
Max
Overshoot
Magnitude
Undershoot
Magnitude
Vss
Overshoot
= Signal - Vss
Magnitude
Undershoot
= VTT - Signal
Magnitude
Datasheet
Time Dependent
Undershoot
63
Intel® Celeron® Processor up to 1.10 GHz
3.5
Non-AGTL+ Signal Quality Specifications and Measurement
Guidelines
There are three signal quality parameters defined for non-AGTL+ signals: overshoot/undershoot,
ringback, and settling limit. All three signal quality parameters are shown in Figure 16 for the nonAGTL+ signal group.
Figure 16. Non-AGTL+ Overshoot/Undershoot, Settling Limit, and Ringback 1
Settling Limit
Overshoot
VHI
Rising-Edge
Ringback
Falling-Edge
Ringback
Settling Limit
VLO
VSS
Time
Undershoot
NOTES:
1. VHI = 1.5 V for all non-AGTL+ signals except for BCLK, PICCLK, and PWRGOOD. VHI = 2.5 V for BCLK,
PICCLK, and PWRGOOD. BCLK and PICCLK signal quality is detailed in Section 3.1.
64
Datasheet
Intel® Celeron® Processor up to 1.10 GHz
4.0
Thermal Specifications and Design Considerations
This section provides needed data for designing a thermal solution. However, for the correct
thermal measuring processes, refer to AP-905, Intel® Pentium® III Processor Thermal Design
Guidelines (Order Number 245087). For the FC-PGA/FC-PGA2 using flip chip pin grid array
packaging technology, Intel specifies the junction temperature (Tjunction). For the S.E.P. package
and PPGA package, Intel specifies the case temperature (Tcase).
4.1
Thermal Specifications
Table 40 provides both the Processor Power and Heatsink Design Target for Celeron processors.
Processor Power is defined as the total power dissipated by the processor core and its package.
Therefore, the S.E.P. Package’s Processor Power would also include power dissipated by the
AGTL+ termination resistors. The overall system chassis thermal design must comprehend the
entire Processor Power. The Heatsink Design Target consists of only the processor core, which
dissipates the majority of the thermal power.
Systems should design for the highest possible thermal power, even if a processor with a lower
thermal dissipation is planned. The processor’s heatslug is the attach location for all thermal
solutions. The maximum and minimum case temperatures are also specified in Table 40. A thermal
solution should be designed to ensure the temperature of the case never exceeds these
specifications. Refer to the Intel developer Web site at http://developer.intel.com for more
information.
Datasheet
65
Intel® Celeron® Processor up to 1.10 GHz
Table 40. Processor Power for the PPGA and FC-PGA Packages
Processor
Core
Frequency
L2
Cache
Size
(KB)
Processor
Thermal
Design
Power2,3
(W) up to
CPUID
0686h
Processor
Thermal
Design
Power2,3
(W) for
CPUID
068Ah
Power
Density 5
(W/cm2)
For
CPUID
0686h
Power
Density 5
(W/cm2)
For
CPUID
068Ah
Min
TCASE
(°C)
Max
TCASE
(°C)
Max10
TJUNCTION
(°C)
TJUNCTION
Offset 6
(°C)
333 MHz
128
19.7
NA
NA
NA
5
85
NA
NA
366 MHz
128
21.7
NA
NA
NA
5
85
NA
NA
400 MHz
128
23.7
NA
NA
NA
5
85
NA
NA
433 MHz
128
24.1
NA
NA
NA
5
85
NA
NA
466 MHz
128
25.6
NA
NA
NA
5
70
NA
NA
500 MHz
128
27.0
NA
NA
NA
5
70
NA
NA
533 MHz
128
28.3
NA
NA
NA
5
70
NA
NA
3
4,7
NA
4
533A MHz
128
14.0
5663 MHz
128
14.94,8
17.5
NA
NA
NA
90
2.6
19.2
18.54
304
NA
NA
90
2.6
6003 MHz
128
15.84,9
19.64
19.74
30.54
633 MHz
NA
NA
90
2.6
128
16.54
20.24
25.84
31.54
NA
NA
82
2.6
667 MHz
128
17.54
21.14
27.34
32.94
NA
NA
82
2.6
700 MHz
128
18.34
21.94
28.64
34.14
NA
NA
80
2.7
733 MHz
128
4
19.1
4
22.8
4
29.8
4
35.5
NA
NA
80
2.8
766 MHz
128
20.04
23.64
31.34
36.84
NA
NA
80
3.0
800 MHz
128
4
20.8
4
24.5
4
32.6
4
38.2
NA
NA
80
3.0
850 MHz
128
22.54
25.74
35.24
40.04
NA
NA
80
3.3
900 MHz
128
NA
26.74
NA
41.64
NA
NA
77
3.6
950 MHz
128
NA
28.0
NA
43.64
NA
NA
79
3.8
1 GHz
128
NA
29.0
NA
45.24
NA
NA
75
3.8
1.10 GHz
128
NA
33.0
NA
51.44
NA
NA
77
4.4
NOTES:
1. These values are specified at nominal VCCCORE for the processor core.
2. Thermal Design Power (TDP) represents the maximum amount of power the thermal solution is required to
dissipate. The thermal solution should be designed to dissipate the TDP power without exceeding the
maximum TJUNCTION specification.
3. FC-PGA package only.
4. The Thermal Design Power (TDP) Celeron® processors in production has been redefined. The updated TDP
values are based on device characterization and do not reflect any silicon design changes to lower processor
power consumption. The TDP values represent the thermal design point required to cool Celeron®
processors in the platform environment while executing thermal validation type software.
5. Power density is the maximum power the processor die can dissipate (i.e., processor power) divided by the
die area over which the power is generated. Power for these processors is generated from the core area
shown in Figure 17.
6. Tjunctionoffset is the worst-case difference between the thermal reading from the on-die thermal diode and the
hottest location on the processor’s core. Tjunctionoffset values do not include any thermal diode kit
measurement error. Diode kit measurement error must be added to the Tjunctionoffset value from the table.
Intel has characterized the use of the Analog Devices AD1021 diode measurement kit and found its
measurement error to be ±1 oC.
7. For processors with a CPUID of 0683h, the TDP number is 11.2 W.
8. For processors with a CPUID of 0683h, the TDP number is 11.9 W.
9. For processors with a CPUID of 0683h, the TDP number is 12.6 W.
10.The Tj min for processors with a CPUID of 068x is 0 oC with a 3 oC– 5 oC margin error.
66
Datasheet
Intel® Celeron® Processor up to 1.10 GHz
Table 41. Intel® Celeron® Processor for the FC-PGA2 Package Thermal Design Power 1
Processor
Processor Core
Frequency (MHz)
System Bus
Frequency (MHz)
Processor
Thermal Design
Power 2,3
CPUID 068Ah (W)
Maximum
Tcase4 (°C)
900
900
100
30.0
72
5
950
950
100
32.0
72
5
1 GHz
1000
100
33.9
69
5
Additional
Notes
NOTES:
1. These values are specified at nominal VCCCORE for the processor pins.
2. Thermal Design Power (TDP) represents the maximum amount of power the thermal solution is required to
dissipate. The thermal solution should be designed to dissipate the TDP power without exceeding the
maximum Tcase specification.
3. TDP does not represent the power delivery and voltage regulation requirements for the processor. Refer to
Table 5 for voltage regulation and electrical specifications.
4. TCaseOffset is the worst-case difference between the maximum case temperature and the thermal diode
temperature on the processor’s core. For more information refer to the document, Intel® Pentium® III
Processor in the FC-PGA2 Package Thermal Design Guide.
5. This processor exists in both FC-PGA and FC-PGA2 packages.
Figure 17 is a block diagram of the Intel Celeron FC-PGA/FC-PGA2 processor die layout. The
layout differentiates the processor core from the cache die area. In effect, the thermal design power
identified in Table 40 is dissipated entirely from the processor core area. Thermal solution designs
should compensate for this smaller heat flux area and not assume that the power is uniformly
distributed across the entire die area.
Figure 17. Processor Functional Die Layout (CPUID 0686h)(1)
0.337”
0.275”
Die Area = 0.90 cm2
Cache Area = 0.26 cm2
Core Area = 0.64 cm2
0.146”
0.414”
Cache Area
0.04 in2
Die Area
0.14 in2
Core Area
0.10 in2
1. For CPUID 0x68A, the die area is 0.94 cm2, the cache area is 0.30 cm2, and the core area is 0.64 cm2.
Figure 18. Processor Functional Die Layout (up to CPUID 0683h)
0.362”
0.292”
Die Area = 1.05 cm2
Cache Area = 0.32 cm2
Core Area = 0.73 cm2
0.170”
0.448”
Datasheet
Cache Area
0.05 in2
Die Area
0.16 in2
Core Area
0.11 in2
67
Intel® Celeron® Processor up to 1.10 GHz
4.1.1
Thermal Diode
The Celeron processor incorporates an on-die diode that can be used to monitor the die
temperature. A thermal sensor located on the motherboard or a standalone measurement kit may
monitor the die temperature of the Intel Celeron processor for thermal management purposes.
Table 42 to Table 44 provide the diode parameter and interface specifications.
Note:
The reading of the thermal sensor connected to the thermal diode will not necessarily reflect the
temperature of the hottest location on the die. This is due to inaccuracies in the thermal sensor, ondie temperature gradients between the location of the thermal diode and the hottest location on the
die at a given point in time, and time based variations in the die temperature measurement. Time
based variations can occur when the sampling rate of the thermal diode (by the thermal sensor) is
slower than the rate at which the Tjunction temperature can change.
Table 42. Thermal Diode Parameters (S.E.P. and PPGA Packages)
Symbol
Min
Iforward bias
5
n_ideality
1.0000
Typ
Max
Unit
500
uA
1.0065
1.0173
Notes
1
2,3
NOTES:
1. Intel does not support or recommend operation of the thermal diode under reverse bias.
2. At room temperature with a forward bias of 630 mV.
3. n_ideality is the diode ideality factor parameter, as represented by the diode equation:
I-Io(e (Vd*q)/(nkT) – 1).
4. Not 100% tested. Specified by design characterization.
Table 43. Thermal Diode Parameters (FC-PGA/FC-PGA2 Packages)
Symbol
Min
Iforward bias
5
n_ideality
1.0057
Typ
Max
Unit
300
uA
1.0080
1.0125
Notes
1
2, 3
NOTES:
1. Intel does not support or recommend operation of the thermal diode under reverse bias.
2. Characterized at 100° C with a forward bias current of 5–300 µA.
3. The ideality factor, n, represents the deviation from ideal diode behavior as exemplified by the diode
equation:
Ifw=Is(e^ ((Vd*q)/(nkT)) – 1), where Is = saturation current, q = electronic charge, Vd = voltage across the
diode, k = Boltzmann Constant, and T = absolute temperature (Kelvin).
4. Not 100% tested. Specified by design characterization.
Table 44. Thermal Diode Interface
68
Pin Name
SC242 Connector
Signal #
370-Pin Socket Pin #
THERMDP
B14
AL31
diode anode (p junction)
THERMDN
B15
AL29
diode cathode (n junction)
Pin Description
Datasheet
Intel® Celeron® Processor up to 1.10 GHz
5.0
Mechanical Specifications
There are three package technologies which Celeron processors use. They are the S.E.P. Package,
the PPGA package, and the FC-PGA/FC-PGA2 packages. The S.E.P. Package and FC-PGA/
FC-PGA2 packages contain the processor core and passive components, while the PPGA package
does not have passive components.
The processor edge connector defined in this document is referred to as the “SC242 connector.”
See the SC242 Design Guidelines (Order Number 243397) for further details on the edge
connector.
The processor socket connector is defined in this document is referred to as the “370-pin socket.”
See the 370-Pin Socket (PGA370) Design Guidelines (Order Number 244410) for further details on
the socket.
5.1
S.E.P. Package
This section defines the mechanical specifications and signal definitions for the Celeron processor
in the S.E.P. Package.
5.1.1
Materials Information
The Celeron processor requires a retention mechanism. This retention mechanism may require
motherboard holes to be 0.159" diameter if low cost plastic fasteners are used to secure the
retention mechanisms. The larger diameter holes are necessary to provide a robust structural design
that can shock and vibe testing. If captive nuts are used in place of the plastic fasteners, then either
the 0.159" or the 0.140" diameter holes will suffice as long as the attach mount is used.
Figure 19 with substrate dimensions is provided to aid in the design of a heatsink and clip. In
Figure 20 all area on the secondary side of the substrate is zoned “keepout”, except for 25 mils
around the tooling holes and the top and side edges of the substrate.
Datasheet
69
Intel® Celeron® Processor up to 1.10 GHz
Figure 19. Processor Substrate Dimensions (S.E.P. Package)
+.007
.062 -.005
-Z-
-Y-
2.608
27.4 mm SR
Opening Square
25.4 mm Copper
Slug Square
1.660
1.370
-Y.615
.323
.814
1.196
3.804
-Y-
Figure 20. Processor Substrate Primary/Secondary Side Dimensions (S.E.P. Package)
.025 Typ Max.
Non-Keepout Area
.025 Typ Max.
Non-Keepout Area
Secondary Side
There Will be No Components on
Secodonary Side
-D-
-G-E-
-H-
.025 Typ Max.
Non-Keepout Area
.025 Typ Max.
Non-Keepout Are
Primary Side
-D-G-H-
5.1.2
-E-
Signal Listing (S.E.P. Package)
Table 45 and Table 46 provide the processor edge finger and SC242 connector signal definitions
for Celeron processor. The signal locations on the SC242 edge connector are to be used for signal
routing, simulation, and component placement on the motherboard.
70
Datasheet
Intel® Celeron® Processor up to 1.10 GHz
Table 45. S.E.P. Package Signal Listing
by Pin Number
Pin
No.
A1
Datasheet
Pin Name
VTT
Signal Buffer Type
Table 45. S.E.P. Package Signal Listing
by Pin Number
Pin
No.
Pin Name
Signal Buffer Type
Power/Other
A35
D60#
AGTL+ I/O
D53#
AGTL+ I/O
A2
VSS
Power/Other
A36
A3
VTT
Power/Other
A37
D57#
AGTL+ I/O
A4
IERR#
CMOS Output
A38
VSS
Power/Other
A5
A20M#
CMOS Input
A39
D46#
AGTL+ I/O
D49#
AGTL+ I/O
A6
VSS
Power/Other
A40
A7
FERR#
CMOS Output
A41
D51#
AGTL+ I/O
A8
IGNNE#
CMOS Input
A42
VSS
Power/Other
A9
TDI
TAP Input
A43
D42#
AGTL+ I/O
D45#
AGTL+ I/O
A10
VSS
Power/Other
A44
A11
TDO
TAP Output
A45
D39#
AGTL+ I/O
A12
PWRGOOD
CMOS Input
A46
VSS
Power/Other
A13
TESTHI
CMOS Test Input
A47
Reserved
Reserved for Future Use
D43#
AGTL+ I/O
A14
VSS
Power/Other
A48
A15
THERMTRIP#
CMOS Output
A49
D37#
AGTL+ I/O
A16
Reserved
Reserved for Future Use
A50
VSS
Power/Other
A17
LINT0/INTR
CMOS Input
A51
D33#
AGTL+ I/O
D35#
AGTL+ I/O
A18
VSS
Power/Other
A52
A19
PICD0
APIC I/O
A53
D31#
AGTL+ I/O
A20
PREQ#
CMOS Input
A54
VSS
Power/Other
A21
BP3#
AGTL+ I/O
A55
D30#
AGTL+ I/O
D27#
AGTL+ I/O
A22
VSS
Power/Other
A56
A23
BPM0#
AGTL+ I/O
A57
D24#
AGTL+ I/O
A24
Reserved
Reserved for Pentium II
processor
A58
VSS
Power/Other
A59
D23#
AGTL+ I/O
A25
Reserved
Reserved for Pentium II
processor
A60
D21#
AGTL+ I/O
A26
VSS
Power/Other
A61
D16#
AGTL+ I/O
VSS
Power/Other
Reserved
Reserved for Pentium II
processor
A62
A27
A63
D13#
AGTL+ I/O
A28
Reserved
Reserved for Pentium II
processor
A64
D11#
AGTL+ I/O
A65
D10#
AGTL+ I/O
A29
Reserved
Reserved for Pentium II
processor
A66
VSS
Power/Other
A30
VSS
Power/Other
A67
D14#
AGTL+ I/O
D9#
AGTL+ I/O
A31
Reserved
Reserved for Pentium II
processor
A68
A69
D8#
AGTL+ I/O
A32
D61#
AGTL+ I/O
A70
VSS
Power/Other
A33
D55#
AGTL+ I/O
A71
D5#
AGTL+ I/O
A34
VSS
Power/Other
71
Intel® Celeron® Processor up to 1.10 GHz
Table 45. S.E.P. Package Signal Listing
by Pin Number
Pin
No.
72
Pin Name
Signal Buffer Type
Table 45. S.E.P. Package Signal Listing
by Pin Number
Pin
No.
Pin Name
Signal Buffer Type
A72
D3#
AGTL+ I/O
A107
REQ2#
AGTL+ I/O
A73
D1#
AGTL+ I/O
A108
REQ3#
AGTL+ I/O
A74
VSS
Power/Other
A109
HITM#
AGTL+ I/O
A75
BCLK
System Bus Clock Input
A110
VSS
Power/Other
A76
Reserved
Reserved for Pentium II
processor
A111
DBSY#
AGTL+ I/O
A112
RS1#
AGTL+ Input
A113
Reserved
Reserved for Future Use
VSS
Power/Other
A77
Reserved
Reserved for Pentium II
processor
A78
VSS
Power/Other
A114
ADS#
AGTL+ I/O
Reserved
Reserved for Pentium II
processor
A115
A79
A116
Reserved
Reserved for Future Use
A117
Reserved
Reserved for Pentium II
processor
A80
Reserved
Reserved for Pentium II
processor
A81
A30#
AGTL+ I/O
A118
VSS
Power/Other
A82
VSS
Power/Other
A119
VID2
Power/Other
A83
A31#
AGTL+ I/O
A120
VID1
Power/Other
A84
A27#
AGTL+ I/O
A121
VID4
Power/Other
A85
A22#
AGTL+ I/O
B1
EMI
Power/Other
A86
VSS
Power/Other
B2
FLUSH#
CMOS Input
A87
A23#
AGTL+ I/O
B3
SMI#
CMOS Input
A88
Reserved
Reserved for Future Use
B4
INIT#
CMOS Input
A89
A19#
AGTL+ I/O
B5
VTT
Power/Other
A90
VSS
Power/Other
B6
STPCLK#
CMOS Input
A91
A18#
AGTL+ I/O
B7
TCK
TAP Input
A92
A16#
AGTL+ I/O
B8
SLP#
CMOS Input
A93
A13#
AGTL+ I/O
B9
VTT
Power/Other
A94
VSS
Power/Other
B10
TMS
TAP Input
A95
A14#
AGTL+ I/O
B13
VCCCORE
Power/Other
A96
A10#
AGTL+ I/O
B14
THERMDP
Power/Other
A97
A5#
AGTL+ I/O
B15
THERMDN
Power/Other
A98
VSS
Power/Other
B16
LINT1/NMI
CMOS Input
A99
A9#
AGTL+ I/O
B17
VCCCORE
Power/Other
A100
A4#
AGTL+ I/O
B18
PICCLK
APIC Clock Input
A101
BNR#
AGTL+ I/O
B19
BP2#
AGTL+ I/O
A102
VSS
Power/Other
B20
Reserved
Reserved for Future Use
A103
BPRI#
AGTL+ Input
B21
BSEL
Power/Other
A104
TRDY#
AGTL+ Input
B22
PICD1
APIC I/O
A105
DEFER#
AGTL+ Input
B23
PRDY#
AGTL+ Output
A106
VSS
Power/Other
B24
BPM1#
AGTL+ I/O
Datasheet
Intel® Celeron® Processor up to 1.10 GHz
Table 45. S.E.P. Package Signal Listing
by Pin Number
Pin
No.
B25
Datasheet
Pin Name
Signal Buffer Type
Table 45. S.E.P. Package Signal Listing
by Pin Number
Pin
No.
Pin Name
Signal Buffer Type
VCCCORE
Power/Other
B61
EMI
Power/Other
B26
Reserved
Reserved for Pentium II
processor
B62
D20#
AGTL+ I/O
B63
D17#
AGTL+ I/O
B27
Reserved
Reserved for Pentium II
processor
B64
D15#
AGTL+ I/O
VCCCORE
Power/Other
Reserved
Reserved for Pentium II
processor
B65
B28
B66
D12#
AGTL+ I/O
B29
VCCCORE
Power/Other
B67
D7#
AGTL+ I/O
B30
D62#
AGTL+ I/O
B68
D6#
AGTL+ I/O
B31
D58#
AGTL+ I/O
B69
VCCCORE
Power/Other
B32
D63#
AGTL+ I/O
B70
D4#
AGTL+ I/O
B33
VCCCORE
Power/Other
B71
D2#
AGTL+ I/O
B34
D56#
AGTL+ I/O
B72
D0#
AGTL+ I/O
B35
D50#
AGTL+ I/O
B73
VCCCORE
Power/Other
B36
D54#
AGTL+ I/O
B74
RESET#
AGTL+ Input
B37
VCCCORE
Power/Other
B75
Reserved
Reserved for Future Use
B38
D59#
AGTL+ I/O
B76
Reserved
Reserved for Future Use
B39
D48#
AGTL+ I/O
B77
VCCCORE
Power/Other
B40
D52#
AGTL+ I/O
B78
Reserved
B41
EMI
Power/Other
Reserved for Pentium II
processor
B42
D41#
AGTL+ I/O
B79
Reserved
Reserved for Pentium II
processor
B43
D47#
AGTL+ I/O
B80
A29#
AGTL+ I/O
B44
D44#
AGTL+ I/O
B81
EMI
Power/Other
B45
VCCCORE
Power/Other
B82
A26#
AGTL+ I/O
B46
D36#
AGTL+ I/O
B83
A24#
AGTL+ I/O
B47
D40#
AGTL+ I/O
B84
A28#
AGTL+ I/O
B48
D34#
AGTL+ I/O
B85
VCCCORE
Power/Other
VCCCORE
Power/Other
B49
B86
A20#
AGTL+ I/O
B50
D38#
AGTL+ I/O
B87
A21#
AGTL+ I/O
B51
D32#
AGTL+ I/O
B88
A25#
AGTL+ I/O
B52
D28#
AGTL+ I/O
B89
VCCCORE
Power/Other
VCCCORE
Power/Other
B53
B90
A15#
AGTL+ I/O
B54
D29#
AGTL+ I/O
B91
A17#
AGTL+ I/O
B55
D26#
AGTL+ I/O
B92
A11#
AGTL+ I/O
B56
D25#
AGTL+ I/O
B93
VCCCORE
Power/Other
VCCCORE
Power/Other
B57
B94
A12#
AGTL+ I/O
B58
D22#
AGTL+ I/O
B95
A8#
AGTL+ I/O
B59
D19#
AGTL+ I/O
B96
A7#
AGTL+ I/O
B60
D18#
AGTL+ I/O
73
Intel® Celeron® Processor up to 1.10 GHz
Table 45. S.E.P. Package Signal Listing
by Pin Number
Pin
No.
74
Pin Name
Signal Buffer Type
B97
VCCCORE
Power/Other
B98
A3#
AGTL+ I/O
B99
A6#
AGTL+ I/O
B100
EMI
Power/Other
B101
SLOTOCC#
Power/Other
B102
REQ0#
AGTL+ I/O
B103
REQ1#
AGTL+ I/O
B104
REQ4#
AGTL+ I/O
B105
VCCCORE
Power/Other
B106
LOCK#
AGTL+ I/O
B107
DRDY#
AGTL+ I/O
B108
RS0#
AGTL+ Input
B109
VCC5
Power/Other
B11
TRST#
TAP Input
B110
HIT#
AGTL+ I/O
B111
RS2#
AGTL+ Input
Table 45. S.E.P. Package Signal Listing
by Pin Number
Pin
No.
B112
Pin Name
Signal Buffer Type
Reserved
Reserved for Future Use
B113
VCCL2
Power/Other. Reserved
for Pentium II processor
B114
Reserved
Reserved for Pentium II
processor
B115
Reserved
Reserved for Pentium II
processor
B116
Reserved
Reserved for Pentium II
processor
B117
VCCL2
Power/Other. Reserved
for Pentium II processor
B118
Reserved
Reserved for Pentium II
processor
B119
VID3
Power/Other
B12
Reserved
Reserved for Future Use
B120
VID0
Power/Other
B121
VCCL2
Power/Other. Reserved
for Pentium II processor
Datasheet
Intel® Celeron® Processor up to 1.10 GHz
Table 46. S.E.P. Package Signal Listing
by Signal Name
Pin Name
A3#
Datasheet
Pin
No.
B98
Signal Buffer Type
Table 46. S.E.P. Package Signal Listing
by Signal Name
Pin Name
Pin
No.
Signal Buffer Type
AGTL+ I/O
BPRI#
A103
AGTL+ Input
B21
Power/Other
A4#
A100
AGTL+ I/O
BSEL
A5#
A97
AGTL+ I/O
D00#
B72
AGTL+ I/O
A6#
B99
AGTL+ I/O
D1#
A73
AGTL+ I/O
A7#
B96
AGTL+ I/O
D2#
B71
AGTL+ I/O
A72
AGTL+ I/O
A8#
B95
AGTL+ I/O
D3#
A9#
A99
AGTL+ I/O
D5#
A71
AGTL+ I/O
A10#
A96
AGTL+ I/O
D6#
B68
AGTL+ I/O
A11#
B92
AGTL+ I/O
D7#
B67
AGTL+ I/O
A69
AGTL+ I/O
A12#
B94
AGTL+ I/O
D8#
A13#
A93
AGTL+ I/O
D9#
A68
AGTL+ I/O
A14#
A95
AGTL+ I/O
D10#
A65
AGTL+ I/O
A15#
B90
AGTL+ I/O
D11#
A64
AGTL+ I/O
B66
AGTL+ I/O
A16#
A92
AGTL+ I/O
D12#
A17#
B91
AGTL+ I/O
D13#
A63
AGTL+ I/O
A18#
A91
AGTL+ I/O
D14#
A67
AGTL+ I/O
A19#
A89
AGTL+ I/O
D15#
B64
AGTL+ I/O
A61
AGTL+ I/O
A20#
B86
AGTL+ I/O
D16#
A20M#
A5
CMOS Input
D17#
B63
AGTL+ I/O
A21#
B87
AGTL+ I/O
D18#
B60
AGTL+ I/O
A22#
A85
AGTL+ I/O
D19#
B59
AGTL+ I/O
B62
AGTL+ I/O
A23#
A87
AGTL+ I/O
D20#
A24#
B83
AGTL+ I/O
D21#
A60
AGTL+ I/O
A25#
B88
AGTL+ I/O
D22#
B58
AGTL+ I/O
A26#
B82
AGTL+ I/O
D23#
A59
AGTL+ I/O
A57
AGTL+ I/O
A27#
A84
AGTL+ I/O
D24#
A28#
B84
AGTL+ I/O
D25#
B56
AGTL+ I/O
A29#
B80
AGTL+ I/O
D26#
B55
AGTL+ I/O
A30#
A81
AGTL+ I/O
D27#
A56
AGTL+ I/O
B52
AGTL+ I/O
A31#
A83
AGTL+ I/O
D28#
ADS#
A115
AGTL+ I/O
D29#
B54
AGTL+ I/O
BCLK
A75
System Bus Clock Input
D30#
A55
AGTL+ I/O
BNR#
A101
AGTL+ I/O
D31#
A53
AGTL+ I/O
B51
AGTL+ I/O
BP2#
B19
AGTL+ I/O
D32#
BP3#
A21
AGTL+ I/O
D33#
A51
AGTL+ I/O
BPM0#
A23
AGTL+ I/O
D34#
B48
AGTL+ I/O
BPM1#
B24
AGTL+ I/O
D35#
A52
AGTL+ I/O
75
Intel® Celeron® Processor up to 1.10 GHz
Table 46. S.E.P. Package Signal Listing
by Signal Name
Pin Name
76
Pin
No.
Signal Buffer Type
Table 46. S.E.P. Package Signal Listing
by Signal Name
Pin Name
Pin
No.
Signal Buffer Type
D36#
B46
AGTL+ I/O
FERR#
A7
CMOS Output
D37#
A49
AGTL+ I/O
FLUSH#
B2
CMOS Input
D38#
B50
AGTL+ I/O
HIT#
B110
AGTL+ I/O
D39#
A45
AGTL+ I/O
HITM#
A109
AGTL+ I/O
D4#
B70
AGTL+ I/O
IERR#
A4
CMOS Output
D40#
B47
AGTL+ I/O
IGNNE#
A8
CMOS Input
D41#
B42
AGTL+ I/O
INIT#
B4
CMOS Input
D42#
A43
AGTL+ I/O
LINT0/INTR
A17
CMOS Input
D43#
A48
AGTL+ I/O
LINT1/NMI
B16
CMOS Input
D44#
B44
AGTL+ I/O
LOCK#
B106
AGTL+ I/O
D45#
A44
AGTL+ I/O
PICCLK
B18
APIC Clock Input
D46#
A39
AGTL+ I/O
PICD0
A19
APIC I/O
D47#
B43
AGTL+ I/O
PICD1
B22
APIC I/O
D48#
B39
AGTL+ I/O
PRDY#
B23
AGTL+ Output
D49#
A40
AGTL+ I/O
PREQ#
A20
CMOS Input
D50#
B35
AGTL+ I/O
PWRGOOD
A12
CMOS Input
D51#
A41
AGTL+ I/O
REQ0#
B102
AGTL+ I/O
D52#
B40
AGTL+ I/O
REQ1#
B103
AGTL+ I/O
D53#
A36
AGTL+ I/O
REQ2#
A107
AGTL+ I/O
D54#
B36
AGTL+ I/O
REQ3#
A108
AGTL+ I/O
D55#
A33
AGTL+ I/O
REQ4#
B104
AGTL+ I/O
D56#
B34
AGTL+ I/O
Reserved
A16
Reserved for Future Use
D57#
A37
AGTL+ I/O
Reserved
A47
Reserved for Future Use
D58#
B31
AGTL+ I/O
Reserved
A77
D59#
B38
AGTL+ I/O
Reserved for Pentium II
processor
D60#
A35
AGTL+ I/O
Reserved
A88
Reserved for Future Use
D61#
A32
AGTL+ I/O
Reserved
A116
Reserved for Future Use
Reserved
B12
Reserved for Future Use
Reserved
A113
Reserved for Future Use
Reserved
B20
Reserved for Future Use
Reserved
B76
Reserved for Future Use
Reserved
B112
Reserved for Future Use
Reserved
B79
Reserved for Pentium II
processor
Reserved
B114
Reserved for Pentium II
processor
Reserved
B115
Reserved for Pentium II
processor
D62#
B30
AGTL+ I/O
D63#
B32
AGTL+ I/O
DBSY#
A111
AGTL+ I/O
DEFER#
A105
AGTL+ Input
DRDY#
B107
AGTL+ I/O
EMI
B1
Power/Other
EMI
B41
Power/Other
EMI
B61
Power/Other
EMI
B81
Power/Other
EMI
B100
Power/Other
Datasheet
Intel® Celeron® Processor up to 1.10 GHz
Table 46. S.E.P. Package Signal Listing
by Signal Name
Pin Name
Reserved
Datasheet
Pin
No.
A117
Signal Buffer Type
Reserved for Pentium II
processor
Table 46. S.E.P. Package Signal Listing
by Signal Name
Pin Name
Pin
No.
Signal Buffer Type
TESTHI
A13
CMOS Test Input
THERMDN
B15
Power/Other
THERMDP
B14
Power/Other
Reserved
B116
Reserved for Pentium II
processor
A15
CMOS Output
A24
Reserved for Pentium II
processor
THERMTRIP#
Reserved
TMS
B10
TAP Input
Reserved
A76
Reserved for Pentium II
processor
TRDY#
A104
AGTL+ Input
Reserved
B75
Reserved for Future Use
TRST#
B11
TAP Input
B109
Power/Other
A79
Reserved for Pentium II
processor
VCC5
Reserved
VCCCORE
B13
Power/Other
Reserved
A80
Reserved for Pentium II
processor
VCCCORE
B17
Power/Other
B25
Power/Other
B78
Reserved for Pentium II
processor
VCCCORE
Reserved
VCCCORE
B29
Power/Other
VCCCORE
Power/Other
B118
Reserved for Pentium II
processor
B33
Reserved
VCCCORE
B37
Power/Other
VCCCORE
B45
Power/Other
VCCCORE
B49
Power/Other
Reserved
A25
Reserved for Pentium II
processor
Reserved
A27
Reserved for Pentium II
processor
VCCCORE
B53
Power/Other
Reserved
B26
Reserved for Pentium II
processor
VCCCORE
B57
Power/Other
B65
Power/Other
A28
Reserved for Pentium II
processor
VCCCORE
Reserved
VCCCORE
B69
Power/Other
VCCCORE
Power/Other
B27
Reserved for Pentium II
processor
B73
Reserved
VCCCORE
B77
Power/Other
VCCCORE
B85
Power/Other
VCCCORE
B89
Power/Other
VCCCORE
B93
Power/Other
VCCCORE
B97
Power/Other
VCCCORE
B105
Power/Other
VCCL2
B113
Power/Other. Reserved
for Pentium II processor
VCCL2
B117
Power/Other. Reserved
for Pentium II processor
Reserved
A29
Reserved for Pentium II
processor
Reserved
A31
Reserved for Pentium II
processor
Reserved
B28
Reserved for Pentium II
processor
RESET#
B74
AGTL+ Input
RS0#
B108
AGTL+ Input
RS1#
A112
AGTL+ Input
RS2#
B111
AGTL+ Input
SLOTOCC#
B101
Power/Other
VCCL2
B121
Power/Other. Reserved
for Pentium II processor
SLP#
B8
CMOS Input
VID0
B120
Power/Other
SMI#
B3
CMOS Input
VID1
A120
Power/Other
STPCLK#
B6
CMOS Input
VID2
A119
Power/Other
TCK
B7
TAP Input
VID3
B119
Power/Other
TDI
A9
TAP Input
VID4
A121
Power/Other
TDO
A11
TAP Output
VSS
A114
Power/Other
77
Intel® Celeron® Processor up to 1.10 GHz
Table 46. S.E.P. Package Signal Listing
by Signal Name
Pin Name
78
Pin
No.
Signal Buffer Type
Table 46. S.E.P. Package Signal Listing
by Signal Name
Pin Name
Pin
No.
Signal Buffer Type
VSS
A118
Power/Other
VSS
A10
Power/Other
VSS
A46
Power/Other
VSS
A14
Power/Other
VSS
A38
Power/Other
VSS
A18
Power/Other
VSS
A42
Power/Other
VSS
A22
Power/Other
VSS
A50
Power/Other
VSS
A26
Power/Other
VSS
A54
Power/Other
VSS
A30
Power/Other
VSS
A58
Power/Other
VSS
A34
Power/Other
VSS
A62
Power/Other
VSS
A98
Power/Other
VSS
A66
Power/Other
VSS
A102
Power/Other
VSS
A70
Power/Other
VSS
A106
Power/Other
VSS
A74
Power/Other
VSS
A110
Power/Other
VSS
A78
Power/Other
VTT
A1
Power/Other
VSS
A82
Power/Other
VTT
A3
Power/Other
VSS
A86
Power/Other
VTT
B5
Power/Other
VSS
A2
Power/Other
VTT
B9
Power/Other
VSS
A6
Power/Other
Datasheet
Intel® Celeron® Processor up to 1.10 GHz
5.2
PPGA Package
This section defines the mechanical specifications and signal definitions for the Celeron processor
in the PPGA packages.
5.2.1
PPGA Package Materials Information
Figure 21 and Table 47 are provided to aid in the design of a heatsink and clip.
Figure 21. Package Dimensions (PPGA Package)
Top View
Bottom View
Heat Slug
D
Solder Resist
D1
S1
D
B1
45° x 0.085
B2
Side View
Seating Plane
D2
A1
A
A2
L
e1
Datasheet
φB
79
Intel® Celeron® Processor up to 1.10 GHz
Table 47. Package Dimensions (PPGA Package)
Millimeters
Symbol
Min
Max
A
1.83
2.23
A1
A2
Inches
Notes
Min
Max
0.072
0.088
1.00
2.72
Notes
0.039
3.33
0.107
0.131
B
0.40
0.51
0.016
0.020
D
49.43
49.63
1.946
1.954
D1
45.59
45.85
1.795
1.805
D2
25.15
25.65
0.099
1.010
e1
2.29
2.79
0.090
0.110
L
3.05
3.30
0.120
0.130
N
S1
370
1.52
Lead Count
2.54
370
0.060
Lead Count
0.100
Table 48. Information Summary (PPGA Package)
80
Package Type
Total Pins
Pin Array
Package Size
Plastic Staggered Pin Grid Array (PPGA)
370
37 x 37
1.95" x 1.95"
4.95 cm x 4.95 cm
Datasheet
Intel® Celeron® Processor up to 1.10 GHz
5.2.2
PPGA Package Signal Listing
Figure 22. PPGA Package (Pin Side View)
1
2
3
4
5
6
7
8
9
10
11 12
13
14 15
16
17
18
19
20
21
22
23
24 25
26
27
28
29
30
31 32
33
34 35
36
37
AN
AN
VSS
AM
VSS
AL
AK
VCC
AJ
AH
EDGCTRL
VCC
AD
A17#
AB
Rsvd
Rsvd
V
T
R
P
VCC
VSS
Rsvd
VCC
RS0# THERMTRIP# SLP#
VCC
VSS
D13#
VCC
PLL1
VCC
D6#
VSS
Rsvd
Rsvd
VCC
D7#
F
D
VCC
VCC
Datasheet
2
3
VCC
VCC
5
VCC
VSS
7
8
9
VCC
11 12
D51#
13
VREF1
VCC
D59#
14 15
D55#
16
17
18
VSS
19
VCC
21
22
23
D56#
VCC
VSS
VSS
27
VCC
29
VCC
Rsvd
Rsvd
28
VREF0
30
VSS
Rsvd
VSS
Rsvd
31 32
VSS
34 35
H
F
D
C
Rsvd
36
K
E
BP3#
VCC
PRDY#
M
G
Rsvd
BPM0# CPUPRES#
VCC
Rsvd
33
VCC
BPM1#
P
J
PREQ#
Rsvd
VCC
VSS
Rsvd
Rsvd
D61#
26
VCC
Rsvd
VCC
VSS
D60#
24 25
VSS
Rsvd
D50#
VSS
D53#
VCC
D62#
VCC
D58#
D46#
20
VSS
Rsvd
VSS
D54#
D57#
D48#
VCC
VCOREDET
VCC
VCC
VSS
D47#
VSS
VSS
VSS
D52#
D40#
D49#
VSS
D44#
VSS
D41#
D42#
D45#
10
D63#
VCC
VSS
VCC
D37#
VCC
D27#
D39#
D36#
D43#
6
Rsvd
D38#
D34#
D28#
4
D22#
VSS
D31#
D29#
1
D32#
VSS
D35#
A
VSS
R
L
LINT1
VSS
PICD0
BP2#
VCC
VSS
D33#
VCC
D19#
LINT0
VCC
T
N
Rsvd
PICD1
PICCLK
VSS
D25#
VSS
VCC
D24#
Rsvd
VSS
VSS
V
Q
Rsvd
Rsvd
VCC
D16#
VCC
D26#
C
B
VREF2
D23#
D21#
E
VSS
D30#
VSS
G
VCC
X
S
Rsvd
Rsvd
Rsvd
D3#
Rsvd
VCC
VCC
Z
U
VSS
Rsvd
VSS
VSS
D9#
VCC
VCC
AA
W
BCLK
Rsvd
PLL2
D11#
VCC
J
H
VSS
VCC
VSS
VSS
Rsvd
AB
Y
VCC
VCC
VREF4
VCC
V2.5
VSS
VREF3
VCMOS
VSS
AD
AC
Rsvd
Rsvd
VSS
Rsvd
VSS
D20#
V1.5
VCC
AF
AE
FLUSH#
FERR#
VSS
M
K
VSS
AH
AG
VSS
IERR#
Rsvd
D18#
L
VCC
VCC
AK
AJ
VID3
STPCLK# IGNNE#
VSS
A18#
VSS
VSS
VCC
AM
AL
VID2
SMI#
BSEL#
VCC
D14#
VID1
VID0
VCC
TMS
VSS
VSS
D10#
D2#
RS1#
PWRGD RS2#
VCC
TDO
VSS
VCC
A23#
D17#
VCC
Rsvd
Rsvd
VSS
TDI
DBSY# THRMDN THRMDP TCK
VSS
D1#
D5#
D12#
N
REQ1# REQ2#
VREF7
VCC
VSS
TRST#
VCC
D15#
Rsvd
BNR#
VSS
VCC
ADS#
VSS
VCC
Q
A4#
REQ0# LOCK#
VCC
HIT#
BR0#
VREF5
Rsvd
D8#
Rsvd
VSS
VSS
VCC
HITM#
DRDY#
A20M#
RESET#
Rsvd
D4#
S
A8#
A5#
A14#
VCC
VSS
Rsvd
REQ3#
TRDY#
VCC
A26#
VSS
U
VREF6
VSS
VCC
VSS
REQ4#
Rsvd
A25#
A29#
D0#
A11#
VCC
VCC
A7#
Rsvd
Rsvd
INIT#
A24#
Rsvd
W
VSS
Rsvd
BPRI# DEFER#
VSS
A30#
VSS
Y
X
A20#
A27#
VCC
Rsvd
VCC
A31#
VCC
AA
Z
Rsvd
VSS
A3#
Rsvd
VSS
A22#
AC
VSS
A9#
VSS
A10#
A19#
Rsvd
VCC
VCC
Rsvd
A6#
A13#
A28#
VSS
VSS
AE
VSS
A15#
VSS
A21#
AG
AF
VCC
VSS
VSS
A16#
A12#
B
A
VSS
37
81
Intel® Celeron® Processor up to 1.10 GHz
Table 49. PPGA Package Signal Listing
by Pin Number
Pin
No.
82
Pin Name
Signal Buffer Type
Table 49. PPGA Package Signal Listing
by Pin Number
Pin
No.
Pin Name
Signal Buffer Type
A3
D29#
AGTL+ I/O
AD4
A31#
AGTL+ I/O
A5
D28#
AGTL+ I/O
AD6
VREF5
Power/Other
A7
D43#
AGTL+ I/O
AD32
VCCCORE
Power/Other
VSS
Power/Other
A9
D37#
AGTL+ I/O
AD34
A11
D44#
AGTL+ I/O
AD36
VCC1.5
Power/Other
A13
D51#
AGTL+ I/O
AE1
A17#
AGTL+ I/O
A15
D47#
AGTL+ I/O
AE3
A22#
AGTL+ I/O
VCCCORE
Power/Other
A17
D48#
AGTL+ I/O
AE5
A19
D57#
AGTL+ I/O
AE33
A20M#
CMOS Input
A21
D46#
AGTL+ I/O
AE35
IERR#
CMOS Output
A23
D53#
AGTL+ I/O
AE37
FLUSH#
CMOS Input
VCCCORE
Power/Other
A25
D60#
AGTL+ I/O
AF2
A27
D61#
AGTL+ I/O
AF4
Reserved
Reserved for Future Use
A29
Reserved
Reserved for Future Use
AF6
A25#
AGTL+ I/O
A31
Reserved
Reserved for Future Use
AF32
VSS
Power/Other
VCCCORE
Power/Other
A33
Reserved
Reserved for Future Use
AF34
A35
PRDY#
AGTL+ Output
AF36
VSS
Power/Other
A37
VSS
Power/Other
AG1
EDGCTRL
Power/Other
AA1
A27#
AGTL+ I/O
AG3
A19#
AGTL+ I/O
VSS
Power/Other
AA3
A30#
AGTL+ I/O
AG5
AA5
VCCCORE
Power/Other
AG33
INIT#
CMOS Input
AA33
Reserved
Reserved for Future Use
AG35
STPCLK#
CMOS Input
AA35
Reserved
Reserved for Future Use
AG37
IGNNE#
CMOS Input
VSS
Power/Other
AA37
VCCCORE
Power/Other
AH2
AB2
VCCCORE
Power/Other
AH4
Reserved
Reserved for Future Use
AB4
A24#
AGTL+ I/O
AH6
A10#
AGTL+ I/O
AB6
A23#
AGTL+ I/O
AH8
A5#
AGTL+ I/O
A8#
AGTL+ I/O
AB32
VSS
Power/Other
AH10
AB34
VCCCORE
Power/Other
AH12
A4#
AGTL+ I/O
AB36
VCCCMOS
Power/Other
AH14
BNR#
AGTL+ I/O
AC1
Reserved
Reserved for Future Use
AH16
REQ1#
AGTL+ I/O
REQ2#
AGTL+ I/O
AC3
A20#
AGTL+ I/O
AH18
AC5
VSS
Power/Other
AH20
Reserved
Reserved for Future Use
AC33
VSS
Power/Other
AH22
RS1#
AGTL+ Input
AC35
FERR#
CMOS Output
AH24
VCCCORE
Power/Other
RS0#
AGTL+ Input
AC37
Reserved
Reserved for Future Use
AH26
AD2
VSS
Power/Other
AH28
THERMTRIP#
CMOS Output
AH30
SLP#
CMOS Input
Datasheet
Intel® Celeron® Processor up to 1.10 GHz
Table 49. PPGA Package Signal Listing
by Pin Number
Pin
No.
Datasheet
Pin Name
Signal Buffer Type
Table 49. PPGA Package Signal Listing
by Pin Number
Pin
No.
Pin Name
Signal Buffer Type
AH32
VCCCORE
Power/Other
AK34
VCCCORE
Power/Other
AH34
VSS
Power/Other
AK36
VSS
Power/Other
AH36
VCCCORE
Power/Other
AL01
VSS
Power/Other
AJ01
A21#
AGTL+ I/O
AL03
VSS
Power/Other
AJ03
VSS
Power/Other
AL05
A15#
AGTL+ I/O
AJ05
VCCCORE
Power/Other
AL07
A13#
AGTL+ I/O
AJ07
VSS
Power/Other
AL09
A9#
AGTL+ I/O
AJ09
VCCCORE
Power/Other
AL11
Reserved
Reserved for Future Use
AJ11
VSS
Power/Other
AL13
Reserved
Reserved for Future Use
AJ13
VCCCORE
Power/Other
AL15
A7#
AGTL+ I/O
AJ15
VSS
Power/Other
AL17
REQ4#
AGTL+ I/O
AJ17
VCCCORE
Power/Other
AL19
REQ3#
AGTL+ I/O
AJ19
VSS
Power/Other
AL21
Reserved
Reserved for Future Use
AJ21
VCCCORE
Power/Other
AL23
HITM#
AGTL+ I/O
AJ23
VSS
Power/Other
AL25
HIT#
AGTL+ I/O
AJ25
VCCCORE
Power/Other
AL27
DBSY#
AGTL+ I/O
AJ27
VSS
Power/Other
AL29
THERMDN
Power/Other
AJ29
VCCCORE
Power/Other
AL31
THERMDP
Power/Other
AJ31
VSS
Power/Other
AL33
TCK
TAP Input
AJ33
BSEL
Power/Other
AL35
VID0
Voltage Identification
AJ35
SMI#
CMOS Input
AL37
VID2
Voltage Identification
AJ37
VID3
Power/Other
AM04
VCCCORE
Power/Other
AK02
VCCCORE
Power/Other
AM06
VSS
Power/Other
AK04
VSS
Power/Other
AM08
VCCCORE
Power/Other
AK06
A28#
AGTL+ I/O
AM10
VSS
Power/Other
AK08
A3#
AGTL+ I/O
AM12
VCCCORE
Power/Other
AK10
A11#
AGTL+ I/O
AM14
VSS
Power/Other
AK12
VREF6
Power/Other
AM16
VCCCORE
Power/Other
AK14
A14#
AGTL+ I/O
AM18
VSS
Power/Other
AK16
Reserved
Reserved for Future Use
AM2
VSS
Power/Other
AK18
REQ0#
AGTL+ I/O
AM20
VCCCORE
Power/Other
AK20
LOCK#
AGTL+ I/O
AM22
VSS
Power/Other
AK22
VREF7
Power/Other
AM24
VCCCORE
Power/Other
AK24
Reserved
Reserved for Future Use
AM26
VSS
Power/Other
AK26
PWRGOOD
CMOS Input
AM28
VCCCORE
Power/Other
AK28
RS2#
AGTL+ Input
AM30
VSS
Power/Other
AK30
Reserved
Reserved for Future Use
AM32
VCCCORE
Power/Other
AK32
TMS
TAP Input
AM34
VSS
Power/Other
83
Intel® Celeron® Processor up to 1.10 GHz
Table 49. PPGA Package Signal Listing
by Pin Number
Pin
No.
84
Pin Name
Signal Buffer Type
Table 49. PPGA Package Signal Listing
by Pin Number
Pin
No.
Pin Name
Signal Buffer Type
AM36
VID1
Voltage Identification
C3
VCCCORE
Power/Other
AN3
VSS
Power/Other
C5
D31#
AGTL+ I/O
AN5
A12#
AGTL+ I/O
C7
D34#
AGTL+ I/O
AN7
A16#
AGTL+ I/O
C9
D36#
AGTL+ I/O
AN9
A6#
AGTL+ I/O
C11
D45#
AGTL+ I/O
AN11
Reserved
Reserved for Future Use
C13
D49#
AGTL+ I/O
AN13
Reserved
Reserved for Future Use
C15
D40#
AGTL+ I/O
AN15
Reserved
Reserved for Future Use
C17
D59#
AGTL+ I/O
AN17
BPRI#
AGTL+ Input
C19
D55#
AGTL+ I/O
AN19
DEFER#
AGTL+ Input
C21
D54#
AGTL+ I/O
AN21
Reserved
Reserved for Future Use
C23
D58#
AGTL+ I/O
AN23
Reserved
Reserved for Future Use
C25
D50#
AGTL+ I/O
AN25
TRDY#
AGTL+ Input
C27
D56#
AGTL+ I/O
AN27
DRDY#
AGTL+ I/O
C29
Reserved
Reserved for Future Use
AN29
BR0#
AGTL+ I/O
C31
Reserved
Reserved for Future Use
AN31
ADS#
AGTL+ I/O
C33
Reserved
Reserved for Future Use
AN33
TRST#
TAP Input
C35
BPM0#
AGTL+ I/O
AN35
TDI
TAP Input
C37
CPUPRES#
Power/Other
AN37
TDO
TAP Output
D2
VSS
Power/Other
B2
D35#
AGTL+ I/O
D4
VSS
Power/Other
B4
VSS
Power/Other
D6
VCCCORE
Power/Other
B6
VCCCORE
Power/Other
D8
D38#
AGTL+ I/O
B8
VSS
Power/Other
D10
D39#
AGTL+ I/O
B10
VCCCORE
Power/Other
D12
D42#
AGTL+ I/O
B12
VSS
Power/Other
D14
D41#
AGTL+ I/O
B14
VCCCORE
Power/Other
D16
D52#
AGTL+ I/O
B16
VSS
Power/Other
D18
VSS
Power/Other
B18
VCCCORE
Power/Other
D20
VCCCORE
Power/Other
B20
VSS
Power/Other
D22
VSS
Power/Other
B22
VCCCORE
Power/Other
D24
VCCCORE
Power/Other
B24
VSS
Power/Other
D26
VSS
Power/Other
B26
VCCCORE
Power/Other
D28
VCCCORE
Power/Other
B28
VSS
Power/Other
D30
VSS
Power/Other
B30
VCCCORE
Power/Other
D32
VCCCORE
Power/Other
B32
VSS
Power/Other
D34
VSS
Power/Other
B34
VCCCORE
Power/Other
D36
VCCCORE
Power/Other
B36
Reserved
Reserved for Future Use
E1
D26#
AGTL+ I/O
C1
D33#
AGTL+ I/O
E3
D25#
AGTL+ I/O
Datasheet
Intel® Celeron® Processor up to 1.10 GHz
Table 49. PPGA Package Signal Listing
by Pin Number
Pin
No.
Datasheet
Pin Name
Signal Buffer Type
Table 49. PPGA Package Signal Listing
by Pin Number
Pin
No.
Pin Name
Signal Buffer Type
E5
VCCCORE
Power/Other
G33
BP2#
AGTL+ I/O
E7
VSS
Power/Other
G35
Reserved
Reserved for Future Use
E9
VCCCORE
Power/Other
G37
Reserved
Reserved for Future Use
E11
VSS
Power/Other
H2
VSS
Power/Other
E13
VCCCORE
Power/Other
H4
D16#
AGTL+ I/O
E15
VSS
Power/Other
H6
D19#
AGTL+ I/O
E17
VCCCORE
Power/Other
H32
VCCCORE
Power/Other
E19
VSS
Power/Other
H34
VSS
Power/Other
E21
VCOREDET
Power/Other
H36
VCCCORE
Power/Other
E23
Reserved
Reserved for Future Use
J1
D7#
AGTL+ I/O
E25
D62#
Power/Other
J3
D30#
AGTL+ I/O
E27
Reserved
Reserved for Future Use
J5
VCCCORE
Power/Other
E29
Reserved
Reserved for Future Use
J33
PICCLK
APIC Clock Input
E31
Reserved
Reserved for Future Use
J35
PICD0
APIC I/O
E33
VREF0
Power/Other
J37
PREQ#
CMOS Input
E35
BPM1#
AGTL+ I/O
K2
VCCCORE
Power/Other
E37
BP3#
AGTL+ I/O
K4
VREF2
Power/Other
F2
VCCCORE
Power/Other
K6
D24#
AGTL+ I/O
F4
VCCCORE
Power/Other
K32
VCCCORE
Power/Other
F6
D32#
AGTL+ I/O
K34
VCCCORE
Power/Other
F8
D22#
AGTL+ I/O
K36
VSS
Power/Other
F10
Reserved
Reserved for Future Use
L1
D13#
AGTL+ I/O
F12
D27#
AGTL+ I/O
L3
D20#
AGTL+ I/O
F14
VCCCORE
Power/Other
L5
VSS
Power/Other
F16
D63#
AGTL+ I/O
L33
Reserved
Reserved for Future Use
F18
VREF1
Power/Other
L35
PICD1
APIC I/O
F20
VSS
Power/Other
L37
LINT1/NMI
CMOS Input
F22
VCCCORE
Power/Other
M2
VSS
Power/Other
F24
VSS
Power/Other
M4
D11#
AGTL+ I/O
F26
VCCCORE
Power/Other
M6
D3#
AGTL+ I/O
F28
VSS
Power/Other
M32
VCCCORE
Power/Other
F30
VCCCORE
Power/Other
M34
VSS
Power/Other
F32
VSS
Power/Other
M36
LINT0/INTR
CMOS Input
F34
VCCCORE
Power/Other
N1
D2#
AGTL+ I/O
F36
VSS
Power/Other
N3
D14#
AGTL+ I/O
G1
D21#
AGTL+ I/O
N5
VCCCORE
Power/Other
G3
D23#
AGTL+ I/O
N33
Reserved
Reserved for Future Use
G5
VSS
Power/Other
N35
Reserved
Reserved for Future Use
85
Intel® Celeron® Processor up to 1.10 GHz
Table 49. PPGA Package Signal Listing
by Pin Number
Pin
No.
86
Pin Name
Signal Buffer Type
Table 49. PPGA Package Signal Listing
by Pin Number
Pin
No.
Pin Name
Signal Buffer Type
N37
Reserved
Reserved for Future Use
U5
VSS
Power/Other
P2
VCCCORE
Power/Other
U33
PLL2
Power/Other
P4
D18#
AGTL+ I/O
U35
Reserved
Reserved for Future Use
P6
D9#
AGTL+ I/O
U37
Reserved
Reserved for Future Use
P32
VSS
Power/Other
V2
VSS
Power/Other
P34
VCCCORE
Power/Other
V4
Reserved
Reserved for Future Use
P36
VSS
Power/Other
V6
VREF4
Power/Other
Q1
D12#
AGTL+ I/O
V32
VCCCORE
Power/Other
Q3
D10#
AGTL+ I/O
V34
VSS
Power/Other
Q5
VSS
Power/Other
V36
VCCCORE
Power/Other
Q33
Reserved
Reserved for Future Use
W1
D0#
AGTL+ I/O
Q35
Reserved
Reserved for Future Use
W3
Reserved
Reserved for Future Use
Q37
Reserved
Reserved for Future Use
W5
VCCCORE
Power/Other
R2
Reserved
Reserved for Future Use
W33
PLL1
Power/Other
R4
D17#
AGTL+ I/O
W35
Reserved
Reserved for Future Use
R6
VREF3
Power/Other
W37
BCLK
System Bus Clock Input
R32
VCCCORE
Power/Other
X2
Reserved
Reserved for Future Use
R34
VSS
Power/Other
X4
RESET#
AGTL+ Input
R36
VCCCORE
Power/Other
X6
Reserved
Reserved for Future Use
S1
D8#
AGTL+ I/O
X32
VSS
Power/Other
S3
D5#
AGTL+ I/O
X34
VCCCORE
Power/Other
S5
VCCCORE
Power/Other
X36
VSS
Power/Other
S33
Reserved
Reserved for Future Use
Y1
Reserved
Reserved for Future Use
S35
Reserved
Reserved for Future Use
Y3
A26#
AGTL+ I/O
S37
Reserved
Reserved for Future Use
Y5
VSS
Power/Other
T2
VCCCORE
Power/Other
Y33
VSS
Power/Other
T4
D1#
AGTL+ I/O
Y35
VCCCORE
Power/Other
T6
D6#
AGTL+ I/O
Y37
VSS
Power/Other
T32
VSS
Power/Other
Z2
VSS
Power/Other
T34
VCCCORE
Power/Other
Z4
A29#
AGTL+ I/O
T36
VSS
Power/Other
Z6
A18#
AGTL+ I/O
U1
D4#
AGTL+ I/O
Z32
VCCCORE
Power/Other
U3
D15#
AGTL+ I/O
Z34
VSS
Power/Other
Z36
VCC2.5
Power/Other
Datasheet
Intel® Celeron® Processor up to 1.10 GHz
Table 50. PPGA Package Signal Listing
in Order by Signal Name
Pin Name
Datasheet
Pin
No.
Signal Buffer Type
Table 50. PPGA Package Signal Listing
in Order by Signal Name
Pin Name
Pin
No.
Signal Buffer Type
A3#
AK8
AGTL+ I/O
CPUPRES#
C37
Power/Other
A4#
AH12
AGTL+ I/O
D0#
W1
AGTL+ I/O
T4
AGTL+ I/O
A5#
AH8
AGTL+ I/O
D1#
A6#
AN9
AGTL+ I/O
D2#
N1
AGTL+ I/O
M6
AGTL+ I/O
A7#
AL15
AGTL+ I/O
D3#
A8#
AH10
AGTL+ I/O
D4#
U1
AGTL+ I/O
S3
AGTL+ I/O
A9#
AL9
AGTL+ I/O
D5#
A10#
AH6
AGTL+ I/O
D6#
T6
AGTL+ I/O
J1
AGTL+ I/O
A11#
AK10
AGTL+ I/O
D7#
A12#
AN5
AGTL+ I/O
D8#
S1
AGTL+ I/O
P6
AGTL+ I/O
A13#
AL7
AGTL+ I/O
D9#
A14#
AK14
AGTL+ I/O
D10#
Q3
AGTL+ I/O
M4
AGTL+ I/O
A15#
AL5
AGTL+ I/O
D11#
A16#
AN7
AGTL+ I/O
D12#
Q1
AGTL+ I/O
L1
AGTL+ I/O
A17#
AE1
AGTL+ I/O
D13#
A18#
Z6
AGTL+ I/O
D14#
N3
AGTL+ I/O
U3
AGTL+ I/O
A19#
AG3
AGTL+ I/O
D15#
A20#
AC3
AGTL+ I/O
D16#
H4
AGTL+ I/O
R4
AGTL+ I/O
A21#
AJ1
AGTL+ I/O
D17#
A22#
AE3
AGTL+ I/O
D18#
P4
AGTL+ I/O
H6
AGTL+ I/O
A23#
AB6
AGTL+ I/O
D19#
A24#
AB4
AGTL+ I/O
D20#
L3
AGTL+ I/O
G1
AGTL+ I/O
A25#
AF6
AGTL+ I/O
D21#
A26#
Y3
AGTL+ I/O
D22#
F8
AGTL+ I/O
G3
AGTL+ I/O
A27#
AA1
AGTL+ I/O
D23#
A28#
AK6
AGTL+ I/O
D24#
K6
AGTL+ I/O
E3
AGTL+ I/O
A29#
Z4
AGTL+ I/O
D25#
A30#
AA3
AGTL+ I/O
D26#
E1
AGTL+ I/O
F12
AGTL+ I/O
A31#
AD4
AGTL+ I/O
D27#
A20M#
AE33
CMOS Input
D28#
A5
AGTL+ I/O
A3
AGTL+ I/O
ADS#
AN31
AGTL+ I/O
D29#
BCLK
W37
System Bus Clock Input
D30#
J3
AGTL+ I/O
C5
AGTL+ I/O
BNR#
AH14
AGTL+ I/O
D31#
BP2#
G33
AGTL+ I/O
D32#
F6
AGTL+ I/O
C1
AGTL+ I/O
BP3#
E37
AGTL+ I/O
D33#
BPM0#
C35
AGTL+ I/O
D34#
C7
AGTL+ I/O
B2
AGTL+ I/O
BPM1#
E35
AGTL+ I/O
D35#
BPRI#
AN17
AGTL+ Input
D36#
C9
AGTL+ I/O
A9
AGTL+ I/O
D8
AGTL+ I/O
BR0#
AN29
AGTL+ I/O
D37#
BSEL
AJ33
Power/Other
D38#
87
Intel® Celeron® Processor up to 1.10 GHz
Table 50. PPGA Package Signal Listing
in Order by Signal Name
Pin Name
88
Pin
No.
Signal Buffer Type
Table 50. PPGA Package Signal Listing
in Order by Signal Name
Pin Name
D39#
D10
AGTL+ I/O
PICD0
D40#
C15
AGTL+ I/O
D41#
D14
AGTL+ I/O
D42#
D12
D43#
A7
D44#
D45#
D46#
D47#
Pin
No.
Signal Buffer Type
J35
APIC I/O
PICD1
L35
APIC I/O
PLL1
W33
Power/Other
AGTL+ I/O
PLL2
U33
Power/Other
AGTL+ I/O
PRDY#
A35
AGTL+ Output
A11
AGTL+ I/O
PREQ#
J37
CMOS Input
C11
AGTL+ I/O
PWRGOOD
AK26
CMOS Input
A21
AGTL+ I/O
REQ0#
AK18
AGTL+ I/O
A15
AGTL+ I/O
REQ1#
AH16
AGTL+ I/O
D48#
A17
AGTL+ I/O
REQ2#
AH18
AGTL+ I/O
D49#
C13
AGTL+ I/O
REQ3#
AL19
AGTL+ I/O
D50#
C25
AGTL+ I/O
REQ4#
AL17
AGTL+ I/O
D51#
A13
AGTL+ I/O
Reserved
AC1
Reserved for Future Use
D52#
D16
AGTL+ I/O
Reserved
AC37
Reserved for Future Use
D53#
A23
AGTL+ I/O
Reserved
AF4
Reserved for Future Use
D54#
C21
AGTL+ I/O
Reserved
AK16
Reserved for Future Use
D55#
C19
AGTL+ I/O
Reserved
AK24
Reserved for Future Use
D56#
C27
AGTL+ I/O
Reserved
AK30
Reserved for Future Use
D57#
A19
AGTL+ I/O
Reserved
AL11
Reserved for Future Use
D58#
C23
AGTL+ I/O
Reserved
AL13
Reserved for Future Use
D59#
C17
AGTL+ I/O
Reserved
AL21
Reserved for Future Use
D60#
A25
AGTL+ I/O
Reserved
AN11
Reserved for Future Use
D61#
A27
AGTL+ I/O
Reserved
AN13
Reserved for Future Use
D62#
E25
AGTL+ I/O
Reserved
AN15
Reserved for Future Use
D63#
F16
AGTL+ I/O
Reserved
AN21
Reserved for Future Use
DBSY#
AL27
AGTL+ I/O
Reserved
AN23
Reserved for Future Use
DEFER#
AN19
AGTL+ Input
Reserved
B36
Reserved for Future Use
DRDY#
AN27
AGTL+ I/O
Reserved
C29
Reserved for Future Use
EDGCTRL
AG1
Power/Other
Reserved
C31
Reserved for Future Use
FERR#
AC35
CMOS Output
Reserved
C33
Reserved for Future Use
FLUSH#
AE37
CMOS Input
Reserved
E23
Reserved for Future Use
HIT#
AL25
AGTL+ I/O
Reserved
E29
Reserved for Future Use
HITM#
AL23
AGTL+ I/O
Reserved
E31
Reserved for Future Use
IERR#
AE35
CMOS Output
Reserved
F10
Reserved for Future Use
IGNNE#
AG37
CMOS Input
Reserved
G35
Reserved for Future Use
INIT#
AG33
CMOS Input
Reserved
G37
Reserved for Future Use
LINT0/INTR
M36
CMOS Input
Reserved
L33
Reserved for Future Use
LINT1/NMI
L37
CMOS Input
Reserved
N33
Reserved for Future Use
LOCK#
AK20
AGTL+ I/O
Reserved
N35
Reserved for Future Use
PICCLK
J33
APIC Clock Input
Reserved
N37
Reserved for Future Use
Datasheet
Intel® Celeron® Processor up to 1.10 GHz
Table 50. PPGA Package Signal Listing
in Order by Signal Name
Pin Name
Datasheet
Pin
No.
Signal Buffer Type
Table 50. PPGA Package Signal Listing
in Order by Signal Name
Pin Name
Pin
No.
Signal Buffer Type
Reserved
Q33
Reserved for Future Use
VCC2.5
Z36
Power/Other
Reserved
Q35
Reserved for Future Use
VCCCMOS
AB36
Power/Other
Reserved
Q37
Reserved for Future Use
VCCCORE
AJ25
Power/Other
Reserved
S33
Reserved for Future Use
VCCCORE
AJ29
Power/Other
Reserved
S37
Reserved for Future Use
VCCCORE
AJ5
Power/Other
Reserved
U35
Reserved for Future Use
VCCCORE
AJ9
Power/Other
Reserved
U37
Reserved for Future Use
VCCCORE
AK2
Power/Other
Reserved
V4
Reserved for Future Use
VCCCORE
AK34
Power/Other
Reserved
W3
Reserved for Future Use
VCCCORE
AM12
Power/Other
Reserved
W35
Reserved for Future Use
VCCCORE
AM16
Power/Other
Reserved
AH20
Reserved for Future Use
VCCCORE
AM20
Power/Other
Reserved
AH4
Reserved for Future Use
VCCCORE
AM24
Power/Other
Reserved
A29
Reserved for Future Use
VCCCORE
AM28
Power/Other
Reserved
A31
Reserved for Future Use
VCCCORE
AM32
Power/Other
Reserved
A33
Reserved for Future Use
VCCCORE
AM4
Power/Other
Reserved
AA33
Reserved for Future Use
VCCCORE
AM8
Power/Other
Reserved
AA35
Reserved for Future Use
VCCCORE
B10
Power/Other
Reserved
X6
Reserved for Future Use
VCCCORE
B14
Power/Other
Reserved
Y1
Reserved for Future Use
VCCCORE
B18
Power/Other
Reserved
E27
Reserved for Future Use
VCCCORE
B22
Power/Other
Reserved
R2
Reserved for Future Use
VCCCORE
B26
Power/Other
Reserved
S35
Reserved for Future Use
VCCCORE
B30
Power/Other
Reserved
X2
Reserved for Future Use
VCCCORE
B34
Power/Other
RESET#
X4
AGTL+ Input
VCCCORE
B6
Power/Other
RS0#
AH26
AGTL+ Input
VCCCORE
C3
Power/Other
RS1#
AH22
AGTL+ Input
VCCCORE
D20
Power/Other
RS2#
AK28
AGTL+ Input
VCCCORE
D24
Power/Other
SLP#
AH30
CMOS Input
VCCCORE
D28
Power/Other
SMI#
AJ35
CMOS Input
VCCCORE
D32
Power/Other
STPCLK#
AG35
CMOS Input
VCCCORE
D36
Power/Other
TCK
AL33
TAP Input
VCCCORE
D6
Power/Other
TDI
AN35
TAP Input
VCCCORE
E13
Power/Other
TDO
AN37
TAP Output
VCCCORE
E17
Power/Other
THERMDN
AL29
Power/Other
VCCCORE
E5
Power/Other
THERMDP
AL31
Power/Other
VCCCORE
E9
Power/Other
THERMTRIP#
AH28
CMOS Output
VCCCORE
F14
Power/Other
TMS
AK32
TAP Input
VCCCORE
F2
Power/Other
TRDY#
AN25
AGTL+ Input
VCCCORE
F22
Power/Other
TRST#
AN33
TAP Input
VCCCORE
F26
Power/Other
VCC1.5
AD36
Power/Other
VCCCORE
AA37
Power/Other
89
Intel® Celeron® Processor up to 1.10 GHz
Table 50. PPGA Package Signal Listing
in Order by Signal Name
Pin Name
90
Pin
No.
Signal Buffer Type
Table 50. PPGA Package Signal Listing
in Order by Signal Name
Pin Name
Pin
No.
AL37
Signal Buffer Type
VCCCORE
AA5
Power/Other
VID2
Power/Other
VCCCORE
AB2
Power/Other
VID3
AJ37
Power/Other
VCCCORE
AB34
Power/Other
VREF0
E33
Power/Other
VCCCORE
AD32
Power/Other
VREF1
F18
Power/Other
VCCCORE
AE5
Power/Other
VREF2
K4
Power/Other
VCCCORE
AF2
Power/Other
VREF3
R6
Power/Other
VCCCORE
AF34
Power/Other
VREF4
V6
Power/Other
VCCCORE
AH24
Power/Other
VREF5
AD6
Power/Other
VCCCORE
AH32
Power/Other
VREF6
AK12
Power/Other
VCCCORE
AH36
Power/Other
VREF7
AK22
Power/Other
VCCCORE
AJ13
Power/Other
VSS
B16
Power/Other
VCCCORE
AJ17
Power/Other
VSS
B20
Power/Other
VCCCORE
AJ21
Power/Other
VSS
B24
Power/Other
VCCCORE
F30
Power/Other
VSS
B28
Power/Other
VCCCORE
F34
Power/Other
VSS
B32
Power/Other
VCCCORE
F4
Power/Other
VSS
B4
Power/Other
VCCCORE
H32
Power/Other
VSS
B8
Power/Other
VCCCORE
H36
Power/Other
VSS
D18
Power/Other
VCCCORE
J5
Power/Other
VSS
D2
Power/Other
VCCCORE
K2
Power/Other
VSS
D22
Power/Other
VCCCORE
K32
Power/Other
VSS
D26
Power/Other
VCCCORE
K34
Power/Other
VSS
D30
Power/Other
VCCCORE
M32
Power/Other
VSS
D34
Power/Other
VCCCORE
N5
Power/Other
VSS
D4
Power/Other
VCCCORE
P2
Power/Other
VSS
E11
Power/Other
VCCCORE
P34
Power/Other
VSS
E15
Power/Other
VCCCORE
R32
Power/Other
VSS
E19
Power/Other
VCCCORE
R36
Power/Other
VSS
E7
Power/Other
VCCCORE
S5
Power/Other
VSS
F20
Power/Other
VCCCORE
T2
Power/Other
VSS
F24
Power/Other
VCCCORE
T34
Power/Other
VSS
F28
Power/Other
VCCCORE
V32
Power/Other
VSS
F32
Power/Other
VCCCORE
V36
Power/Other
VSS
F36
Power/Other
VCCCORE
W5
Power/Other
VSS
G5
Power/Other
VCCCORE
X34
Power/Other
VSS
H2
Power/Other
VCCCORE
Y35
Power/Other
VSS
H34
Power/Other
VCCCORE
Z32
Power/Other
VSS
K36
Power/Other
VCOREDET
E21
Power/Other
VSS
L5
Power/Other
VID0
AL35
Power/Other
VSS
M2
Power/Other
VID1
AM36
Power/Other
VSS
M34
Power/Other
Datasheet
Intel® Celeron® Processor up to 1.10 GHz
Table 50. PPGA Package Signal Listing
in Order by Signal Name
Pin Name
Datasheet
Pin
No.
VSS
P32
VSS
VSS
VSS
VSS
Signal Buffer Type
Table 50. PPGA Package Signal Listing
in Order by Signal Name
Pin Name
Pin
No.
Signal Buffer Type
Power/Other
VSS
AJ7
Power/Other
P36
Power/Other
VSS
AK36
Power/Other
Q5
Power/Other
VSS
AK4
Power/Other
R34
Power/Other
VSS
AL1
Power/Other
T32
Power/Other
VSS
AL3
Power/Other
VSS
T36
Power/Other
VSS
AM10
Power/Other
VSS
U5
Power/Other
VSS
AM14
Power/Other
VSS
V2
Power/Other
VSS
AM18
Power/Other
VSS
A37
Power/Other
VSS
AM2
Power/Other
VSS
AB32
Power/Other
VSS
AM22
Power/Other
VSS
AC33
Power/Other
VSS
AM26
Power/Other
VSS
AC5
Power/Other
VSS
AM30
Power/Other
VSS
AD2
Power/Other
VSS
AM34
Power/Other
VSS
AD34
Power/Other
VSS
AM6
Power/Other
VSS
AF32
Power/Other
VSS
AN3
Power/Other
VSS
AF36
Power/Other
VSS
B12
Power/Other
VSS
AG5
Power/Other
VSS
V34
Power/Other
VSS
AH2
Power/Other
VSS
X32
Power/Other
VSS
AH34
Power/Other
VSS
X36
Power/Other
VSS
AJ11
Power/Other
VSS
Y37
Power/Other
VSS
AJ15
Power/Other
VSS
Y5
Power/Other
VSS
AJ19
Power/Other
VSS
Z2
Power/Other
VSS
AJ23
Power/Other
VSS
Z34
Power/Other
VSS
AJ27
Power/Other
VSS
AJ31
Power/Other
VSS
AJ3
Power/Other
VSS
Y33
Power/Other
91
Intel® Celeron® Processor up to 1.10 GHz
5.3
FC-PGA/FC-PGA2 Packages
This section defines the mechanical specifications and signal definitions for the Intel Celeron
processor in the FC-PGA and FC-PGA2 packages.
5.3.1
FC-PGA Mechanical Specifications
Figure 23 is provided to aid in the design of heatsink and clip solutions as well as demonstrate
where pin-side capacitors will be located on the processor. Table 51 provides the measurements for
these dimensions in both inches and millimeters.
Figure 23. Package Dimensions (FC-PGA Package)
NOTES:
1. Unless otherwise specified, the following drawings are dimensioned in inches.
2. All dimensions provided with tolerances are guaranteed to be met for all normal production product.
3. Figures and drawings labeled as “Reference Dimensions” are provided for informational purposes only.
Reference dimensions are extracted from the mechanical design database and are nominal dimensions with
no tolerance information applied. Reference dimensions are NOT checked as part of the processor
manufacturing. Unless noted as such, dimensions in parentheses without tolerances are reference
dimensions.
4. Drawing not to scale.
92
Datasheet
Intel® Celeron® Processor up to 1.10 GHz
Table 51. Package Dimensions (FC-PGA Package)
Millimeters
Symbol
Min
Max
A1
0.787
A2
Inches
Notes
Min
Max
0.889
0.031
0.035
1.000
1.200
0.039
0.047
B1
11.183
11.285
0.440
0.445
B2
9.225
9.327
0.363
0.368
C1
23.495 max
0.925 max
C2
21.590 max
0.850 max
D
49.428
49.632
1.946
1.954
D1
45.466
45.947
1.790
1.810
G1
0.000
17.780
1
0.000
0.700
G2
0.000
17.780
1
0.000
0.700
G3
0.000
0.889
1
0.000
0.035
H
2.540
Nominal
0.100
Nominal
L
3.048
3.302
0.120
0.130
ϕP
0.431
0.483
0.017
0.019
Pin TP
0.508 Diametric True Position (Pin-to-Pin)
Notes
0.020 Diametric True Position (Pin-to-Pin)
NOTES:
1. Capacitors and resistors may be placed on the pin-side of the FC-PGA package in the area defined by G1,
G2, and G3. This area is a keepout zone for motherboard designers.
The bare processor die has mechanical load limits that should not be exceeded during heatsink
assembly, mechanical stress testing, or standard drop and shipping conditions. The heatsink attach
solution must not induce permanent stress into the processor substrate with the exception of a
uniform load to maintain the heatsink to the processor thermal interface. The package dynamic and
static loading parameters are listed in Table 52.
For Table 52, the following apply:
1. It is not recommended to use any portion of the processor substrate as a mechanical reference
or load bearing surface for thermal solutions.
2. Parameters assume uniformly applied loads
Table 52. Processor Die Loading Parameters (FC-PGA Package)
Dynamic (max)1
Static (max)2
Unit
Silicon Die Surface
200
50
lbf
Silicon Die Edge
100
12
lbf
Parameter
NOTES:
1. This specification applies to a uniform and a non-uniform load.
2. This is the maximum static force that can be applied by the heatsink and clip to maintain the heatsink and
processor interface.
Datasheet
93
Intel® Celeron® Processor up to 1.10 GHz
5.3.2
Mechanical Specifications (FC-PGA2 Package)
Figure 24 is provided to aid in the design of heatsink and clip solutions as well as demonstrate
where pin-side capacitors will be located on the processor. Table 53 lists the measurements for
these dimensions in both inches and millimeters.
Figure 24. Package Dimensions (FC-PGA2 Package)
94
Datasheet
Intel® Celeron® Processor up to 1.10 GHz
Table 53. Package Dimensions (FC-PGA2 Package)
Millimeters
Inches
Symbol
Minimum
Maximum
A1
2.266
A2
Notes
Minimum
Maximum
2.690
0.089
0.106
0.980
1.180
0.038
0.047
B1
30.800
31.200
1.212
1.229
B2
30.800
31.200
1.212
1.229
C1
33.000 max
1.299 max
C2
33.000 max
1.299 max
D
49.428
49.632
1.946
1.954
D1
45.466
45.974
1.790
1.810
G1
0.000
17.780
0.000
0.700
G2
0.000
17.780
0.000
0.700
G3
0.000
0.889
0.000
0.035
H
2.540
Nominal
0.100
Nominal
L
3.048
3.302
0.120
0.130
ΦP
0.431
0.483
0.017
0.019
Pin TP
0.508 Diametric True Position (Pin-to-Pin)
Notes
0.020 Diametric True Position (Pin-to-Pin)
NOTE: Capacitors will be placed on the pin-side of the FC-PGA2 package in the area defined by G1, G2, and
G3. This area is a keepout zone for motherboard designers.
For Table 52, the following apply:
1. It is not recommended to use any portion of the processor substrate as a mechanical reference
or load bearing surface for thermal solutions.
2. Parameters assume uniformly applied loads.
Table 54. Processor Case Loading Parameters (FC-PGA2 Package)
Dynamic (max)1
Static (max)2,3
Unit
IHS Surface
200
100
lbf
IHS Edge
125
N/A
lbf
IHS Corner
75
N/A
ibf
Parameter
NOTES:
1. This specification applies to a uniform and a non-uniform load.
2. This is the maximum static force that can be applied by the heatsink and clip to maintain the heatsink and
processor interface.
3. See socket manufacturer’s force loading specification also to ensure compliance. Maximum static loading
listed here does not account for the maximum reaction forces on the socket tabs or pins.
Datasheet
95
Intel® Celeron® Processor up to 1.10 GHz
5.3.2.1
Recommended Mechanical Keep-Out Zones (FC-PGA2 Package)
Figure 25. Volumetric Keep-Out
Figure 26. Component Keep-Out
96
Datasheet
Intel® Celeron® Processor up to 1.10 GHz
5.3.3
FC-PGA/FC-PGA2 Package Signal List
Figure 27. Package Dimensions (FC-PGA/FC-PGA2 Packages)
1
2
3
4
5
6
7
8
9
10
11 12
13
14 15
16
17
18
19
20
21
22
23
24 25
26
27
28
29
30
31 32
33
34 35
36
37
AN
AN
VSS
A16
A12
A6
RSV
RSV
RSV
BPRI
DEFER
RSV
RSV
TRDY
DRDY
BR0
ADS
TRST
TDI
TDO
AM
AM
RSV
AL
VCC
VSS
VSS
VSS
VCC
A15
A13
VSS
VCC
A9
VSS
RSV
RSV
VSS
VCC
A7
REQ4
VCC
REQ3
VCC
VSS
RSV
HITM
VSS
HIT
VCC
DBSY
VCC
VSS
THRMDN
VSS
THRMDP
VID1
TCK
VID0
AL
VID2
AK
AK
VCC
VSS
A28
A3
VREF6
A11
A14
RSV
REQ0
VREF7
LOCK
RSV
RS2
PWRGD
RSV
TMS
VCC
VSS
AJ
AJ
A21
VSS
VCC
VSS
VCC
VSS
VCC
VSS
VCC
VSS
VCC
VSS
VCC
VSS
VCC
BSEL1
BSEL0
SMI
VID3
AH
AH
VSS
RSV
A10
A5
A8
A4
BNR
REQ1
REQ2
RSV
RS1
VCC
RS0
AG
AF
A19
EDGCTRL
SLP
THERM
VCC
VSS
AG
TRIP
VSS
VCC
INIT
STPCLK
IGNNE
AF
VCC
A17
VSS
A25
RSV
AE
VSS
AE
VCC
A22
VCC
A20M
IERR
FLUSH
AD
AD
VSS
A31
VCC
VREF5
VSS
V_1.5
AC
AC
RSV
A20
VSS
VSS
FERR
RSV
AB
AB
A24
VCC
VSS
A23
VCC
V_CMOS
AA
Z
AA
A27
A30
RSV
VCC
VSS
A29
RSV
VCC
A18
VCC
Z
V_2.5
VSS
Y
Y
RSV
A26
RSV
VSS
VCC
VSS
X
RSV
RESET
VSS
RSV
VCC
X
VSS
W
W
D0
PLL1
VCC
RSV
RSV
BCLK
V
V
VSS
RSV
VREF4
D4
D15
VCC
PIN SIDE VIEW
U
VSS
VCC
U
PLL2
VSS
RSV
RSV
T
T
VCC
D1
D6
VSS
VCC
VSS
S
S
D8
D5
VCC
RTT
CTRL
RSV
R
RSV
VREF3
D17
VCC
RSV
R
VCC
VSS
Q
Q
D12
VSS
D10
RSV
RSV
RSV
P
P
VCC
D18
D9
VSS
VCC
VSS
N
N
D2
D14
VCC
RSV
RSV
RSV
M
M
D11
VSS
D3
VCC
VSS
LINT0
L
L
D13
D20
VSS
RSV
PICD1
LINT1
K
K
VCC
VREF2
D24
VCC
VCC
VSS
J
J
D7
D30
PICCLK
VCC
PREQ
PICD0
H
H
VSS
D16
VCC
D19
VSS
VCC
G
G
D21
D23
VSS
BP2
RSV
RSV
F
F
VCC
VCC
D32
D22
RSV
D27
VCC
D63
VREF1
E
D26
D25
VCC
VSS
VCC
VSS
VCC
VSS
VCC
VSS
VSS
VCC
RSV
VSS
RSV
VCC
VSS
VCC
D38
D39
D41
D42
D52
VSS
VCC
VSS
VCC
VSS
VSS
VCC
SLEW
CTRL
D62
D
VSS
VSS
RSV
VCC
VSS
E
RSV VREF0
BPM1
BP3
D
VCC
VSS
VCC
VSS
VCC
C
C
D33
VCC
D31
D34
D36
D45
D40
D49
D59
D55
D54
D58
D50
D56
RSV
RSV
RSV
BPM0
CPUPRES
B
D35
VSS
VCC
VCC
VSS
VCC
VSS
VCC
VSS
VSS
VCC
VSS
VCC
VSS
VCC
VSS
VCC
B
RSV
A
A
D29
1
2
3
D28
4
5
D37
D43
6
7
8
9
D44
10
11 12
D51
13
D47
14 15
D48
16
17
D57
18
19
D46
20
21
D53
22
23
D60
24 25
D61
26
27
RSV
28
29
RSV
30
31 32
RSV
33
PRDY
34 35
36
VSS
37
Table 55 and Table 56 provide the processor pin definitions. The signal locations on the PGA370
socket are to be used for signal routing, simulation, and component placement on the baseboard.
Figure 27 provides a pin-side view of the Intel Celeron FC-PGA/FC-PGA2 processor pin-out.
Datasheet
97
Intel® Celeron® Processor up to 1.10 GHz
Table 55. FC-PGA/FC-PGA2 Signal
Listing in Order by Signal
Name
Pin Name
98
Pin
Signal Group
Table 55. FC-PGA/FC-PGA2 Signal
Listing in Order by Signal
Name
Pin Name
Pin
Signal Group
A3#
AK8
AGTL+ I/O
BSEL0
AJ33
CMOS I/O
A4#
AH12
AGTL+ I/O
BSEL15
AJ31
Power/Other
A5#
AH8
AGTL+ I/O
CPUPRES#
C37
Power/Other
A6#
AN9
AGTL+ I/O
D0#
W1
AGTL+ I/O
A7#
AL15
AGTL+ I/O
D1#
T4
AGTL+ I/O
A8#
AH10
AGTL+ I/O
D2#
N1
AGTL+ I/O
A9#
AL9
AGTL+ I/O
D3#
M6
AGTL+ I/O
A10#
AH6
AGTL+ I/O
D4#
U1
AGTL+ I/O
A11#
AK10
AGTL+ I/O
D5#
S3
AGTL+ I/O
A12#
AN5
AGTL+ I/O
D6#
T6
AGTL+ I/O
A13#
AL7
AGTL+ I/O
D7#
J1
AGTL+ I/O
A14#
AK14
AGTL+ I/O
D8#
S1
AGTL+ I/O
A15#
AL5
AGTL+ I/O
D9#
P6
AGTL+ I/O
A16#
AN7
AGTL+ I/O
D10#
Q3
AGTL+ I/O
A17#
AE1
AGTL+ I/O
D11#
M4
AGTL+ I/O
A18#
Z6
AGTL+ I/O
D12#
Q1
AGTL+ I/O
A19#
AG3
AGTL+ I/O
D13#
L1
AGTL+ I/O
A20#
AC3
AGTL+ I/O
D14#
N3
AGTL+ I/O
A21#
AJ1
AGTL+ I/O
D15#
U3
AGTL+ I/O
A22#
AE3
AGTL+ I/O
D16#
H4
AGTL+ I/O
A23#
AB6
AGTL+ I/O
D17#
R4
AGTL+ I/O
A24#
AB4
AGTL+ I/O
D18#
P4
AGTL+ I/O
A25#
AF6
AGTL+ I/O
D19#
H6
AGTL+ I/O
A26#
Y3
AGTL+ I/O
D20#
L3
AGTL+ I/O
A27#
AA1
AGTL+ I/O
D21#
G1
AGTL+ I/O
A28#
AK6
AGTL+ I/O
D22#
F8
AGTL+ I/O
A29#
Z4
AGTL+ I/O
D23#
G3
AGTL+ I/O
A30#
AA3
AGTL+ I/O
D24#
K6
AGTL+ I/O
A31#
AD4
AGTL+ I/O
D25#
E3
AGTL+ I/O
A20M#
AE33
CMOS Input
D26#
E1
AGTL+ I/O
ADS#
AN31
AGTL+ I/O
D27#
F12
AGTL+ I/O
BCLK
W37
System Bus Clock
D28#
A5
AGTL+ I/O
BNR#
AH14
AGTL+ I/O
D29#
A3
AGTL+ I/O
BP2#
G33
AGTL+ I/O
D30#
J3
AGTL+ I/O
BP3#
E37
AGTL+ I/O
D31#
C5
AGTL+ I/O
BPM0#
C35
AGTL+ I/O
D32#
F6
AGTL+ I/O
BPM1#
E35
AGTL+ I/O
D33#
C1
AGTL+ I/O
BPRI#
AN17
AGTL+ Input
D34#
C7
AGTL+ I/O
BR0#
AN29
AGTL+ I/O
D35#
B2
AGTL+ I/O
Datasheet
Intel® Celeron® Processor up to 1.10 GHz
Table 55. FC-PGA/FC-PGA2 Signal
Listing in Order by Signal
Name
Pin Name
Datasheet
Pin
Signal Group
Table 55. FC-PGA/FC-PGA2 Signal
Listing in Order by Signal
Name
Pin Name
Pin
Signal Group
D36#
C9
AGTL+ I/O
GND
AD34
Power/Other
D37#
A9
AGTL+ I/O
GND
AF32
Power/Other
D38#
D8
AGTL+ I/O
GND
AF36
Power/Other
D39#
D10
AGTL+ I/O
GND
AG5
Power/Other
D40#
C15
AGTL+ I/O
GND
AH2
Power/Other
D41#
D14
AGTL+ I/O
GND
AH34
Power/Other
D42#
D12
AGTL+ I/O
GND
AJ3
Power/Other
D43#
A7
AGTL+ I/O
GND
AJ7
Power/Other
D44#
A11
AGTL+ I/O
GND
AJ11
Power/Other
D45#
C11
AGTL+ I/O
GND
AJ15
Power/Other
D46#
A21
AGTL+ I/O
GND
AJ19
Power/Other
D47#
A15
AGTL+ I/O
GND
AJ23
Power/Other
D48#
A17
AGTL+ I/O
GND
AJ27
Power/Other
D49#
C13
AGTL+ I/O
GND
AK4
Power/Other
D50#
C25
AGTL+ I/O
GND
AK36
Power/Other
D51#
A13
AGTL+ I/O
GND
AL1
Power/Other
D52#
D16
AGTL+ I/O
GND
AL3
Power/Other
D53#
A23
AGTL+ I/O
GND
AM6
Power/Other
D54#
C21
AGTL+ I/O
GND
AM10
Power/Other
D55#
C19
AGTL+ I/O
GND
AM14
Power/Other
D56#
C27
AGTL+ I/O
GND
AM18
Power/Other
D57#
A19
AGTL+ I/O
GND
AM22
Power/Other
D58#
C23
AGTL+ I/O
GND
AM26
Power/Other
D59#
C17
AGTL+ I/O
GND
AM30
Power/Other
D60#
A25
AGTL+ I/O
GND
AM34
Power/Other
D61#
A27
AGTL+ I/O
GND
AN3
Power/Other
D62#
E25
AGTL+ I/O
GND
B4
Power/Other
D63#
F16
AGTL+ I/O
GND
B8
Power/Other
DBSY#
AL27
AGTL+ I/O
GND
B12
Power/Other
DEFER#
AN19
AGTL+ Input
GND
B16
Power/Other
DRDY#
AN27
AGTL+ I/O
GND
B20
Power/Other
EDGCTRL 2,8
AG1
Power/Other
GND
B24
Power/Other
FERR#
AC35
CMOS Output
GND
B28
Power/Other
FLUSH#
AE37
CMOS Input
GND
B32
Power/Other
GND
A37
Power/Other
GND
D2
Power/Other
GND
AB32
Power/Other
GND
D4
Power/Other
GND
AC5
Power/Other
GND
D18
Power/Other
GND
AC33
Power/Other
GND
D22
Power/Other
GND
AD2
Power/Other
GND
D26
Power/Other
99
Intel® Celeron® Processor up to 1.10 GHz
Table 55. FC-PGA/FC-PGA2 Signal
Listing in Order by Signal
Name
Pin Name
100
Pin
Signal Group
Table 55. FC-PGA/FC-PGA2 Signal
Listing in Order by Signal
Name
Pin Name
Pin
Signal Group
GND
D30
Power/Other
LINT0/INTR
M36
CMOS Input
GND
D34
Power/Other
LINT1/NMI
L37
CMOS Input
GND
E7
Power/Other
LOCK#
AK20
AGTL+ I/O
GND
E11
Power/Other
PICCLK
J33
APIC Clock Input
GND
E15
Power/Other
PICD0
J35
APIC I/O
GND
E19
Power/Other
PICD1
L35
APIC I/O
GND
F20
Power/Other
PLL1
W33
Power/Other
GND
F24
Power/Other
PLL2
U33
Power/Other
GND
F28
Power/Other
PRDY#
A35
AGTL+ Output
GND
F32
Power/Other
PREQ#
J37
CMOS Input
GND
F36
Power/Other
PWRGOOD
AK26
CMOS Input
GND
G5
Power/Other
REQ0#
AK18
AGTL+ I/O
GND
H2
Power/Other
REQ1#
AH16
AGTL+ I/O
GND
H34
Power/Other
REQ2#
AH18
AGTL+ I/O
GND
K36
Power/Other
REQ3#
AL19
AGTL+ I/O
GND
L5
Power/Other
REQ4#
AL17
AGTL+ I/O
GND
M2
Power/Other
Reserved
A29
Reserved for future use
GND
M34
Power/Other
Reserved
A31
Reserved for future use
GND
P32
Power/Other
Reserved
A33
Reserved for future use
GND
P36
Power/Other
Reserved
AC1
Reserved for future use
GND
Q5
Power/Other
Reserved
AC37
Reserved for future use
GND
R34
Power/Other
Reserved
AF4
Reserved for future use
GND
T32
Power/Other
Reserved
AH20
Reserved for future use
GND
T36
Power/Other
Reserved
AK16
Reserved for future use
GND
U5
Power/Other
Reserved
AK24
Reserved for future use
GND
V2
Power/Other
Reserved
AK30
Reserved for future use
GND
V34
Power/Other
Reserved
AL11
Reserved for future use
GND
X32
Power/Other
Reserved
AL13
Reserved for future use
Reserved
X34
Reserved for future use
Reserved
AL21
Reserved for future use
GND
X36
Power/Other
Reserved
AN11
Reserved for future use
GND
Y5
Power/Other
Reserved
AN13
Reserved for future use
GND
Y37
Power/Other
Reserved
AN15
Reserved for future use
GND
Z2
Power/Other
Reserved
AN21
Reserved for future use
GND
Z34
Power/Other
Reserved
AN23
Reserved for future use
HIT#
AL25
AGTL+ I/O
Reserved
B36
Reserved for future use
HITM#
AL23
AGTL+ I/O
Reserved
C29
Reserved for future use
IERR#
AE35
CMOS Output
Reserved
C31
Reserved for future use
IGNNE#
AG37
CMOS Input
Reserved
C33
Reserved for future use
INIT#
AG33
CMOS Input
Reserved
E23
Reserved for future use
Datasheet
Intel® Celeron® Processor up to 1.10 GHz
Table 55. FC-PGA/FC-PGA2 Signal
Listing in Order by Signal
Name
Pin Name
Signal Group
Pin Name
Pin
Signal Group
Reserved
E29
Reserved for future use
TDO
AN37
TAP Output
Reserved
E31
Reserved for future use
THERMDN
AL29
Power/Other
Reserved
F10
Reserved for future use
THERMDP
AL31
Power/Other
Reserved
G35
Reserved for future use
THERMTRIP#
AH28
CMOS Output
Reserved
G37
Reserved for future use
TMS
AK32
TAP Input
Reserved
L33
Reserved for future use
TRDY#
AN25
AGTL+ Input
Reserved
N33
Reserved for future use
TRST#
AN33
TAP Input
Reserved
N35
Reserved for future use
VCC1.5 1
AD36
Power/Other
Reserved
N37
Reserved for future use
Vcc2.5
Z36
Power/Other
Reserved
Q33
Reserved for future use
VCCCMOS
AB36
Power/Other
Reserved
Q35
Reserved for future use
VCCCORE
AA5
Power/Other
Reserved
Q37
Reserved for future use
VCCCORE
AA37
Power/Other
Reserved
R2
Reserved for future use
VCCCORE
AB2
Power/Other
Reserved
S33
Reserved for future use
VCCCORE
AB34
Power/Other
Reserved
S37
Reserved for future use
VCCCORE
AD32
Power/Other
Reserved
U35
Reserved for future use
VCCCORE
AE5
Power/Other
Reserved
U37
Reserved for future use
VCCCORE
AF2
Power/Other
Reserved
V4
Reserved for future use
VCCCORE
AF34
Power/Other
Reserved
W3
Reserved for future use
VCCCORE
AH24
Power/Other
Reserved
W35
Reserved for future use
VCCCORE
AH32
Power/Other
Reserved
X6
Reserved for future use
VCCCORE
AH36
Power/Other
Reserved
X20
Reserved for future use
VCCCORE
AJ5
Power/Other
Reserved
Y1
Reserved for future use
VCCCORE
AJ9
Power/Other
Reserved
AA33
Reserved for future use
VCCCORE
AJ13
Power/Other
Reserved
AA35
Reserved for future use
VCCCORE
AJ17
Power/Other
Reserved
AM2
Reserved for future use
VCCCORE
AJ21
Power/Other
Reserved4
Y33
Reserved for future use
VCCCORE
AJ25
Power/Other
6
AH4
Power/Other
VCCCORE
AJ29
Power/Other
7
RESET#
X4
Power/Other
VCCCORE
AK2
Power/Other
RS0#
AH26
AGTL+ Input
VCCCORE
AK34
Power/Other
RS1#
AH22
AGTL+ Input
VCCCORE
AM4
Power/Other
RS2#
AK28
AGTL+ Input
VCCCORE
AM8
Power/Other
RTTCTRL
S35
Power/Other
VCCCORE
AM12
Power/Other
SLEWCTRL
E27
Power/Other
VCCCORE
AM16
Power/Other
SLP#
AH30
CMOS Input
VCCCORE
AM20
Power/Other
SMI#
AJ35
CMOS Input
VCCCORE
AM24
Power/Other
STPCLK#
AG35
CMOS Input
VCCCORE
AM28
Power/Other
TCK
AL33
TAP Input
VCCCORE
AM32
Power/Other
TDI
AN35
TAP Input
VCCCORE
B6
Power/Other
3
RESET#
Datasheet
Pin
Table 55. FC-PGA/FC-PGA2 Signal
Listing in Order by Signal
Name
101
Intel® Celeron® Processor up to 1.10 GHz
Table 55. FC-PGA/FC-PGA2 Signal
Listing in Order by Signal
Name
Pin Name
102
Pin
Signal Group
Table 55. FC-PGA/FC-PGA2 Signal
Listing in Order by Signal
Name
Pin Name
Pin
Signal Group
VCCCORE
B10
Power/Other
VCCCORE
T34
Power/Other
VCCCORE
B14
Power/Other
VCCCORE
V32
Power/Other
VCCCORE
B18
Power/Other
VCCCORE
V36
Power/Other
VCCCORE
B22
Power/Other
VCCCORE
W5
Power/Other
VCCCORE
B26
Power/Other
VCCCORE
X34
Power/Other
VCCCORE
B30
Power/Other
VCCCORE
Y35
Power/Other
VCCCORE
B34
Power/Other
VCCCORE
Z32
Power/Other
VCCCORE
C3
Power/Other
VCORE_DET
E21
Power/Other
VCCCORE
D6
Power/Other
VID0
AL35
Power/Other
VCCCORE
D20
Power/Other
VID1
AM36
Power/Other
VCCCORE
D24
Power/Other
VID2
AL37
Power/Other
VCCCORE
D28
Power/Other
VID3
AJ37
Power/Other
VCCCORE
D32
Power/Other
VREF0
E33
Power/Other
VCCCORE
D36
Power/Other
VREF1
F18
Power/Other
VCCCORE
E5
Power/Other
VREF2
K4
Power/Other
VCCCORE
E9
Power/Other
VREF3
R6
Power/Other
VCCCORE
E13
Power/Other
VREF4
V6
Power/Other
VCCCORE
E17
Power/Other
VREF5
AD6
Power/Other
VCCCORE
F2
Power/Other
VREF6
AK12
Power/Other
VCCCORE
F4
Power/Other
VREF7
AK22
Power/Other
VCCCORE
F14
Power/Other
VCCCORE
F22
Power/Other
VCCCORE
F26
Power/Other
VCCCORE
F30
Power/Other
VCCCORE
F34
Power/Other
VCCCORE
H32
Power/Other
VCCCORE
H36
Power/Other
VCCCORE
J5
Power/Other
VCCCORE
K2
Power/Other
VCCCORE
K32
Power/Other
VCCCORE
K34
Power/Other
VCCCORE
M32
Power/Other
VCCCORE
N5
Power/Other
VCCCORE
P2
Power/Other
VCCCORE
P34
Power/Other
VCCCORE
R32
Power/Other
VCCCORE
R36
Power/Other
VCCCORE
S5
Power/Other
VCCCORE
T2
Power/Other
NOTES:
1. VCC1.5 must be supplied by the same voltage
source supplying VTT on the motherboard.
2. Previously this pin functioned as the EDGCTRL
signal.
3. Previously, PGA370 designs defined this pin as a
GND. For flexible PGA370 designs, it must be left
unconnected (NC).
4. Previously, PGA370 designs defined this pin as a
GND.
5. Intel Celeron processor in the FC-PGA/FC-PGA2
packages do not use this pin.
6. This pin is only reset for processors with a CPUID
of 0686h. For previous Celeron processors prior
to 0686h (not including 0686h) this pin is
reserved.
7. This pin is reserved for Intel Celeron processors
with a CPUID of 0686h.
8. For CPUID of 0681h, this is a VSS. For other
068xh processors, this pin is a No Connect (NC).
Datasheet
Intel® Celeron® Processor up to 1.10 GHz
Table 56. FC-PGA/FC-PGA2 Signal
Listing in Order by Pin
Number
Pin
No.
Datasheet
Pin Name
Signal Group
Table 56. FC-PGA/FC-PGA2 Signal
Listing in Order by Pin
Number
Pin
No.
Pin Name
Signal Group
A3
D29#
AGTL+ I/O
AD32
VCCCORE
Power/Other
A5
D28#
AGTL+ I/O
AD34
GND
Power/Other
A7
D43#
AGTL+ I/O
AD36
VCC1.5 1
Power/Other
A9
D37#
AGTL+ I/O
AE1
A17#
AGTL+ I/O
A11
D44#
AGTL+ I/O
AE3
A22#
AGTL+ I/O
A13
D51#
AGTL+ I/O
AE5
VCCCORE
Power/Other
A15
D47#
AGTL+ I/O
AE33
A20M#
CMOS Input
A17
D48#
AGTL+ I/O
AE35
IERR#
CMOS Output
A19
D57#
AGTL+ I/O
AE37
FLUSH#
CMOS Input
A21
D46#
AGTL+ I/O
AF2
VCCCORE
Power/Other
A23
D53#
AGTL+ I/O
AF4
Reserved
Reserved for future use
A25
D60#
AGTL+ I/O
AF6
A25#
AGTL+ I/O
A27
D61#
AGTL+ I/O
AF32
GND
Power/Other
A29
Reserved
Reserved for future use
AF34
VCCCORE
Power/Other
A31
Reserved
Reserved for future use
AF36
GND
Power/Other
2,8
A33
Reserved
Reserved for future use
AG1
EDGCTRL
A35
PRDY#
AGTL+ Output
AG3
A19#
A37
GND
Power/Other
AG5
GND
Power/Other
AA1
A27#
AGTL+ I/O
AG33
INIT#
CMOS Input
AA3
A30#
AGTL+ I/O
AG35
STPCLK#
CMOS Input
AA5
VCCCORE
Power/Other
AG37
IGNNE#
CMOS Input
AA33
Reserved
Reserved for future use
AH2
GND
Power/Other
AGTL+ I/O
Power/Other
6
AA35
Reserved
Reserved for future use
AH4
RESET#
Power/Other
AA37
VCCCORE
Power/Other
AH6
A10#
AGTL+ I/O
AB2
VCCCORE
Power/Other
AH8
A5#
AGTL+ I/O
AB4
A24#
AGTL+ I/O
AH10
A8#
AGTL+ I/O
AB6
A23#
AGTL+ I/O
AH12
A4#
AGTL+ I/O
AB32
GND
Power/Other
AH14
BNR#
AGTL+ I/O
AB34
VCCCORE
Power/Other
AH16
REQ1#
AGTL+ I/O
AB36
VCCCMOS
Power/Other
AH18
REQ2#
AGTL+ I/O
AC1
Reserved
Reserved for future use
AH20
Reserved
Reserved for future use
AC3
A20#
AGTL+ I/O
AH22
RS1#
AGTL+ Input
AC5
GND
Power/Other
AH24
VCCCORE
Power/Other
AC33
GND
Power/Other
AH26
RS0#
AGTL+ Input
AC35
FERR#
CMOS Output
AH28
THERMTRIP#
CMOS Output
AC37
Reserved
Reserved for future use
AH30
SLP#
CMOS Input
AD2
GND
Power/Other
AH32
VCCCORE
Power/Other
AD4
A31#
AGTL+ I/O
AH34
GND
Power/Other
AD6
VREF5
Power/Other
AH36
VCCCORE
Power/Other
103
Intel® Celeron® Processor up to 1.10 GHz
Table 56. FC-PGA/FC-PGA2 Signal
Listing in Order by Pin
Number
Pin
No.
AJ1
104
Pin Name
A21#
Signal Group
Table 56. FC-PGA/FC-PGA2 Signal
Listing in Order by Pin
Number
Pin
No.
Pin Name
AGTL+ I/O
AL5
A15#
Signal Group
AGTL+ I/O
AJ3
GND
Power/Other
AL7
A13#
AGTL+ I/O
AJ5
VCCCORE
Power/Other
AL9
A9#
AGTL+ I/O
AJ7
GND
Power/Other
AL11
Reserved
Reserved for future use
AJ9
VCCCORE
Power/Other
AL13
Reserved
Reserved for future use
AJ11
GND
Power/Other
AL15
A7#
AGTL+ I/O
AJ13
VCCCORE
Power/Other
AL17
REQ4#
AGTL+ I/O
AJ15
GND
Power/Other
AL19
REQ3#
AGTL+ I/O
AJ17
VCCCORE
Power/Other
AL21
Reserved
Reserved for future use
AJ19
GND
Power/Other
AL23
HITM#
AGTL+ I/O
AJ21
VCCCORE
Power/Other
AL25
HIT#
AGTL+ I/O
AJ23
GND
Power/Other
AL27
DBSY#
AGTL+ I/O
AJ25
VCCCORE
Power/Other
AL29
THERMDN
Power/Other
AJ27
GND
Power/Other
AL31
THERMDP
Power/Other
AJ29
VCCCORE
Power/Other
AL33
TCK
TAP Input
Power/Other
5
AJ31
BSEL1
Power/Other
AL35
VID0
AJ33
BSEL0
CMOS I/O
AL37
VID2
Power/Other
3
AJ35
SMI#
CMOS Input
AM2
Reserved
Reserved for future use
AJ37
VID3
Power/Other
AM4
VCCCORE
Power/Other
AK2
VCCCORE
Power/Other
AM6
GND
Power/Other
AK4
GND
Power/Other
AM8
VCCCORE
Power/Other
AK6
A28#
AGTL+ I/O
AM10
GND
Power/Other
AK8
A3#
AGTL+ I/O
AM12
VCCCORE
Power/Other
AK10
A11#
AGTL+ I/O
AM14
GND
Power/Other
AK12
VREF6
Power/Other
AM16
VCCCORE
Power/Other
AK14
A14#
AGTL+ I/O
AM18
GND
Power/Other
AK16
Reserved
Reserved for future use
AM20
VCCCORE
Power/Other
AK18
REQ0#
AGTL+ I/O
AM22
GND
Power/Other
AK20
LOCK#
AGTL+ I/O
AM24
VCCCORE
Power/Other
AK22
VREF7
Power/Other
AM26
GND
Power/Other
AK24
Reserved
Reserved for future use
AM28
VCCCORE
Power/Other
AK26
PWRGOOD
CMOS Input
AM30
GND
Power/Other
AK28
RS2#
AGTL+ Input
AM32
VCCCORE
Power/Other
AK30
Reserved
Reserved for future use
AM34
GND
Power/Other
AK32
TMS
TAP Input
AM36
VID1
Power/Other
AK34
VCCCORE
Power/Other
AN3
GND
Power/Other
AK36
GND
Power/Other
AN5
A12#
AGTL+ I/O
AL1
GND
Power/Other
AN7
A16#
AGTL+ I/O
AL3
GND
Power/Other
AN9
A6#
AGTL+ I/O
Datasheet
Intel® Celeron® Processor up to 1.10 GHz
Table 56. FC-PGA/FC-PGA2 Signal
Listing in Order by Pin
Number
Pin
No.
Datasheet
Pin Name
Signal Group
Table 56. FC-PGA/FC-PGA2 Signal
Listing in Order by Pin
Number
Pin
No.
Pin Name
Signal Group
AN11
Reserved
Reserved for future use
C15
D40#
AGTL+ I/O
AN13
Reserved
Reserved for future use
C17
D59#
AGTL+ I/O
AN15
Reserved
Reserved for future use
C19
D55#
AGTL+ I/O
AN17
BPRI#
AGTL+ Input
C21
D54#
AGTL+ I/O
AN19
DEFER#
AGTL+ Input
C23
D58#
AGTL+ I/O
AN21
Reserved
Reserved for future use
C25
D50#
AGTL+ I/O
AN23
Reserved
Reserved for future use
C27
D56#
AGTL+ I/O
AN25
TRDY#
AGTL+ Input
C29
Reserved
Reserved for future use
AN27
DRDY#
AGTL+ I/O
C31
Reserved
Reserved for future use
AN29
BR0#
AGTL+ I/O
C33
Reserved
Reserved for future use
AN31
ADS#
AGTL+ I/O
C35
BPM0#
AGTL+ I/O
AN33
TRST#
TAP Input
C37
CPUPRES#
Power/Other
AN35
TDI
TAP Input
D2
GND
Power/Other
AN37
TDO
TAP Output
D4
GND
Power/Other
B2
D35#
AGTL+ I/O
D6
VCCCORE
Power/Other
B4
GND
Power/Other
D8
D38#
AGTL+ I/O
B6
VCCCORE
Power/Other
D10
D39#
AGTL+ I/O
B8
GND
Power/Other
D12
D42#
AGTL+ I/O
B10
VCCCORE
Power/Other
D14
D41#
AGTL+ I/O
B12
GND
Power/Other
D16
D52#
AGTL+ I/O
B14
VCCCORE
Power/Other
D18
GND
Power/Other
B16
GND
Power/Other
D20
VCCCORE
Power/Other
B18
VCCCORE
Power/Other
D22
GND
Power/Other
B20
GND
Power/Other
D24
VCCCORE
Power/Other
B22
VCCCORE
Power/Other
D26
GND
Power/Other
B24
GND
Power/Other
D28
VCCCORE
Power/Other
B26
VCCCORE
Power/Other
D30
GND
Power/Other
B28
GND
Power/Other
D32
VCCCORE
Power/Other
B30
VCCCORE
Power/Other
D34
GND
Power/Other
B32
GND
Power/Other
D36
VCCCORE
Power/Other
B34
VCCCORE
Power/Other
E1
D26#
AGTL+ I/O
B36
Reserved
Reserved for future use
E5
VCCCORE
Power/Other
C1
D33#
AGTL+ I/O
E7
GND
Power/Other
C3
VCCCORE
Power/Other
E9
VCCCORE
Power/Other
C5
D31#
AGTL+ I/O
E11
GND
Power/Other
C7
D34#
AGTL+ I/O
E13
VCCCORE
Power/Other
C9
D36#
AGTL+ I/O
E15
GND
Power/Other
C11
D45#
AGTL+ I/O
E17
VCCCORE
Power/Other
C13
D49#
AGTL+ I/O
E19
GND
Power/Other
105
Intel® Celeron® Processor up to 1.10 GHz
Table 56. FC-PGA/FC-PGA2 Signal
Listing in Order by Pin
Number
Pin
No.
106
Pin Name
Signal Group
Table 56. FC-PGA/FC-PGA2 Signal
Listing in Order by Pin
Number
Pin
No.
Pin Name
Signal Group
E21
VCORE_DET
Power/Other
H36
VCCCORE
Power/Other
E23
Reserved
Reserved for future use
J1
D7#
AGTL+ I/O
E25
D62#
AGTL+ I/O
J3
D30#
AGTL+ I/O
E27
SLEWCTRL
Power/Other
J5
VCCCORE
Power/Other
E29
Reserved
Reserved for future use
J33
PICCLK
APIC Clock Input
E3
D25#
AGTL+ I/O
J35
PICD0
APIC I/O
E31
Reserved
Reserved for future use
J37
PREQ#
CMOS Input
E33
VREF0
Power/Other
K2
VCCCORE
Power/Other
E35
BPM1#
AGTL+ I/O
K4
VREF2
Power/Other
E37
BP3#
AGTL+ I/O
K6
D24#
AGTL+ I/O
F2
VCCCORE
Power/Other
K32
VCCCORE
Power/Other
F4
VCCCORE
Power/Other
K34
VCCCORE
Power/Other
F6
D32#
AGTL+ I/O
K36
GND
Power/Other
F8
D22#
AGTL+ I/O
L1
D13#
AGTL+ I/O
F10
Reserved
Reserved for future use
L3
D20#
AGTL+ I/O
F12
D27#
AGTL+ I/O
L5
GND
Power/Other
F14
VCCCORE
Power/Other
L33
Reserved
Reserved for future use
F16
D63#
AGTL+ I/O
L35
PICD1
APIC I/O
F18
VREF1
Power/Other
L37
LINT1/NMI
CMOS Input
F20
GND
Power/Other
M2
GND
Power/Other
F22
VCCCORE
Power/Other
M4
D11#
AGTL+ I/O
F24
GND
Power/Other
M6
D3#
AGTL+ I/O
F26
VCCCORE
Power/Other
M32
VCCCORE
Power/Other
F28
GND
Power/Other
M34
GND
Power/Other
F30
VCCCORE
Power/Other
M36
LINT0/INTR
CMOS Input
F32
GND
Power/Other
N1
D2#
AGTL+ I/O
F34
VCCCORE
Power/Other
N3
D14#
AGTL+ I/O
F36
GND
Power/Other
N5
VCCCORE
Power/Other
G1
D21#
AGTL+ I/O
N33
Reserved
Reserved for future use
G3
D23#
AGTL+ I/O
N35
Reserved
Reserved for future use
G5
GND
Power/Other
N37
Reserved
Reserved for future use
G33
BP2#
AGTL+ I/O
P2
VCCCORE
Power/Other
G35
Reserved
Reserved for future use
P4
D18#
AGTL+ I/O
G37
Reserved
Reserved for future use
P6
D9#
AGTL+ I/O
H2
GND
Power/Other
P32
GND
Power/Other
H4
D16#
AGTL+ I/O
P34
VCCCORE
Power/Other
H6
D19#
AGTL+ I/O
P36
GND
Power/Other
H32
VCCCORE
Power/Other
Q1
D12#
AGTL+ I/O
H34
GND
Power/Other
Q3
D10#
AGTL+ I/O
Datasheet
Intel® Celeron® Processor up to 1.10 GHz
Table 56. FC-PGA/FC-PGA2 Signal
Listing in Order by Pin
Number
Pin
No.
Q5
Datasheet
Pin Name
GND
Signal Group
Power/Other
Table 56. FC-PGA/FC-PGA2 Signal
Listing in Order by Pin
Number
Pin
No.
Pin Name
Signal Group
W37
BCLK
System Bus Clock
Power/Other
Reserved for future use
Q33
Reserved
Reserved for future use
X4
RESET#7
Q35
Reserved
Reserved for future use
X6
Reserved
Q37
Reserved
Reserved for future use
X20
Reserved
Reserved for future use
R2
Reserved
Reserved for future use
X32
GND
Power/Other
R4
D17#
AGTL+ I/O
X34
Reserved
Reserved for future use
R6
VREF3
Power/Other
X36
GND
Power/Other
R32
VCCCORE
Power/Other
Y1
Reserved
Reserved for future use
R34
GND
Power/Other
Y3
A26#
AGTL+ I/O
R36
VCCCORE
Power/Other
Y5
GND
Power/Other
S1
D8#
AGTL+ I/O
Y33
Reserved4
Reserved for future use
S3
D5#
AGTL+ I/O
Y35
VCCCORE
Power/Other
S5
VCCCORE
Power/Other
Y37
GND
Power/Other
S33
Reserved
Reserved for future use
Z2
GND
Power/Other
S35
RTTCTRL
Power/Other
Z4
A29#
AGTL+ I/O
S37
Reserved
Reserved for future use
Z6
A18#
AGTL+ I/O
T2
VCCCORE
Power/Other
Z32
VCCCORE
Power/Other
T4
D1#
AGTL+ I/O
Z34
GND
Power/Other
T6
D6#
AGTL+ I/O
Z36
Vcc2.5
Power/Other
T32
GND
Power/Other
T34
VCCCORE
Power/Other
T36
GND
Power/Other
U1
D4#
AGTL+ I/O
U3
D15#
AGTL+ I/O
U5
GND
Power/Other
U33
PLL2
Power/Other
U35
Reserved
Reserved for future use
U37
Reserved
Reserved for future use
V2
GND
Power/Other
V4
Reserved
Reserved for future use
V6
VREF4
Power/Other
V32
VCCCORE
Power/Other
V34
GND
Power/Other
V36
VCCCORE
Power/Other
W1
D0#
AGTL+ I/O
W3
Reserved
Reserved for future use
W5
VCCCORE
Power/Other
W33
PLL1
Power/Other
W35
Reserved
Reserved for future use
NOTES:
1. VCC1.5 must be supplied by the same voltage
source supplying VTT on the motherboard.
2. Previously this pin functioned as the EDGCTRL
signal.
3. Previously, PGA370 designs defined this pin as a
GND. For flexible PGA370 designs, it must be left
unconnected (NC).
4. Previously, PGA370 designs defined this pin as a
GND.
5. Celeron processor in the FC-PGA/FC-PGA2
packages does not make use of this pin.
6. This pin is only reset for processors with a CPUID
of 0686h. For previous Celeron processors prior
to 0686h (not including 0686h) this pin is
reserved.
7. This pin is reserved for Celeron processors with a
CPUID of 0686h.
8. For CPUID of 0681h, this is a VSS. For other
068xh processors, this pin is a No Connect (NC).
107
Intel® Celeron® Processor up to 1.10 GHz
5.4
Processor Markings (PPGA/FC-PGA/FC-PGA2 Packages)
Figure 28 through Figure 30 show processor top-side markings; the markings aid in the
identification of a Celeron processor for the PGA370 socket. Package dimension measurements are
provided in Table 47 for the PPGA package, Table 51 for the FC-PGA package, and Table 53 for
the FC-PGA2 package.
Figure 28. Top Side Processor Markings (PPGA Package)
Country of Origin
Celeron logo
Product Code
Celeron ®
M ALAY
RB80526RX566128
FFFFFFFF-0001 SSSSS
FPO # - S/N
S-Spec#
Figure 29. Top Side Processor Markings (FC-PGA Package)
GRP1LINE1
GRP1LINE2
GRP2LINE1
GRP2LINE2
GRP1LN1: Intel (m )(c) '01__-__(Country Of Origin)
GRP1LN2: (Core Freq)/(Cache)/(Bus Freq)/(Voltage)
GRP2LN1: (FPO)-(S/N)
GRP2LN2: Celeron (S-Spec)
2D M atrix
M ark
Figure 30. Top Side Processor Markings (FC-PGA2 Package)
108
GRP1LN1
GRP1LN2
GRP1LN1: Intel (m )(c) '01__-__(Country Of Origin)
GRP1LN2: (Core Freq)/(Cache)/(Bus Freq)/(Voltage)
GRP2LN1
GRP2LN2
GRP2LN1: (FPO)-(S/N)
GRP2LN2: Celeron (S-Spec)
Datasheet
Intel® Celeron® Processor up to 1.10 GHz
5.5
Heatsink Volumetric Keepout Zone Guidelines
When designing a system platform it is necessary to ensure sufficient space is left for a heatsink to
be installed without mechanical interference. Due to the large number of proprietary heatsink
designs, Intel cannot specify a keepout zone that covers all passive and active-fan heatsinks. It is
the system designer’s responsibility to consider their own proprietary solution when designing the
desired keepout zone in their system platform. Please refer to the Intel® Celeron® Processor
(PPGA) at 466 MHz Thermal Solutions Guidelines (Order Number 245156) for further guidance.
Note:
Datasheet
The heatsink keepout zones found in Section 6.0, “Boxed Processor Specifications” on page 110
refer specifically to the Boxed Processor’s active-fan heatsink. This does not reflect the worst-case
dimensions that may exist with other third party passive or active-fan heatsinks. Contact your
vendor of choice for their passive or active-fan heatsink dimensions to ensure that mechanical
interference with system platform components does not occur.
109
Intel® Celeron® Processor up to 1.10 GHz
6.0
Boxed Processor Specifications
The Celeron processor is also offered as an Intel boxed processor in the FC-PGA/FC-PGA2,
PPGA, and S.E.P. Packages. Intel boxed processors are intended for system integrators who build
systems from motherboards and standard components. The boxed Celeron processor in the S.E.P.
Package is supplied with an attached fan heatsink. The boxed Celeron processors in FC-PGA/
FC-PGA2 and PPGA packages are supplied with unattached fan heatsinks.
This section documents motherboard and system requirements for the fan heatsink that is supplied
with the boxed Intel Celeron processor. This section is particularly important for OEMs that
manufacture motherboards for system integrators. Unless otherwise noted, all figures in this
section are dimensioned in inches.
Note:
Drawings in this section reflect only the specifications of the Intel boxed processor product. These
dimensions should not be used as a generic keepout zone for all heatsinks. It is the system
designer’s responsibility to consider their proprietary solution when designing to the required
keepout zone on their system platform and chassis. Refer to the package specific Thermal /
Mechanical Solution Functional Specifications for further guidance. Contact your local Intel Sales
Representative for these documents.
6.1
Mechanical Specifications for the Boxed Intel® Celeron®
Processor
6.1.1
Mechanical Specifications for the S.E.P. Package
This section documents the mechanical specifications of the boxed Celeron processor fan heatsink
in the S.E.P. Package. The boxed processor in the S.E.P. Package ships with an attached fan
heatsink. Figure 31 shows a mechanical representation of the boxed Intel Celeron processor in a
S.E.P. Package in the retention mechanism, which is not shipped with the boxed Intel Celeron
processor.
The space requirements and dimensions for the boxed processor in the S.E.P. Package are shown in
Figure 32 and Figure 33. Also, a conceptual attachment interface to low profile retention
mechanism is shown in Figure 38.
Note:
110
The heatsink airflow keepout zones found in Table 57 and Figure 38 refer specifically to the boxed
processor’s active fan heatsink. This does not reflect the worst-case dimensions that may exist with
other third party passive or active fan heatsinks.
Datasheet
Intel® Celeron® Processor up to 1.10 GHz
Figure 31. Retention Mechanism for the Boxed Intel® Celeron® Processor in the S.E.P.
Package
Figure 32. Side View Space Requirements for the Boxed Processor in the S.E.P.
Package
1.386
(A)
S.E.P.P.
Fan Heatsink
242-Contact Slot Connector
0.576 (B)
Datasheet
111
Intel® Celeron® Processor up to 1.10 GHz
Figure 33. Front View Space Requirements for the Boxed Processor in the S.E.P. Package
5.40 (E)
4.74 (D)
2.02 (C)
Table 57. Boxed Processor Fan Heatsink Spatial Dimensions for the S.E.P. Package
Fig. Ref.
Label
6.1.1.1
Dimensions (Inches)
Min
Typ
Max
A
Fan Heatsink Depth (see Figure 27)
B
Fan Heatsink Height from Motherboard (see Figure 27)
1.40
C
Fan Heatsink Height (see Figure 31)
2.00
D
Fan Heatsink Width (see Figure 31)
4.80
E
Fan Heatsink Base Width (see Figure 31)
F
Airflow Keepout Zones from end of Fan Heatsink
0.4
G
Airflow Keepout Zones from face of Fan Heatsink
0.2
0.58
5.4
Boxed Processor Heatsink Weight
The heatsink for the boxed Intel Celeron processor in the S.E.P. Package will not weigh more than
225 grams.
6.1.1.2
Boxed Processor Retention Mechanism
The boxed Intel Celeron processor requires a S.E.P. Package retention mechanism to secure the
processor in the 242-contact slot connector. A S.E.P. Package retention mechanism are provided
with the boxed processor. Motherboards designed for use by system integrators should include a
retention mechanism and appropriate installation instructions.
The boxed Intel Celeron processor does not require additional fan heatsink supports. Fan heatsink
supports are not shipped with the boxed Intel Celeron processor.
Motherboards designed for flexible use by system integrators must still recognize the boxed
Pentium II processor’s fan heatsink clearance requirements, which are described in the Pentium® II
Processor at 233, 266, 300, and 333 MHz Datasheet (Order Number 243335).
112
Datasheet
Intel® Celeron® Processor up to 1.10 GHz
6.1.2
Mechanical Specifications for the PPGA Package
This section documents the mechanical specifications for the fan heatsink of the boxed Celeron
processor in the PPGA package. The boxed processor in the PPGA package ships with an
unattached fan heatsink which has an integrated clip. Figure 34 shows a mechanical representation
of the boxed Intel Celeron processor in the PPGA package.
Note that the airflow of the fan heatsink is into the center and out of the sides of the fan heatsink.
Clearance is required around the fan heatsink to ensure unimpeded airflow for proper cooling. The
space requirements and dimensions for the boxed processor with an integrated fan heatsink are
shown in Figure 35. All dimensions are in inches.
Note:
The heatsink airflow keepout zones found in Figure 39 refer specifically to the boxed processor’s
active fan heatsink. This does not reflect the worst-case dimensions that may exist with other third
party passive or active fan heatsinks.
Figure 34. Boxed Intel® Celeron® Processor in the PPGA Package
Figure 35. Side View Space Requirements for the Boxed Processor in the PPGA Package
Datasheet
113
Intel® Celeron® Processor up to 1.10 GHz
6.1.2.1
Boxed Processor Heatsink Weight
The heatsink for the boxed Intel Celeron processor in the PPGA package will not weigh more than
180 grams.
6.1.3
Mechanical Specifications for the FC-PGA/FC-PGA2 Packages
This section documents the mechanical specifications of the fan heatsink for the boxed Intel
Celeron processor in the FC-PGA/FC-PGA2 (Flip-Chip Pin Grid Array) packages. The boxed
processor in the FC-PGA/FC-PGA2 packages ships with a fan heatsink which has an integrated
clip. Figure 36 shows a mechanical representation of the boxed Intel Celeron processor in the
FC-PGA/FC-PGA2 packages.
Figure 39 and Figure 41 show the REQUIRED keepout dimensions for the boxed processor
thermal solution. The cooling fin orientation on the heatsink relative to the PGA-370 socket is
subject to change. Contact your local Intel sales representative for documentation specific to the
boxed fan heatsink orientation relative to the PGA-370 socket.
The boxed processor fan heatsink is also asymmetrical in that the mechanical step feature
(specified in Figure 37) must sit over the socket’s cam. The step allows the heatsink to securely
interface with the processor in order to meet the processors thermal requirements.
Figure 36. Conceptual Drawing of the Boxed Intel® Celeron® Processor in the 370-Pin Socket
(FC-PGA/FC-PGA2 Packages)
Figure 37. Dimensions of Mechanical Step Feature in Heatsink Base for the FC-PGA/
FC-PGA2 Packages
0.043
0.472
U nits = inches
114
Datasheet
Intel® Celeron® Processor up to 1.10 GHz
6.1.3.1
Boxed Processor Heatsink Weight
The heatsink for the boxed Intel Celeron processor in the FC-PGA/FC-PGA2 packages will not
weigh more than 180 grams.
6.2
Thermal Specifications
This section describes the cooling requirements of the fan heatsink solution utilized by the boxed
processors.
6.2.1
Thermal Requirements for the Boxed Intel® Celeron® Processor
6.2.1.1
Boxed Processor Cooling Requirements
The boxed processor is directly cooled with a fan heatsink. However, meeting the processor's
temperature specification is also a function of the thermal design of the entire system, and
ultimately the responsibility of the system integrator. The processor temperature specification is
found in Section 4.0 of this document. The boxed processor fan heatsink is able to keep the
processor temperature within the specifications (see Section 4.0) in chassis that provide good
thermal management.
For the boxed processor fan heatsink to operate properly, it is critical that the airflow provided to
the fan heatsink is unimpeded. Airflow of the fan heatsink is into the center and out of the sides of
the fan heatsink. Airspace is required around the fan to ensure that the airflow through the fan
heatsink is not blocked. Blocking the airflow to the fan heatsink reduces the cooling efficiency and
decreases fan life. Figure 38 and Figure 39 illustrate an acceptable airspace clearance for the fan
heatsink. It is also recommended that the air temperature entering the fan be kept below 45 °C.
Again, meeting the processor's temperature specification is the responsibility of the system
integrator. The processor temperature specification is found in Section 4.0 of this document.
Figure 38. Top View Airspace Requirements for the Boxed Processor in the S.E.P. Package
Fan Heatsink
Processor
Airspace
0.20 Min
Air Space
(G)
Measure ambient temperature
0.3" above center of fan inlet
Datasheet
0.40 Min Air Space (F)
(both ends)
115
Intel® Celeron® Processor up to 1.10 GHz
Figure 39. Side View Airspace Requirements for the Boxed Intel® Celeron® Processor in the
FC-PGA/FC-PGA2 and PPGA Packages
Measure ambient temperature 0.3"
above center of fan inlet
0.20 Min
Air Space
0.20 Min
Air Space
Fan Heatsink
Processor
Figure 40. Volumetric Keepout Requirements for The Boxed Fan Heatsink
116
Datasheet
Intel® Celeron® Processor up to 1.10 GHz
6.2.1.2
Boxed Processor Thermal Cooling Solution Clip
The boxed processor thermal solution requires installation by a system integrator to secure the
thermal cooling solution to the processor after it is installed in the 370-pin socket ZIF socket.
Motherboards designed for use by system integrators should take care to consider the implications
of clip installation and potential scraping of the motherboard PCB underneath the 370-pin socket
attach tabs. Motherboard components should not be placed too close to the 370-pin socket attach
tabs in a way that interferes with the installation of the boxed processor thermal cooling solution
(see Figure 41 for specifications).
Figure 41. Clip Keepout Requirements for the 370-Pin (Top View)
6.3
Electrical Requirements for the Boxed Intel® Celeron®
Processor
6.3.1
Electrical Requirements
The boxed processor's fan heatsink requires a +12 V power supply. A fan power cable is shipped
with the boxed processor to draw power from a power header on the motherboard. The power cable
connector and pin-out are shown in Figure 42. Motherboards must provide a matched power header
to support the boxed processor. Table 58 contains specifications for the input and output signals at
the fan heatsink connector. The fan heatsink outputs a SENSE signal (an open-collector output)
that pulses at a rate of two pulses per fan revolution. A motherboard pull-up resistor provides VOH
to match the motherboard-mounted fan speed monitor requirements, if applicable. Use of the
SENSE signal is optional. If the SENSE signal is not used, pin 3 of the connector should be tied to
GND.
Datasheet
117
Intel® Celeron® Processor up to 1.10 GHz
The boxed Intel Celeron processors in the PPGA package at 500 MHz and below are shipped with
an unattached fan heatsink with two wire power-supply cables. These two wire fans do NOT
support the motherboard-mounted fan speed monitor feature. The Intel Celeron processor at
533 MHz and above ship with unattached fan heatsinks that have three power-supply cables. These
three wire fans DO support the motherboard-mounted fan speed monitor feature.
The power header on the baseboard must be positioned to allow the fan heatsink power cable to
reach it. The power header identification and location should be documented in the motherboard
documentation or on the motherboard. Figure 43 shows the recommended location of the fan
power connector relative to the 242-contact slot connector. Figure 44 shows the recommended
location of the fan power connector relative to the 370-pin socket. For the S.E.P. Package, the
motherboard power header should be positioned within 4.75 inches (lateral) of the fan power
connector. The motherboard power header should be positioned within 4.00 inches (lateral) of the
fan power connector for the PPGA and FC-PGA/FC-PGA2 packages.
Figure 42. Boxed Processor Fan Heatsink Power Cable Connector Description
Pin
Signal
1
GND
Straight square pin, 3-pin terminal housing with
polarizing ribs and friction locking ramp.
2
+12V
0.100" pin pitch, 0.025" square pin width.
3
SENSE
Waldom*/Molex* P/N 22-01-3037 or equivalent.
Match with straight pin, friction lock header on motherboard
Waldom/Molex P/N 22-23-2031, AMP* P/N 640456-3,
or equivalent.
1
2
3
Table 58. Fan Heatsink Power and Signal Specifications
Description
+12V: 12 volt fan power supply
Min
Typ
Max
10.2V
12V
13.8V
IC: Fan current draw
SENSE: SENSE frequency (motherboard should pull this
pin up to appropriate Vcc with resistor)
118
100 mA
2 pulses per
fan revolution
Datasheet
Intel® Celeron® Processor up to 1.10 GHz
Figure 43. Motherboard Power Header Placement for the S.E.P. Package
242-Contact Slot Connector
Fan power connector location
(1.56 inches above motherboard
1.428"
1.449"
r = 4.75"
Motherboard fan power header should be
positioned within 4.75 inches of the fan
power connector (lateral distance).
Figure 44. Motherboard Power Header Placement Relative to the 370-pin Socket
R = 4.00"
PGA370
ppga1.vsd
Datasheet
119
Intel® Celeron® Processor up to 1.10 GHz
7.0
Processor Signal Description
Table 59 provides an alphabetical listing of all Celeron processor signals. The tables at the end of
this section summarize the signals by direction (output, input, and I/O).
Note:
Unless otherwise noted, the signals apply to S.E.P., PPGA, and FC-PGA/FC-PGA2 Packages.
Table 59. Alphabetical Signal Reference (Sheet 1 of 7)
Signal
Type
Description
I/O
The A[31:3]# (Address) signals define a 232-byte physical memory address space.
When ADS# is active, these pins transmit the address of a transaction; when ADS#
is inactive, these pins transmit transaction type information. These signals must
connect the appropriate pins of all agents on the Intel® Celeron® processor system
bus. The A[31:24]# signals are parity-protected by the AP1# parity signal, and the
A[23:3]# signals are parity-protected by the AP0# parity signal.
On the active-to-inactive transition of RESET#, the processors sample the A[31:3]#
pins to determine their power-on configuration. See the Pentium® II Processor
Developer’s Manual (Order Number 243502) for details.
I
If the A20M# (Address-20 Mask) input signal is asserted, the Intel Celeron
processor masks physical address bit 20 (A20#) before looking up a line in any
internal cache and before driving a read/write transaction on the bus. Asserting
A20M# emulates the 8086 processor's address wrap-around at the 1 MB boundary.
Assertion of A20M# is only supported in real mode.
A20M# is an asynchronous signal. However, to ensure recognition of this signal
following an I/O write instruction, it must be valid along with the TRDY# assertion of
the corresponding I/O Write bus transaction.
I/O
The ADS# (Address Strobe) signal is asserted to indicate the validity of the
transaction address on the A[31:3]# pins. All bus agents observe the ADS#
activation to begin parity checking, protocol checking, address decode, internal
snoop, or deferred reply ID match operations associated with the new transaction.
This signal must connect the appropriate pins on all Intel Celeron processor system
bus agents.
I
The BCLK (Bus Clock) signal determines the bus frequency. All Intel Celeron
processor system bus agents must receive this signal to drive their outputs and latch
their inputs on the BCLK rising edge.
All external timing parameters are specified with respect to the BCLK signal.
BNR#
I/O
The BNR# (Block Next Request) signal is used to assert a bus stall by any bus
agent who is unable to accept new bus transactions. During a bus stall, the current
bus owner cannot issue any new transactions.
Since multiple agents might need to request a bus stall at the same time, BNR# is a
wire-OR signal which must connect the appropriate pins of all Intel Celeron
processor system bus agents. In order to avoid wire-OR glitches associated with
simultaneous edge transitions driven by multiple drivers, BNR# is activated on
specific clock edges and sampled on specific clock edges.
BP[3:2]#
I/O
The BP[3:2]# (Breakpoint) signals are outputs from the processor that indicate the
status of breakpoints.
I/O
The BPM[1:0]# (Breakpoint Monitor) signals are breakpoint and performance
monitor signals. They are outputs from the processor which indicate the status of
breakpoints and programmable counters used for monitoring processor
performance.
A[31:3]#
A20M#
ADS#
BCLK
BPM[1:0]#
120
Datasheet
Intel® Celeron® Processor up to 1.10 GHz
Table 59. Alphabetical Signal Reference (Sheet 2 of 7)
Signal
BPRI#
BSEL[1:0]
BR0#
Type
Description
I
The BPRI# (Bus Priority Request) signal is used to arbitrate for ownership of the
Intel Celeron processor system bus. It must connect the appropriate pins of all Intel
Celeron processor system bus agents. Observing BPRI# active (as asserted by the
priority agent) causes all other agents to stop issuing new requests, unless such
requests are part of an ongoing locked operation. The priority agent keeps BPRI#
asserted until all of its requests are completed, then releases the bus by deasserting
BPRI#.
I/O
These signals are used to select the system bus frequency. The frequency is
determined by the processor(s), chipset, and frequency synthesizer capabilities. All
system bus agents must operate at the same frequency. Individual processors will
only operate at their specified front side bus (FSB) frequency. On motherboards
which support operation at either 66 MHz or 100 MHz, a BSEL[1:0] = “x1” will select
a 100 MHz system bus frequency and a BSEL[1:0] = “x0” will select a 66 MHz
system bus frequency.
These signals must be pulled up to 2.5 V or 3.3 V with 1 KΩ resistor and provided as
a frequency selection signal to the clock driver/synthesizer. See Section 2.7.2 for
implementation examples.
note: BSEL1 is not used by the Celeron processor.
I/O
The BR0# (Bus Request) pin drives the BREQ[0]# signal in the system. During
power-up configuration, the central agent asserts the BREQ0# bus signal in the
system to assign the symmetric agent ID to the processor. The processor samples
it’s BR0# pin on the active-to-inactive transition of RESET# to obtain it’s symmetric
agent ID. The processor asserts BR0# to request the system bus.
The CPUPRES# signal provides the ability for a system board to detect the
presence of a processor. This pin is a ground on the processor indicating to the
system that a processor is installed.
Combined with the VID combination of VID[3:0]= 1111 (see Section 2.5), a system
can determine if a socket is occupied, and whether a processor core is present. See
the table below for states and values for determining the presence of a device.
CPUPRES#
(PPGA,
FC-PGA/
FC-PGA2 only)
Datasheet
PGA370 Socket Occupation Truth Table
O
Signal
Value
Status
CPUPRES#
VID[3:0]
0
Anything other
than ‘1111’
Processor core installed in the PGA370
socket.
CPUPRES#
VID[3:0]
1
Any value
PGA370 socket not occupied.
D[63:0]#
I/O
The D[63:0]# (Data) signals are the data signals. These signals provide a 64-bit data
path between the Intel Celeron processor system bus agents, and must connect the
appropriate pins on all such agents. The data driver asserts DRDY# to indicate a
valid data transfer.
DBSY#
I/O
The DBSY# (Data Bus Busy) signal is asserted by the agent responsible for driving
data on the Intel Celeron processor system bus to indicate that the data bus is in
use. The data bus is released after DBSY# is deasserted. This signal must connect
the appropriate pins on all Intel Celeron processor system bus agents.
DEFER#
I
The DEFER# signal is asserted by an agent to indicate that a transaction cannot be
guaranteed in-order completion. Assertion of DEFER# is normally the responsibility
of the addressed memory or I/O agent. This signal must connect the appropriate
pins of all Intel Celeron processor system bus agents.
DRDY#
I/O
The DRDY# (Data Ready) signal is asserted by the data driver on each data
transfer, indicating valid data on the data bus. In a multicycle data transfer, DRDY#
may be deasserted to insert idle clocks. This signal must connect the appropriate
pins of all Intel Celeron processor system bus agents.
121
Intel® Celeron® Processor up to 1.10 GHz
Table 59. Alphabetical Signal Reference (Sheet 3 of 7)
Signal
Description
I
The EDGCTRL input provides AGTL+ edge control and should be pulled up to
VCCCORE with a 51 Ω ± 5% resistor.
NOTE: This signal is NOT used on the FC-PGA/FC-PGA2 packages.
EMI
(S.E.P.P. only)
I
EMI pins should be connected to motherboard ground and/or to chassis ground
through zero ohm (0 Ω) resistors. The zero ohm resistors should be placed in close
proximity to the Intel Celeron processor connector. The path to chassis ground
should be short in length and have a low impedance. These pins are used for EMI
management purposes.
FERR#
O
The FERR# (Floating-point Error) signal is asserted when the processor detects an
unmasked floating-point error. FERR# is similar to the ERROR# signal on the
Intel 387 coprocessor, and is included for compatibility with systems using MSDOS*-type floating-point error reporting.
I
When the FLUSH# input signal is asserted, the processor writes back all data in the
Modified state from the internal cache and invalidates all internal cache lines. At the
completion of this operation, the processor issues a Flush Acknowledge transaction.
The processor does not cache any new data while the FLUSH# signal remains
asserted.
FLUSH# is an asynchronous signal. However, to ensure recognition of this signal
following an I/O write instruction, it must be valid along with the TRDY# assertion of
the corresponding I/O Write bus transaction.
On the active-to-inactive transition of RESET#, the processor samples FLUSH# to
determine its power-on configuration. See Pentium® Pro Family Developer’s
Manual, Volume 1: Specifications (Order Number 242690) for details.
EDGCTRL
FLUSH#
HIT#, HITM#
IERR#
IGNNE#
INIT#
122
Type
I/O
The HIT# (Snoop Hit) and HITM# (Hit Modified) signals convey transaction snoop
operation results, and must connect the appropriate pins of all Intel Celeron
processor system bus agents. Any such agent may assert both HIT# and HITM#
together to indicate that it requires a snoop stall, which can be continued by
reasserting HIT# and HITM# together.
O
The IERR# (Internal Error) signal is asserted by a processor as the result of an
internal error. Assertion of IERR# is usually accompanied by a SHUTDOWN
transaction on the Intel Celeron processor system bus. This transaction may
optionally be converted to an external error signal (e.g., NMI) by system core logic.
The processor will keep IERR# asserted until the assertion of RESET#, BINIT#, or
INIT#.
I
The IGNNE# (Ignore Numeric Error) signal is asserted to force the processor to
ignore a numeric error and continue to execute noncontrol floating-point instructions.
If IGNNE# is deasserted, the processor generates an exception on a noncontrol
floating-point instruction if a previous floating-point instruction caused an error.
IGNNE# has no effect when the NE bit in control register 0 is set.
IGNNE# is an asynchronous signal. However, to ensure recognition of this signal
following an I/O write instruction, it must be valid along with the TRDY# assertion of
the corresponding I/O Write bus transaction.
I
The INIT# (Initialization) signal, when asserted, resets integer registers inside all
processors without affecting their internal (L1) caches or floating-point registers.
Each processor then begins execution at the power-on Reset vector configured
during power-on configuration. The processor continues to handle snoop requests
during INIT# assertion. INIT# is an asynchronous signal and must connect the
appropriate pins of all bus agents.
If INIT# is sampled active on the active to inactive transition of RESET#, then the
processor executes its Built-in Self-Test (BIST).
Datasheet
Intel® Celeron® Processor up to 1.10 GHz
Table 59. Alphabetical Signal Reference (Sheet 4 of 7)
Signal
Type
Description
I
The LINT[1:0] (Local APIC Interrupt) signals must connect the appropriate pins of all
APIC Bus agents, including all processors and the core logic or I/O APIC
component. When the APIC is disabled, the LINT0 signal becomes INTR, a
maskable interrupt request signal, and LINT1 becomes NMI, a nonmaskable
interrupt. INTR and NMI are backward compatible with the signals of those names
on the Pentium® processor. Both signals are asynchronous.
Both of these signals must be software configured via BIOS programming of the
APIC register space to be used either as NMI/INTR or LINT[1:0]. Because the APIC
is enabled by default after Reset, operation of these pins as LINT[1:0] is the default
configuration.
LOCK#
I/O
The LOCK# signal indicates to the system that a transaction must occur atomically.
This signal must connect the appropriate pins of all system bus agents. For a locked
sequence of transactions, LOCK# is asserted from the beginning of the first
transaction end of the last transaction.
When the priority agent asserts BPRI# to arbitrate for ownership of the system bus,
it will wait until it observes LOCK# deasserted. This enables symmetric agents to
retain ownership of the system bus throughout the bus locked operation and ensure
the atomicity of lock.
PICCLK
I
The PICCLK (APIC Clock) signal is an input clock to the processor and core logic or
I/O APIC which is required for operation of all processors, core logic, and I/O APIC
components on the APIC bus.
I/O
The PICD[1:0] (APIC Data) signals are used for bidirectional serial message passing
on the APIC bus, and must connect the appropriate pins of the Intel Celeron
processor for proper initialization.
PLL1, PLL2
(PGA packages
only)
I
All Intel Celeron processors have internal analog PLL clock generators that require
quiet power supplies. PLL1 and PLL2 are inputs to the internal PLL and should be
connected to VCCCORE through a low-pass filter that minimizes jitter. See the
platform design guide for implementation details.
PRDY#
O
The PRDY (Probe Ready) signal is a processor output used by debug tools to
determine processor debug readiness.
PREQ#
I
The PREQ# (Probe Request) signal is used by debug tools to request debug
operation of the processors.
LINT[1:0]
PICD[1:0]
PWRGOOD
I
The PWRGOOD (Power Good) signal is a 2.5 V tolerant processor input. The
processor requires this signal to be a clean indication that the clocks and power
supplies (VCCCORE, etc.) are stable and within their specifications. Clean implies
that the signal will remain low (capable of sinking leakage current), without glitches,
from the time that the power supplies are turned on until they come within
specification. The signal must then transition monotonically to a high (2.5 V) state.
Figure 43 illustrates the relationship of PWRGOOD to other system signals.
PWRGOOD can be driven inactive at any time, but clocks and power must again be
stable before a subsequent rising edge of PWRGOOD. It must also meet the
minimum pulse width specification in Table 17 and Table 18, and be followed by a
1 ms RESET# pulse.
The PWRGOOD signal must be supplied to the processor; it is used to protect
internal circuits against voltage sequencing issues. It should be driven high
throughout boundary scan operation.
PWRGOOD Relationship at Power-On
BCLK
VCCCORE,
VREF
PWRGOOD
1 ms
RESET#
Datasheet
123
Intel® Celeron® Processor up to 1.10 GHz
Table 59. Alphabetical Signal Reference (Sheet 5 of 7)
Signal
Type
Description
I/O
The REQ[4:0]# (Request Command) signals must connect the appropriate pins of
all processor system bus agents. They are asserted by the current bus owner over
two clock cycles to define the currently active transaction type.
RESET#
I
Asserting the RESET# signal resets the processor to a known state and invalidates
the L1 cache without writing back any of the contents. RESET# must stay active for
at least one millisecond after VCCCORE and CLK have reached their proper
specifications. On observing active RESET#, all system bus agents will deassert
their outputs within two clocks.
A number of bus signals are sampled at the active-to-inactive transition of RESET#
for power-on configuration. These configuration options are described in the
Pentium® Pro Family Developer’s Manual, Volume 1: Specifications (Order Number
242690).
The processor may have its outputs tristated via power-on configuration. Otherwise,
if INIT# is sampled active during the active-to-inactive transition of RESET#, the
processor will execute its Built-in Self-Test (BIST). Whether or not BIST is executed,
the processor will begin program execution at the power on Reset vector (default
0_FFFF_FFF0h). RESET# must connect the appropriate pins of all processor
system bus agents.
RS[2:0]#
I
The RS[2:0]# (Response Status) signals are driven by the response agent (the
agent responsible for completion of the current transaction), and must connect the
appropriate pins of all processor system bus agents.
RTTCTRL
I
The RTTCTRL input signal provides AGTL+ termination control. The Celeron
FC-PGA/FC-PGA2 processor samples this input to sense the presence of
motherboard AGTL+ termination. See the platform design guide for implementation
details.
SLEWCTRL
I
The SLEWCTRL input signal provides AGTL+ slew rate control. The Celeron
FC-PGA/FC-PGA2 processor samples this input to determine the slew rate for
AGTL+ signals when it is the driving agent. See the platform design guide for
implementation details.
REQ[4:0]#
SLOTOCC# is defined to allow a system design to detect the presence of a
terminator card or processor in a SC242 connector. This pin is not a signal; rather, it
is a short to VSS. Combined with the VID combination of VID[4:0]= 11111 (see
Section 2.5), a system can determine if a SC242 connector is occupied, and
whether a processor core is present. The states and values for determining the type
of cartridge in the SC242 connector is shown below.
SC242 Occupation Truth Table
SLOTOCC#
(S.E.P.P. only)
SLP#
124
O
I
Signal
Value
Status
SLOTOCC#
VID[4:0]
0
Anything other than ‘11111’
Processor with core in SC242
connector.
SLOTOCC#
VID[4:0]
0
11111
Terminator cartridge in SC242
connector (i.e., no core present).
SLOTOCC#
VID[4:0]
1
Any value
SC242 connector not occupied.
The SLP# (Sleep) signal, when asserted in Stop-Grant state, causes processors to
enter the Sleep state. During Sleep state, the processor stops providing internal
clock signals to all units, leaving only the Phase-Locked Loop (PLL) still operating.
Processors in this state will not recognize snoops or interrupts. The processor will
recognize only assertions of the SLP#, STPCLK#, and RESET# signals while in
Sleep state. If SLP# is deasserted, the processor exits Sleep state and returns to
Stop-Grant state, restarting its internal clock signals to the bus and APIC processor
core units.
Datasheet
Intel® Celeron® Processor up to 1.10 GHz
Table 59. Alphabetical Signal Reference (Sheet 6 of 7)
Signal
Description
I
The SMI# (System Management Interrupt) signal is asserted asynchronously by
system logic. On accepting a System Management Interrupt, processors save the
current state and enter System Management Mode (SMM). An SMI Acknowledge
transaction is issued, and the processor begins program execution from the SMM
handler.
STPCLK#
I
The STPCLK# (Stop Clock) signal, when asserted, causes processors to enter a low
power Stop-Grant state. The processor issues a Stop-Grant Acknowledge
transaction, and stops providing internal clock signals to all processor core units
except the bus and APIC units. The processor continues to snoop bus transactions
and may latch interrupts while in Stop-Grant state. When STPCLK# is deasserted,
the processor restarts its internal clock to all units, resumes execution, and services
any pending interrupt. The assertion of STPCLK# has no effect on the bus clock;
STPCLK# is an asynchronous input.
TCK
I
The TCK (Test Clock) signal provides the clock input for the Intel Celeron processor
Test Access Port.
TDI
I
The TDI (Test Data In) signal transfers serial test data into the processor. TDI
provides the serial input needed for JTAG specification support.
TDO
O
The TDO (Test Data Out) signal transfers serial test data out of the processor. TDO
provides the serial output needed for JTAG specification support.
TESTHI
(S.E.P.P. only)
I
Refer to Section 2.6 for implementation details.
THERMDN
O
Thermal Diode p-n junction. Used to calculate core temperature. See Section 4.1.
THERMDP
I
Thermal Diode p-n junction. Used to calculate core temperature. See Section 4.1.
THERMTRIP#
O
The processor protects itself from catastrophic overheating by use of an internal
thermal sensor. This sensor is set well above the normal operating temperature to
ensure that there are no false trips. The processor will stop all execution when the
junction temperature exceeds approximately 135 °C. This is signaled to the system
by the THERMTRIP# (Thermal Trip) pin. Once activated, the signal remains latched,
and the processor stopped, until RESET# goes active. There is no hysteresis built
into the thermal sensor itself; as long as the die temperature drops below the trip
level, a RESET# pulse will reset the processor and execution will continue. If the
temperature has not dropped below the trip level, the processor will reassert
THERMTRIP# and remain stopped. The system designer should not act upon
THERMTRIP# until after the RESET# input is deasserted. Until this time, the
THERMTRIP# is indeterminate.
TMS
I
The TMS (Test Mode Select) signal is a JTAG specification support signal used by
debug tools.
TRDY#
I
The TRDY# (Target Ready) signal is asserted by the target to indicate that it is ready
to receive a write or implicit writeback data transfer. TRDY# must connect the
appropriate pins of all system bus agents.
TRST#
I
The TRST# (Test Reset) signal resets the Test Access Port (TAP) logic. Intel
Celeron processors require this signal to be driven low during power on Reset. A
680 ohm resistor is the suggested value for a pull down resistor on TRST#.
VCC1.5
(PGA packages
only)
I
The VCCCMOS pin provides the CMOS voltage for use by the platform. The 2.5 V
must be provided to the VCC2.5 input and 1.5 V must be provided to the VCC1.5 input.
The processor re-routes the 1.5 V input to the VCCCMOS output via the package. The
supply for VCC1.5 must be the same one used to supply VTT.
VCC2.5
(PGA packages
only)
I
The VCCCMOS pin provides the CMOS voltage for use by the platform. The 2.5 V
must be provided to the VCC2.5 input and 1.5 V must be provided to the VCC1.5 input.
The processor re-routes the 2.5 V input to the VCCCMOS output via the package.
VCCCMOS
(PGA packages
only)
O
The VCCCMOS pin provides the CMOS voltage for use by the platform. The 2.5 V
must be provided to the VCC2.5 input and 1.5 V must be provided to the VCC1.5 input.
SMI#
Datasheet
Type
125
Intel® Celeron® Processor up to 1.10 GHz
Table 59. Alphabetical Signal Reference (Sheet 7 of 7)
Signal
Type
Description
VCOREDET
(PGA packages
only)
O
The VCOREDET signal will float for 2.0 V core processors and will be grounded for the
Celeron® FC-PGA/FC-PGA2 processor with a 1.5V core voltage.
O
The VID (Voltage ID) pins can be used to support automatic selection of power
supply voltages. These pins are not signals, but are either an open circuit or a short
circuit to VSS on the processor. The combination of opens and shorts defines the
voltage required by the processor. The VID pins are needed to cleanly support
voltage specification variations on Intel Celeron processors. See Table 2 for
definitions of these pins. The power supply must supply the voltage that is requested
by these pins, or disable itself.
I
These input signals are used by the AGTL+ inputs as a reference voltage. AGTL+
inputs are differential receivers and will use this voltage to determine whether the
signal is a logic high or logic low.
For the FC-PGA/FC-PGA2 packages, VREF is typically 2/3 of VTT
VID[4:0]
(S.E.P.P.)
VID[3:0]
(PGA packages
only)
VREF[7:0]
(PGA packages
only)
7.1
Signal Summaries
Table 60 through Table 63 list attributes of the Celeron processor output, input, and I/O signals.
Table 60. Output Signals
126
Name
Active Level
Clock
Signal Group
CPUPRES# (PGA
packages only)
Low
Asynch
Power/Other
FERR#
Low
Asynch
CMOS Output
IERR#
Low
Asynch
CMOS Output
PRDY#
Low
BCLK
AGTL+ Output
SLOTOCC#
(S.E.P.P. only)
Low
Asynch
Power/Other
TDO
High
TCK
TAP Output
THERMDN
N/A
Asynch
Power/Other
THERMTRIP#
Low
Asynch
CMOS Output
VCOREDET
(PGA packages only)
High
Asynch
Power/Other
VID[4:0] (S.E.P.P.)
VID[3:0] (PGA
packages)
High
Asynch
Power/Other
Datasheet
Intel® Celeron® Processor up to 1.10 GHz
Table 61. Input Signals
Name
A20M#
Active Level
Clock
Signal Group
Qualified
CMOS Input
Always
AGTL+ Input
Always
System Bus Clock
Always
1
Low
Asynch
BPRI#
Low
BCLK
BCLK
High
—
DEFER#
Low
BCLK
AGTL+ Input
Always
FLUSH#
Low
Asynch
CMOS Input
Always 1
IGNNE#
Low
Asynch
CMOS Input
Always 1
INIT#
Low
Asynch
CMOS Input
Always 1
INTR
High
Asynch
CMOS Input
APIC disabled mode
LINT[1:0]
High
Asynch
CMOS Input
APIC enabled mode
NMI
High
Asynch
CMOS Input
APIC disabled mode
PICCLK
High
—
APIC Clock
Always
PREQ#
Low
Asynch
CMOS Input
Always
PWRGOOD
High
Asynch
CMOS Input
Always
RESET#
Low
BCLK
AGTL+ Input
Always
RS[2:0]#
Low
BCLK
AGTL+ Input
Always
RTTCTRL
N/A
Asynch
Power/Other
SLEWCTRL
N/A
Asynch
Power/Other
SLP#
Low
Asynch
CMOS Input
SMI#
Low
Asynch
CMOS Input
STPCLK#
Low
Asynch
TCK
High
—
TAP Input
TAP Input
During Stop-Grant state
CMOS Input
TDI
High
TCK
TESTHI
(S.E.P.P.
only)
High
Asynch
Power/Other
THERMDP
N/A
Asynch
Power/Other
TMS
High
TCK
TAP Input
TRST#
Low
Asynch
TAP Input
TRDY#
Low
BCLK
Always
AGTL+ Input
NOTE:
1. Synchronous assertion with active TRDY# ensures synchronization.
Datasheet
127
Intel® Celeron® Processor up to 1.10 GHz
Table 62. Input/Output Signals (Single Driver)
Name
Active Level
Clock
BSEL[1:0]
Low
Asynch
Signal Group
Power/Other
Qualified
Always
BP[3:2]
Low
BCLK
AGTL+ I/O
Always
BR0#
Low
BCLK
AGTL+I/O
Always
A[31:3]#
Low
BCLK
AGTL+ I/O
ADS#, ADS#+1
ADS#
Low
BCLK
AGTL+ I/O
Always
BPM[1:0]#
Low
BCLK
AGTL+ I/O
Always
D[63:0]#
Low
BCLK
AGTL+ I/O
DRDY#
DBSY#
Low
BCLK
AGTL+ I/O
Always
DRDY#
Low
BCLK
AGTL+ I/O
Always
LOCK#
Low
BCLK
AGTL+ I/O
Always
REQ[4:0]#
Low
BCLK
AGTL+ I/O
ADS#, ADS#+1
Table 63. Input/Output Signals (Multiple Driver)
Name
128
Active Level
Clock
Signal Group
Qualified
BNR#
Low
BCLK
AGTL+ I/O
Always
HIT#
Low
BCLK
AGTL+ I/O
Always
AGTL+ I/O
Always
APIC I/O
Always
HITM#
Low
BCLK
PICD[1:0]
High
PICCLK
Datasheet