OPA171 OPA2171 OPA4171 www.ti.com SBOS516B – SEPTEMBER 2010 – REVISED NOVEMBER 2010 36V, Single-Supply, SOT553, General-Purpose OPERATIONAL AMPLIFIERS Check for Samples: OPA171, OPA2171, OPA4171 FEATURES DESCRIPTION • • • • • • • • • • • • The OPA171, OPA2171 and OPA4171 (OPAx171) are a family of 36V, single-supply, low-noise operational amplifiers with the ability to operate on supplies ranging from +2.7V (±1.35V) to +36V (±18V). These devices are available in micro-packages and offer low offset, drift, and bandwidth with low quiescent current. The single, dual, and quad versions all have identical specifications for maximum design flexibility. 1 2 • Supply Range: +2.7V to +36V, ±1.35V to ±18V Low Noise: 14nV/√Hz Low Offset Drift: ±0.3µV/°C (typ) RFI Filtered Inputs Input Range Includes the Negative Supply Input Range Operates to Positive Supply Rail-to-Rail Output Gain Bandwidth: 3MHz Low Quiescent Current: 475µA per Amplifier High Common-Mode Rejection: 120dB (typ) Low Input Bias Current: 8pA Industry-Standard Packages: – 8-Pin SOIC – 14-Pin TSSOP microPackages: – Single in SOT553 – Dual in VSSOP-8 APPLICATIONS • • • • • • • • • Tracking Amplifier in Power Modules Merchant Power Supplies Transducer Amplifiers Bridge Amplifiers Temperature Measurements Strain Gauge Amplifiers Precision Integrators Battery-Powered Instruments Test Equipment Unlike most op amps, which are specified at only one supply voltage, the OPAx171 family is specified from +2.7V to +36V. Input signals beyond the supply rails do not cause phase reversal. The OPAx171 family is stable with capacitive loads up to 300pF. The input can operate 100mV below the negative rail and within 2V of the top rail during normal operation. Note that these devices can operate with full rail-to-rail input 100mV beyond the top rail, but with reduced performance within 2V of the top rail. The OPAx171 series of op amps are specified from –40°C to +125°C. Package Footprint Comparison (to Scale) Product Family DEVICE PACKAGE OPA171 SOT553, SOT23-5, SO-8 OPA2171 (dual) VSSOP-8, SO-8 OPA4171 (quad) TSSOP-14, SO-14 Package Height Comparison (to Scale) D (SO-8) DBV (SOT23-5) DRL (SOT553) Smallest Packaging for 36V Op Amps 1 2 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. All trademarks are the property of their respective owners. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2010, Texas Instruments Incorporated OPA171 OPA2171 OPA4171 SBOS516B – SEPTEMBER 2010 – REVISED NOVEMBER 2010 www.ti.com This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. PACKAGE/ORDERING INFORMATION (1) PRODUCT PACKAGE-LEAD PACKAGE DESIGNATOR PACKAGE MARKING SOT553 DRL DAP OPA171 SOT23-5 DBV OSUI SO-8 D O171A VSSOP-8 DCU OPOC SO-8 D 2171A SO-14 D OPA4171A OPA2171 OPA4171 TSSOP-14 (1) PW OPA4171A ORDERING NUMBER TRANSPORT MEDIA, QUANTITY OPA171AIDRLT Tape and Reel, 250 OPA171AIDRLR Tape and Reel, 4000 OPA171AIDBVT Tape and Reel, 250 OPA171AIDBVR Tape and Reel, 3000 OPA171AID Rail, 75 OPA171AIDR Tape and Reel, 2500 OPA2171AIDCUT Tape and Reel, 250 OPA2171AIDCUR Tape and Reel, 3000 OPA2171AID Rail, 75 OPA2171AIDR Tape and Reel, 2500 OPA42171AID Rail, 50 OPA42171AIDR Tape and Reel, 2500 OPA42171AIPW Rail, 90 OPA42171AIPWR Tape and Reel, 2000 For the most current package and ordering information, see the Package Option Addendum at the end of this document, or visit the device product folder at www.ti.com. ABSOLUTE MAXIMUM RATINGS (1) Over operating free-air temperature range, unless otherwise noted. Supply voltage Signal input terminals OPAx171 UNIT ±20 V Voltage (V–) – 0.5 to (V+) + 0.5 V Current ±10 mA Output short circuit (2) Continuous Operating temperature –55 to +150 °C Storage temperature –65 to +150 °C Junction temperature +150 °C 4 kV 750 V ESD ratings: (1) (2) 2 Human body model (HBM) Charged device model (CDM) Stresses above these ratings may cause permanent damage. Exposure to absolute maximum conditions for extended periods may degrade device reliability. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those specified is not implied. Short-circuit to ground, one amplifier per package. Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s): OPA171 OPA2171 OPA4171 OPA171 OPA2171 OPA4171 www.ti.com SBOS516B – SEPTEMBER 2010 – REVISED NOVEMBER 2010 THERMAL INFORMATION THERMAL METRIC (1) OPA171AID OPA171AIDBV OPA171AIDBV (IC # 5240) OPA171AIDRL D DBV DBV (SOT23) DRL 8 PINS 5 PINS 5 PINS 5 PINS qJA Junction-to-ambient thermal resistance 149.5 245.8 277.3 208.1 qJC(top) Junction-to-case(top) thermal resistance 97.9 133.9 193.3 0.1 qJB Junction-to-board thermal resistance 87.7 83.6 121.2 42.4 yJT Junction-to-top characterization parameter 35.5 18.2 51.8 0.5 yJB Junction-to-board characterization parameter 89.5 83.1 109.5 42.2 qJC(bottom) Junction-to-case(bottom) thermal resistance n/a n/a n/a n/a (1) UNITS °C/W For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953. THERMAL INFORMATION THERMAL METRIC OPA2171AIDCU (IC # 5241) OPA2171AID OPA4171AID OPA4171AIPW DCU (VSSOP) D D PW (1) 8 PINS 8 PINS 14 PINS 14 PINS qJA Junction-to-ambient thermal resistance 175.2 134.3 93.2 106.9 qJC(top) Junction-to-case(top) thermal resistance 74.9 72.1 51.8 24.4 qJB Junction-to-board thermal resistance 22.2 60.6 49.4 59.3 yJT Junction-to-top characterization parameter 1.6 18.2 13.5 0.6 yJB Junction-to-board characterization parameter 22.8 53.8 42.2 54.3 qJC(bottom) Junction-to-case(bottom) thermal resistance n/a n/a n/a n/a (1) UNITS °C/W For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953. Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s): OPA171 OPA2171 OPA4171 Submit Documentation Feedback 3 OPA171 OPA2171 OPA4171 SBOS516B – SEPTEMBER 2010 – REVISED NOVEMBER 2010 www.ti.com ELECTRICAL CHARACTERISTICS Boldface limits apply over the specified temperature range, TA = –40°C to +125°C. At TA = +25°C, VS = +2.7V to +36V, VCM = VOUT = VS/2, and RLOAD = 10kΩ connected to VS/2, unless otherwise noted. OPA171, OPA2171, OPA4171 PARAMETER TEST CONDITIONS MIN TYP MAX UNIT 0.25 ±1.8 mV 0.3 ±2 mV OFFSET VOLTAGE Input offset voltage VOS Over temperature Drift dVOS/dT vs power supply PSRR Channel separation, dc 0.3 ±2 µV/°C VS = +4V to +36V 1 ±3 µV/V dc 5 µV/V INPUT BIAS CURRENT Input bias current IB ±8 Over temperature Input offset current IOS ±15 pA ±3.5 nA ±3.5 nA ±4 pA Over temperature NOISE Input voltage noise Input voltage noise density en f = 0.1Hz to 10Hz 3 µVPP f = 100Hz 25 nV/√Hz f = 1kHz 14 nV/√Hz INPUT VOLTAGE Common-mode voltage range (1) Common-mode rejection ratio VCM CMRR (V–) – 0.1V (V+) – 2V V VS = ±2V, (V–) – 0.1V < VCM < (V+) – 2V 90 104 dB VS = ±18V, (V–) – 0.1V < VCM < (V+) – 2V 104 120 dB INPUT IMPEDANCE Differential Common-mode 100 || 3 MΩ || pF 6 || 3 1012Ω || pF 130 dB 3.0 MHz 1.5 V/µs OPEN-LOOP GAIN Open-loop voltage gain AOL VS = +4V to +36V, (V–) + 0.35V < VO < (V+) – 0.35V 110 FREQUENCY RESPONSE Gain bandwidth product Slew rate Settling time GBP SR tS Overload recovery time Total harmonic distortion + noise G = +1 To 0.1%, VS = ±18V, G = +1, 10V step 6 µs To 0.01% (12 bit), VS = ±18V, G = +1, 10V step 10 µs 2 µs 0.0002 % VIN × Gain > VS THD+N G = +1, f = 1kHz, VO = 3VRMS OUTPUT Voltage output swing from rail VO Short-circuit current ISC Capacitive load drive Open-loop output resistance RL = 10kΩ, AOL ≥ 110dB (V–) + 0.35 CLOAD RO (V+) – 0.35 +25/–35 See Typical Characteristics f = 1MHz, IO = 0A V mA pF Ω 150 POWER SUPPLY Specified voltage range VS Quiescent current per amplifier IQ Over temperature +2.7 IO = 0A 475 IO = 0A +36 V 595 µA 650 µA TEMPERATURE Specified range –40 +125 °C Operating range –55 +150 °C (1) 4 The input range can be extended beyond (V+) – 2V up to V+. See the Typical Characteristics and Application Information sections for additional information. Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s): OPA171 OPA2171 OPA4171 OPA171 OPA2171 OPA4171 www.ti.com SBOS516B – SEPTEMBER 2010 – REVISED NOVEMBER 2010 PIN CONFIGURATIONS DRL PACKAGE: OPA171 SOT-553 (TOP VIEW) IN+ 1 V- 2 IN- 3 D AND DCU PACKAGES: OPA2171 SO-8 AND VSSOP-8 (TOP VIEW) 5 V+ 4 OUT DBV PACKAGE: OPA171 SOT23-5 (TOP VIEW) OUT 1 V- 2 +IN 3 5 V+ 4 -IN 1 8 V+ -IN A 2 7 OUT B +IN A 3 6 -IN B V- 4 5 +IN B D AND PW PACKAGES: OPA4171 SO-14 AND TSSOP-14 (TOP VIEW) D PACKAGE: OPA171 SO-8 (TOP VIEW) (1) OUT A NC(1) 1 8 NC(1) -IN 2 7 V+ +IN 3 6 OUT V- 4 5 NC(1) OUT A 1 14 OUT D -IN A 2 13 -IN D +IN A 3 12 +IN D V+ 4 11 V- +IN B 5 10 +IN C -IN B 6 9 -IN C OUT B 7 8 OUT C No internal connection. Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s): OPA171 OPA2171 OPA4171 Submit Documentation Feedback 5 OPA171 OPA2171 OPA4171 SBOS516B – SEPTEMBER 2010 – REVISED NOVEMBER 2010 www.ti.com TYPICAL CHARACTERISTICS TABLE OF GRAPHS Table 1. Characteristic Performance Measurements 6 DESCRIPTION FIGURE Offset Voltage Production Distribution Figure 1 Offset Voltage Drift Distribution Figure 2 Offset Voltage vs Temperature Figure 3 Offset Voltage vs Common-Mode Voltage Figure 4 Offset Voltage vs Common-Mode Voltage (Upper Stage) Figure 5 Offset Voltage vs Power Supply Figure 6 IB and IOS vs Common-Mode Voltage Figure 7 Input Bias Current vs Temperature Figure 8 Output Voltage Swing vs Output Current (Maximum Supply) Figure 9 CMRR and PSRR vs Frequency (Referred-to Input) Figure 10 CMRR vs Temperature Figure 11 PSRR vs Temperature Figure 12 0.1Hz to 10Hz Noise Figure 13 Input Voltage Noise Spectral Density vs Frequency Figure 14 THD+N Ratio vs Frequency Figure 15 THD+N vs Output Amplitude Figure 16 Quiescent Current vs Temperature Figure 17 Quiescent Current vs Supply Voltage Figure 18 Open-Loop Gain and Phase vs Frequency Figure 19 Closed-Loop Gain vs Frequency Figure 20 Open-Loop Gain vs Temperature Figure 21 Open-Loop Output Impedance vs Frequency Figure 22 Small-Signal Overshoot vs Capacitive Load (100mV Output Step) Figure 23, Figure 24 No Phase Reversal Figure 25 Positive Overload Recovery Figure 26 Negative Overload Recovery Figure 27 Small-Signal Step Response (100mV) Figure 28, Figure 29 Large-Signal Step Response Figure 30, Figure 31 Large-Signal Settling Time (10V Positive Step) Figure 32 Large-Signal Settling Time (10V Negative Step) Figure 33 Short-Circuit Current vs Temperature Figure 34 Maximum Output Voltage vs Frequency Figure 35 Channel Separation vs Frequency Figure 36 Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s): OPA171 OPA2171 OPA4171 OPA171 OPA2171 OPA4171 www.ti.com SBOS516B – SEPTEMBER 2010 – REVISED NOVEMBER 2010 TYPICAL CHARACTERISTICS VS = ±18V, VCM = VS/2, RLOAD = 10kΩ connected to VS/2, and CL = 100pF, unless otherwise noted. OFFSET VOLTAGE PRODUCTION DISTRIBUTION OFFSET VOLTAGE DRIFT DISTRIBUTION 25 Distribution Taken From 3500 Amplifiers 14 Percentage of Amplifiers (%) Percentage of Amplifiers (%) 16 12 10 8 6 4 2 0 Distribution Taken From 110 Amplifiers 20 15 10 5 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 1.9 2 -1200 -1100 -1000 -900 -800 -700 -600 -500 -400 -300 -200 -100 0 100 200 300 400 500 600 700 800 900 1000 1100 1200 0 Offset Voltage Drift (mV/°C) Offset Voltage (mV) Figure 1. Figure 2. OFFSET VOLTAGE vs TEMPERATURE OFFSET VOLTAGE vs COMMON-MODE VOLTAGE 1000 600 10 Typical Units Shown 5 Typical Units Shown 800 400 400 VOS (mV) Offset Voltage (mV) 600 200 0 -200 200 0 -200 -400 -400 -600 -600 -800 -800 VCM = -18.1V -1000 -75 -50 -25 0 25 50 75 100 125 150 -20 -15 -10 0 -5 5 10 15 20 VCM (V) Temperature (°C) Figure 3. Figure 4. OFFSET VOLTAGE vs COMMON-MODE VOLTAGE (Upper Stage) OFFSET VOLTAGE vs POWER SUPPLY 10000 350 10 Typical Units Shown 8000 VSUPPLY = ±1.35V to ±18V 10 Typical Units Shown 250 6000 150 2000 VOS (mV) VOS (mV) 4000 0 -2000 -4000 Normal Operation -50 -150 VCM = +18.1V -6000 -250 -8000 -10000 15.5 50 -350 16 16.5 17 17.5 18 18.5 0 2 4 VCM (V) 6 8 10 12 14 16 18 20 VSUPPLY (V) Figure 5. Figure 6. Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s): OPA171 OPA2171 OPA4171 Submit Documentation Feedback 7 OPA171 OPA2171 OPA4171 SBOS516B – SEPTEMBER 2010 – REVISED NOVEMBER 2010 www.ti.com TYPICAL CHARACTERISTICS (continued) VS = ±18V, VCM = VS/2, RLOAD = 10kΩ connected to VS/2, and CL = 100pF, unless otherwise noted. INPUT BIAS CURRENT vs TEMPERATURE 10000 IB+ -IB IB- +IB -IOS VCM = -18.1V 1000 Input Bias Current (pA) IB and IOS (pA) IB AND IOS vs COMMON-MODE VOLTAGE 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 IB IOS 100 10 IOS 1 VCM = 16V 0 -20 -18 -12 0 -6 6 12 18 20 -75 -50 0 -25 VCM (V) 100 125 OUTPUT VOLTAGE SWING vs OUTPUT CURRENT (Maximum Supply) CMRR AND PSRR vs FREQUENCY (Referred-to Input) 150 140 Common-Mode Rejection Ratio (dB), Power-Supply Rejection Ratio (dB) Output Voltage (V) 75 Figure 8. 17 16 15 14.5 -14.5 -15 -40°C +25°C +85°C +125°C -16 -17 120 100 80 60 40 +PSRR -PSRR CMRR 20 0 -18 0 2 4 6 8 10 12 14 1 16 10 100 1k 10k 100k 1M 10M Frequency (Hz) Output Current (mA) Figure 9. Figure 10. CMRR vs TEMPERATURE PSRR vs TEMPERATURE 3 Power-Supply Rejection Ratio (mV/V) 30 Common-Mode Rejection Ratio (mV/V) 50 Figure 7. 18 20 10 0 -10 VS = 2.7V -20 VS = 4V VS = 36V -30 2 1 0 -1 -2 VS = 2.7V to 36V VS = 4V to 36V -3 -75 8 25 Temperature (°C) -50 -25 0 25 50 75 100 125 150 -75 -50 -25 0 25 50 Temperature (°C) Temperature (°C) Figure 11. Figure 12. Submit Documentation Feedback 75 100 125 150 Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s): OPA171 OPA2171 OPA4171 OPA171 OPA2171 OPA4171 www.ti.com SBOS516B – SEPTEMBER 2010 – REVISED NOVEMBER 2010 TYPICAL CHARACTERISTICS (continued) VS = ±18V, VCM = VS/2, RLOAD = 10kΩ connected to VS/2, and CL = 100pF, unless otherwise noted. INPUT VOLTAGE NOISE SPECTRAL DENSITY vs FREQUENCY 0.1Hz TO 10Hz NOISE 1mV/div Voltage Noise Density (nV/ÖHz) 1000 100 10 1 Time (1s/div) 1 10 100 1k 10k 100k 1M Frequency (Hz) Figure 13. Figure 14. THD+N RATIO vs FREQUENCY THD+N vs OUTPUT AMPLITUDE 0.001 -100 0.0001 -120 G = +1, RL = 10kW G = -1, RL = 2kW 0.00001 10 100 1k 10k -140 20k Total Harmonic Distortion + Noise (%) VOUT = 3VRMS BW = 80kHz 0.1 -80 BW = 80kHz 0.01 -100 0.001 -120 0.0001 G = +1, RL = 10kW G = -1, RL = 2kW 0.00001 0.01 -140 0.1 1 10 20 Output Amplitude (VRMS) Frequency (Hz) Figure 15. Figure 16. QUIESCENT CURRENT vs TEMPERATURE QUIESCENT CURRENT vs SUPPLY VOLTAGE 0.65 0.6 0.6 0.55 0.5 IQ (mA) 0.55 IQ (mA) Total Harmonic Distortion + Noise (dB) -80 Total Harmonic Distortion + Noise (dB) Total Harmonic Distortion + Noise (%) 0.01 0.5 0.45 0.4 0.45 0.35 0.4 0.3 0.35 0.25 Specified Supply-Voltage Range -75 -50 -25 0 25 50 75 100 125 150 0 4 8 Temperature (°C) Figure 17. 12 16 20 24 28 32 36 Supply Voltage (V) Figure 18. Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s): OPA171 OPA2171 OPA4171 Submit Documentation Feedback 9 OPA171 OPA2171 OPA4171 SBOS516B – SEPTEMBER 2010 – REVISED NOVEMBER 2010 www.ti.com TYPICAL CHARACTERISTICS (continued) VS = ±18V, VCM = VS/2, RLOAD = 10kΩ connected to VS/2, and CL = 100pF, unless otherwise noted. OPEN-LOOP GAIN AND PHASE vs FREQUENCY CLOSED-LOOP GAIN vs FREQUENCY 180 180 25 Gain 20 135 135 15 Phase Gain (dB) 45 45 Phase (°) Gain (dB) 10 90 90 5 0 -5 -10 0 0 G = 10 G=1 G = -1 -15 -45 1 10 100 1k 10k 100k -20 -45 10M 1M 10k 100k 1M Figure 19. 100M Figure 20. OPEN-LOOP GAIN vs TEMPERATURE OPEN-LOOP OUTPUT IMPEDANCE vs FREQUENCY 3 1M 5 Typical Units Shown VS = 2.7V VS = 4V VS = 36V 2.5 100k 10k ZO (W) 2 AOL (mV/V) 10M Frequency (Hz) Frequency (Hz) 1.5 1k 100 1 10 0.5 1 0 1m -75 -50 -25 0 25 50 75 100 150 125 1 10 100 Temperature (°C) 100k 1M 10M Figure 22. SMALL-SIGNAL OVERSHOOT vs CAPACITIVE LOAD (100mV Output Step) SMALL-SIGNAL OVERSHOOT vs CAPACITIVE LOAD (100mV Output Step) 50 RL = 10kW ROUT = 0W 40 40 ROUT = 25W 35 35 ROUT = 50W 30 25 20 10 ROUT = 25W 5 ROUT = 50W G = +1 +18V ROUT = 0W 15 Overshoot (%) 45 45 Overshoot (%) 10k Figure 21. 50 30 25 20 RI = 10kW 15 ROUT RF = 10kW G = -1 +18V OPA171 RL CL 10 ROUT OPA171 -18V CL 5 -18V 0 0 0 10 1k Frequency (Hz) 100 200 300 400 500 600 700 800 900 1000 0 100 200 300 400 500 600 700 800 900 1000 Capacitive Load (pF) Capacitive Load (pF) Figure 23. Figure 24. Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s): OPA171 OPA2171 OPA4171 OPA171 OPA2171 OPA4171 www.ti.com SBOS516B – SEPTEMBER 2010 – REVISED NOVEMBER 2010 TYPICAL CHARACTERISTICS (continued) VS = ±18V, VCM = VS/2, RLOAD = 10kΩ connected to VS/2, and CL = 100pF, unless otherwise noted. NO PHASE REVERSAL POSITIVE OVERLOAD RECOVERY +18V Output VOUT OPA171 VIN 5V/div 5V/div -18V 37VPP Sine Wave (±18.5V) 20kW +18V 2kW OPA171 Output VOUT VIN -18V G = -10 Time (5ms/div) Time (100ms/div) Figure 25. Figure 26. NEGATIVE OVERLOAD RECOVERY SMALL-SIGNAL STEP RESPONSE (100mV) RL = 10kW CL = 100pF +18V RL CL 20mV/div -18V VIN 5V/div G = +1 OPA171 20kW +18V 2kW OPA171 VOUT VIN VOUT -18V G = -10 Time (5ms/div) Time (1ms/div) Figure 27. Figure 28. SMALL-SIGNAL STEP RESPONSE (100mV) LARGE-SIGNAL STEP RESPONSE G = +1 RL = 10kW CL = 100pF RI = 2kW RF 2V/div 20mV/div CL = 100pF = 2kW +18V OPA171 CL -18V G = -1 Time (20ms/div) Time (5ms/div) Figure 29. Figure 30. Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s): OPA171 OPA2171 OPA4171 Submit Documentation Feedback 11 OPA171 OPA2171 OPA4171 SBOS516B – SEPTEMBER 2010 – REVISED NOVEMBER 2010 www.ti.com TYPICAL CHARACTERISTICS (continued) VS = ±18V, VCM = VS/2, RLOAD = 10kΩ connected to VS/2, and CL = 100pF, unless otherwise noted. LARGE-SIGNAL SETTLING TIME (10V Positive Step) LARGE-SIGNAL STEP RESPONSE 10 G = -1 RL = 10kW CL = 100pF G = -1 2V/div D From Final Value (mV) 8 6 4 12-Bit Settling 2 0 -2 (±1/2LSB = ±0.024%) -4 -6 -8 -10 Time (4ms/div) 0 4 8 12 16 20 24 28 32 36 Time (ms) Figure 31. Figure 32. LARGE-SIGNAL SETTLING TIME (10V Negative Step) 10 G = -1 8 45 6 40 4 35 12-Bit Settling 2 ISC (mA) D From Final Value (mV) SHORT-CIRCUIT CURRENT vs TEMPERATURE 50 0 -2 (±1/2LSB = ±0.024%) ISC, Sink 30 25 20 -4 15 -6 10 -8 5 ISC, Source 0 -10 0 4 8 12 16 20 24 28 32 36 -75 -50 0 -25 Time (ms) 25 50 75 100 125 150 Temperature (°C) Figure 33. Figure 34. MAXIMUM OUTPUT VOLTAGE vs FREQUENCY CHANNEL SEPARATION vs FREQUENCY 15 -60 VS = ±15V 10 Channel Separation (dB) Output Voltage (VPP) 12.5 Maximum output voltage without slew-rate induced distortion. 7.5 VS = ±5V 5 2.5 -80 -90 -100 -110 VS = ±1.35V 0 -120 10k 12 -70 100k 1M 10M 10 100 1k Frequency (Hz) Frequency (Hz) Figure 35. Figure 36. Submit Documentation Feedback 10k 100k Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s): OPA171 OPA2171 OPA4171 OPA171 OPA2171 OPA4171 www.ti.com SBOS516B – SEPTEMBER 2010 – REVISED NOVEMBER 2010 APPLICATION INFORMATION The OPAx171 family of operational amplifiers provide high overall performance, making them ideal for many general-purpose applications. The excellent offset drift of only 2µV/°C provides excellent stability over the entire temperature range. In addition, the device offers very good overall performance with high CMRR, PSRR, and AOL. As with all amplifiers, applications with noisy or high-impedance power supplies require decoupling capacitors close to the device pins. In most cases, 0.1µF capacitors are adequate. OPERATING CHARACTERISTICS The OPAx171 family of amplifiers is specified for operation from 2.7V to 36V (±1.35V to ±18V). Many of the specifications apply from –40°C to +125°C. Parameters that can exhibit significant variance with regard to operating voltage or temperature are presented in the Typical Characteristics. This device can operate with full rail-to-rail input 100mV beyond the top rail, but with reduced performance within 2V of the top rail. The typical performance in this range is summarized in Table 2. PHASE-REVERSAL PROTECTION The OPAx171 family has an internal phase-reversal protection. Many op amps exhibit a phase reversal when the input is driven beyond its linear common-mode range. This condition is most often encountered in noninverting circuits when the input is driven beyond the specified common-mode voltage range, causing the output to reverse into the opposite rail. The input of the OPAx171 prevents phase reversal with excessive common-mode voltage. Instead, the output limits into the appropriate rail. This performance is shown in Figure 37. +18V Output GENERAL LAYOUT GUIDELINES -18V 37VPP Sine Wave (±18.5V) 5V/div For best operational performance of the device, good printed circuit board (PCB) layout practices are recommended. Low-loss, 0.1µF bypass capacitors should be connected between each supply pin and ground, placed as close to the device as possible. A single bypass capacitor from V+ to ground is applicable to single-supply applications. OPA171 Output COMMON-MODE VOLTAGE RANGE Time (100ms/div) The input common-mode voltage range of the OPAx171 series extends 100mV below the negative rail and within 2V of the top rail for normal operation. Figure 37. No Phase Reversal Table 2. Typical Performance Range PARAMETER MIN Input Common-Mode Voltage TYP (V+) – 2 Offset voltage vs Temperature MAX (V+) + 0.1 UNIT V 7 mV 12 µV/°C Common-mode rejection 65 dB Open-loop gain 60 dB GBW 0.7 MHz Slew rate 0.7 V/µs Noise at f = 1kHz 30 nV/√Hz Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s): OPA171 OPA2171 OPA4171 Submit Documentation Feedback 13 OPA171 OPA2171 OPA4171 SBOS516B – SEPTEMBER 2010 – REVISED NOVEMBER 2010 www.ti.com CAPACITIVE LOAD AND STABILITY The dynamic characteristics of the OPAx171 have been optimized for commonly encountered operating conditions. The combination of low closed-loop gain and high capacitive loads decreases the phase margin of the amplifier and can lead to gain peaking or oscillations. As a result, heavier capacitive loads must be isolated from the output. The simplest way to achieve this isolation is to add a small resistor (for example, ROUT equal to 50Ω) in series with the output. Figure 38 and Figure 39 illustrate graphs of small-signal overshoot versus capacitive load for several values of ROUT. Also, refer to Applications Bulletin AB-028 (SBOA015), available for download from the TI website for details of analysis techniques and application circuits. 50 functions have electrical stress limits determined by the voltage breakdown characteristics of the particular semiconductor fabrication process and specific circuits connected to the pin. Additionally, internal electrostatic discharge (ESD) protection is built into these circuits to protect them from accidental ESD events both before and during product assembly. These ESD protection diodes also provide in-circuit, input overdrive protection, as long as the current is limited to 10mA as stated in the Absolute Maximum Ratings. Figure 40 shows how a series input resistor may be added to the driven input to limit the input current. The added resistor contributes thermal noise at the amplifier input and its value should be kept to a minimum in noise-sensitive applications. RL = 10kW 45 V+ IOVERLOAD 10mA max Overshoot (%) 40 35 OPA171 5kW 25 20 10 ROUT = 25W 5 ROUT = 50W G = +1 +18V ROUT = 0W 15 ROUT 0 RL CL -18V 100 200 300 400 500 600 700 800 900 1000 Capacitive Load (pF) Figure 38. Small-Signal Overshoot versus Capacitive Load (100mV Output Step) 50 45 ROUT = 0W 40 ROUT = 25W 35 ROUT = 50W 30 25 20 RI = 10kW 15 Figure 40. Input Current Protection OPA171 0 Overshoot (%) VOUT VIN 30 RF = 10kW G = -1 +18V 10 ROUT OPA171 CL 5 An ESD event produces a short duration, high-voltage pulse that is transformed into a short duration, high-current pulse as it discharges through a semiconductor device. The ESD protection circuits are designed to provide a current path around the operational amplifier core to prevent it from being damaged. The energy absorbed by the protection circuitry is then dissipated as heat. When the operational amplifier connects into a circuit, the ESD protection components are intended to remain inactive and not become involved in the application circuit operation. However, circumstances may arise where an applied voltage exceeds the operating voltage range of a given pin. Should this condition occur, there is a risk that some of the internal ESD protection circuits may be biased on, and conduct current. Any such current flow occurs through ESD cells and rarely involves the absorption device. -18V 0 0 100 200 300 400 500 600 700 800 900 1000 Capacitive Load (pF) Figure 39. Small-Signal Overshoot versus Capacitive Load (100mV Output Step) ELECTRICAL OVERSTRESS Designers often ask questions about the capability of an operational amplifier to withstand electrical overstress. These questions tend to focus on the device inputs, but may involve the supply voltage pins or even the output pin. Each of these different pin 14 If there is an uncertainty about the ability of the supply to absorb this current, external zener diodes may be added to the supply pins. The zener voltage must be selected such that the diode does not turn on during normal operation. However, its zener voltage should be low enough so that the zener diode conducts if the supply pin begins to rise above the safe operating supply voltage level. Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s): OPA171 OPA2171 OPA4171 OPA171 OPA2171 OPA4171 www.ti.com SBOS516B – SEPTEMBER 2010 – REVISED NOVEMBER 2010 REVISION HISTORY NOTE: Page numbers for previous versions may differ from page numbers in the current version. Changes from Revision A (November, 2010) to Revision B Page • Changed input offset voltage specification ........................................................................................................................... 4 • Changed input offset voltage, over temperature specification .............................................................................................. 4 • Changed quiescent current per amplifier, over temperature specification ........................................................................... 4 Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s): OPA171 OPA2171 OPA4171 Submit Documentation Feedback 15 PACKAGE OPTION ADDENDUM www.ti.com 6-Dec-2010 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/ Ball Finish MSL Peak Temp (3) Samples (Requires Login) OPA171AID ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR Request Free Samples OPA171AIDBVR ACTIVE SOT-23 DBV 5 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR Purchase Samples OPA171AIDBVT ACTIVE SOT-23 DBV 5 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR Request Free Samples OPA171AIDR ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR Purchase Samples OPA171AIDRLR PREVIEW SOT DRL 5 4000 TBD Call TI Call TI Samples Not Available OPA171AIDRLT PREVIEW SOT DRL 5 250 TBD Call TI Call TI Samples Not Available OPA2171AID PREVIEW SOIC D 8 TBD Call TI Call TI Samples Not Available OPA2171AIDCUR PREVIEW US8 DCU 8 TBD Call TI Call TI Samples Not Available OPA2171AIDCUT PREVIEW US8 DCU 8 TBD Call TI Call TI Samples Not Available OPA2171AIDR PREVIEW SOIC D 8 TBD Call TI Call TI Samples Not Available TBD Call TI Call TI Samples Not Available TBD Call TI Call TI Samples Not Available OPA4171AID PREVIEW SOIC D 14 OPA4171AIDR PREVIEW SOIC D 14 OPA4171AIPW PREVIEW TSSOP PW 14 TBD Call TI Call TI Samples Not Available OPA4171AIPWR PREVIEW TSSOP PW 14 TBD Call TI Call TI Samples Not Available 2500 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) Addendum-Page 1 PACKAGE OPTION ADDENDUM www.ti.com (3) 6-Dec-2010 MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. 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Addendum-Page 2 MECHANICAL DATA MTSS001C – JANUARY 1995 – REVISED FEBRUARY 1999 PW (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE 14 PINS SHOWN 0,30 0,19 0,65 14 0,10 M 8 0,15 NOM 4,50 4,30 6,60 6,20 Gage Plane 0,25 1 7 0°– 8° A 0,75 0,50 Seating Plane 0,15 0,05 1,20 MAX PINS ** 0,10 8 14 16 20 24 28 A MAX 3,10 5,10 5,10 6,60 7,90 9,80 A MIN 2,90 4,90 4,90 6,40 7,70 9,60 DIM 4040064/F 01/97 NOTES: A. B. C. D. All linear dimensions are in millimeters. This drawing is subject to change without notice. Body dimensions do not include mold flash or protrusion not to exceed 0,15. Falls within JEDEC MO-153 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. 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