TM124BBK32F, TM124BBK32U 1048576 BY 32-BIT DYNAMIC RAM MODULE TM248CBK32F, TM248CBK32U 2097152 BY 32-BIT DYNAMIC RAM MODULE SMMS649A – DECEMBER 1994 – REVISED JUNE 1995 D D D D D D D D D D D D Organization TM124BBK32F . . . 1 048 576 × 32 TM248CBK32F . . . 2 097 152 × 32 Single 5-V Power Supply (±10% Tolerance) 72-Pin Single-In-Line Memory Module (SIMM) for Use With Socket TM124BBK32F – Utilizes Two 16-Megabit DRAMs in Plastic Small-Outline J-Lead (SOJ) Packages TM248CBK32F – Utilizes Four 16-Megabit DRAMs in Plastic Small-Outline J-Lead (SOJ) Packages Long Refresh Period 16 ms (1024 Cycles) All Inputs, Outputs, Clocks Fully TTL Compatible 3-State Output Common CAS Control for Eight Common Data-In and Data-Out Lines in Four Blocks Enhanced Page-Mode Operation With CAS-Before-RAS ( CBR), RAS-Only, and Hidden Refresh Presence Detect Performance Ranges: ACCESS TIME tRAC D D D D ’124BBK32F-60 ’124BBK32F-70 ’124BBK32F-80 ’248CBK32F-60 ’248CBK32F-70 ’248CBK32F-80 (MAX) 60 ns 70 ns 80 ns 60 ns 70 ns 80 ns ACCESS ACCESS READ TIME TIME OR tAA tCAC WRITE CYCLE (MAX) (MAX) (MIN) 30 ns 15 ns 110 ns 35 ns 18 ns 130 ns 40 ns 20 ns 150 ns 30 ns 15 ns 110 ns 35 ns 18 ns 130 ns 40 ns 20 ns 150 ns Low Power Dissipation Operating Free-Air Temperature Range 0°C to 70°C Gold-Tabbed Versions Available:† – TM124BBK32F – TM248CBK32F Tin-Lead (Solder) Tabbed Versions Available: – TM124BBK32U – TM248CBK32U description TM124BBK32F The TM124BBK32F is a 32-megabit dynamic random-access memory (DRAM) organized as four times 1 048 576 × 8 in a 72-pin SIMM. The SIMM is composed of two TMS418160DZ, 1 048 576 × 16-bit DRAMs, each in a 42-lead plastic SOJ package mounted on a substrate with decoupling capacitors. The TMS418160DZ is described in the TMS418160 data sheet. The TM124BBK32F SIMM is available in the single-sided BK-leadless module for use with sockets. TM248CBK32F The TM248CBK32F is a 64-megabit DRAM organized as four times 2 097 152 × 8 in a 72-pin SIMM. The SIMM is composed of four TMS418160DZ, 1 048 576 × 16-bit DRAMs, each in a 42-lead plastic SOJ package mounted on a substrate with decoupling capacitors. The TMS418160DZ is described in the TMS418160 data sheet. The TM248CBK32F SIMM is available in the double-sided BK-leadless module for use with sockets. operation The TM124BBK32F operates as two TMS418160DZs connected as shown in the functional block diagram and Table 1. The TM248CBK32F operates as four TMS418160DZs connected as shown in the functional block diagram and Table 1. The common I / O feature dictates the use of early-write cycles to prevent contention on D and Q. † Part numbers in this data sheet are for the gold-tabbed version; the information applies to both gold-tabbed and solder-tabbed versions. Copyright 1995, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. • POST OFFICE BOX 655303 DALLAS, TEXAS 75265 POST OFFICE BOX 1443 HOUSTON, TEXAS 77251–1443 • 1 TM124BBK32F, TM124BBK32U 1048576 BY 32-BIT DYNAMIC RAM MODULE TM248CBK32F, TM248CBK32U 2097152 BY 32-BIT DYNAMIC RAM MODULE SMMS649A – DECEMBER 1994 – REVISED JUNE 1995 BK SINGLE-IN-LINE MEMORY MODULE ( TOP VIEW ) 2 VSS DQ0 DQ16 DQ1 DQ17 DQ2 DQ18 DQ3 DQ19 VCC NC A0 A1 A2 A3 A4 A5 A6 NC DQ4 DQ20 DQ5 DQ21 DQ6 DQ22 DQ7 DQ23 A7 NC VCC A8 A9 RAS3 RAS2 NC NC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 NC NC VSS CAS0 CAS2 CAS3 CAS1 RAS0 RAS1 NC W NC DQ8 DQ24 DQ9 DQ25 DQ10 DQ26 DQ11 DQ27 DQ12 DQ28 VCC DQ29 DQ13 DQ30 DQ14 DQ31 DQ15 NC PD1 PD2 PD3 PD4 NC VSS 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 TM124BBK32F ( SIDE VIEW ) TM248CBK32F ( SIDE VIEW ) PIN NOMENCLATURE A0 – A9 CAS0 – CAS3 DQ0 – DQ31 NC PD1 – PD4 RAS0 – RAS3 VCC VSS W Address Inputs Column-Address Strobe Data In/Data Out No Connection Presence Detects Row-Address Strobe 5-V Supply Ground Write Enable PRESENCE DETECT SIGNAL (PIN) PD1 (67) PD2 (68) VSS VSS VSS VSS 80 ns VSS NC VSS NC 70 ns NC NC 60 ns NC NC 80 ns TM124BBK32F 70 ns 60 ns TM248CBK32F • POST OFFICE BOX 655303 DALLAS, TEXAS 75265 POST OFFICE BOX 1443 HOUSTON, TEXAS 77251–1443 • PD3 (69) PD4 (70) NC VSS NC VSS NC NC VSS NC NC VSS NC NC TM124BBK32F, TM124BBK32U 1048576 BY 32-BIT DYNAMIC RAM MODULE TM248CBK32F, TM248CBK32U 2097152 BY 32-BIT DYNAMIC RAM MODULE SMMS649A – DECEMBER 1994 – REVISED JUNE 1995 Table 1. Connection Table DATA BLOCK RASx SIDE 1 SIDE 2† CASx DQ0 – DQ7 RAS0 RAS1 CAS0 DQ8 – DQ15 RAS0 RAS1 CAS1 DQ16 – DQ23 RAS2 RAS3 CAS2 DQ24 – DQ31 RAS2 RAS3 CAS3 † Side 2 applies to the TM248CBK32F only. single-in-line memory module and components PC substrate: 1,27 ± 0,1 mm (0.05 inch) nominal thickness; 0.005 inch / inch maximum warpage Bypass capacitors: Multilayer ceramic Contact area for TM124BBK32F and TM248CBK32F: Nickel plate and gold plate over copper Contact area for TM124BBK32U and TM248CBK32U: Nickel plate and tin / lead over copper functional block diagram (TM124BBK32F and TM248CBK32F, side 1) 10 A0 – A9 RAS0 RAS2 W 10 CAS0 CAS1 1M × 16 A0 –A9 DQ0 – DQ7 RAS W LCAS DQ8 – UCAS DQ15 10 D0 – D7 CAS2 CAS3 D8 – D15 1M × 16 A0 –A9 DQ0 – RAS DQ7 W LCAS DQ8 – UCAS DQ15 D16 – D23 D24 – D31 functional block diagram (TM248CBK32F, side 2) 10 A0 – A9 RAS1 RAS3 W 10 CAS1 CAS0 1M × 16 A0 –A9 DQ0 – RAS DQ7 W LCAS DQ8 – UCAS DQ15 10 D8 – D15 CAS3 CAS2 D0 – D7 • POST OFFICE BOX 655303 DALLAS, TEXAS 75265 POST OFFICE BOX 1443 HOUSTON, TEXAS 77251–1443 • 1M × 16 A0 –A9 DQ0 – RAS DQ7 W LCAS DQ8 – UCAS DQ15 D24 – D31 D16 – D23 3 TM124BBK32F, TM124BBK32U 1048576 BY 32-BIT DYNAMIC RAM MODULE TM248CBK32F, TM248CBK32U 2097152 BY 32-BIT DYNAMIC RAM MODULE SMMS649A – DECEMBER 1994 – REVISED JUNE 1995 absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range, VCC (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 1 V to 7 V Voltage range on any pin (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 1 V to 7 V Short-circuit output current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA Power dissipation: TM124BBK32F, TM124BBK32U . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 W TM248CBK32F, TM248CBK32U . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 W Operating free-air temperature range, TA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 55°C to 125°C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTE 1: All voltage values are with respect to VSS. recommended operating conditions MIN NOM MAX VCC VIH Supply voltage 4.5 5 5.5 V High-level input voltage 2.4 6.5 V VIL TA Low-level input voltage (see Note 2) –1 0.8 V 0 70 °C Operating free-air temperature UNIT NOTE 2: The algebraic convention, where the more negative (less positive) limit is designated as minimum, is used for logic-voltage levels only. electrical characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER VOH VOL High-level output voltage Low-level output voltage ’124BBK32F - 60 TEST CONDITIONS MIN IOH = – 5 mA IOL = 4.2 mA MAX 2.4 ’124BBK32F - 70 MIN MAX 2.4 ’124BBK32F - 80 MIN MAX 2.4 UNIT V 0.4 0.4 0.4 V ± 10 ± 10 ± 10 µA II Input current (leakage) VCC = 5.5 V, VI = 0 V to 6.5 V, All other pins = 0 V to VCC IO Output current (leakage) VCC = 5.5 V, VO = 0 V to VCC, CAS high ± 10 ± 10 ± 10 µA ICC1 Read- or write-cycle current VCC = 5.5 V, Minimum cycle 180 160 140 mA VIH = 2.4 V (TTL), After 1 memory cycle, RAS and CAS high 4 4 4 mA VIH = VCC – 0.2 V (CMOS), After 1 memory cycle, RAS and CAS high 2 2 2 mA ICC2 Standby current ICC3 Average refresh current (RAS only or CBR) VCC = 5.5 V, Minimum cycle, RAS cycling, CAS high (RAS only); RAS low after CAS low (CBR) 180 160 140 mA ICC4 Average page current VCC = 5.5 V, tPC = MIN, CAS cycling RAS low, 180 160 140 mA 4 • POST OFFICE BOX 655303 DALLAS, TEXAS 75265 POST OFFICE BOX 1443 HOUSTON, TEXAS 77251–1443 • TM124BBK32F, TM124BBK32U 1048576 BY 32-BIT DYNAMIC RAM MODULE TM248CBK32F, TM248CBK32U 2097152 BY 32-BIT DYNAMIC RAM MODULE SMMS649A – DECEMBER 1994 – REVISED JUNE 1995 electrical characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)† PARAMETER VOH High-level output voltage IOH = – 5 mA VOL Low-level output voltage IOL = 4.2 mA II Input current (leakage) IO ICC1 ICC2 ’248CBK32F - 60 TEST CONDITIONS MIN ’248CBK32F - 70 MAX 2.4 MIN ’248CBK32F - 80 MAX MIN 2.4 MAX 2.4 UNIT V 0.4 0.4 0.4 V VCC = 5.5 V, VI = 0 V to 6.5 V, All other pins = 0 V to VCC ± 10 ± 10 ± 10 µA Output current (leakage) VCC = 5.5 V, VO = 0 V to VCC, CAS high ± 20 ± 20 ± 20 µA Read- or write-cycle current (see Note 3) VCC = 5.5 V, 184 164 144 mA VIH = 2.4 V (TTL), After 1 memory cycle, RAS and CAS high 8 8 8 mA VIH = VCC – 0.2 V (CMOS), After 1 memory cycle, RAS and CAS high 4 4 4 mA Standby current Minimum cycle ICC3 Average refresh current (RAS only or CBR) (see Note 3) VCC = 5.5 V, Minimum cycle, RAS cycling, CAS high (RAS only); RAS low after CAS low (CBR) 360 320 280 mA ICC4 Average page current (see Note 4) VCC = 5.5 V, RAS low, 184 164 144 mA tPC = MIN, CAS cycling † For test conditions shown as MIN / MAX, use the appropriate value specified under recommended operating conditions. NOTES: 3. Measured with a maximum of one address change while RAS = VIL 4. Measured with a maximum of one address change while CAS = VIH capacitance over recommended ranges of supply voltage and operating free-air temperature, f = 1 MHz (see Note 5) ’124BBK32F PARAMETER MIN MAX ’248CBK32F MIN MAX UNIT Ci(A) Input capacitance, A0 – A9 10 20 pF Ci(R) Input capacitance, RAS inputs 7 7 pF Ci(C) Input capacitance, CAS inputs 7 14 pF Ci(W) Input capacitance, W 14 28 pF Co(DQ) Output capacitance on DQ0 – DQ31 7 14 pF NOTE 5: VCC = 5 V ± 0.5 V, and the bias on pins under test is 0 V. • POST OFFICE BOX 655303 DALLAS, TEXAS 75265 POST OFFICE BOX 1443 HOUSTON, TEXAS 77251–1443 • 5 TM124BBK32F, TM124BBK32U 1048576 BY 32-BIT DYNAMIC RAM MODULE TM248CBK32F, TM248CBK32U 2097152 BY 32-BIT DYNAMIC RAM MODULE SMMS649A – DECEMBER 1994 – REVISED JUNE 1995 switching characteristics over recommended ranges of supply voltage and operating free-air temperature ’124BBK32F - 60 ’248CBK32F - 60 PARAMETER MIN MAX ’124BBK32F - 70 ’248CBK32F - 70 MIN MAX ’124BBK32F - 80 ’248CBK32F - 80 MIN UNIT MAX tAA tCAC Access time from column address 30 35 40 ns Access time from CAS low 15 18 20 ns tRAC tCPA Access time from RAS low 60 70 80 ns Access time from column precharge 35 40 45 ns tCLZ tOH CAS to output in low-impedance state 0 0 0 Output disable time from start of CAS high 3 3 3 tOFF Output disable time after CAS high (see Note 6) NOTE 6: tOFF is specified when the output is no longer driven. 0 15 0 18 0 ns ns 20 ns timing requirements over recommended ranges of supply voltage and operating free-air temperature ’124BBK32F - 60 ’248CBK32F - 60 MIN MAX ’124BBK32F - 70 ’248CBK32F - 70 MIN MAX ’124BBK32F - 80 ’248CBK32F - 80 MIN UNIT MAX tRC tRWC Cycle time, random read or write (see Note 7) 110 130 150 ns Cycle time, read-write 155 181 205 ns tPC tRASP Cycle time, page-mode read or write (see Notes 7 and 8) 40 45 Pulse duration, page mode, RAS low 60 100 000 70 100 000 80 100 000 ns tRAS tCAS Pulse duration, nonpage mode, RAS low 60 10 000 70 10 000 80 10 000 ns Pulse duration, CAS low 15 10 000 18 10 000 20 10 000 ns tCP tRP Pulse duration, CAS high 10 10 10 ns Pulse duration, RAS high (precharge) 40 50 60 ns tWP tASC Pulse duration, W low 10 10 10 ns Setup time, column address before CAS low 0 0 0 ns tASR tDS Setup time, row address before RAS low 0 0 0 ns Setup time, data before CAS low 0 0 0 ns tRCS tCWL Setup time, W high before CAS low 0 0 0 ns Setup time, W low before CAS high 15 18 20 ns tRWL tWCS Setup time, W low before RAS high 15 18 20 ns 0 0 0 ns tWRP Setup time, W high before RAS low (CBR refresh only) 10 10 10 ns tCAH tRHCP Hold time, column address after CAS low 10 15 15 ns Hold time, RAS high from CAS precharge 35 40 45 ns tDH tRAH Hold time, data after CAS low 10 15 15 ns Hold time, row address after RAS low 10 10 10 ns tRCH tRRH Hold time, W high after CAS high (see Note 9) 0 0 0 ns Hold time, W high after RAS high (see Note 9) 0 0 0 ns Setup time, W low before CAS low NOTES: 7. All cycles assume tT = 5 ns. 8. To assure tPC min, tASC should be ≥ tCP . 9. Either tRRH or tRCH must be satisfied for a read cycle. 6 • POST OFFICE BOX 655303 DALLAS, TEXAS 75265 POST OFFICE BOX 1443 HOUSTON, TEXAS 77251–1443 • 50 ns TM124BBK32F, TM124BBK32U 1048576 BY 32-BIT DYNAMIC RAM MODULE TM248CBK32F, TM248CBK32U 2097152 BY 32-BIT DYNAMIC RAM MODULE SMMS649A – DECEMBER 1994 – REVISED JUNE 1995 timing requirements over recommended ranges of supply voltage and operating free-air temperature (continued) ’124BBK32F - 60 ’248CBK32F - 60 MIN ’124BBK32F - 70 ’248CBK32F - 70 MAX MIN MAX ’124BBK32F - 80 ’248CBK32F - 80 MIN UNIT MAX tWCH tWRH Hold time, W low after CAS low 10 15 15 ns Hold time, W high after RAS low (CBR refresh only) 10 10 10 ns tCHR tCRP Delay time, RAS low to CAS high (CBR refresh only) 10 10 10 ns Delay time, CAS high to RAS low 5 5 5 ns tCSH tCSR Delay time, RAS low to CAS high 60 70 80 ns tRAD tRAL Delay time, RAS low to column address (see Note 10) 15 Delay time, column address to RAS high 30 35 40 tCAL tRCD Delay time, column address to CAS high 30 35 40 Delay time, RAS low to CAS low (see Note 10) 20 tRPC tRSH Delay time, RAS high to CAS low (CBR only) tREF tT Refresh time interval Delay time, CAS low to RAS low (CBR refresh only) 5 Delay time, CAS low to RAS high 5 30 45 15 20 52 15 20 ns 40 ns ns ns 60 ns 0 0 0 ns 15 18 20 ns 16 Transition time 5 35 3 30 16 3 30 3 16 ms 30 ns NOTE 10: The maximum value is specified only to assure access time. device symbolization (TM124BBK32F illustrated) TM124BBK32F -SS YY MM T -SS = = = = YYMMT Year Code Month Code Assembly Site Code Speed Code NOTE: Location of symbolization may vary. • POST OFFICE BOX 655303 DALLAS, TEXAS 75265 POST OFFICE BOX 1443 HOUSTON, TEXAS 77251–1443 • 7 TM124BBK32F, TM124BBK32U 1048576 BY 32-BIT DYNAMIC RAM MODULE TM248CBK32F, TM248CBK32U 2097152 BY 32-BIT DYNAMIC RAM MODULE SMMS649A – DECEMBER 1994 – REVISED JUNE 1995 8 • POST OFFICE BOX 655303 DALLAS, TEXAS 75265 POST OFFICE BOX 1443 HOUSTON, TEXAS 77251–1443 • IMPORTANT NOTICE Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. 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