TM124FBK32, TM124FBK32S 1048576 BY 32-BIT TM248GBK32, TM248GBK32S 2097152 BY 32-BIT DYNAMIC RAM MODULES SMMS664A – DECEMBER 1995 – REVISED JUNE 1996 D D D D D D D D D D D Organization TM124FBK32 . . . 1 048 576 × 32 TM248GBK32 . . . 2 097 152 × 32 Single 5-V Power Supply 72-pin Single In-Line Memory Module (SIMM) for Use With Sockets TM124FBK32 Utilizes Eight 4M-Bit Dynamic RAMs (DRAMs) in Plastic Small-Outline J-Lead (SOJ) Packages TM248GBK32 Utilizes Sixteen 4M-Bit DRAMs in Plastic SOJ Packages Long Refresh Period 16 ms (1 024 Cycles) All Inputs, Outputs, Clocks Fully TTL Compatible 3-State Output Common CAS Control for Eight Common Data-In and Data-Out Lines, In Four Blocks Extended Data-Out (EDO) Operation With CAS-Before-RAS (CBR), RAS-Only, and Hidden Refresh JEDEC First Generation 72-Pin SIMM Pinout D D Presence Detect Performance Ranges: ’124FBK32-60 ’124FBK32-70 ’124FBK32-80 ’248GBK32-60 ’248GBK32-70 ’248GBK32-80 D D D D ACCESS TIME tRAC (MAX) 60 ns 70 ns 80 ns 60 ns 70 ns 80 ns ACCESS ACCESS EDO TIME TIME CYCLE tAA tCAC tHPC (MAX) (MIN) (MIN) 30 ns 15 ns 25 ns 35 ns 18 ns 30 ns 40 ns 20 ns 35 ns 30 ns 15 ns 25 ns 35 ns 18 ns 30 ns 40 ns 20 ns 35 ns Low Power Dissipation Operating Free-Air Temperature Range . . . 0°C to 70°C Gold-Tabbed Versions Available:† – TM124FBK32 – TM248GBK32 Tin-Lead- (Solder-) Tabbed Versions Available: – TM124FBK32S – TM248GBK32S description TM124FBK32 The TM124FBK32 is a 4M-byte DRAM organized as four times 1 048 576 × 8 in a 72-pin leadless SIMM. The SIMM is composed of eight TMS44409, 1 048 576 × 4-bit DRAMs, each in a 20/26-lead plastic SOJ package, mounted on a substrate together with decoupling capacitors. Each TMS44409 is described in the TMS44409 data sheet. The TM124FBK32 is available in the single-sided BK leadless module for use with sockets. TM248GBK32 The TM248GBK32 is a 8M-byte DRAM organized as four times 2 097 152 × 8 in a 72-pin leadless SIMM. The SIMM is composed of sixteen TMS44409, 1 048 576 × 4-bit DRAMs, each in a 20/26-lead plastic SOJ package, mounted on a substrate together with decoupling capacitors. Each TMS44409 is described in the TMS44409 data sheet. The TM248GBK32 is available in the double-sided BK leadless module for use with sockets. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. † Part numbers in this data sheet are for the gold-tabbed version; the information applies to both gold-tabbed and solder-tabbed versions. Copyright 1996, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 1 TM124FBK32, TM124FBK32S 1048576 BY 32-BIT TM248GBK32, TM248GBK32S 2097152 BY 32-BIT DYNAMIC RAM MODULES SMMS664A – DECEMBER 1995 – REVISED JUNE 1996 operation TM124FBK32 The TM124FBK32 operates as eight TMS44409DJs connected as shown in the functional block diagram. Refer to the TMS44409 data sheet for details of operation. The common I/O feature of the TM124FBK32 dictates the use of early write cycles to prevent contention on D and Q. TM248GBK32 The TM248GBK32 operates as sixteen TMS44409DJs connected as shown in the functional block diagram. Refer to the TMS44409 data sheet for details of operation. The common I/O feature of the TM248GBK32 dictates the use of early write cycles to prevent contention on D and Q. specifications Refresh period is extended to 16 ms and, during this period, each of the 1 024 rows must be strobed with RAS in order to retain data. A0–A9 address lines must be refreshed every 16 ms as required by the TMS44409 DRAM. CAS can remain high during the refresh sequence to conserve power. single in-line memory module and components PC substrate: 1,27 ± 0,1 mm (0.05 inch) nominal thickness; 0.005 inch/inch maximum warpage Bypass capacitors: Multilayer ceramic Contact area for TM124FBK32 and TM248GBK32: Nickel plate and gold plate over copper Contact area for TM124FBK32S and TM248GBK32S: Nickel plate and tin-lead over copper 2 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 TM124FBK32, TM124FBK32S 1048576 BY 32-BIT TM248GBK32, TM248GBK32S 2097152 BY 32-BIT DYNAMIC RAM MODULES SMMS664A – DECEMBER 1995 – REVISED JUNE 1996 BK SINGLE IN-LINE PACKAGE† TM124FBK32† TM248GBK32† (TOP VIEW) (SIDE VIEW) (SIDE VIEW) VSS DQ0 DQ16 DQ1 DQ17 DQ2 DQ18 DQ3 DQ19 VCC NC A0 A1 A2 A3 A4 A5 A6 NC DQ4 DQ20 DQ5 DQ21 DQ6 DQ22 DQ7 DQ23 A7 NC VCC A8 A9 RAS3 RAS2 NC NC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 NC NC VSS CAS0 CAS2 CAS3 CAS1 RAS0 RAS1 NC W NC DQ8 DQ24 DQ9 DQ25 DQ10 DQ26 DQ11 DQ27 DQ12 DQ28 VCC DQ29 DQ13 DQ30 DQ14 DQ31 DQ15 NC PD1 PD2 PD3 PD4 NC VSS 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 PIN NOMENCLATURE A0–A9 CAS0, CAS3 DQ0–DQ31 NC PD1– PD4 RAS0–RAS3 VCC VSS W Address Inputs Column-Address Strobe Data In/Data Out No Connection Presence Detects Row-Address Strobe 5-V Supply Ground Write Enable PRESENCE DETECT SIGNAL (PIN) PD1 (67) PD2 (68) VSS VSS VSS VSS 80 ns VSS NC VSS NC 70 ns NC NC 60 ns NC NC 80 ns TM124FBK32 70 ns 60 ns TM248GBK32 PD3 (69) PD4 (70) NC VSS NC VSS NC NC VSS NC NC VSS NC NC † The packages shown here are for pinout reference only and are not drawn to scale. POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 3 10 RAS0 RAS2 W CAS0 CAS1 10 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 10 1M × 4 A0–A9 RAS W CAS OE DQ1– DQ4 1M × 4 A0–A9 RAS W CAS OE DQ1– DQ4 10 DQ0– DQ3 10 DQ4– DQ7 CAS3 CAS2 1M × 4 A0–A9 RAS W CAS OE DQ1– DQ4 1M × 4 A0–A9 RAS W CAS OE DQ1– DQ4 10 DQ8– DQ11 10 DQ12– DQ15 1M × 4 A0–A9 RAS W CAS OE DQ1– DQ4 1M × 4 A0–A9 RAS W CAS OE DQ1– DQ4 10 DQ16– DQ19 10 DQ20– DQ23 1M × 4 A0–A9 RAS W CAS OE DQ1– DQ4 1M × 4 A0–A9 RAS W CAS OE DQ1– DQ4 DQ24– DQ27 DQ28– DQ31 Template Release Date: 7–11–94 A0–A9 TM124FBK32, TM124FBK32S 1048576 BY 32-BIT TM248GBK32, TM248GBK32S 2097152 BY 32-BIT DYNAMIC RAM MODULES SMMS664A – DECEMBER 1995 – REVISED JUNE 1996 4 functional block diagram (for TM124FBK32 and TM248GBK32, Side 1) functional block diagram (for TM248GBK32, Side 2) A0–A9 10 RAS1 RAS3 W CAS0 CAS1 10 DQ0– DQ3 10 DQ4– DQ7 1M × 4 A0–A9 RAS W CAS OE DQ1– DQ4 1M × 4 A0–A9 RAS W CAS OE DQ1– DQ4 10 DQ8– DQ11 10 DQ12– DQ15 1M × 4 A0–A9 RAS W CAS OE DQ1– DQ4 1M × 4 A0–A9 RAS W CAS OE DQ1– DQ4 10 DQ16– DQ19 10 DQ20– DQ23 1M × 4 A0–A9 RAS W CAS OE DQ1– DQ4 1M × 4 A0–A9 RAS W CAS OE DQ1– DQ4 DQ24– DQ27 DQ28– DQ31 5 TM124FBK32, TM124FBK32S 1048576 BY 32-BIT TM248GBK32, TM248GBK32S 2097152 BY 32-BIT DYNAMIC RAM MODULES 1M × 4 A0–A9 RAS W CAS OE DQ1– DQ4 10 SMMS664A – DECEMBER 1995 – REVISED JUNE 1996 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 10 1M × 4 A0–A9 RAS W CAS OE DQ1– DQ4 CAS3 CAS2 TM124FBK32, TM124FBK32S 1048576 BY 32-BIT TM248GBK32, TM248GBK32S 2097152 BY 32-BIT DYNAMIC RAM MODULES SMMS664A – DECEMBER 1995 – REVISED JUNE 1996 absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Voltage range on any pin (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 1 V to 7 V Voltage range on VCC (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 1 V to 7 V Short circuit output current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA Power dissipation: TM124FBK32, TM124FBK32S . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 W TM248GBK32, TM248GBK32S . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 W Operating free-air temperature range, TA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 55°C to 125°C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTE 1: All voltage values are with respect to VSS. recommended operating conditions MIN NOM MAX 5 UNIT VCC VIH Supply voltage 4.5 5.5 V High-level input voltage 2.4 6.5 V VIL TA Low-level input voltage (see Note 2) –1 0.8 V 0 70 °C Operating free-air temperature NOTE 2: The algebraic convention, where the more negative (less positive) limit is designated as minimum, is used for logic voltage levels only. electrical characteristics over full ranges of recommended operating conditions (unless otherwise noted) PARAMETER VOH VOL High-level output voltage Low-level output voltage TEST CONDITIONS ’124FBK32-60 MIN IOH = – 5 mA IOL = 4.2 mA MAX 2.4 ’124FBK32-70 MIN MAX 2.4 ’124FBK32-80 MIN MAX 2.4 UNIT V 0.4 0.4 0.4 V ±10 ±10 ±10 µA II Input current (leakage) VI = 0 to 6.5 V, VCC = 5 V, All other pins = 0 to VCC IO Output current (leakage) VO = 0 to VCC, CAS high VCC = 5.5 V, ±10 ±10 ±10 µA ICC1 Read- or write-cycle current (see Note 3) Minimum cycle, VCC = 5.5 V 840 720 640 mA 16 16 16 ICC1 Standby current After one memory cycle, RAS and CAS high, VIH = 2.4 V (TTL) mA After one memory cycle, RAS and CAS high, VIH = VCC – 0.2 V (CMOS) 8 8 8 ICC3 Average refresh current (RAS-only or CBR) (see Note 3) Minimum cycle, VCC = 5.5 V, RAS cycling, CAS high (RAS-only), RAS low after CAS low (CBR) 840 720 640 mA ICC4 Average page current (see Note 4) tPC = minimum, VCC = 5.5 V, RAS low, CAS cycling 720 640 560 mA NOTES: 3. Measured with a maximum of one address change while RAS = VIL. 4. Measured with a maximum of one address change while CAS = VIH. 6 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 TM124FBK32, TM124FBK32S 1048576 BY 32-BIT TM248GBK32, TM248GBK32S 2097152 BY 32-BIT DYNAMIC RAM MODULES SMMS664A – DECEMBER 1995 – REVISED JUNE 1996 electrical characteristics over full ranges of recommended operating conditions (unless otherwise noted) PARAMETER VOH VOL High-level output voltage Low-level output voltage TEST CONDITIONS ’248GBK32-60 MIN IOH = – 5 mA IOL = 4.2 mA MAX 2.4 ’248GBK32-70 MIN MAX 2.4 ’248GBK32-80 MIN MAX 2.4 UNIT V 0.4 0.4 0.4 V ±20 ±20 ±20 µA II Input current (leakage) VI = 0 to 6.5 V, VCC = 5 V, All other pins = 0 to VCC IO Output current (leakage) VO = 0 to VCC, CAS high VCC = 5.5 V, ±20 ±20 ±20 µA ICC1 Read- or write-cycle current (see Note 3) Minimum cycle, VCC = 5.5 V 856 736 656 mA After one memory cycle, RAS and CAS high, VIH = 2.4 V (TTL) 32 32 32 After one memory cycle, RAS and CAS high, VIH = VCC – 0.2 V (CMOS) 16 16 16 1680 1440 1280 mA 736 656 576 mA ICC1 Standby current ICC3 Average refresh current (RAS-only or CBR) (see Note 3) Minimum cycle, VCC = 5.5 V, RAS cycling, CAS high (RAS-only), RAS low after CAS low (CBR) ICC4 Average EDO current (see Note 4) tPC = minimum, VCC = 5.5 V, RAS low, CAS cycling mA NOTES: 3. Measured with a maximum of one address change while RAS = VIL. 4. Measured with a maximum of one address change while CAS = VIH. capacitance over recommended ranges of supply voltage and operating free-air temperature f = 1 MHz (see Note 5) ’124FBK32 MIN ’248GBK32 MAX MIN MAX UNIT Ci(A) Input capacitance, address inputs 40 80 pF Ci(R) Input capacitance, RAS 28 28 pF Ci(C) Input capacitance, CAS 14 28 pF Ci(W) Input capacitance, write-enable input 56 112 pF Co(DQ) Output capacitance on DQ pins 7 14 pF NOTE 5: VCC equal to 5 V ± 0.5 V and the bias on pins under test is 0 V. POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 7 TM124FBK32, TM124FBK32S 1048576 BY 32-BIT TM248GBK32, TM248GBK32S 2097152 BY 32-BIT DYNAMIC RAM MODULES SMMS664A – DECEMBER 1995 – REVISED JUNE 1996 switching characteristics over recommended ranges of supply voltage and operating free-air temperature ’124FBK32-60 ’248GBK32-60 PARAMETER MIN MAX ’124FBK32-70 ’248GBK32-70 MIN MAX ’124FBK32-80 ’248GBK32-80 MIN UNIT MAX tAA tCAC Access time from column address 30 35 40 ns Access time from CAS low 15 18 20 ns tRAC tCPA Access time from RAS low 60 70 80 ns Access time from column precharge 35 40 45 ns tCLZ tREZ CAS to output in the low-impedance state 0 Output disable time after RAS high (see Note 6) 3 15 3 18 3 20 ns 3 15 3 18 3 20 ns tWEZ Output disable time after W low (see Note 6) NOTE 6: tREZ and tWEZ are specified when the output is no longer driven. 0 0 ns EDO timing requirements over recommended ranges of supply voltage and operating free-air temperature ’124FBK32-60 ’248GBK32-60 MIN MAX ’124FBK32-70 ’248GBK32-70 MIN MAX ’124FBK32-80 ’248GBK32-80 MIN UNIT MAX tHPC tPRWC Cycle time, EDO page-mode read or write 25 30 35 ns Cycle time, EDO read-write 80 90 100 ns tCSH tDOH Hold time, CAS from RAS 50 55 60 ns 3 3 3 ns tCAS tWPE Pulse duration, CAS Pulse duration, W (output disable only) 5 5 5 ns tCP Precharge time, CAS 5 5 5 ns 8 Hold time, output from CAS 10 POST OFFICE BOX 1443 10 000 • HOUSTON, TEXAS 77251–1443 12 10 000 15 10 000 ns TM124FBK32, TM124FBK32S 1048576 BY 32-BIT TM248GBK32, TM248GBK32S 2097152 BY 32-BIT DYNAMIC RAM MODULES SMMS664A – DECEMBER 1995 – REVISED JUNE 1996 timing requirements over recommended range of supply voltage and operating free-air temperature ’124FBK32-60 ’248GBK32-60 MIN MAX ’124FBK32-70 ’248GBK32-70 MIN MAX ’124FBK32-80 ’248GBK32-80 MIN UNIT MAX tRC tRWC Cycle time, random read or write (see Note 7) 110 130 150 ns Cycle time, read-write 150 175 200 ns tRASP tRAS Pulse duration, page-mode, RAS low 60 100 000 70 100 000 80 100 000 ns Pulse duration, non-page-mode, RAS low 60 70 80 ns tRP tWP Pulse duration, RAS high (precharge) 40 50 60 Pulse duration, W low 10 10 10 ns tRASS tRPS Pulse duration, self-refresh entry from RAS low 100 100 100 µs Pulse duration, RAS precharge after self-refresh 110 130 150 ns tASC tASR Setup time, column address before CAS low 0 0 0 ns Setup time, row address before RAS low 0 0 0 ns tDS tRCS Setup time, data before CAS low 0 0 0 ns Setup time, W high before CAS low 0 0 0 ns tCWL tRWL Setup time, W low before CAS high 10 12 15 ns Setup time, W low before RAS high 10 12 15 ns tWCS tWRP Setup time, W low before CAS low 0 0 0 ns Setup time, W high before RAS low (see Note 8) 10 10 10 ns tCAH tDH Hold time, column address after CAS low 10 15 15 ns Hold time, data after CAS low 10 15 15 ns tRAH tRCH Hold time, row address after RAS low 10 10 10 ns Hold time, W high after CAS high (see Note 9) 0 0 0 ns tRRH tWCH Hold time, W high after RAS high (see Note 9) 0 0 0 ns Hold time, W low after CAS low 10 15 15 ns tWRH tRHCP Hold time, W high after RAS low (see Note 8) 10 10 10 ns Hold time, RAS high from CAS precharge 35 40 45 ns tCHS tCHR Hold time, CAS low after RAS high (self-refresh) – 50 – 50 – 50 ns 10 10 10 ns tCRP tCSR Delay time, CAS high to RAS low 5 5 5 ns tRAD tRAL Delay time, RAS low to column address (see Note 10) 15 Delay time, column address to RAS high 30 tCAL tRCD Delay time, column address to CAS high 20 Delay time, RAS low to CAS low (see Note 10) 20 tRPC tRSH Delay time, RAS high to CAS low (CBR only) tREF tT Refresh time interval Delay time, RAS low to CAS high (see Note 8) Delay time, CAS low to RAS low (see Note 8) 5 Delay time, CAS low to RAS high 10 000 5 30 15 20 15 20 0 0 0 12 15 30 16 2 ns 40 30 2 ns ns 30 52 10 2 ns 40 25 45 10 000 5 35 35 16 Transition time NOTES: 7. 8. 9. 10. 10 000 ns 60 ns ns ns 16 ms 30 ns All cycled times assume tT = 5 ns. CBR refresh only Either tRRH or tRCH must be satisfied for a read cycle. Maximum value specified only to assure access time. POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 9 TM124FBK32, TM124FBK32S 1048576 BY 32-BIT TM248GBK32, TM248GBK32S 2097152 BY 32-BIT DYNAMIC RAM MODULES SMMS664A – DECEMBER 1995 – REVISED JUNE 1996 MECHANICAL DATA BK (R-PSIM-N72) SINGLE-IN-LINE MEMORY MODULE 0.054 (1,37) 0.047 (1,19) 4.255 (108,08) 4.245 (107,82) 0.125 (3,18) TYP 1.005 (25,53) 0.995 (25,27) 0.128 (3,25) 0.120 (3,05) 0.050 (1,27) 0.010 (0,25) MAX 0.400 (10,16) TYP 0.040 (1,02) TYP 0.208 (5,28) MAX 0.360 (9,14) MAX (For Double-Sided SIMM) 4040197 / C 4/95 NOTES: A. All linear dimensions are in inches (millimeters). B. This drawing is subject to change without notice. device symbolization (TM124FBK32 illustrated) TM124FBK32 –SSL YY MM T –SS L = = = = = Year Code Month Code Assembly Site Code Speed Code Temperature Range NOTE: Location of symbolization may vary. 10 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 YYMMT IMPORTANT NOTICE Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those pertaining to warranty, patent infringement, and limitation of liability. TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in accordance with TI’s standard warranty. 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TI does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property right of TI covering or relating to any combination, machine, or process in which such semiconductor products or services might be or are used. TI’s publication of information regarding any third party’s products or services does not constitute TI’s approval, warranty or endorsement thereof. Copyright 1998, Texas Instruments Incorporated