TPS84259 www.ti.com SLVSBA0 – AUGUST 2012 4.5-V to 40-V Input, 15-W, Negative Output, Integrated Power Solution Check for Samples: TPS84259 FEATURES 1 • • • • • • • • • • • • • • Complete Integrated Power Solution Allows Small Footprint, Low-Profile Design Wide Input Voltage Range from 4.5 V to 40 V Output Adjustable from –3.0 V to –17 V Supplies up to 2-A of Output Current 45-V Surge Capability Synchronizes to an External Clock Adjustable Slow-Start Programmable Undervoltage Lockout (UVLO) Output Overcurrent Protection Over Temperature Protection Operating Temperature Range: –40°C to 85°C Enhanced Thermal Performance: 14°C/W Meets EN55022 Class B Emissions For Design Help visit http://www.ti.com/TPS84259 APPLICATIONS • • • • DESCRIPTION The TPS84259 is an easy-to-use negative output voltage power module that combines a 15-W DC/DC converter with an inductor, and passives into a low profile, QFN package. This total power solution allows as few as five external components and eliminates the loop compensation and magnetics part selection process. The 9x11x2.8 mm QFN package is easy to solder onto a printed circuit board and allows a compact design with fewer components and excellent power dissipation capability. The TPS84259 offers the flexibility and the feature-set of a discrete design and is ideal for powering a wide range of ICs and analog circuits requiring a negative output voltage. Advanced packaging technology affords a robust and reliable power solution compatible with standard QFN mounting and testing techniques. SIMPLIFIED APPLICATION TPS84259 VIN Industrial and Motor Controls Automated Test Equipment Bipolar Amplifiers in Audio/Video High Density Power Systems VIN -VOUT VOUT VOUT_PT CIN COUT A_VOUT INH/UVLO RT Safe Operating Current CLK 2.2 STSEL 2 Output Current (A) VADJ SS 1.8 GND 1.6 RSET 1.4 1.2 1 0.8 0.6 VO = –3.3 V VO = –5 V VO = –12 V VO = –15 V 0.4 0.2 0 5 10 15 20 25 Input Voltage (V) 30 35 40 G000 This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. 1 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2012, Texas Instruments Incorporated TPS84259 SLVSBA0 – AUGUST 2012 www.ti.com ABSOLUTE MAXIMUM RATINGS (1) over operating temperature range (unless otherwise noted) Input Voltage Output Voltage MIN MAX UNIT VIN –0.3 45 V INH/UVLO –0.3 5 (2) V VADJ –0.3 3 (2) V SS –0.3 3 (2) V STSEL –0.3 3 (2) V (2) V RT –0.3 3.6 CLK –0.3 3.6 (2) V PH –0.6 45 V –2 45 V PH 10ns Transient VOUT –0.6 VDIFF (VOUT to exposed thermal pad) VIN (2) V ±200 mV Source Current INH/UVLO 100 µA Sink Current SS 200 µA 105 (3) °C 150 °C 1500 G Operating Junction Temperature –40 Storage Temperature –65 Mechanical Shock Mil-STD-883D, Method 2002.3, 1 ms, 1/2 sine, mounted Mechanical Vibration Mil-STD-883D, Method 2007.2, 20-2000Hz (1) 20 Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. This voltage rating is referenced to A_VOUT, not GND. See the temperature derating curves in the Typical Characteristics section for thermal information. (2) (3) RECOMMENDED OPERATING CONDITIONS over operating free-air temperature range (unless otherwise noted) VIN Input Voltage VOUT Output Voltage MIN MAX 4.5 40 UNIT V –3.0 –17 V PACKAGE SPECIFICATIONS TPS84259 Weight Flammability MTBF Calculated reliability UNIT 0.9 grams Meets UL 94 V-O Per Bellcore TR-332, 50% stress, TA = 40°C, ground benign 31.7 MHrs ORDERING INFORMATION For the most current package and ordering information, see the Package Option Addendum at the end of this datasheet, or see the TI website at www.ti.com. 2 Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Links: TPS84259 TPS84259 www.ti.com SLVSBA0 – AUGUST 2012 ELECTRICAL CHARACTERISTICS -40°C ≤ TA ≤ +85°C, VIN = 12 V, VOUT = –5.0 V, IOUT = 2.0A CIN = 2 x 2.2 µF ceramic, COUT = 2 x 47 µF ceramic (unless otherwise noted) MAX UNIT IOUT Output current PARAMETER Over input voltage and output voltage range 0 (1) 2.0 (2) A VIN Input voltage range Over output current range 4.5 40 (3) V UVLO VIN Undervoltage lockout Rising only, RUVLO1 = 174 kΩ, RUVLO2 = 63.4 kΩ VOUT(adj) Output voltage adjust range Over output current range Set-point voltage tolerance TA = 25°C, IOUT = 100 mA Temperature variation –40°C ≤ TA ≤ +85°C ±0.5% Line regulation Over input voltage range ±0.1% Load regulation From 100 mA to IOUT(max) ±0.4% Total output voltage variation Includes set-point, line, load, and temperature variation VOUT TEST CONDITIONS VIN = 24 V η Efficiency Output voltage ripple ILIM VIN = 12 V Inhibit threshold voltage INH with respect to A_VOUT 77 % VOUT = –12 V, IOUT = 0.6 A 86 % VOUT = –5.0 V, IOUT = 1.0 A 81 % VOUT = –3.3 V, IOUT = 1.0 A 78 % INH pin to A_VOUT fSW Switching frequency RT pin to A_VOUT fCLK Synchronization frequency VCLK-H CLK High-Level Threshold With respect to A_VOUT VCLK-L CLK Low-Level Threshold With respect to A_VOUT DCLK CLK Duty cycle CIN External input capacitance COUT External output capacitance (4) 1% Recovery time VOUT over/undershoot A 500 µs 80 1.15 700 RRT = 0 Ω RRT = 93.1 kΩ 1.25 mV 1.36 (6) V μA μA 1.3 4 µA 800 900 kHz 700 (7) 900 (7) kHz 400 (7) 600 (7) kHz 1.9 0.5 0.7 25% 50% Thermal shutdown Thermal shutdown hysteresis Ceramic VOUT (5) –3.8 Input standby current (9) 81 % VOUT = –3.3 V, IOUT = 1.0 A VINH > 1.36 V II(stby) (7) (8) 85 % –0.9 INH Input current (5) (6) VOUT = –12 V, IOUT = 1.0 A VOUT = –5.0 V, IOUT = 1.0 A V (4) ±1.0% 3.0% VINH < 1.15 V IINH (2) (3) (4) 2.0% 3.0 Transient response V –17 (3) –3.0 20 MHz bandwith, 100 mA ≤ IOUT ≤ IOUT(max) 1.0 A/µs load step from 25 to 75% IOUT(max) Thermal Shutdown TYP 4.5 Current limit threshold VINH (1) MIN 4.7 (8) Non-ceramic 2.2 V 75% 180 °C 15 °C 10 µF 22 100 (9) V 430 (9) µF This device can regulate VOUT down to 0 A, however the ripple may increase due to pulse-skipping at light loads. See Light-Load Behavior for more information. See No-Load Operation when operating at 0 A. The maximum current is dependant on VIN and VOUT, see Figure 33. The sum of VIN + |VOUT| must not exceed 50 V. The stated limit of the set-point voltage tolerance includes the tolerance of both the internal voltage reference and the internal adjustment resistor. The overall output voltage tolerance will be affected by the tolerance of the external RSET resistor. This product is not designed to endure a sustained (> 5 sec) over-current condition. If this pin is left open circuit, the device operates when input power is applied. An external level-shifter is required to interface with this pin. See Output On/Off Inhibit (INH) for further guidance. The synchronization frequency is dependant on VIN and VOUT as shown in Switching Frequency. RRT must be either 0 Ω or 93.1kΩ. A minimum of 4.7 µF of ceramic external capacitance is required across the input (VIN and PGND connected) for proper operation. Locate the capacitor close to the device. See Table 1 for more details. The amount of required capacitance must include at least 2 x 47 µF ceramic capacitor (or 4 x 22 µF). Locate the capacitance close to the device. Adding additional capacitance close to the load improves the response of the regulator to load transients. See Table 1 for more details. See Inrush Current section when adding additional output capacitance. Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Links: TPS84259 3 TPS84259 SLVSBA0 – AUGUST 2012 www.ti.com THERMAL INFORMATION TPS84259 THERMAL METRIC (1) RKG UNIT 41 PINS Junction-to-ambient thermal resistance (2) θJA 14 (3) ψJT Junction-to-top characterization parameter ψJB Junction-to-board characterization parameter (4) (1) (2) (3) (4) 3.3 °C/W 6.8 For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953. The junction-to-ambient thermal resistance, θJA, applies to devices soldered directly to a 100 mm x 100 mm double-sided PCB with 1 oz. copper and natural convection cooling. Additional airflow reduces θJA. The junction-to-top characterization parameter, ψJT, estimates the junction temperature, TJ, of a device in a real system, using a procedure described in JESD51-2A (sections 6 and 7). TJ = ψJT * Pdis + TT; where Pdis is the power dissipated in the device and TT is the temperature of the top of the device. The junction-to-board characterization parameter, ψJB, estimates the junction temperature, TJ, of a device in a real system, using a procedure described in JESD51-2A (sections 6 and 7). TJ = ψJB * Pdis + TB; where Pdis is the power dissipated in the device and TB is the temperature of the board 1mm from the device. DEVICE INFORMATION FUNCTIONAL BLOCK DIAGRAM TPS84259 CLK Thermal Shutdown RT Shutdown Logic SS OCP STSEL OSC w/PLL + + VADJ VREF Comp INH/UVLO VIN UVLO PH Power Stage and Control Logic A_VOUT 4 VIN GND VOUT Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Links: TPS84259 TPS84259 www.ti.com SLVSBA0 – AUGUST 2012 PIN DESCRIPTIONS TERMINAL NAME VIN DESCRIPTION NO. 26 Input voltage. This pin supplies all power to the converter. Connect this pin to the input supply and connect bypass capacitors between this pin and GND. 16 17 VOUT 18 19 Negative output voltage with respect to GND. Connect these pins to the output load and connect external bypass capacitors between these pins and GND. Pad 40 should be connected to PCB VOUT planes using multiple vias for good thermal performance. 20 40 10 11 12 GND 13 14 This is the return current path for the power stage of the device. These pins are connected to the internal output inductor. Connect these pins to the load and to the bypass capacitors associated with VIN and VOUT. 15 39 6 7 21 PH 22 23 Phase switch node. Do not place any external component on these pins or tie them to a pin of another function. 24 38 41 VOUT_PT 8 9 VOUT and A_VOUT Connection Point. Connect VOUT to A_VOUT at these pins as shown in the Layout Considerations section. These pins are not connected to internal circuitry, but are connected to each other. 2 DNC 3 25 Do Not Connect. Do not connect these pins to GND, to another DNC pin, or to any other voltage. These pins are connected to internal circuitry. Each pin must be soldered to an isolated pad. 35 1 4 5 A_VOUT 32 33 34 These pins are connected to the internal analog reference (A_VOUT) of the device. This node should be treated as the negative voltage reference for the analog control circuitry. Pad 37 should be connected to the PCB A_VOUT plane using multiple vias for good thermal performance. Not all pins are connected together internally. All pins must be connected together externally with a copper plane or pour directly under the module. Connect A_VOUT to VOUT at a single point (VOUT_PT; pins 8 & 9). See Layout Recommendations. 37 RT 30 Switching frequency adjust pin. To operate at the recommended free-running frequency, connect this pin to A_VOUT. Connecting a resistor between this pin and A_VOUT will reduce the switching frequency. See Switching Frequency section. CLK 31 Use this pin to synchronize to an external clock. If unused, isolate this pin from any other signal. INH/UVLO 27 Inhibit and UVLO adjust pin. Use an external level-shifter device to ground this pin to control the INH function. A resistor divider between this pin, A_VOUT, and VIN sets the UVLO voltage. SS 28 Slow-start pin. Connecting an external capacitor between this pin and A_VOUT adjusts the output voltage rise time. STSEL 29 Slow-start select. Connect this pin to A_VOUT to enable the internal SS capacitor. VADJ 36 Connecting a resistor between this pin and GND sets the output voltage. A dedicated GND sense line connected at the load will improve regulation at the load. See Figure 48 in the Layout Considerations section. Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Links: TPS84259 5 TPS84259 SLVSBA0 – AUGUST 2012 www.ti.com RKG PACKAGE (TOP VIEW) 6 Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Links: TPS84259 TPS84259 www.ti.com SLVSBA0 – AUGUST 2012 TYPICAL CHARACTERISTICS (VIN = 5 V) 50 95 45 Output Voltage Ripple (mV) 100 Efficiency (%) 90 85 80 75 70 65 VO = –15 V, fsw = 800 kHz VO = –12 V, fsw = 800 kHz VO = –5.0 V, fsw = 800 kHz VO = –3.3 V, fsw = 800 kHz 60 55 50 0 0.2 0.4 0.6 Output Current (A) 0.8 VO = –15 V, fsw = 800 kHz VO = –12 V, fsw = 800 kHz VO = –5.0 V, fsw = 800 kHz VO = –3.3 V, fsw = 800 kHz 40 35 30 25 20 15 10 5 0 1 0 0.2 G000 Figure 1. Efficiency vs. Output Current 0.4 0.6 Output Current (A) 0.8 1 G000 Figure 2. Voltage Ripple vs. Output Current 2.5 90 VO = –15 V, fsw = 800 kHz VO = –12 V, fsw = 800 kHz VO = –5.0 V, fsw = 800 kHz VO = –3.3 V, fsw = 800 kHz 2 80 Ambient Temperature (°C) Power Dissipation (W) (1) (2) 1.5 1 0.5 70 60 50 40 30 VO = –5 V 0 0 0.2 0.4 0.6 Output Current (A) 0.8 20 1 0 0.1 G000 90 90 80 80 70 60 50 40 30 (2) 0.6 G000 70 60 50 40 0 0.05 VO = –15 V Natural Convection 0.1 0.15 0.2 Output Current (A) 0.25 0.3 20 0 G000 Figure 5. Safe Operating Area (1) 0.5 30 VO = –12 V 20 0.2 0.3 0.4 Output Current (A) Figure 4. Safe Operating Area Ambient Temperature (°C) Ambient Temperature (°C) Figure 3. Power Dissipation vs. Output Current Natural Convection 0.05 Natural Convection 0.1 0.15 Output Current (A) 0.2 0.25 G000 Figure 6. Safe Operating Area The electrical characteristic data has been developed from actual products tested at 25°C. This data is considered typical for the converter. Applies to Figure 1, Figure 2, and Figure 3. The temperature derating curves represent the conditions at which internal components are at or below the manufacturer's maximum operating temperatures. Derating limits apply to devices soldered directly to a 100 mm × 100 mm, 4-layer, double-sided PCB with 1 oz. copper. Applies to Figure 4, Figure 5, and Figure 6. Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Links: TPS84259 7 TPS84259 SLVSBA0 – AUGUST 2012 www.ti.com TYPICAL CHARACTERISTICS (VIN = 12 V) 50 95 45 Output Voltage Ripple (mV) 100 90 Efficiency (%) 85 80 75 70 65 VO = –15 V, fsw = 800 kHz VO = –12 V, fsw = 800 kHz VO = –5.0 V, fsw = 800 kHz VO = –3.3 V, fsw = 800 kHz 60 55 50 0 0.3 0.6 0.9 1.2 Output Current (A) 1.5 VO = –15 V, fsw = 800 kHz VO = –12 V, fsw = 800 kHz VO = –5.0 V, fsw = 800 kHz VO = –3.3 V, fsw = 800 kHz 40 35 30 25 20 15 10 5 0 1.8 0 0.3 0.6 0.9 1.2 Output Current (A) G000 Figure 7. Efficiency vs. Output Current Ambient Temperature (°C) 1 70 60 50 40 400 LFM 200 LFM Natural Convection 30 VO = –5 V 0 0.3 0.6 0.9 1.2 Output Current (A) 1.5 20 1.8 0 0.2 90 80 80 Ambient Temperature (°C) Ambient Temperature (°C) 90 70 60 50 40 0 0.1 0.3 0.4 0.5 Output Current (A) 0.6 0.7 1.6 G000 50 40 200 LFM Natural Convection VO = –15 V 0.8 20 0 G000 Figure 11. Safe Operating Area 8 1.4 60 Natural Convection 0.2 1.2 70 30 VO = –12 V 0.6 0.8 1 Output Current (A) Figure 10. Safe Operating Area 30 (2) 0.4 G000 Figure 9. Power Dissipation vs. Output Current (1) G000 80 2 20 1.8 90 VO = –15 V, fsw = 800 kHz VO = –12 V, fsw = 800 kHz VO = –5.0 V, fsw = 800 kHz VO = –3.3 V, fsw = 800 kHz 3 0 1.5 Figure 8. Voltage Ripple vs. Output Current 4 Power Dissipation (W) (1) (2) 0.1 0.2 0.3 0.4 0.5 Output Current (A) 0.6 0.7 G000 Figure 12. Safe Operating Area The electrical characteristic data has been developed from actual products tested at 25°C. This data is considered typical for the converter. Applies to Figure 7, Figure 8, and Figure 9. The temperature derating curves represent the conditions at which internal components are at or below the manufacturer's maximum operating temperatures. Derating limits apply to devices soldered directly to a 100 mm × 100 mm, 4-layer, double-sided PCB with 1 oz. copper. Applies to Figure 10, Figure 11, and Figure 12. Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Links: TPS84259 TPS84259 www.ti.com SLVSBA0 – AUGUST 2012 TYPICAL CHARACTERISTICS (VIN = 24 V) 50 95 45 Output Voltage Ripple (mV) 100 Efficiency (%) 90 85 80 75 70 65 VO = –15 V, fsw = 800 kHz VO = –12 V, fsw = 800 kHz VO = –5.0 V, fsw = 500 kHz VO = –3.3 V, fsw = 500 kHz 60 55 50 0 0.4 0.8 1.2 Output Current (A) 1.6 VO = –15 V, fsw = 800 kHz VO = –12 V, fsw = 800 kHz VO = –5.0 V, fsw = 500 kHz VO = –3.3 V, fsw = 500 kHz 40 35 30 25 20 15 10 5 0 2 0 0.4 0.8 1.2 Output Current (A) G000 Figure 13. Efficiency vs. Output Current Ambient Temperature (°C) 2 1 70 60 50 40 400 LFM 200 LFM Natural Convection 30 VO = –5 V 0 0.4 0.8 1.2 Output Current (A) 1.6 20 2 0 0.4 80 80 Ambient Temperature (°C) Ambient Temperature (°C) 90 70 60 50 40 400 LFM 200 LFM Natural Convection VO = –12 V 0 0.2 0.4 0.6 0.8 1 Output Current (A) 1.2 1.4 (3) 2 G000 70 60 50 40 400 LFM 200 LFM Natural Convection 30 VO = –15 V 1.6 20 0 G000 Figure 17. Safe Operating Area (2) 1.6 Figure 16. Safe Operating Area 90 30 0.8 1.2 Output Current (A) G000 Figure 15. Power Dissipation vs. Output Current (1) G000 80 3 20 2 90 VO = –15 V, fsw = 800 kHz VO = –12 V, fsw = 800 kHz VO = –5.0 V, fsw = 500 kHz VO = –3.3 V, fsw = 500 kHz 4 0 1.6 Figure 14. Voltage Ripple vs. Output Current 5 Power Dissipation (W) (1) (2) (3) 0.2 0.4 0.6 0.8 Output Current (A) 1 1.2 1.4 G000 Figure 18. Safe Operating Area The electrical characteristic data has been developed from actual products tested at 25°C. This data is considered typical for the converter. Applies to Figure 13, Figure 14, and Figure 15. At light load the output voltage ripple may increase due to pulse skipping. See Light-Load Behavior for more information. Applies to Figure 14. The temperature derating curves represent the conditions at which internal components are at or below the manufacturer's maximum operating temperatures. Derating limits apply to devices soldered directly to a 100 mm × 100 mm, 4-layer, double-sided PCB with 1 oz. copper. Applies to Figure 16, Figure 17, and Figure 18. Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Links: TPS84259 9 TPS84259 SLVSBA0 – AUGUST 2012 www.ti.com TYPICAL CHARACTERISTICS (VIN = 36 V) 50 95 45 Output Voltage Ripple (mV) 100 90 Efficiency (%) 85 80 75 70 65 VO = –15 V, fsw = 800 kHz VO = –12 V, fsw = 800 kHz VO = –5.0 V, fsw = 500 kHz VO = –3.3 V, fsw = 500 kHz 60 55 50 0 0.4 0.8 1.2 Output Current (A) 1.6 VO = –15 V, fsw = 800 kHz VO = –12 V, fsw = 800 kHz VO = –5.0 V, fsw = 500 kHz VO = –3.3 V, fsw = 500 kHz 40 35 30 25 20 15 10 5 0 2 0 0.4 G000 Figure 19. Efficiency vs. Output Current 0.8 1.2 Output Current (A) Ambient Temperature (°C) 2 1 70 60 50 40 400 LFM 200 LFM Natural Convection 30 VO = –5 V 0 0.4 0.8 1.2 Output Current (A) 1.6 20 2 0 0.4 G000 90 90 80 80 70 60 50 40 400 LFM 200 LFM Natural Convection 30 VO = –12 V 0 0.3 0.6 0.9 1.2 Output Current (A) 1.5 10 1.6 2 G000 70 60 50 40 400 LFM 200 LFM Natural Convection 30 VO = –15 V 1.8 20 0 G000 Figure 23. Safe Operating Area (2) (3) 0.8 1.2 Output Current (A) Figure 22. Safe Operating Area Ambient Temperature (°C) Ambient Temperature (°C) Figure 21. Power Dissipation vs. Output Current (1) G000 80 3 20 2 90 VO = –15 V, fsw = 800 kHz VO = –12 V, fsw = 800 kHz VO = –5.0 V, fsw = 500 kHz VO = –3.3 V, fsw = 500 kHz 4 0 1.6 Figure 20. Voltage Ripple vs. Output Current 5 Power Dissipation (W) (1) (2) (3) 0.25 0.5 0.75 Output Current (A) 1 1.25 G000 Figure 24. Safe Operating Area The electrical characteristic data has been developed from actual products tested at 25°C. This data is considered typical for the converter. Applies to Figure 19, Figure 20, and Figure 21. At light load the output voltage ripple may increase due to pulse skipping. See for more information. Applies to Figure 20. The temperature derating curves represent the conditions at which internal components are at or below the manufacturer's maximum operating temperatures. Derating limits apply to devices soldered directly to a 100 mm × 100 mm, 4-layer, double-sided PCB with 1 oz. copper. Applies to Figure 22, Figure 23, and Figure 24. Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Links: TPS84259 TPS84259 www.ti.com SLVSBA0 – AUGUST 2012 120 30 90 30 90 20 60 20 60 10 30 10 30 0 0 0 0 Gain Phase −40 1000 10000 Frequency (kHz) 100000 −60 −20 −90 −30 −120 300000 −40 1000 100000 −120 300000 G000 Figure 26. VIN= 5 V, VOUT= –12 V, IOUT= 0.3 A, COUT= 4 x 22 µF ceramic, fSW= 800 kHz 120 40 120 30 90 30 90 20 60 20 60 10 30 10 30 0 0 0 0 −30 −10 −20 −30 Gain Phase −40 1000 10000 Frequency (kHz) 100000 Gain (dB) 40 Phase (°) Gain (dB) −90 10000 Frequency (kHz) G000 Figure 25. VIN= 5 V, VOUT= –5 V, IOUT= 0.6 A, COUT= 4 x 22µF ceramic, fSW= 800 kHz −60 −20 −90 −30 −120 300000 −30 −10 −60 Gain Phase −40 1000 −90 10000 Frequency (kHz) G000 Figure 27. VIN= 12 V, VOUT= –5 V, IOUT= 1.6 A, COUT= 4 x 22 µF ceramic, fSW= 800 kHz 100000 −120 300000 G000 Figure 28. VIN= 12 V, VOUT= –12 V, IOUT= 0.8 A, COUT= 4 x 22 µF ceramic, fSW= 800 kHz 120 40 120 30 90 30 90 20 60 20 60 10 30 10 30 0 0 0 0 −30 −10 −20 −30 −40 1000 Gain Phase 10000 Frequency (kHz) 100000 Gain (dB) 40 Phase (°) Gain (dB) −60 Gain Phase −20 −90 −30 −120 300000 −30 −10 −60 −60 Gain Phase −40 1000 −90 10000 Frequency (kHz) G000 Figure 29. VIN= 24 V, VOUT= –5 V, IOUT= 2.0 A, COUT= 4 x 22 µF ceramic, fSW= 500 kHz Phase (°) −30 −30 −10 Phase (°) −30 −10 Phase (°) 40 Gain (dB) 120 −20 (1) (1) 40 Phase (°) Gain (dB) TYPICAL CHARACTERISTICS (BODE PLOTS) 100000 −120 300000 G000 Figure 30. VIN= 24 V, VOUT= –12 V, IOUT= 1.5 A, COUT= 4 x 22 µF ceramic, fSW= 800 kHz The electrical characteristic data has been developed from actual products tested at 25°C. This data is considered typical for the converter. Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Links: TPS84259 11 TPS84259 SLVSBA0 – AUGUST 2012 www.ti.com (continued) 40 120 30 90 30 90 20 60 20 60 10 30 10 30 0 0 0 0 −30 −10 −60 −20 −30 Gain Phase −40 1000 100000 −30 −10 −60 −20 −90 10000 Frequency (kHz) Gain (dB) 120 Gain Phase −30 −120 300000 −40 1000 −90 10000 Frequency (kHz) G000 Figure 31. VIN= 36 V, VOUT= –5 V, IOUT= 2.0 A, COUT= 4 x 22 µF ceramic, fSW= 500 kHz Phase (°) (2) 40 Phase (°) Gain (dB) TYPICAL CHARACTERISTICS (BODE PLOTS) 100000 −120 300000 G000 Figure 32. VIN= 36 V, VOUT= –12 V, IOUT= 1.8 A, COUT= 4 x 22 µF ceramic, fSW= 800 kHz CAPACITOR RECOMMENDATIONS FOR THE TPS84259 POWER SUPPLY Capacitor Technologies Electrolytic, Polymer-Electrolytic Capacitors When using electrolytic capacitors, high-quality, computer-grade electrolytic capacitors are recommended. Polymer-electrolytic type capacitors are recommended for applications where the ambient operating temperature is less than 0°C. The Sanyo OS-CON capacitor series is suggested due to the lower ESR, higher rated surge, power dissipation, ripple current capability, and small package size. Aluminum electrolytic capacitors provide adequate decoupling over the frequency range of 2 kHz to 150 kHz, and are suitable when ambient temperatures are above 0°C. Ceramic Capacitors The performance of aluminum electrolytic capacitors is less effective than ceramic capacitors above 150 kHz. Multilayer ceramic capacitors have a low ESR and a resonant frequency higher than the bandwidth of the regulator. They can be used to reduce the reflected ripple current at the input as well as improve the transient response of the output. Tantalum, Polymer-Tantalum Capacitors Polymer-tantalum type capacitors are recommended for applications where the ambient operating temperature is less than 0°C. The Sanyo POSCAP series and Kemet T530 capacitor series are recommended rather than many other tantalum types due to their lower ESR, higher rated surge, power dissipation, ripple current capability, and small package size. Tantalum capacitors that have no stated ESR or surge current rating are not recommended for power applications. Input Capacitor The TPS84259 requires a minimum input capacitance of 4.7 μF of ceramic type. The voltage rating of input capacitors must be greater than the maximum input voltage. The ripple current rating of the capacitor must be at least 450 mArms. Table 1 includes a preferred list of capacitors by vendor. Output Capacitor The required output capacitance of the TPS84259 can be comprised of either all ceramic capacitors, or a combination of ceramic and bulk capacitors. The required output capacitance must include at least 2 × 47 µF of ceramic type (or 4 × 22 µF). The voltage rating of output capacitors must be greater than the output voltage. When adding additional non-ceramic bulk capacitors, low-ESR devices like the ones recommended in Table 1 are required. Additional capacitance above the required minimum is determined by actual transient deviation requirements. Table 1 includes a preferred list of capacitors by vendor. 12 Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Links: TPS84259 TPS84259 www.ti.com SLVSBA0 – AUGUST 2012 Table 1. Recommended Input/Output Capacitors (1) CAPACITOR CHARACTERISTICS VENDOR SERIES PART NUMBER WORKING VOLTAGE (V) CAPACITANCE (µF) ESR (2) (mΩ) Murata X5R GRM31CR61H225KA88L 50 2.2 2 TDK X5R C3216X5R1H475K 50 4.7 2 Murata X5R GRM32ER61E226K 16 22 2 TDK X5R C3225X5R0J476K 6.3 47 2 Murata X5R GRM32ER60J476M 6.3 47 2 Sanyo POSCAP 16TQC68M 16 68 50 Sanyo POSCAP 6TPE100MI 6.3 100 25 Kemet T530 T530D227M006ATE006 6.3 220 6 (1) (2) Capacitor Supplier Verification, RoHS, Lead-free and Material Details Consult capacitor suppliers regarding availability, material composition, RoHS and lead-free status, and manufacturing process requirements for any capacitors identified in this table. Maximum ESR @ 100 kHz, 25°C. Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Links: TPS84259 13 TPS84259 SLVSBA0 – AUGUST 2012 www.ti.com APPLICATION INFORMATION Adjusting the Output Voltage The TPS84259 is designed to provide output voltages from –3 V to –17 V. The output voltage is determined by the value of RSET, which must be connected between the VADJ pin (Pin 36) and GND. Table 2 gives the standard external RSET resistor for a number of common bus voltages. Table 2. Standard RSET Resistor Values for Common Output Voltages OUTPUT VOLTAGE VOUT (V) –3.3 –5.0 –8.0 –12.0 –15.0 RSET (kΩ) 31.6 52.3 90.9 140 178 For other output voltages the value of RSET can be calculated using the following formula, or simply selected from the range of values given in Table 3. æ VOUT ö - 1÷ (kW ) RSET = 10 ´ ç ç 0.798 ÷ è ø (1) Table 3. Standard RSET Resistor Values VOUT (V) RSET (kΩ) VOUT (V) RSET (kΩ) VOUT (V) RSET (kΩ) –3.0 27.4 –7.5 84.5 –12.5 147 –3.3 31.6 –8.0 90.9 –13.0 154 –3.5 34.0 –8.5 97.6 –13.5 158 –4.0 40.2 –9.0 102 –14.0 165 –4.5 46.4 –9.5 110 –14.5 174 –5.0 52.3 –10.0 115 –15.0 178 –5.5 48.7 –10.5 121 –15.5 187 –6.0 64.9 –11.0 127 –16.0 191 –6.5 71.5 –11.5 133 –16.5 196 –7.0 78.7 –12.0 140 –17.0 205 Safe Operating Current The amount of output current that can safely be delivered by the TPS84259 depends on the input voltage and the output voltage. Figure 33 shows the maximum output current for four standard output voltages over input voltage. 2.2 2 Output Current (A) 1.8 1.6 1.4 1.2 1 0.8 0.6 VO = –3.3 V VO = –5 V VO = –12 V VO = –15 V 0.4 0.2 0 5 10 15 20 25 Input Voltage (V) 30 35 40 G000 Figure 33. Safe Operating Current 14 Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Links: TPS84259 TPS84259 www.ti.com SLVSBA0 – AUGUST 2012 Application Schematics VIN 24 V VOUT –12 V @ 1.25 A TPS84259 VOUT VIN VOUT_PT 4.7 F 50 V 174 kΩ 47 F 16 V A_VOUT INH/UVLO 47 F 16 V RT STSEL 11.5 kΩ VADJ GND 140 kΩ Figure 34. Typical Schematic VIN = 24 V, VOUT = –12 V VIN 12 V VOUT –5 V @ 1.5 A TPS84259 VOUT VIN VOUT_PT 4.7 F 25 V 174 kΩ 47 F 6.3 V A_VOUT INH/UVLO 47 F 6.3 V RT STSEL 24.3 kΩ VADJ GND 52.3kΩ Figure 35. Typical Schematic VIN = 12 V, VOUT = –5 V Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Links: TPS84259 15 TPS84259 SLVSBA0 – AUGUST 2012 www.ti.com Input Voltage The TPS84259 operates over the input voltage range of 4.5 V to 40 V. The maximum input voltage is 40 V, however, the sum of VIN + |VOUT| must not exceed 50 V. See the Undervoltage Lockout (UVLO) Threshold section of this datasheet for more information. Undervoltage Lockout (UVLO) Threshold At turn-on, the VON UVLO threshold determines the input voltage level where the device begins power conversion. RUVLO1 and RUVLO2 set the turn-on threshold as shown in Figure 36. The UVLO threshold is not present during the power-down sequence. Applications requiring a turn-off threshold must monitor the input voltage with external circuitry and shut-down using the INH control (see Output On/Off Inhibit (INH)). The VON UVLO threshold must be set to at least 4.5 V to insure proper start-up and reduce current surges on the host input supply as the voltage rises. If possible, it is recommended to set the UVLO threshold to appproximantely 80 to 85% of the minimum expected input voltage. Use Equation 2 and Equation 3 to calculate the values of RUVLO1 and RUVLO2. VON is the voltage threshold during power-up when the input voltage is rising. Table 4 lists standard resistor values for RUVLO1 and RUVLO2 for adjusting the VON UVLO threshold for several input voltages. 0.5 RUVLO1 = (kW ) 2.9 ´ 10-3 (2) 1.25 RUVLO2 = (kW ) æ (VON - 1.25 ) ö -3 çç ÷÷ + 0.9 ´ 10 è RUVLO1 ø (3) VIN VIN RUVLO1 INH/UVLO RUVLO2 A_VOUT Figure 36. Adjustable VIN UVLO Table 4. Standard Resistor Values to set VON UVLO Threshold VON THRESHOLD (V) 16 4.5 5.0 6.5 8.0 9.0 10.0 15.0 20.0 RUVLO1 (kΩ) 174 174 174 174 174 174 174 174 174 RUVLO2 (kΩ) 63.4 56.2 40.2 31.6 27.4 24.3 15.8 11.5 7.50 Submit Documentation Feedback 30.0 Copyright © 2012, Texas Instruments Incorporated Product Folder Links: TPS84259 TPS84259 www.ti.com SLVSBA0 – AUGUST 2012 Power-Up Characteristics When configured as shown in the application schematics, the TPS84259 produces a regulated output voltage following the application of a valid input voltage. During the power-up, internal soft-start circuitry slows the rate that the output voltage rises, thereby limiting the amount of in-rush current that can be drawn from the input source. The soft-start circuitry introduces a short time delay from the point that a valid input voltage is recognized. Figure 37 shows the start-up waveforms for a TPS84259, operating from a 12 V input and the output voltage adjusted to –5 V. The waveform were measured with a 1.5-A constant current load. Figure 37. Start-Up Sequence Light-Load Behavior The TPS84259 is a non-synchronous converter. One of the characteristics of non-synchronous operation is that as the output load current decreases, a point is reached where the energy delivered by a single switching pulse is more than the load can absorb. This energy causes the output voltage to rise slightly. This rise in output voltage is sensed by the feedback loop and the device responds by skipping one or more switching cycles until the output voltages falls back to the set point. At very light loads or no load, many switching cycles are skipped. The observed effect during this pulse skipping mode of operation is an increase in the peak to peak ripple voltage, and a decrease in the ripple frequency. The amount of load current when pulse skipping begins is a function of the input voltage, the output voltage, and the switching frequency. No-Load Operation When operating at no load or very light load and the input voltage is removed, the output voltage discharges very slowly. If the input voltage is re-applied before the output voltage discharges, the slow-start circuit does not activate and the amount of inrush current is extremely large and may cause an over-current condition. To avoid this condition the output voltage must be allowed to discharge before re-applying the input voltage. Applying a 50-mA to 100-mA minimum load helps discharge the output voltage. Additionally, monitoring the input voltage with a supervisor and shuting-down using the INH control (see Output On/Off Inhibit (INH)) activates the internal slow-start circuit. Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Links: TPS84259 17 TPS84259 SLVSBA0 – AUGUST 2012 www.ti.com Switching Frequency The recommended switching frequency of the TPS84259 is 800 kHz. To operate at the recommended switching frequency, connect the RT pin (Pin 30) to A_VOUT (at pin 32). It is recommended to adjust the switching frequency in applications with both, higher input voltage (> 18V) and lower output voltage (< –8V). For these applications, improved operating performance can be obtained by decreasing the operating frequency to 500 kHz by adding a resistor, RRT of 93.1 kΩ between the RT pin and A_VOUT as shown in Figure 38. Figure 39 shows the recommended switching frequency over input voltage and output voltage. RT RRT A_VOUT Figure 38. RRT Resistor Placement Figure 39. Recommended Switching Frequency Table 5. Standard Resistor Values For Setting Switching Frequency fSW (kHz) 500 800 RRT(kΩ) 93.1 0 (short) Synchronization (CLK) An internal phase locked loop (PLL) allows synchronization from 700 kHz to 900 kHz for 800 kHz applications, or 400 kHz to 600 kHz for 500 kHz applications. See Figure 39 to determine switching frequency based on input voltage and output voltage. To implement the synchronization feature, connect a square wave clock signal to the RT/CLK pin with a duty cycle between 25% to 75%. The clock signal amplitude must transition lower than 0.5 V and higher than 2.2 V. The start of the switching cycle is synchronized to the falling edge of RT/CLK pin. In applications requiring CLK mode, configure the device as shown in Figure 40 (800 kHz) and Figure 41 (500kHz). Before the external clock is present, the device works in RT mode where the switching frequency is set by the RRT resistor. When the external clock is present, the CLK mode overrides the RT mode. The first time the CLK pin is pulled above the RT/CLK high threshold (2.2 V), the device switches from RT mode to CLK mode and the CLK pin becomes high impedance as the PLL starts to lock onto the frequency of the external clock. It is not recommended to switch from CLK mode back to RT mode because the internal switching frequency drops to 100 kHz first before returning to the switching frequency set by the RT resistor. 3.3 V 3.3 V BAV99 BAV99 External Clock 700 kHz to 900 kHz 470 pF External Clock 400 kHz to 600 kHz 1 kΩ CLK 470 pF 1 kΩ CLK BAV99 BAV99 RT RT A_VOUT A_VOUT 93.1k GND GND Figure 40. CLK Configuration (800 kHz Typ) 18 Figure 41. CLK Configuration (500 kHz Typ) Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Links: TPS84259 TPS84259 www.ti.com SLVSBA0 – AUGUST 2012 Output On/Off Inhibit (INH) The INH pin provides electrical on/off control of the device. Once the INH pin voltage exceeds the threshold voltage, the device starts operation. If the INH pin voltage is pulled below the threshold voltage, the regulator stops switching and enters low quiescent current state. The INH pin has an internal pull-up current source, allowing the user to float the INH pin for enabling the device. If an application requires controlling the INH pin, an external level-shifter is required to interface with the pin because in a positive-to-negative buck-boost supply, the INH pin is referenced to VOUT, not GND. Adding a level-shifter (U1) as shown in Figure 42, allows the INH control to be refernced to GND. A recommended levelshifter part # is DCX144EH-7 from Diodes Inc. Pulling the input of U1 to GND applies a low voltage to the inhibit control pin and disables the output of the supply, shown in Figure 43. Releasing the input of U1 enables the device, which executes a soft-start power-up sequence, as shown in Figure 44. The device produces a regulated output voltage within 10 ms. The waveforms were measured with a 1.5-A constant current load. VIN VIN U1 RUVLO1 INH/UVLO INH Control A_VOUT RUVLO2 GND Figure 42. Typical Inhibit Control Figure 43. Inhibit Turn-Off Figure 44. Inhibit Turn-On Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Links: TPS84259 19 TPS84259 SLVSBA0 – AUGUST 2012 www.ti.com Slow-Start Circuit (SS) Connecting the STSEL pin (Pin 29) to A_VOUT while leaving SS pin (Pin 28) open, enables the internal SS capacitor with a slow-start interval of approximately 10 ms. Adding additional capacitance between the SS pin and A_VOUT increases the slow-start time. Figure 45 shows an additional SS capacitor connected to the SS pin and the STSEL pin connected to A_VOUT. See Table 6 below for SS capacitor values and timing interval. SS CSS (Optional) STSEL A_VOUT Figure 45. Slow-Start Capacitor (CSS) and STSEL Connection Table 6. Slow-Start Capacitor Values and Slow-Start Time CSS (nF) open 10 15 22 SS Time (ms) 10 15 17 20 Inrush Current During turn-on, as the TPS84259 performs a slow-start sequence, an inrush current is induced as the output capacitors charge up. The inrush current is in addition to the DC input current. The amount of inrush current depends on the input voltage, output voltage and amount of output capacitance. Table 7 shows the typical inrush current for the input voltage, output voltage and the amount of output capacitance. Increasing the slow-start capacitor reduces the inrush current by slowing down the ramp of the output voltage. See Slow-Start Circuit (SS). Table 7. Typical Inrush Current Output Capacitance → VIN (V) 5 12 24 36 (1) 20 100 µF ceramic 200 µF VOUT (V) (1) 320 µF (1) 430 µF (1) Inrush Current (A) –3.3 0.1 0.1 0.1 0.1 –5 0.1 0.2 0.2 0.3 –12 0.3 0.8 1.2 1.8 –15 0.4 1.3 2.5 3.6 –3.3 0.1 0.1 0.1 0.1 –5 0.1 0.1 0.1 0.2 –12 0.2 0.4 0.6 0.8 –15 0.3 0.5 0.9 1.3 –3.3 0.1 0.1 0.1 0.1 –5 0.1 0.1 0.2 0.2 –12 0.2 0.2 0.3 0.5 –15 0.3 0.3 0.5 0.7 –3.3 0.2 0.2 0.2 0.2 –5 0.2 0.2 0.2 0.2 –12 0.2 0.3 0.4 0.4 This amount of capacitance includes the required 100 µF of ceramic capacitance with additional bulk capacitance. Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Links: TPS84259 TPS84259 www.ti.com SLVSBA0 – AUGUST 2012 Input to Output Coupling Capacitor Adding an input to output coupling capacitor (CIO) across VIN to VOUT as shown in Figure 46 can help reduce output voltage ripple and improve transient response. A typical value for CIO is 2.2 µF ceramic with a voltage rating greater than the sum of VIN + |VOUT|. CIO TPS84259 VIN VIN -VOUT VOUT CIN COUT Figure 46. Input to Output Coupling Capacitor Overcurrent Protection For protection against load faults, the TPS84259 incorporates cycle-by-cycle current limiting. During an overcurrent condition the output current is limited and the output voltage is reduced. If the output voltage drops more than 25%, the switching frequency is lowered to reduce power dissipation within the device. When the overcurrent condition is removed, the output voltage returns to the established voltage. The TPS84259 is not designed to endure a sustained short circuit condition. The use of an output fuse, voltage supervisor circuit, or other overcurrent protection circuit is recommended. Thermal Shutdown The internal thermal shutdown circuitry forces the device to stop switching if the junction temperature exceeds 180°C typically. The device reinitiates the power up sequence when the junction temperature drops below 165°C typically. Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Links: TPS84259 21 TPS84259 SLVSBA0 – AUGUST 2012 www.ti.com Layout Considerations To achieve optimal electrical and thermal performance, an optimized PCB layout is required. Figure 47 and Figure 48 show two layers of a typical PCB layout. Some considerations for an optimized layout are: • Use large copper areas for power planes (VIN, VOUT, and GND) to minimize conduction loss and thermal stress. • Place ceramic input and output capacitors close to the module pins to minimize high frequency noise. • Locate additional output capacitors between the ceramic capacitor and the load. • Place a dedicated A_VOUT copper area beneath the TPS84259. • Isolate the PH copper area from the GND copper area using the VOUT copper area. • Connect the VOUT and A_VOUT copper areas at one point; at pins 8 & 9. • Place RSET, RRT, and CSS as close as possible to their respective pins. • Use multiple vias to connect the power planes to internal layers. • Use a dedicated sense line to connect RSET to GND near the load for best regulation. LOAD GND sense Via VOUT Plane Thermal Vias RSET GND sense Via Figure 47. Typical Top-Layer Recommended Layout 22 Figure 48. Typical VOUT-Layer Recommended Layout Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Links: TPS84259 PACKAGE OPTION ADDENDUM www.ti.com 10-Dec-2012 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Qty Drawing Eco Plan Lead/Ball Finish (2) MSL Peak Temp Samples (3) (Requires Login) TPS84259RKGR ACTIVE B1QFN RKG 41 500 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR TPS84259RKGT ACTIVE B1QFN RKG 41 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. 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