MDT10P43 1. General Description 3. Applications This 8-bit Micro-controller with built-in carrier l generator uses a fully static CMOS technology to Remote controller achieve high speed, small size, low power and high noise immunity. 4. Pin Assignment On chip memory includes 512 words of ROM, and 28 bytes of static RAM. ※ P – PDIP, S - PSOP 2. Features u Fully COMS static design u 8-bit data bus u On chip ROM size : 512 words u Internal RAM size : 28 bytes MDT10P43P11, MDT10P43S11 PA2 PA3 PA6 PA7 VSS PB0 PB1 PB2 PB3 (24general purpose registers, 4 special registers) u 34 single word instructions u 14-bit instructions u 2-level stacks u Operating voltage : 2.0V ~ 6 V u Addressing modes include direct, indirect Power-on Reset u System clock : 455KHz crystal (OSC1 cap PA5 PA2 PA3 PA6 PA7 VSS PB0 PB1 PB2 PB3 50P; OSC2 cap 100P) u PA0-7 : 8 input only pins with pull-high resistor and input low wakeup detect circuit. u PB0 : CMOS output. u PB1~7 : Seven open drain output pins. u Built in remote control carrier synthesizer 18 17 16 15 14 13 12 11 10 PA1 PA0 OSC1 OSC2 VDD PB7 PB6 PB5 PB4 MDT10P43P21, MDT10P43S21 and relative addressing modes u 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 PA4 PA1 PA0 OSC1 OSC2 VDD PB7 PB6 PB5 PB4 Fosc/8 (56.9K) or Fosc/12 (37.9K) by firmware setting. u 2048 clocks for oscillator start up time. This specification is subject to be changed without notice. Please visit our web site for the most updated information. http://www.mdtic.com.tw 1 of 10 2005.8 Ver. 1.3 MDT10P43 5. Block Diagram Stack Two Levels RAM 24×8 ROM 512×14 Port PA0~PA7 8 bits Port A 9 bits Program Counters 9 bits 14 bits Instruction Register Special Register Port PB0 D0~D7 Port B Instruction Decoder Port PB1 ~PB7 Control Circuit External XT Data 8bit Power on Reset Power Down Reset Working Register Status Register ALU This specification is subject to be changed without notice. Please visit our web site for the most updated information. http://www.mdtic.com.tw 2 of 10 2005.8 Ver. 1.3 MDT10P43 6. Pin Function Description Pin Name I/O PA0~PA7 I Function Description Port A, TTL input level. Built in 50K ohm pull-high resistor. In sleep mode, a high-to-low change on any pin will cause chip reset. PB0 O CMOS output pin PB1~PB7 O Port B open drain output pins, 50K ohm pull-high resistor. OSC1 I OSC2 O Crystal oscillation input pin Crystal oscillation output pin Vdd Power supply Vss Ground 7. Memory Map (A) Register Map Address Description 00 Indirect Addressing Register 01 Unimplemented 02 PC 03 STATUS 04 MSR 05 Port A (Input Only) 06 Port B output register (Using “CPIO PB“ Instruction change to PB Output data only) 07 08~1F Unimplemented Internal RAM, General Purpose Register (1) IAR ( Indirect Address Register) : R0 This specification is subject to be changed without notice. Please visit our web site for the most updated information. http://www.mdtic.com.tw 3 of 10 2005.8 Ver. 1.3 MDT10P43 (2) PC (Program Counter) : R2 Write PC, CALL --- always 0 LJUMP, JUMP, LCALL --- from instruction word RTIW, RET --- from STACK A9 A8 A7~A0 Write PC, JUMP, CALL --- from STATUS b5 LJUMP, LCALL --- from instruction word RTIW, RET --- from STACK Write PC --- from ALU LJUMP, JUMP, LCALL, CALL --- from instruction word RTIW, RET --- from STACK (3) STATUS (Status register) : R3 Bit Symbol Function 0 C Carry bit 1 HC Half Carry bit 2 Z Zero bit 3 PF Power loss Flag bit 4 LPT Low power detect =0 : Vdd is lower than 2.3 ~ 2.5V =1 : Vdd is higher than 2.3 ~ 2.5V 5 —— General purpose bit 6—7 —— Carrier frequency control bits =00 No carrier (default) =01 Fosc/8, 1/2 duty =10 Fosc/12, 1/2 duty =11 Fosc/12, 1/3 duty (1/3 – Hi ; 2/3 - Low) (4) MSR (Memory Select Register) : R4 (5) PORT A : R5 Bit 7-0 : Port A data input (6) CPIO PB : R6 Bit 7-1 : PB7-PB1 output register (open drain output) Bit 0 : PB0 output register (CMOS output) This specification is subject to be changed without notice. Please visit our web site for the most updated information. http://www.mdtic.com.tw 4 of 10 2005.8 Ver. 1.3 MDT10P43 8. Reset Condition for all Registers Register Address Power-On Reset IAR 00h － PC 02h 1111 1111 STATUS 03h 0001 1xxx MSR 04h 111x xxxx PB Output data 06h 1111 1110 Note : “ x “＝unknown, “ – “＝unimplemented, read as “0” 10. Instruction Set Instruction Code Mnemonic Operands Function Operating 010000 00000000 NOP No operation None 010000 00000010 SLEEP Sleep mode 0→WT, Status TF, PF stop OSC 010000 00000100 RET Return Stack→PC None 010000 00000rrr CPIO R Control I/O port register W→CPIO 010001 1rrrrrrr STWR R Store W to register W→R 011000 trrrrrrr LDR R, t Load register R→t Z 111010 iiiiiiii LDWI I Load immediate to W I→W None 010111 trrrrrrr SWAPR R, t Swap halves register [R(0~3) ↔ R(4~7)]→t None 011001 trrrrrrr INCR R, t Increment register R + 1→t Z 011010 trrrrrrr INCRSZ R, t Increment register, skip if zero R + 1→t None 011011 trrrrrrr ADDWR R, t Add W and register W + R→t C, HC, Z 011100 trrrrrrr SUBWR R, t Subtract W from register R ﹣W→t (R+/W+1→t) C, HC, Z 011101 trrrrrrr DECR R, t Decrement register R ﹣1→t Z 011110 trrrrrrr DECRSZ R, t Decrement register, skip if zero R ﹣1→t None 010010 trrrrrrr ANDWR R, t AND W and register R ∩ W→t Z 110100 iiiiiiii ANDWI i AND W and immediate i ∩ W→W Z 010011 trrrrrrr IORWR R, t Inclu. OR W and register R ∪ W→t Z 110101 iiiiiiii IORWI i Inclu. OR W and immediate i ∪ W→W Z 010100 trrrrrrr XORWR R, t Exclu. OR W and register R ♁ W→t Z r None None This specification is subject to be changed without notice. Please visit our web site for the most updated information. http://www.mdtic.com.tw 5 of 10 2005.8 Ver. 1.3 MDT10P43 Instruction Code Mnemonic Operands Function Operating Status 110110 iiiiiiii XORWI i Exclu. OR W and immediate i ♁ W→W Z 011111 trrrrrrr COMR R, t Complement register /R→t Z 010110 trrrrrrr RRR Rotate right register R(n) →R(n-1), C →R(7), C R, t R(0)→C 010101 trrrrrrr RLR R, t Rotate left register R(n)→r(n+1), C C→R(0), R(7)→C 010000 1xxxxxxx CLRW Clear working register 0→W Z 010001 0rrrrrrr CLRR Clear register 0→R Z 0000bb brrrrrrr BCR R, b Bit clear 0→R(b) None 0010bb brrrrrrr BSR R, b Bit set 1→R(b) None 0001bb brrrrrrr BTSC R, b Bit Test, skip if clear Skip if R(b)=0 None 0011bb brrrrrrr BTSS R, b Bit Test, skip if set Skip if R(b)=1 None 1000nn nnnnnnnn LCALL n Long CALL subroutine n→PC, None R PC+1→Stack 1010nn nnnnnnnn LJUMP n Long JUMP to address n→PC None 110000 nnnnnnnn CALL Call subroutine n→PC, None n PC+1→Stack 110001 iiiiiiii RTIW i Return, place immediate to W Stack→PC, None i→W 11001n nnnnnnnn JUMP n JUMP to address n→PC None Note : W CPIO HC Z C PF PC OSC Inclu. Exclu. AND : : : : : : : : : : : Working register Control I/O port register Half carry Zero flag Carry flag Power loss flag Program Counter Oscillator Inclusive ‘∪’ Exclusive ‘♁’ Logic AND ‘∩’ b : t : R i n / x Bit position Target 0 : Working register 1 : General register : : : : : General register address Immediate data ( 8 bits ) Immediate address Complement Don’t care This specification is subject to be changed without notice. Please visit our web site for the most updated information. http://www.mdtic.com.tw 6 of 10 2005.8 Ver. 1.3 MDT10P43 11. Electrical Characteristics (Operating temperature at 25℃). Sym Description Condition Max Unit 2.0 6.0 V Vdd=5V -0.6 1.0 V PA Vdd=5V 2.0 Vdd+0.6 V IIL Input leakage current Vdd=5V +/-1 µA VOL Output Low Voltage Vdd Operating voltage VIL Typ Input Low Voltage PA VIH Min Input high Voltage PB Vdd=5V, IOL=20mA 0.6 V Vdd=5V, IOL=5mA 0.2 V Vdd=5V, IOH= -20mA 2.8 V Vdd=5V, IOH= -5mA 4.2 V 1.8 V VOH Output High Voltage PB0 Vpr Power Edge-detector Reset Voltage This specification is subject to be changed without notice. Please visit our web site for the most updated information. http://www.mdtic.com.tw 7 of 10 2005.8 Ver. 1.3 MDT10P43 12. PA0 ~ PA7 Equivalent Circuit Sleep Input low wake_up PA0~7: Pull_Hi 50K Data Bus TTL Input Resistor Read TTL Input Level Port Input Pad 13. (A) PB0 Equivalent Circuit Carrier Fosc/12 Fosc/ 8 D TRIS C Reset RB Q DFFRA Latch Port Output Pad QB Data Bus Read This specification is subject to be changed without notice. Please visit our web site for the most updated information. http://www.mdtic.com.tw 8 of 10 2005.8 Ver. 1.3 MDT10P43 (B) PB1~7 Equivalent Circuit D TRIS C Reset PB Q PB1~7: Pull_Hi 50K DFFPA Latch QB Port Output Pad Data Bus Read This specification is subject to be changed without notice. Please visit our web site for the most updated information. http://www.mdtic.com.tw 9 of 10 2005.8 Ver. 1.3 MDT10P43 This specification is subject to be changed without notice. Please visit our web site for the most updated information. http://www.mdtic.com.tw 10 of 10 2005.8 Ver. 1.3