TPS92510 www.ti.com SLUSAE4A – JANUARY 2012 – REVISED AUGUST 2012 1.5-A Constant-Current Buck Converter for High-Brightness LEDs with Integrated LED Thermal Foldback Check for Samples: TPS92510 FEATURES 1 • • • • • 2 • • • • • • DESCRIPTION 3.5-V to 60-V Input Voltage Range Integrated 200-mΩ High-Side MOSFET 200 mV Internal Voltage Reference ±3% LED Current Accuracy 100 kHz to 2.5 MHz Switching Frequency Range Dedicated PWM Dimming Input LED Thermal Foldback Adjustable UVLO Overcurrent Protection Over-Temperature Protection MSOP-10 (DGQ) PowerPAD™ Package The TPS92510 is a 60-V, 1.5-A peak current-mode step-down converter with an integrated high-side MOSFET. It is specifically designed for driving highbrightness LEDs with a constant current. The tighttolerance, 200-mV internal reference voltage reduces power dissipation in the current-sense resistor. A dedicated pulse width modulation input pin allows linear control of the light output. The TPS92510 integrates a thermal foldback feature that reduces the average output current to ensure that the sensed LED temperature never exceeds a specific value, improving the reliability of the overall system. An integrated frequency synchronization feature allows a reduction of unwanted beatfrequencies in multi-string applications and simplifies EMI filtering. The adjustable input voltage UVLO feature accommodates the various deep discharge levels of multiple battery types. APPLICATIONS • • • • • Street Lighting Emergency Lighting General Illumination Industrial and Commercial Lighting MR16 LED Bulbs The TPS92510 includes cycle-by-cycle overcurrent protection, and thermal shutdown protection. It is available in a 10-pin MSOP PowerPAD™ package. SIMPLIFIED APPLICATION TSENSE BOOT VIN PH PDIM TPS92510 T EN COMP VSENSE RT/CLK GND Pad UDG-11042 1 2 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PowerPAD is a trademark of Texas Instruments. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2012, Texas Instruments Incorporated TPS92510 SLUSAE4A – JANUARY 2012 – REVISED AUGUST 2012 www.ti.com This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. ORDERING INFORMATION (1) (1) TJ PACKAGE PINS –40°C to 150°C PowerPAD Plastic Small Outline (MSOP) 10 OUTPUT SUPPLY MINIMUM QUANTITY ORDERABLE DEVICE NUMBER Tube 80 TPS92510DGQ Tape and Reel 2500 TPS92510DGQR For the most current package and ordering information see the Package Option Addendum at the end of this document, or see the TI website at www.ti.com. ABSOLUTE MAXIMUM RATINGS (1) Over operating temperature range (unless otherwise noted). VALUE Input voltage MAX VIN –0.3 65 PDIM, EN –0.3 BOOT VSENSE, TSENSE, COMP –0.3 3 RT/CLK –0.3 3.6 –0.6 65 –2 65 Source current V PAD to GND ±200 EN 100 μA BOOT 100 mA VSENSE PH RT/CLK Sink current V 8 PH PH, 10-ns Transient Voltage Difference 6 73 BOOT-PH Output voltage UNIT MIN VIN COMP, VSENSE, EN Electrostatic Discharge (HBM) QSS 009-105 (JESD22-A114A) Electrostatic Discharge (CDM) QSS 009-147 (JESD22-C101B.01) mV 10 μA Current Limit A 100 μA Current Limit A 100 μA 2 kV 500 V Operating junction temperature, TJ –40 150 °C Storage temperature, Tstg –65 150 °C (1) 2 Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Links: TPS92510 TPS92510 www.ti.com SLUSAE4A – JANUARY 2012 – REVISED AUGUST 2012 THERMAL INFORMATION TPS92510 THERMAL METRIC (1) MSOP UNITS 10 PINS Junction-to-ambient thermal resistance (2) θJA 66.7 (3) θJCtop Junction-to-case (top) thermal resistance θJB Junction-to-board thermal resistance (4) 37.5 ψJT Junction-to-top characterization parameter (5) 1.8 ψJB Junction-to-board characterization parameter (6) 37.1 θJCbot Junction-to-case (bottom) thermal resistance (7) 15.4 (1) (2) (3) (4) (5) (6) (7) 45.8 °C/W For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953. The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, high-K board, as specified in JESD51-7, in an environment described in JESD51-2a. The junction-to-case (top) thermal resistance is obtained by simulating a cold plate test on the package top. No specific JEDECstandard test exists, but a close description can be found in the ANSI SEMI standard G30-88. The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB temperature, as described in JESD51-8. The junction-to-top characterization parameter, ψJT, estimates the junction temperature of a device in a real system and is extracted from the simulation data for obtaining θJA, using a procedure described in JESD51-2a (sections 6 and 7). The junction-to-board characterization parameter, ψJB, estimates the junction temperature of a device in a real system and is extracted from the simulation data for obtaining θJA , using a procedure described in JESD51-2a (sections 6 and 7). The junction-to-case (bottom) thermal resistance is obtained by simulating a cold plate test on the exposed (power) pad. No specific JEDEC standard test exists, but a close description can be found in the ANSI SEMI standard G30-88. Spacer RECOMMENDED OPERATING CONDITIONS over operating free-air temperature range (unless otherwise noted) MIN PWM dimming input frequency 120 PWM dimming minimum on-time 10 VVIN Input voltage 3.5 tON(min) High-side MOSFET on-time 350 IL(pk-pk) Peak-to-peak inductor current 150 TJ Operating junction temperature –40 NOM MAX UNIT 1000 Hz µs 60 mA 125 Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Links: TPS92510 V ns °C 3 TPS92510 SLUSAE4A – JANUARY 2012 – REVISED AUGUST 2012 www.ti.com ELECTRICAL CHARACTERISTICS –40°C ≤ TJ ≤ 125°C, VVIN = 12 V (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT SUPPLY VOLTAGE (VIN PIN) VVIN Input voltage VUVLO Internal undervoltage lockout threshold No voltage hysteresis, rising and falling 3.5 2.5 60 IVINSD Shutdown supply current VEN = 0 V, TA=25°C, 3.5 V ≤ VVIN ≤ 60 V 1.3 4 IVIN Non-switching supply current VVSENSE = 210 mV, TA=25°C 305 400 1.22 1.34 V V μA ENABLE AND UVLO (EN PIN) VEN Enable threshold voltage Input current No voltage hysteresis, rising and falling, 25°C 1.10 VREF threshold +50 mV –3.8 VREF threshold –50 mV –0.9 Hysteresis current V μA μA –2.9 VOLTAGE REFERENCE VREF Voltage reference 3.5 ≤ VVIN ≤ 60 V, TJ = 25°C 194 3.5 ≤ VVIN ≤ 60 V, -40°C ≤ TJ ≤ 125°C 190 200 206 210 mV HIGH-SIDE MOSFET RDS(on) VVIN = 3.5 V, (VBOOT– VPH) = 3 V 300 VVIN = 12 V, (VBOOT– VPH) = 6 V 200 50 nA Error amplifier transconductance gain –2 μA < ICOMP < 2 μA, VCOMP = 1 V 310 μA/V Error amplifier dc gain VVSENSE = 0.2 V 10 kV/V 2.7 MHz On-resistance 410 mΩ ERROR AMPLIFIER Input current gM(ea) Error amplifier bandwidth Error amplifier source/sink VCOMP = 1 V, 100 mV overdrive COMP to switch current transconductance ±27 μA 10.5 A/V 4.0 A 150 °C 20 °C CURRENT LIMIT Current limit threshold TJ = 25°C 2.5 THERMAL SHUTDOWN TSD Thermal shutdown Thermal shutdown hysteresis TIMING RESISTOR AND EXTERNAL CLOCK (RT/CLK PIN) fSW Switching frequency range using RT mode fSW Switching frequency 100 RRT = 200 kΩ Switching frequency range using CLK mode 450 581 300 Minimum CLK input pulse width 40 RT/CLK high threshold 1.9 RT/CLK low threshold 0.5 RT/CLK falling edge to PH rising edge delay Measured at 500 kHz with RT resistor in series Phase loop (PLL) lock-in time fSW = 500 kHz 2500 kHz 720 kHz 2200 kHz ns 2.2 V 0.7 V 60 ns 100 μs PWM DIMMING (PDIM) VIH High-level input voltage VIL Low-level input voltage 1.35 0.75 1.55 0.90 V V THERMAL FOLDBACK PROTECTION (TSENSE) PWM ramp valley voltage 0 100 250 1.75 1.95 2.15 V PWM frequency 3.5 6.0 9.0 kHz Current source 70 95 125 μA PWM ramp peak voltage 4 Submit Documentation Feedback mV Copyright © 2012, Texas Instruments Incorporated Product Folder Links: TPS92510 TPS92510 www.ti.com SLUSAE4A – JANUARY 2012 – REVISED AUGUST 2012 DEVICE INFORMATION TPS92510 MSOP-10 (Top View) BOOT 1 10 PH VIN 2 9 GND EN 3 8 COMP PDIM 4 7 VSENSE RT/CLK 5 6 TSENSE PIN FUNCTIONS PIN I/O DESCRIPTION NAME NO. BOOT 1 O A bootstrap capacitor is required between BOOT and PH. If the voltage on this capacitor is below the minimum required by the output device, the output is forced to switch off until the capacitor is refreshed. COMP 8 O Error amplifier output, and input to the output switch current comparator. Connect frequency compensation components to this pin. EN 3 I Enable pin, internal pull-up current source. Pull below 1.2-V to disable. Float to enable. Adjust the input undervoltage lockout with two resistors. GND 9 – Ground PDIM 4 I PWM dimming input pin. The duty cycle of the PWM signal linearly controls the average current output of the converter. 10 O The source of the internal high-side MOSFET. Pad – GND pin must be electrically connected to the exposed pad on the printed circuit board for proper operation. PH PowerPAD RT/CLK 5 I Resistor timing and external clock. An internal amplifier holds this pin at a fixed voltage when using an external resistor to ground to program the switching frequency. If the pin is pulled above the PLL upper threshold, a mode change occurs and the pin becomes a synchronization input. The internal amplifier is disabled and the pin becomes a high impedance clock input to the internal PLL. If the clocking edges stop, the internal amplifier is re-enabled and the mode returns to the resistor-programmed function. TSENSE 6 I Temperature fold-back pin. An NTC thermistor connected from this pin to ground provides a thermal feedback to decrease the average LED current as the sensed LED temperature increases. It is recommended to bypass this pin with a capacitor with a value of 0.01 µF (or larger) to GND. VIN 2 I Input supply voltage, 3.5 V to 60 V. VSENSE 7 I Inverting node of the transconductance (gM) error amplifier. Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Links: TPS92510 5 TPS92510 SLUSAE4A – JANUARY 2012 – REVISED AUGUST 2012 www.ti.com FUNCTIONAL BLOCK DIAGRAM 2.9 µA Thermal Shutdown VIN UVLO 0.9 µA EN + VSENSE 7 Error Amplifier Shutdown Logic R S + 1 µA PDIM + 4 BOOT 10 PH BOOT UVLO COMP S/H + 200 mV 1 Enable Comparator 1.25 V 8 VIN BOOT Charge 3 COMP 2 R R PDIM Comparator 1.35 V Logic and PWM Latch R Q S Current Sense EA Clamp Slope Compensation Oscillator with PLL PowerPAD 100 µA TSENSE 6 + Temperature Comparator 9 GND 2V 5.9 kHz 0V TPS92510 5 UDG-11043 RT/CLK 6 Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Links: TPS92510 TPS92510 www.ti.com SLUSAE4A – JANUARY 2012 – REVISED AUGUST 2012 TYPICAL CHARACTERISTICS 210 VIN = 12 V 208 400 Voltage Reference (mV) Static D−to−S On−Resistance (mΩ) 500 300 200 100 BOOT–PH = 3 V BOOT–PH = 6 V 0 −40 −25 −10 5 20 35 50 65 80 Junction Temperature (°C) 95 206 204 202 200 198 196 194 192 190 −40 −25 −10 110 125 G000 Figure 1. On-Resistance vs. Junction Temperature 5 20 35 50 65 80 Junction Temperature (°C) 95 110 125 G000 Figure 2. Reference Voltage vs. Junction Temperature 4.3 590 VIN = 12 V Switching Frequency (kHz) 4.2 Switch Current Limit (A) VIN = 12 V 4.1 4 3.9 3.8 3.7 3.6 585 VIN = 12 V RRT = 200 kΩ 580 575 570 565 3.5 3.4 −40 −25 −10 5 20 35 50 65 80 Junction Temperature (°C) 95 560 −40 −25 −10 110 125 G000 Figure 3. Switch Current vs. Junction Temperature 95 110 125 G000 Figure 4. Switching Frequency vs. Junction Temperature 2500 500 VIN = 12 V T J =25°C High Frequency Range 2000 1500 1000 500 0 0 75 100 125 150 175 25 50 200 Timing and External Clock (RT /CLK ) Resistance (kW) Figure 5. Switching Frequency vs. RT/CLK Resistance VIN = 12 V Switching Frequ ency (kHz) Switching Frequ ency (kHz) 5 20 35 50 65 80 Junction Temperature (°C) T J =25°C Low Frequency Range 400 300 200 100 0 200 400 1200 600 800 1000 Timing and External Clock (RT/CLK) Resistance (kW ) Figure 6. Switching Frequency vs. RT/CLK Resistance Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Links: TPS92510 7 TPS92510 SLUSAE4A – JANUARY 2012 – REVISED AUGUST 2012 www.ti.com 1.40 VIN = 12 V VIN = 12 V 450 1.35 Enable Threshold (V) Error Amplifier Transconductance (µA/V) TYPICAL CHARACTERISTICS (continued) 500 400 350 300 250 1.30 1.25 1.20 1.15 200 −40 −25 −10 5 20 35 50 65 80 Junction Temperature (°C) 95 1.10 −40 −25 −10 110 125 G000 Figure 7. Error Amplifier Transconductance vs. Junction Temperature G000 T J =25°C 3.50 3.00 1 .5 Q uiesce nt Curren t (mA) Shutdown Quiescent Current (µA) 110 125 2 .0 2.50 2.00 1.50 1.00 0.50 1 .0 0 .5 VIN = 12 V 0.00 −40 −25 −10 5 20 35 50 65 80 Junction Temperature (°C) 95 110 125 0 G000 0 Figure 9. Shutdown Quiescent Current vs. Junction Temperature 20 30 40 Input Voltage (V) 50 60 −3.80 VIN = 12 V VEN_THRESHOLD –50 mV −0.92 −3.85 Enable Current (µA) −0.94 −0.96 −0.98 −1.00 −1.02 −1.04 −1.06 VIN = 12 V VEN_THRESHOLD +50 mV −3.90 −3.95 −4.00 −4.05 −4.10 −4.15 −1.08 −1.10 −40 −25 −10 10 Figure 10. Shutdown Quiescent Current vs. Input Voltage −0.90 Enable Current (µA) 95 Figure 8. Enable Voltage vs. Junction Temperature 4.00 5 20 35 50 65 80 Junction Temperature (°C) 95 110 125 −4.20 −40 −25 −10 G000 Figure 11. Enable Current vs. Junction Temperature 8 5 20 35 50 65 80 Junction Temperature (°C) 5 20 35 50 65 80 Junction Temperature (°C) 95 110 125 G000 Figure 12. Enable Current vs. Junction Temperature Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Links: TPS92510 TPS92510 www.ti.com SLUSAE4A – JANUARY 2012 – REVISED AUGUST 2012 TYPICAL CHARACTERISTICS (continued) 320 VIN = 12 V VVSENSE = 210 mV 316 Input Supply Current (µA) Input Supply Current (µA) 318 314 312 310 308 306 304 302 300 −40 −25 −10 5 20 35 50 65 80 Junction Temperature (°C) 95 110 125 330 320 310 300 290 280 270 260 250 240 230 220 210 200 5 10 15 20 25 30 35 40 Input Voltage (V) 45 50 55 60 G000 Figure 14. Input Supply Current vs. Input Voltage 2.20 2.55 Input Voltage UVLO (V) 2.15 BOOT−PH UVLO (V) 0 G000 Figure 13. Input Supply Current vs. Junction Temperature 2.10 2.05 2.00 1.95 1.90 −40 −25 −10 TJ = 25°C VVSENSE = 210 mV 5 20 35 50 65 80 Junction Temperature (°C) 95 110 125 2.54 2.53 2.52 2.51 2.50 −40 −25 −10 G000 5 20 35 50 65 80 Junction Temperature (°C) 95 110 125 G000 Figure 15. BOOT-PH UVLO vs. Junction Temperature Figure 16. Input Voltage UVLO vs. Junction Temperature Figure 17. PDIM Rising Figure 18. PDIM Falling Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Links: TPS92510 9 TPS92510 SLUSAE4A – JANUARY 2012 – REVISED AUGUST 2012 www.ti.com TYPICAL CHARACTERISTICS (continued) Figure 19. Enable Rising Figure 20. Enable Falling Figure 21. TSENSE and High-Side MOSFET 10 Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Links: TPS92510 TPS92510 www.ti.com SLUSAE4A – JANUARY 2012 – REVISED AUGUST 2012 OVERVIEW The TPS92510 is a 60-V, 1.5-A, step-down (buck) regulator with an integrated high-side N-channel MOSFET. To improve performance during line and load transients the device implements a constant frequency, peak-current mode control which reduces output capacitance and simplifies external frequency compensation design. The wide switching frequency of 100 kHz to 2500 kHz allows for efficiency and size optimization when selecting the output filter components. The switching frequency is adjusted using a resistor to ground on the RT/CLK pin. The device has an internal phase lock loop (PLL) on the RT/CLK pin that is used to synchronize the power switch turn on to a falling edge of an external system clock. The TPS92510 has a default start up voltage of approximately 2.5 V. The EN pin has an internal pull-up current source that can be used to adjust the input voltage under voltage lockout (UVLO) threshold with two external resistors. In addition, the pull up current provides a default condition. When the EN pin is floating the device operates. The operating current is 138 μA when not switching and under no load. When the device is disabled, the supply current is 1.3 μA. The integrated 200 mΩ high-side MOSFET allows for high efficiency power supply designs capable of delivering 1.5 A of continuous current to a load. The TPS92510 reduces the external component count by integrating the boot recharge diode. The bias voltage for the integrated high-side MOSFET is supplied by a capacitor on the BOOT to PH pin. The boot capacitor voltage is monitored by an UVLO circuit and turns the high-side MOSFET off when the boot voltage falls below a preset threshold. The TPS92510 can operate at high duty cycles because of the boot UVLO. DETAILED DESCRIPTION Start-Up The VIN and EN UVLO conditions must be satisfied before the TPS92510 is allowed to switch. When the EN pin is held low the device enters a low-power shutdown mode, and some internal circuits are deactivated to conserve power. When EN returns high these circuits are enabled, which results in a delay of approximately 50 µs (typical) before switching starts. During start-up the TPS92510 operates in a minimum pulse width mode, which is an open-loop control. At the start of each switching cycle the internal oscillator initiates a SET pulse. The high-side MOSFET turns on with a minimum pulse width of 300 ns (typical), independent of the COMP voltage. The device does not pulse skip. While operating in minimum pulse width mode the LED bypass capacitor is being charged, causing an in-rush current. Also, the COMP voltage begins to rise as the error amplifier output current charges the compensation network. When the COMP voltage reaches approximately 0.7 V, the error amplifier is ensured to be out of saturation and to have sufficient gain to regulate the loop. The TPS92510 then transitions from minimum pulse width mode to regulation mode. During regulation mode the error amplifier is now in closed-loop control of the system. The gain of the error amplifier quickly increases the duty cycle, which causes the output voltage to increase. Once the output voltage approaches the forward voltage of the LED string the LED current quickly begins to increase until it reaches regulation. There is a slight delay from the time the VIN and EN UVLO conditions are satisfied until the time the error amplifier has control of the feedback loop. This delay is a result of the time it takes COMP to charge the compensation components to 0.7 V. This delay can be approximated as shown in Equation 1 . tDELAY = C1´ (0.7 V - (R1´ 32 mA )) 32 mA where • • C1 is the integrator capacitor from COMP to GND R1 is the resistor in series with the integrator capacitor (1) Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Links: TPS92510 11 TPS92510 SLUSAE4A – JANUARY 2012 – REVISED AUGUST 2012 www.ti.com DETAILED DESCRIPTION (continued) The peak in-rush current can be calculated to a first approximation using Equation 2. VIN ´ tON(min ) ´ fSW IPEAK = L + RSENSE COUT where • tON(min) is the minimum on-time and can be between 200 ns and 300 ns (2) Minimum Pulse Width Limitations The TPS92510 is designed to output a minimum pulse width during each switching cycle of 280 ns (typical). The control loop cannot regulate the system to an on-time less than this amount, and it does not skip pulses. When attempting to operate below the minimum on-time the system loses regulation and the LED current increases. This puts a practical limitation on the system operating conditions, as shown in Equation 3. VOUT VIN = fSW ´ tON(min ) where • VOUT equals the forward voltage of the LED string plus the reference voltage (3) The system can avoid this operating condition by limiting the maximum input voltage as shown in Equation 3 . If the input voltage cannot be limited due to application, then the switching frequency can be lowered, or the output voltage increased. This region of operation typically occurs with high input voltages, high operating frequencies, and low output voltages (one LED). Enable and Adjusting Undervoltage Lockout The TPS92510 is enabled when the VIN pin voltage is above 2.5 V and when the EN pin voltage is above 1.25 V. The VIN pin voltage threshold has no hysteresis. Figure 22 shows how to use the EN pin to adjust the input voltage UVLO to a higher threshold and increase the input voltage hysteresis. The EN pin has an internal pull-up current source, I1, of 0.9 µA that provides a default ON state when the EN pin is floating. Once the EN pin voltage exceeds 1.25 V, an additional 2.9 µA of hysteresis, IHYS, is added. This additional current provides some input voltage hysteresis. Use Equation 4 to set the external hysteresis for the input voltage. Use Equation 5 to set the input start voltage. When the EN pin is held low the internal regulators are shut down and the device enters a low-power mode. In addition, the error amplifier output discharges the COMP voltage through a diode path to GND. TPS92510 VIN 2 I1 0.9 mA R1 EN IHYS 2.9 mA RESD + 3 1.25 V VEN R2 UDG-11051 Figure 22. Adjustable Undervoltage Lockout (UVLO) R1 = 12 ( ) VHYS ´ VEN - (I1´ RESD ) - IHYS ´ RESD ´ VSTART IHYS ´ VEN (4) Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Links: TPS92510 TPS92510 www.ti.com SLUSAE4A – JANUARY 2012 – REVISED AUGUST 2012 DETAILED DESCRIPTION (continued) R2 = ( ( )) R1´ VEN - RESD ´ (I1 + IHYS ) (VSTOP - VEN ) + (I1 + IHYS )´ (R1 + RESD ) (5) VHYS = VSTART - VSTOP RESD = 10kW (6) (7) Fixed Frequency PWM Control The TPS92510 uses an adjustable, fixed-frequency, peak current mode control. Each switching cycle an internal oscillator initiates the turn-on of the MOSFET. The LED current flows through the sense resistor and develops the feedback voltage on the VSENSE pin. The error amplifier output (COMP pin) is compared to the high-side MOSFET current. When the MOSFET current reaches the level set by the COMP pin voltage the MOSFET is turned off. Slope Compensation The TPS92510 adds a compensating ramp to the MOSFET current signal. The slope compensation prevents sub-harmonic oscillations. The available peak inductor current remains constant over the full duty-cycle range. Constant Switching Frequency and Timing Resistor (RT/CLK Pin) The switching frequency of the TPS92510 is adjustable over a wide range from approximately 100 kHz to 2500 kHz by placing a resistor on the RT/CLK pin. The RT/CLK pin voltage is typically 0.5V and must have a resistor to ground to set the switching frequency. To determine the timing resistance for a given switching frequency, use Equation 8 or the curves in Figure 5 or Figure 6. To reduce the solution size one typically sets the switching frequency as high as possible, but tradeoffs of the supply efficiency, maximum input voltage and minimum controllable on time should be considered. The minimum controllable on time limits the maximum operating input voltage. XXX RRT (kW ) = 206033 (fSW )1.0888 (kHz ) (8) æ 1 ö ç ÷ öè 1.0888 ø æ fSW (kHz ) = ç 206033 ÷ ç R (kW ) ÷ è RT ø (9) Synchronization to an External System Clock (RT/CLK) The RT/CLK pin can be used to synchronize the regulator to an external system clock by connecting a square wave to the RT/CLK pin through the circuit network as shown in Figure 23. The square wave amplitude must transition lower than 0.5 V and higher than 2.2 V on the RT/CLK pin and have an on-time greater than 40 ns and an off-time greater than 40 ns. The synchronization frequency range is 300 kHz to 2200 kHz. The rising edge of the PH is synchronized to the falling edge of RT/CLK pin signal. The external synchronization circuit default frequency is set by connecting the resistor from the RT/CLK pin to ground should the synchronization signal turn off. It is recommended to use a frequency set resistor connected as shown in Figure 23 through a 50-Ω resistor to ground. The resistor should set the switching frequency close to the external CLK frequency. It is recommended to ac couple the synchronization signal through a 470-pF ceramic capacitor to RT/CLK pin and a 4-kΩ series resistor. The series resistor reduces PH jitter in heavy load applications when synchronizing to an external clock and in applications which transition from synchronizing to RT mode. The first time the CLK is pulled above the CLK threshold the device switches from the RT resistor frequency to PLL mode. The internal 0.5-V voltage source is removed and the CLK pin becomes high impedance as the PLL starts to lock onto the external signal. Since there is a PLL on the regulator the switching frequency can be higher or lower than the frequency set with the external resistor. The device transitions from the resistor mode to the PLL mode and then increases or decreases the switching frequency until the PLL locks onto the CLK frequency within 100 microseconds. Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Links: TPS92510 13 TPS92510 SLUSAE4A – JANUARY 2012 – REVISED AUGUST 2012 www.ti.com When the device transitions from the PLL to resistor mode, the switching frequency slows down from the CLK frequency to 150 kHz, then reapply the 0.5-V voltage and the resistor then sets the switching frequency. It is not recommended that a system transition from PLL mode to resistor mode repeatedly during operation. When the PLL loses the external clock input the default 150-kHz switching frequency creates long on-times, which result in higher inductor ripple currents. This can lead to inductor saturation if the system is not designed to operate at this frequency. Figure 24, shows the device synchronized to an external system clock in continuous conduction mode (CCM). TPS92510 470 pF 4 kW RRT RT/CLK 5 External Clock Source PH Phase-Lock Loop (PLL) 50 W EXT IL UDG-11052 Figure 23. Synchronizing to a System Clock Figure 24. Plot of Synchronizing in CCM Error Amplifier The TPS92510 error amplifier is a transconductance amplifier. It compares the VSENSE voltage to the internal 0.2-V voltage reference. The transconductance (gm) of the error amplifier is 310 μA/V. The frequency compensation components are connected from the COMP pin to ground. Voltage Reference and Output Current The internal voltage reference is accurate to ± 5% over temperature. The LED current is programmed with a sense resistor from the VSENSE pin to GND. It is recommended to use a 1% tolerance resistor, or better. PWM Dimming The TPS92510 incorporates a PWM dimming input pin, which directly controls the enable/disable state of the internal gate driver. When PDIM is low, the gate driver is disabled. The PDIM pin has a 1-µA pull-up current source, which creates a default ON state when the PDIM pin is floating. When PDIM goes low and the gate driver shuts off, and the LED current quickly reduces to zero. The TPS92510 uses a sample-and-hold switch on the error amplifier output. During the PDIM off-time the COMP voltage remains unchanged. Also, the error amplifier output is internally clamped low. These techniques help the system recover to its regulation duty cycle quickly. Duty Cycle and Bootstrap Voltage (BOOT) The TPS92510 requires a small 0.1-µF ceramic capacitor between the BOOT and PH pins to provide the gate drive voltage for the high-side MOSFET. The BOOT capacitor is refreshed when the high-side MOSFET turns off, and the freewheeling diode conducts. A ceramic capacitor with an X7R or X5R dielectric and a minimum voltage rating of 10 V is recommended. 14 Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Links: TPS92510 TPS92510 www.ti.com SLUSAE4A – JANUARY 2012 – REVISED AUGUST 2012 The TPS92510 is designed to operate up to 100% duty cycle as long as the BOOT to PH voltage is greater than 2.1V. If the BOOT capacitor voltage drops below 2.1 V, then the BOOT UVLO circuit turns off the MOSFET, which allows the BOOT capacitor to be refreshed. The current required from the BOOT capacitor to keep the MOSFET on is quite low. Therefore, many switching cycles occur before the BOOT capacitor is refreshed. In this way, the effective duty cycle of the converter is quite high. Attention must be taken in maximum duty cycle applications which experience extended time periods with little or no load current. When the voltage across the BOOT capacitor falls below the 2.1 V UVLO threshold, the highside MOSFET is turned off, but there may not be enough inductor current to pull the PH pin down to recharge the BOOT capacitor. The high-side MOSFET of the regulator stops switching because the voltage across the BOOT capacitor is less than 2.1 V. The output capacitor then decays until the difference between the input voltage and output voltage is greater than 2.1 V, at which point the BOOT UVLO threshold is exceeded, and the device starts switching again until the desired output current is reached. This operating condition persists until the input voltage and/or the load current increases. It is recommended to adjust the VIN stop voltage greater than the BOOT UVLO trigger condition at the minimum load of the application using the adjustable VIN UVLO feature with resistors on the EN pin. Overcurrent Protection An overcurrent fault condition is unlikely. It can be the result of a shorted sense resistor, or a direct short from VOUT to GND. In either case, the voltage at the VSENSE pin is zero, and this causes the COMP pin voltage to rise. When VCOMP reaches approximately 2.2 V it is internally clamped, and functions as a MOSFET current limit. The TPS92510 limits the MOSFET current to 4 A (typical). If the shorted condition persists the TPS92510 junction temperature increases. If it increases above 150°C, the thermal shutdown protection is activated. LED Thermal Foldback Protection The TPS92510 implements a thermal foldback protection to limit the LED temperature in case of a system failure, such as an incorrectly programmed LED current, a poor thermal design or increasing thermal impedance over time. A 100-µA current source generates a voltage across an NTC resistor that is located near the LED load. When the NTC voltage drops below 2 V at the TSENSE pin (due to excessive LED temperature) the device begins to modulate the converter at a frequency of 5.9 kHz. The more the NTC voltage drops, the longer the offtime of the converter. Therefore, the delivered output power is reduced until the NTC cools, the TSENSE voltage (VTSENSE) increases, and the system no longer requires reduced output power. The thermal foldback protection slowly reduces the output power, as a function of the thermal time constant. Thermal foldback protection is intended for protection only. It is not intended to be used as a regulation feature. During thermal foldback the error amplifier output is internally clamped low, and the COMP sample-and-hold switch is open, preserving the COMP pin voltage. Figure 25 shows the thermal foldback linearity. 100 Normalized LED Current (%) 90 80 70 60 50 40 30 20 10 0 0 0.5 1 1.5 TSENSE Voltage (V) 2 2.5 G000 Figure 25. Thermal Foldback Linearity Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Links: TPS92510 15 TPS92510 SLUSAE4A – JANUARY 2012 – REVISED AUGUST 2012 www.ti.com Over-Temperature Fault Protection When the TPS92510 junction temperature reaches 150ºC, the driver immediately disables the high-side MOSFET. The COMP sample-and-hold switch closes, and the COMP pin internally clamps low until the junction temperature drops by approximately 20ºC. At this time, the COMP clamp is removed and the driver attempts to regulate. APPLICATION INFORMATION Open LED Fault Protection An open circuit can be the result of an open LED or an open wire connection. In either case, the voltage at the VSENSE pin becomes zero, and this causes the COMP pin voltage to rise, commanding wide duty cycles. The output voltage eventually rises to the input voltage. This is a safe operating mode, provided that the output capacitors are rated for the input voltage potential. As shown in Figure 26, a transient voltage suppressor (TVS) device from VOUT to GND, or a diode from VOUT to the VIN pin can be used to clamp the L-C resonant output voltage ringing caused by the inductor and the output capacitor at the moment the LED string opens, particularly at high-input voltage and high-output voltage operating conditions. The TVS should have a voltage rating greater than the maximum output voltage, so that it does not conduct under normal operation. Either of these devices can be used to limit the output voltage to safe levels during an open LED fault. If the current sense resistor also opens, current attempts to flow into the ESD structure of the VSENSE pin. To prevent damage to the device, a series resistor (RESD) on the VSENSE pin can be used to limit this current. The VSENSE pin has an internal, 8-V clamp, and the continuous current should be limited to a maximum of 20 mA. 6 1 TSENSE BOOT 2 VIN 4 PDIM 3 EN 8 COMP PH 10 TPS92510 TVS RESD VSENSE 5 7 RT/CLK GND Pad 9 UDG-11108 Figure 26. Output Voltage Clamp An external overvoltage protection circuit consisting of VZ and RZ shown in Figure 27, can be applied to the VSENSE pin to regulate the output voltage to less than the input voltage potential. 16 Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Links: TPS92510 TPS92510 www.ti.com SLUSAE4A – JANUARY 2012 – REVISED AUGUST 2012 6 1 TSENSE BOOT 2 VIN 4 PDIM 3 EN 8 COMP PH 10 TPS92510 VZ RESD VSENSE 5 RZ 7 RT/CLK GND Pad 9 UDG-11109 Figure 27. Output Voltage Limiter Shorted LED(s) Fault Protection Some LEDs fail to a shorted state. It is unlikely that multiple LEDs fail short simultaneously. If a bypass capacitor is in parallel with the LED string it is charged to the LED string forward voltage. When one or more LEDs instantaneously short, the bypass capacitor senses a voltage transient from the initial LED string voltage to something less, depending on the number of LEDs that are now shorted. The voltage change across the capacitor causes the capacitor to discharge some energy in the form of a transient current through the LED string. This current flows from the bypass capacitor through the LED string, but not through the current sense resistor. Therefore, the TPS92510 does not sense the fault event, and does not respond to it. The peak transient current is a function of the change in forward voltage due to the shorted LED(s), and the dynamic resistance of the LED string at the moment the short occurs. This current can be substantial, and may require a protection circuit as shown in Figure 28, unless the LEDs can survive the transient current. After the LED has shorted the error amplifier continues to regulate the programmed LED current at the new, lower output voltage. PH VIN 2 LBUCK LLIMIT 10 C OUT short R ESR DI R SENSE UDG-11110 Figure 28. LED Current Limiter Due to a Shorted LED Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Links: TPS92510 17 TPS92510 SLUSAE4A – JANUARY 2012 – REVISED AUGUST 2012 www.ti.com Equation 10 shows how to reduce the peak transient current (ΔI) by adding a series inductance (LLIMIT). Typically, the bypass capacitor (COUT) is used to reduce the high-frequency ripple current through the LED. Adding inductance into this path is counter productive. Alternatively, the buck inductance, or switching frequency can be increased to achieve a lower LED ripple current. In this way, the output capacitor can be reduced in value, which allows LLIMIT to be smaller. The end result of low LED ripple current can still be achieved. Reducing the output capacitor (COUT) does not reduce the magnitude of the transient current, but it does reduce the settling time. DVF DI = L RDYNAMIC + RESR + LIMIT COUT (10) Open Current Sense Resistor Fault Protection An open current sense resistor is unlikely, but may be caused by a failing resistor, an open solder joint, or an open PCB trace. As the current sense resistor opens, the output voltage quickly rises due to the energy stored in the inductor, similar to an open LED fault. Therefore, it is necessary to clamp the output voltage, either with a TVS to GND or a diode from VOUT to VIN. It is also necessary to use a current limiting resistor on the VSENSE pin. Otherwise, the output voltage spike causes the VSENSE voltage to break down its internal ESD structure. The ESD device should be limited to 20 mA. In this condition, the converter attempts to regulate the output current through the ESD structure, which results in a very low regulated current. Typically, the output voltage overcharges and holds the VSENSE voltage high within a few switching cycles. The device stops switching, and there is a long off-time between consecutive start-up attempts. The consecutive attempts result in lower peak current through the ESD structure than the initial event. Shorted Output Fault A shorted output fault is considered rare, because the system does not require any single component from VOUT to GND. Therefore, a single component failure cannot cause this fault condition. If this failure mode were to occur it would most likely be due to a mechanical short, or a foreign object. In the unlikely event of this failure mode, the TPS92510 responds in the following way. With the output voltage shorted directly to ground the COMP voltage saturates high, because the feedback voltage is zero. The controller would naturally command wide duty cycle PH pulses. However, as soon as the gate driver turns on, very quickly an overcurrent event is detected and the PH pulse is truncated. This results in minimum on-time pulses at the PH node. Depending upon the impedance of the short, large currents can build up in the inductor, which naturally raises the junction temperature of the TPS92510. The over-temperature protection feature protects the device. Control-to-Output Transfer Function The TPS92510 converter uses peak current mode control in order to regulate the average LED current. Slope compensation is utilized internally to eliminate sub-harmonic oscillations over a wide range of operating duty cycles. To properly compensate the closed-loop system the control to output gain characteristics must be calculated. The control to output transfer function is shown in Equation 11. GC2O (s ) = 167 ´ 10-6 ´ fM ´ RSENSE ´ Gi (s ) 1 + 17 ´ 10-6 ´ fM ´ Gi (s )´ He (s ) - fM ´ GV ´ Gi (s )´ ZOUT (s ) where • RSENSE is the LED current sense resistance (11) 3 fM = 117 ´ 10 ´ L ´ fSW VIN - VOUT + 3 ´ fSW ´ L where • • 18 L is the output inductance fSW is the switching frequency in Hz Submit Documentation Feedback (12) Copyright © 2012, Texas Instruments Incorporated Product Folder Links: TPS92510 TPS92510 www.ti.com SLUSAE4A – JANUARY 2012 – REVISED AUGUST 2012 Gi (s ) = VIN æ ö 1 ç RESR + ÷ ´ RLED s ´ C OUT ø è s ´ L + RDCR + RSENSE + æ ö 1 ç RESR + ÷ + RLED s ´ COUT ø è where • • • • RDCR is the DC resistance of the output inductor COUT is the output capacitance. RESR is the equivalent series resistance of the output capacitor RLED is the dynamic resistance of the entire LED string and is dependent upon the LED current (ILED) (13) 2 He (s ) = 1 + GV = s s + 2 -2 ´ fSW (p ´ f SW ) (14) VOUT 117.2 ´ 103 ´ L ´ VIN ´ fSW (15) æ ö 1 RLED ´ ç RESR + ÷ s ´ COUT ø è + RSENSE ZOUT = æ ö 1 RLED + RESR + ç ÷ è s ´ COUT ø (16) VOUT = VF ´ n + 0.2 V where • • VF is the forward voltage of an individual LED n is the number of LEDs in the string (17) The control-to-output transfer function can be understood best by plotting it using a computer aided mathematics program such as Mathcad. The resulting plot shows that the control to output DC gain is typically very low, which can also be computed with Equation 18. 167 ´ VIN ´ fM ´ RSENSE GDC = 17 ´ VIN ´ fM + 1000000 ´ RDCR + RSENSE + RLED - fM ´ VIN ´ GV ´ (RSENSE + RLED ) ( ) (18) Compensating the Loop The control-to-output transfer function is compensated by the error amplifier in order to accomplish the following functions. • more DC gain is required for better current regulation • more bandwidth is desired for better PWM dimming and transient performance • adequate phase margin is needed for system stability The TPS92510 utilizes peak current mode control, which effectively reduces the power stage’s second order pole to a first order pole. A single pole power stage can be compensated easily with a single capacitor from COMP to GND, which forms a dominate pole. This compensation topology is referred to as Type I and is shown in Figure 29. In most applications, a Type I compensation network can be used when a low cross-over frequency (typically less than 10 kHz) is desired. Equation 19 calculates the required capacitance from the COMP pin to GND in order to achieve a desired cross-over frequency (fCO), knowing the DC gain of the power stage (GDC). Type I Compensation gM(ea ) ´ GDC C1 = 2 ´ p ´ fCO (19) Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Links: TPS92510 19 TPS92510 SLUSAE4A – JANUARY 2012 – REVISED AUGUST 2012 www.ti.com The compensated loop gain is equal to the control to output transfer function multiplied by the error amplifier transfer function as shown in Equation 20. GCL = GC2O ´ GEA (20) gM(ea ) GEA = s ´ C1 (21) The transconductance gain of the error amplifier (gM(ea)) is 310 µA/V. Type II Compensation When using PWM dimming, it is beneficial to extend the loop bandwidth beyond 10 kHz. In this case, a Type II compensation topology can be used. The gain of the error amplifier changes as shown in Equation 22. GEA = gM(ea ) 1 + (s ´ R1´ C1) ( s ´ (C1 + C2 ) + s2 ´ R1´ C1´ C2 ) (22) VOUT VOUT COUT COUT RLED RLED RESR RESR VSENSE COMP VSENSE COMP gM + gM + C1 VREF C2 VREF C1 RSENSE RSENSE R1 UDG-11211 UDG-11210 Figure 29. Type I Compensation Figure 30. Type II Compensation Knowing the desired cross-over frequency (fCO) and the power stage DC dain (GDC), the error amplifier can be easily compensated with a Type II network. Equation 23 through Equation 25 show some simple approximations for the compensation values. Capacitor C1 has the biggest influence on the cross-over frequency and lowfrequency gain. Resistor R1 creates a zero in the error amplifier transfer function, which improves the phase margin particularly near the cross-over frequency. Capacitor C2 creates a high-frequency pole to reduce gain beyond the cross-over frequency. gM(ea ) ´ GDC C1 = 2 ´ p ´ fCO (23) R1 = 1 2p ´ K ´ fCO ´ C1 where • K is a multiplier of the desired cross-over frequency C1 C2 = 10 (24) (25) For reference, the error amplifier zero frequency and high-frequency pole equations are shown in Equation 26 through Equation 27. 20 Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Links: TPS92510 TPS92510 www.ti.com SLUSAE4A – JANUARY 2012 – REVISED AUGUST 2012 1 2p ´ R1´ C1 1 1 fEA(pole) = @ æ C1´ C2 ö 2p ´ R1´ C2 2p ´ R1´ ç ÷ è C1 + C2 ø fEA(zero) = (26) (27) The compensation equations above are given as a guideline. It is strongly recommended to verify the closed loop response for adequate gain and phase margin by directly measuring the circuit. The value of C1 is inversely proportional to the closed loop bandwidth of the system: as C1 decreases, the loop bandwidth increases. If the measured loop gain is too high, increase the value of C1 and recalculate R1 and C2. For a Type II compensation network a good cross-over frequency target is between 10 kHz and 50 kHz, but should not exceed one-fifth (1/5) of the switching frequency (fSW). When calculating the value of R1 the K multiplier must be chosen. Typically, this value is between 1.5 and 4. A good starting value for K is 2 or 3. This places the error amplifier zero frequency two or three times higher than the desired cross-over frequency. When measuring the loop response, if additional phase margin is needed the K value can be reduced, resulting in a larger R1 value. Alternatively, as the K multiplier increases beyond 4 the value of R1 becomes so small that its benefit to phase margin becomes insignificant, and the error amplifier performance begins to approach a Type I network. Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Links: TPS92510 21 TPS92510 SLUSAE4A – JANUARY 2012 – REVISED AUGUST 2012 www.ti.com Changes from Original (JANUARY 2012) to Revision A Page • Changed corrected y-axis label on Figure 8 ......................................................................................................................... 8 • Changed corrected test condition on Figure 14 .................................................................................................................... 9 22 Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Links: TPS92510 PACKAGE OPTION ADDENDUM www.ti.com 22-Oct-2012 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/ Ball Finish MSL Peak Temp TPS92510DGQ ACTIVE MSOPPowerPAD DGQ 10 80 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TPS92510DGQR ACTIVE MSOPPowerPAD DGQ 10 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM (3) Samples (Requires Login) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. 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Addendum-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 19-Oct-2012 TAPE AND REEL INFORMATION *All dimensions are nominal Device TPS92510DGQR Package Package Pins Type Drawing MSOPPower PAD DGQ 10 SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) 2500 330.0 12.4 Pack Materials-Page 1 5.3 B0 (mm) K0 (mm) P1 (mm) 3.4 1.4 8.0 W Pin1 (mm) Quadrant 12.0 Q1 PACKAGE MATERIALS INFORMATION www.ti.com 19-Oct-2012 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TPS92510DGQR MSOP-PowerPAD DGQ 10 2500 358.0 335.0 35.0 Pack Materials-Page 2 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. 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