TPS61175 www.ti.com SLVS892A – DECEMBER 2008 – REVISED OCTOBER 2010 3-A High Voltage Boost Converter with Soft-start and Programmable Switching Frequency Check for Samples: TPS61175 FEATURES 1 • • • • 2 • • • • DESCRIPTION 2.9-V to 18-V Input Voltage Range 3A, 40V Internal Switch High Efficiency Power Conversion: Up to 93% Frequency Set by External Resistor: 200-kHz to 2.2-MHz Synchronous External Switching Frequency User Defined Soft Start into Full Load Skip-Switching Cycle for Output Regulation at Light Load 14-pin HTSSOP Package with PowerPad™ The TPS61175 is a monolithic switching regulator with integrated 3-A, 40-V power switch. It can be configured in several standard switching-regulator topologies, including boost, SEPIC and flyback. The device has a wide input voltage range to support application with input voltage from multi-cell batteries or regulated 5-V, 12-V power rails. The TPS61175 regulates the output voltage with current mode PWM (pulse width modulation) control. The switching frequency of PWM is either set by an external resistor or an external clock signal. The user can program the switching frequency from 200-kHz to 2.2-MHz. APPLICATIONS • • • • 5V to 12V, 24V power conversion Supports SEPIC, Flyback topology ADSL Modems TV Tuner The device features a programmable soft-start function to limit inrush current during start-up, and has built-in other protection features, such as pulse-by-pulse over current limit and thermal shutdown. The TPS61175 is available in 14-pin HTSSOP package with Powerpad. TYPICAL APPLICATION FOR BOOST CONVERTER VIN D1 L1 VOUT C2 C1 TPS61175 VIN SW EN SW FREQ SS FB PGND COMP PGND R4 C3 Syn R3 AGND R1 R2 PGND NC C4 Figure 1. Typical Application 1 2 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PowerPad is a trademark of Texas Instruments. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2008–2010, Texas Instruments Incorporated TPS61175 SLVS892A – DECEMBER 2008 – REVISED OCTOBER 2010 www.ti.com These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. ORDERING INFORMATION (1) (1) (2) TA PART NUMBER PACKAGE (2) –40°C to 85°C TPS61175PWP HTSSOP-14 For the most current package and ordering information, see the TI Web site at www.ti.com. The PWP package is available in tape and reel. Add R suffix (TPS61175PWPR) to order quantities of 2000 parts per reel. Without suffix, the TPS61175PWP is shipped in tubes with 90 parts per tube. ABSOLUTE MAXIMUM RATINGS (1) over operating free-air temperature range (unless otherwise noted) Supply Voltages on pin VIN Voltages on pins EN (2) (2) VALUE UNIT –0.3 to 20 V –0.3 to 20 V Voltage on pin FB, FREQ and COMP (2) –0.3 to 3 V Voltage on pin SYNC, SS (2) –0.3 to 7 V Voltage on pin SW (2) –0.3 to 40 V Continuous Power Dissipation See Dissipation Rating Table Operating Junction Temperature Range –40 to +150 °C Storage Temperature Range –65 to +150 °C (1) (2) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. All voltage values are with respect to network ground terminal. DISSIPATION RATINGS (1) PACKAGE THERMAL RESISTANCE RqJA TA ≤ 25°C POWER RATING TA = 85°C POWER RATING 14 pin PWP (1) 44.5°C/W 2.25 W 0.9 W Rating based on JEDEC high thermal conductivity (High K) board with 2x2 array of thermal vias. See Texas Instruments application report (SLMA002) regarding thermal characteristics of the PowerPAD package RECOMMENDED OPERATING CONDITIONS over operating free-air temperature range (unless otherwise noted) MIN NOM MAX UNIT VIN Input voltage range 2.9 18 VO Output voltage range VIN 38 V L Inductor (1) 4.7 47 mH fSW Switching frequency 200 2200 kHz CI Input Capacitor 4.7 CO Output Capacitor 4.7 VSYN External Switching Frequency Logic TA Operating ambient temperature TJ Operating junction temperature (1) 2 V mF mF 5 V –40 85 °C –40 125 °C The inductance value depends on the switching frequency and end application. While larger values may be used, values between 4.7-mH and 47-mH have been successfully tested in various applications. Refer to the Inductor Selection for detail. Submit Documentation Feedback Copyright © 2008–2010, Texas Instruments Incorporated Product Folder Link(s): TPS61175 TPS61175 www.ti.com SLVS892A – DECEMBER 2008 – REVISED OCTOBER 2010 ELECTRICAL CHARACTERISTICS FSW = 1.2 MHz (Rfreq=80 kΩ), Vin=3.6V, TA = –40°C to +85°C, typical values are at TA = 25°C (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT SUPPLY CURRENT VIN Input voltage range IQ Operating quiescent current into Vin Device PWM switching without load 2.9 ISD Shutdown current EN=GND VUVLO Under-voltage lockout threshold 2.5 Vhys Under-voltage lockout hysteresis 130 18 V 3.5 mA 1.5 mA 2.7 V mV ENABLE AND REFERENCE CONTROL Venh EN logic high voltage Vin = 2.9 V to 18 V Venl EN logic low voltage Vin = 2.9 V to 18 V VSYNh SYN logic high voltage VSYNl SYN logic low voltage Ren EN pull down resistor Toff Shutdown delay, SS discharge 1.2 V 0.4 V 0.4 V 1.2 400 EN high to low 800 1600 kΩ 10 ms VOLTAGE AND CURRENT CONTROL VREF Voltage feedback regulation voltage 1.204 1.229 1.254 V IFB Voltage feedback input bias current Isink Comp pin sink current VFB = VREF + 200 mV, VCOMP = 1 V 50 mA Isource Comp pin source current VFB = VREF –200 mV, VCOMP = 1 V 130 mA VCCLP Comp pin Clamp Voltage High Clamp, VFB = 1 V Low Clamp, VFB = 1.5 V 3 0.75 V VCTH Comp pin threshold Duty cycle = 0% Gea Error amplifier transconductance Rea Error amplifier output resistance fea Error amplifier crossover frequency 200 nA 0.95 240 340 V 440 mmho 10 MΩ 500 KHz FREQUENCY fS Oscillator frequency Dmax Maximum duty cycle VFREQ FREQ pin voltage Tmin_on Minimum on pulse width Rfreq = 480 kΩ 0.16 0.21 Rfreq = 80 kΩ 1.0 1.2 1.4 Rfreq = 40 kΩ 1.76 2.2 2.64 VFB = 1.0 V, Rfreq = 80 kΩ 89% Rfreq = 80 kΩ 0.26 MHz 93% 1.229 V 60 ns POWER SWITCH RDS(ON) N-channel MOSFET on-resistance VIN = VGS = 3.6 V VIN = VGS = 3.0 V ILN_NFET N-channel leakage current VDS = 40 V, TA = 25°C 0.13 0.13 0.25 0.3 Ω 1 mA OC, OVP AND SS ILIM N-Channel MOSFET current limit D = Dmax ISS Soft start bias current Vss = 0 V 3 3.8 5 A 6 mA 160 °C 15 °C THERMAL SHUTDOWN Tshutdown Thermal shutdown threshold T hysteresis Thermal shutdown threshold hysteresis Submit Documentation Feedback Copyright © 2008–2010, Texas Instruments Incorporated Product Folder Link(s): TPS61175 3 TPS61175 SLVS892A – DECEMBER 2008 – REVISED OCTOBER 2010 www.ti.com DEVICE INFORMATION PIN ASSIGNMENTS TSSOP 14-pin (TOP VIEW) SW SW VIN EN SS SYNC AGND 1 2 3 4 5 6 7 PGND PGND PGND NC FREQ FB COMP 14 13 12 11 10 9 8 PIN FUNCTIONS PIN NAME NO. DESCRIPTION I/O VIN 3 I The input supply pin for the IC. Connect VIN to a supply voltage between 2.9V and 18V. It is acceptable for the voltage on the pin to be different from the boost power stage input for applications requiring voltage beyond VIN range. SW 1,2 I This is the switching node of the IC. Connect SW to the switched side of the inductor. FB 9 I Feedback pin for positive voltage regulation. Connect to the center tap of a resistor divider to program the output voltage. EN 4 I Enable pin. When the voltage of this pin falls below the enable threshold for more than 10ms, the IC turns off. COMP 8 O Output of the internal transconductance error amplifier. An external RC network is connected to this pin to compensate the regulator. SS 5 O Soft start programming pin. A capacitor between the SS pin and GND pin programs soft start timing. See application section for information on how to size the SS capacitor. FREQ 10 O Switch frequency program pin. An external resistor is connected to this pin to set switch frequency. See application section for information on how to size the FREQ resistor. AGND 7 I Signal ground of the IC PGND 12,13,14 I Power ground of the IC. It is connected to the source of the PWM switch. SYNC 6 I Switch frequency synchronous pin. Customers can use an external signal to set the IC switch frequency between 200-kHz and 2.2-MHz. If not used, this pin should be tied to AGND as short as possbile to avoid noise coupling. NC 11 I Reserved pin. Must connect this pin to ground. Thermal Pad 4 The thermal pad should be soldered to the analog ground. If possible, use thermal via to connect to top and internal ground plane layers for ideal power dissipation. Submit Documentation Feedback Copyright © 2008–2010, Texas Instruments Incorporated Product Folder Link(s): TPS61175 TPS61175 www.ti.com SLVS892A – DECEMBER 2008 – REVISED OCTOBER 2010 FUNCTIONAL BLOCK DIAGRAM L1 D1 C1 C2 R1 FB SW VIN R2 FB EA EN Gate Dirver 1.229 V Reference COMP PWM Control R3 C4 Ramp Generator Current Sensor + Oscillator SS C3 FREQ SYNC AGND PGND R4 TYPICAL CHARACTERISTICS TABLE OF GRAPHS Circuit of Figure 1; L1 = D104C2-10mH; D1 = SS3P6L-E3/86A, R4 = 80kΩ, R3 = 10kΩ, C4 = 22nF, C2 = 10mF;Vin = 5V, Vout = 24V, Iout = 200mA; unless otherwise noted FIGURE Efficiency VIN = 5V, Vout = 12V, 24V, 35V 2 Efficiency VIN = 5V, 12V; Vout = 24V 3 Error amplifier transconductance vs Temperature 4 Switch current limit vs Temperature 5 Switch current limit vs Duty cycle 6 FB accuracy vs Temperature 7 Line transient response Vin = 4.5 V to 5 V 8 Load transient response Iout = 100 mA to 300 mA; refer to 'compensating the control loop' for optimization PWM Operation 9 10 Pulse skipping No load 11 Start-up C3 = 47 nF 12 Submit Documentation Feedback Copyright © 2008–2010, Texas Instruments Incorporated Product Folder Link(s): TPS61175 5 TPS61175 SLVS892A – DECEMBER 2008 – REVISED OCTOBER 2010 www.ti.com EFFICIENCY vs OUTPUT CURRENT EFFICIENCY vs OUTPUT CURRENT 100 100 VI = 5 V VO = 12 V 90 VI = 12 V 90 VI = 5 V Efficiency - % Efficiency - % VO = 24 V 80 VO = 35 V 70 80 70 60 60 VO = 24 V 50 50 0.2 0.4 0.6 0.8 IO - Output Current - A 1 0 1.2 ERROR AMPLIFIER TRANSCONDUCTANCE vs FREE-AIR TEMPERATURE OVERCURRENT LIMIT vs DUTY CYCLE 5 380 4.5 360 1 1.2 4 3.5 340 -20 0 20 40 60 80 TA - Free-Air Temperature - °C 100 120 3 0.2 Figure 4. 6 0.4 0.6 0.8 IO - Output Current - A Figure 3. 400 320 -40 0.2 Figure 2. Overcurrent Limit - A EA Transconductance - mhos 0 0.4 0.6 Duty Cycle - % 0.8 1 Figure 5. Submit Documentation Feedback Copyright © 2008–2010, Texas Instruments Incorporated Product Folder Link(s): TPS61175 TPS61175 www.ti.com SLVS892A – DECEMBER 2008 – REVISED OCTOBER 2010 OVERCURRENT LIMIT vs FREE-AIR TEMPERATURE FB VOLTAGE vs FREE-AIR TEMPERATURE 4 1240 3.9 FB Voltage - mV Overcurrent Limit - A 1235 3.8 3.7 1230 1225 3.6 3.5 -40 -20 0 80 60 20 40 TA - Free-Air Temperature - °C 100 120 1220 -40 -20 0 20 40 60 80 TA - Free-Air Temperature - °C Figure 6. Figure 7. Line Transient Response Load Transient Response 100 120 VOUT 500 mV/div AC VIN 1 V/div AC VOUT 100 mV/div AC ILOAD 200 mA/div t - 100 ms/div t - 200 ms/div Figure 8. Figure 9. PWM Operation Pulse Skipping VOUT 1 V/div 20 V offset SW 20 V/div VOUT 20 mV/div AC IL 500 mA/div IL 100 mA/div VOUT 100 mV/div AC t - 400 ms/div t - 400 ns/div Figure 10. Figure 11. Submit Documentation Feedback Copyright © 2008–2010, Texas Instruments Incorporated Product Folder Link(s): TPS61175 7 TPS61175 SLVS892A – DECEMBER 2008 – REVISED OCTOBER 2010 www.ti.com Soft Startup EN 2 V/div VOUT 5 V/div IL 500 mA/div t - 1 ms/div Figure 12. DETAILED DESCRIPTION OPERATION The TPS61175 integrates a 40-V low side switch FET for up to 38-V output. The device regulates the output with current mode PWM (pulse width modulation) control. The PWM control circuitry turns on the switch at the beginning of each switching cycle. The input voltage is applied across the inductor and stores the energy as inductor current ramps up. During this portion of the switching cycle, the load current is provided by the output capacitor. When the inductor current rises to the threshold set by the error amplifier output, the power switch turns off and the external Schottky diode is forward biased. The inductor transfers stored energy to replenish the output capacitor and supply the load current. This operation repeats each every switching cycle. As shown in the block diagram, the duty cycle of the converter is determined by the PWM control comparator which compares the error amplifier output and the current signal. The switching frequency is programmed by the external resistor or synchronized to an external clock signal. A ramp signal from the oscillator is added to the current ramp to provide slope compensation. Slope compensation is necessary to avoid subharmonic oscillation that is intrinsic to the current mode control at duty cycle higher than 50%. If the inductor value is lower than 4.7mH, the slope compensation may not be adequate. The feedback loop regulates the FB pin to a reference voltage through a transconductance error amplifier. The output of the error amplifier is connected to the COMP pin. An external RC compensation network is connected to the COMP pin to optimize the feedback loop for stability and transient response. SWITCHING FREQUENCY The switch frequency is set by a resistor (R4) connected to the FREQ pin of the TPS61175. Do not leave this pin open. A resistor must always be connected for proper operation. See Table 1 and Figure 13 for resistor values and corresponding frequencies. Table 1. Switching Frequency vs External Resistor 8 R4 (kΩ) fSW (kHz) 443 240 256 400 176 600 80 1200 51 2000 Submit Documentation Feedback Copyright © 2008–2010, Texas Instruments Incorporated Product Folder Link(s): TPS61175 TPS61175 www.ti.com SLVS892A – DECEMBER 2008 – REVISED OCTOBER 2010 3500 3000 f - Frequency - kHz 2500 2000 1500 1000 500 0 10 100 External Resistor - kW 1000 Figure 13. Switching Frequency vs External Resistor Alternatively, the TPS61175 switching frequency will synchronize to an external clock signal that is applied to the SYNC pin. The logic level of the external clock is shown in the specification table. The duty cycle of the clock is recommended in the range of 10% to 90%. The resistor also must be connected to the FREQ pin when IC is switching by the external clock. The external clock frequency must be within ±20% of the corresponding frequency set by the resistor. For example, if the corresponding frequency as set by a resistor on the FREQ pin is 1.2-MHz, the external clock signal should be in the range of 0.96-MHz to 1.44-MHz. If the external clock signal is higher than the frequency per the resistor on the FREQ pin, the maximum duty cycle specification (DMAX) should be lowered by 2%. For instance, if the resistor set value is 2.5MHz, and the external clock is 3MHz, DMAX is 87% instead of 89%. SOFT START The TPS61175 has a built-in soft start circuit which significantly reduces the start-up current spike and output voltage overshoot. When the IC is enabled, an internal bias current (6-mA typically) charges a capacitor (C3) on the SS pin. The voltage at the capacitor clamps the output of the internal error amplifier that determines the duty cycle of PWM control, thereby the input inrush current is eliminated. Once the capacitor reaches 1.8-V, the soft start cycle is completed and the soft start voltage no longer clamps the error amplifier output. Refer to Figure 13 for the soft start waveform. See Table 2 for C3 and corresponding soft start time. A 47-nF capacitor eliminates the output overshoot and reduces the peak inductor current for most applications. Table 2. Soft Start Time vs C3 Vin (V) 5 12 Vout (V) 24 35 Load (A) 0.4 0.6 Cout (mF) 10 10 fSW (MHz) 1.2 2 C3 (nF) tSS(ms) Overshot (mV) 47 4 none 10 0.8 210 100 6.5 none 10 0.4 300 When the EN is pulled low for 10-ms, the IC enters shutdown and the SS capacitor discharges through a 5kΩ resistor for the next soft start. OVERCURRENT PROTECTION The TPS61175 has a cycle-by-cycle overcurrent limit protection that turns off the power switch once the inductor current reaches the overcurrent limit threshold. The PWM circuitry resets itself at the beginning of the next switch cycle. During an overcurrent event, the output voltage begins to droop as a function of the load on the output. When the FB voltage drops lower than 0.9-V, the switching frequency is automatically reduced to 1/4 of the set value. The switching frequency does not reset until the overcurrent condition is removed. This feature is disabled during soft start. Submit Documentation Feedback Copyright © 2008–2010, Texas Instruments Incorporated Product Folder Link(s): TPS61175 9 TPS61175 SLVS892A – DECEMBER 2008 – REVISED OCTOBER 2010 www.ti.com ENABLE AND THERMAL SHUTDOWN The TPS61175 enters shutdown when the EN voltage is less than 0.4-V for more than 10-ms. In shutdown, the input supply current for the device is less than 1.5-mA (max). The EN pin has an internal 800-kΩ pull down resistor to disable the device when it is floating. An internal thermal shutdown turns off the device when the typical junction temperature of 160°C is exceeded. The IC restarts when the junction temperature drops by 15°C. UNDER VOLTAGE LOCKOUT (UVLO) An under voltage lockout circuit prevents mis-operation of the device at input voltages below 2.5-V (typical). When the input voltage is below the under voltage threshold, the device remains off and the internal switch FET is turned off. The under voltage lockout threshold is set below minimum operating voltage of 2.9V to avoid any transient VIN dip triggering the UVLO and causing the device to reset. For the input voltages between UVLO threshold and 2.9V, the device attempts to operate, but the specifications are not ensured. MINIMUM ON TIME and PULSE SKIPPING Once the PWM switch is turned on, the TPS61175 has minimum ON pulse width of 60-ns. This sets the limit of the minimum duty cycle of the PWM switch, and it is independent of the set switching frequency. When operating conditions result in the TPS61175 having a minimum ON pulse width less than 60-ns, the IC enters pulse-skipping mode. In this mode, the device keeps the power switch off for several switching cycles to keep the output voltage from rising above the regulated voltage. This operation typically occurs in light load condition when the PWM operates in discontinuous mode. Pulse skipping increases the output voltage ripple, see the Figure 14. 10 Submit Documentation Feedback Copyright © 2008–2010, Texas Instruments Incorporated Product Folder Link(s): TPS61175 TPS61175 www.ti.com SLVS892A – DECEMBER 2008 – REVISED OCTOBER 2010 APPLICATION INFORMATION The following section provides a step-by-step design approach for configuring the TPS61175 as a voltage regulating boost converter, as shown in Figure 14. When configured as SEPIC or flyback converter, a different design approach is required. VIN D1 L1 VOUT C2 C1 TPS61175 VIN SW EN SW FREQ SS FB PGND COMP PGND R4 C3 R3 Syn AGND R1 R2 PGND NC C4 Figure 14. Boost Converter Configuration DETERMINING THE DUTY CYCLE The TPS61175 has a maximum worst case duty cycle of 89% and a minimum on time of 60 ns. These two constraints place limitations on the operating frequency that can be used for a given input to output conversion ratio. The duty cycle at which the converter operates is dependent on the mode in which the converter is running. If the converter is running in discontinuous conduction mode (DCM), where the inductor current ramps to zero at the end of each cycle, the duty cycle varies with changes to the load much more than it does when running in continuous conduction mode (CCM). In continuous conduction mode, where the inductor maintains a dc current, the duty cycle is related primarily to the input and output voltages as computed below: V + VD - VIN D = OUT VOUT + VD (1) In discontinuous mode the duty cycle is a function of the load, input and output voltages, inductance and switching frequency as computed below: 2 ´ (VOUT + VD ) ´ IOUT ´ L ´ ¦ SW D= VIN 2 (2) All converters using a diode as the freewheeling or catch component have a load current level at which they transition from discontinuous conduction to continuous conduction. This is the point where the inductor current just falls to zero. At higher load currents, the inductor current does not fall to zero but remains flowing in a positive direction and assumes a trapezoidal wave shape as opposed to a triangular wave shape. This load boundary between discontinuous conduction and continuous conduction can be found for a set of converter parameters as follows. IOUT(crit) = (VOUT + VD - VIN ) ´ VIN2 2 ´ (VOUT + VD ) 2 ´ ¦ SW ´ L (3) For loads higher than the result of the equation above, the duty cycle is given by Equation 1 and for loads less that the results of Equation 2, the duty cycle is given Equation 3. For Equation 1 through Equation 3, the variable definitions are as follows. • VOUT is the output voltage of the converter in V • VD is the forward conduction voltage drop across the rectifier or catch diode in V • VIN is the input voltage to the converter in V • IOUT is the output current of the converter in A • L is the inductor value in H • fSW is the switching frequency in Hz Submit Documentation Feedback Copyright © 2008–2010, Texas Instruments Incorporated Product Folder Link(s): TPS61175 11 TPS61175 SLVS892A – DECEMBER 2008 – REVISED OCTOBER 2010 www.ti.com Unless otherwise stated, the design equations that follow assume that the converter is running in continuous mode. SELECTING THE INDUCTOR The selection of the inductor affects steady state operation as well as transient behavior and loop stability. These factors make it the most important component in power regulator design. There are three important inductor specifications, inductor value, DC resistance and saturation current. Considering inductor value alone is not enough. Inductor values can have ±20% tolerance with no current bias. When the inductor current approaches saturation level, its inductance can fall to some percentage of its 0-A value depending on how the inductor vendor defines saturation current. For CCM operation, the rule of thumb is to choose the inductor so that its inductor ripple current (ΔIL) is no more than a certain percentage (RPL% = 20–40%) of its average DC value (IIN(AVG) = IL(AVG)) V ´ D (VOUT + VD - VIN ) ´ (1 - D) 1 = = D IL = IN L ´ ¦SW L ´ ¦S W é æ 1 1 öù + êL ´ ¦ SW ´ ç ÷ú êë è VO UT + VD - VIN VIN ø úû PO UT £ RPL% ´ VIN ´ ηes t (4) Rearranging and solving for L gives ηest ´ VIN L £ é æ 1 1 öù + ê ¦S W ç ÷ ú ´ RPL% POUT êë è VOUT + VD - VIN VIN ø úû (5) Choosing the inductor ripple current to closer to 20% of the average inductor current results in a larger inductance value, maximizes the converter’s potential output current and minimizes EMI. Choosing the inductor ripple current closer to 40% of IL(AVG) results in a smaller inductance value, and a physically smaller inductor, improves transient response but results in potentially higher EMI and lower efficiency if the DCR of the smaller packaged inductor is significantly higher. Using an inductor with a smaller inductance value than computed above may result in the converter operating in DCM. This reduces the boost converter’s maximum output current, causes larger input voltage and output ripple and typically reduces efficiency. Table 3 lists the recommended inductor for the TPS61175. Table 3. Recommended Inductors for TPS61175 PART NUMBER L (mH) DCR MAX (mΩ) SATURATION CURRENT (A) SIZE (L × W × H mm) VENDOR D104C2 10 44 3.6 10.4x10.4x4.8 TOKO VLF10040 15 42 3.1 10.0x9.7x4.0 TDK CDRH105RNP 22 61 2.9 10.5x10.3x5.1 Sumida MSS1038 15 50 3.8 10.0x10.2x3.8 Coilcraft The device has built-in slope compensation to avoid subharmonic oscillation associated with current mode control. If the inductor value is lower than 4.7mH, the slope compensation may not be adequate, and the loop can be unstable. Applications requiring inductors above 47mH have not been evaluated. Therefore, the user is responsible for verifying operation if they select an inductor that is outside the 4.7mH–47mH recommended range. COMPUTING THE MAXIMUM OUTPUT CURRENT The over-current limit for the integrated power FET limits the maximum input current and thus the maximum input power for a given input voltage. Maximum output power is less than maximum input power due to power conversion losses. Therefore, the current limit setting, input voltage, output voltage and efficiency can all change the maximum current output (IOUT(MAX)). The current limit clamps the peak inductor current, therefore the ripple has to be subtracted to derive maximum DC current. 12 Submit Documentation Feedback Copyright © 2008–2010, Texas Instruments Incorporated Product Folder Link(s): TPS61175 TPS61175 www.ti.com SLVS892A – DECEMBER 2008 – REVISED OCTOBER 2010 IOUT(max) = VIN(min) ´ ηest VOUT = VIN(min) ´ ILIM ´ (1 - %RPL/2) ´ ηest VOUT (6) where ILIM = over current limit hest= efficiency estimate based on similar applications or computed above For instance, when VIN = 12-V is boosted to VOUT = 24-V, the inductor is 10-uH, the Schottky forward voltage is 0.4-V and the switching frequency is 1.2-MHz; then the maximum output current is 1.2-A in typical condition, assuming 90% efficiency and a %RPL = 20%. SETTING OUTPUT VOLTAGE To set the output voltage in either DCM or CCM, select the values of R1 and R2 according to the following equation. æ R1 ö Vout = 1.229 V ´ ç + 1÷ è R2 ø æ Vout ö - 1÷ R1 = R2 ´ ç 1.229V è ø (7) Considering the leakage current through the resistor divider and noise decoupling into FB pin, an optimum value for R2 is around 10k. The output voltage tolerance depends on the VFB accuracy and the tolerance of R1 and R2. SETTING THE SWITCHING FREQUENCY Choose the appropriate resistor from the resistance versus frequency table Table 1 or graph Figure 13. A resistor must be placed from the FREQ pin to ground, even if an external oscillation is applied for synchronization. Increasing switching frequency reduces the value of external capacitors and inductors, but also reduces the power conversion efficiency. The user should set the frequency for the minimum tolerable efficiency. SETTING THE SOFT START TIME Choose the appropriate capacitor from the soft start table Table 2. Increasing the soft start time reduces the overshoot during start-up. SELECTING THE SCHOTTKY DIODE The high switching frequency of the TPS61175 demands a high-speed rectification for optimum efficiency. Ensure that the diode’s average and peak current rating exceed the average output current and peak inductor current. In addition, the diode’s reverse breakdown voltage must exceed the switch FET rating voltage of 40V. So, the VISHAY SS3P6L-E3/86A is recommended for TPS61175. The power dissipation of the diode's package must be larger than IOUT(max) x VD SELECTING THE INPUT AND OUTPUT CAPACITORS The output capacitor is mainly selected to meet the requirements for the output ripple and load transient. Then the loop is compensated for the output capacitor selected. The output ripple voltage is related to the capacitor’s capacitance and its equivalent series resistance (ESR). Assuming a capacitor with zero ESR, the minimum capacitance needed for a given ripple can be calculated by Cout = (VOUT - VIN )Iout VOUT ´ Fs ´ Vripple (8) where, Vripple= peak to peak output ripple. The additional output ripple component caused by ESR is calculated using: Vripple_ESR = I × RESR Submit Documentation Feedback Copyright © 2008–2010, Texas Instruments Incorporated Product Folder Link(s): TPS61175 13 TPS61175 SLVS892A – DECEMBER 2008 – REVISED OCTOBER 2010 www.ti.com Due to its low ESR, Vripple_ESR can be neglected for ceramic capacitors, but must be considered if tantalum or electrolytic capacitors are used. The minimum ceramic output capacitance needed to meet a load transient requirement can be estimated by the equation below: ΔITRAN COUT = 2 ´ p ´ fLOOP-BW ´ ΔVTRAN (9) Where ΔITRAN is the transient load current step ΔVTRAN is the allowed voltage dip for the load current step fLOOP-BW is the control loop bandwidth (i.e., the frequency where the control loop gain crosses zero). Care must be taken when evaluating a ceramic capacitor’s derating under dc bias, aging and AC signal. For example, larger form factor capacitors (in 1206 size) have their self resonant frequencies in the range of the switching frequency. So the effective capacitance is significantly lower. The DC bias can also significantly reduce capacitance. Ceramic capacitors can loss as much as 50% of its capacitance at its rated voltage. Therefore, one must add margin on the voltage rating to ensure adequate capacitance at the required output voltage. For a typical boost converter implementation, at least 4.7mF of ceramic input and output capacitance is recommended. Additional input and output capacitance may be required to meet ripple and/or transient requirements. The popular vendors for high value ceramic capacitors are: TDK (http://www.component.tdk.com/components.php) Murata (http://www.murata.com/cap/index.html) COMPENSATING THE SMALL SIGNAL CONTROL LOOP All continuous mode boost converters have a right half plane zero (ƒRHPZ) due to the inductor being removed from the output during charging. In a traditional voltage mode controlled boost converter, the inductor and output capacitor form a small signal double pole. For a negative feedback system to be stable, the fed back signal must have a gain less than 1 before having 180 degrees of phase shift. With its double pole and RHPZ all providing phase shift, voltage mode boost converters are a challenge to compensate. In a converter with current mode control, there are essentially two loops, an inner current feedback loop created by the inductor current information sensed across RSENSE (40mΩ) and the output voltage feedback loop. The inner current loop allows the switch, inductor and modulator to be lumped together into a small signal variable current source controlled by the error amplifier, as shown in Figure 15. (1-D) RSENSE R1 + _ C2 Vref C4 RO 2 C5 (optional) R3 R2 RESR Figure 15. Small Signal Model of a Current Mode Boost in CCM The new power stage, including the slope compensation, small signal model becomes: 14 Submit Documentation Feedback Copyright © 2008–2010, Texas Instruments Incorporated Product Folder Link(s): TPS61175 TPS61175 www.ti.com SLVS892A – DECEMBER 2008 – REVISED OCTOBER 2010 æ öæ s s ç1 + ÷ ç1 2 ´ p ´ ¦ESR ø è 2 ´ p ´ ¦RHPZ ROUT ´ (1 - D) è ´ GPS (s) = s 2 ´ RSENSE 1+ 2 ´ p ´ ¦P ö ÷ ø ´ He(s) (10) Where ¦P = 2 2 p ´ RO ´ C2 ¦ESR » ¦RHPZ = (11) 1 2p ´ RESR ´ C2 (12) 2 æ V ö ´ ç IN ÷ 2p ´ L è VOUT ø RO (13) And He(s) = 1 éæ ù Se ö s ´ êç1 + ÷ ´ (1 - D) - 0.5ú Sn ø s2 ëè û + 1+ 2 ¦S W ( p ´ ¦ SW ) (14) He(s) models the inductor current sampling effect as well as the slope compensation effect on the small signal response. Note that if Sn > Se, e.g., when L is smaller than recommended, the converter operates as a voltage mode converter and the above model no longer holds. The slope compensation in TPS61175 is shown as follow V + VD - VIN Sn = OUT ´ RSENSE L 0.32 V / R4 0.5 mA Se = + 16 ´ (1 - D )´ 6pF 6 pF Where R4 is the frequency setting resistor (15) (16) Figure 16 shows a bode plot of a typical CCM boost converter power stage Submit Documentation Feedback Copyright © 2008–2010, Texas Instruments Incorporated Product Folder Link(s): TPS61175 15 TPS61175 SLVS892A – DECEMBER 2008 – REVISED OCTOBER 2010 www.ti.com 180 120 Gain 0 Phase – ° Gain − dB 60 –60 Phase –120 –180 fP f − Frequency − kHz Figure 16. Bode Plot of Power Stage Gain and Phase The TPS61175 COMP pin is the output of the internal trans-conductance amplifier. Equation 17 shows the equation for feedback resistor network and the error amplifier. s 1+ 2 ´ p ´ ¦Z R2 HEA = GEA ´ REA ´ ´ R2 + R1 æ ö æ ö s s ç1 + ÷ ´ ç1 + ÷ 2 2 ´ p ´ ¦ ´ p ´ ¦ P1 ø è P2 ø è (17) where GEA and REA are the amplifier’s trans-conductance and output resistance located in the ELECTRICAL CHARACTERISTICS table. ¦ P1 = ¦P2 1 2 p ´ R EA ´ C4 (18) 1 = (optional) 2p ´ R3 ´ C5 C5 is optional and can be modeled as 10 pF stray capacitance. (19) and ¦Z = 1 2p ´ R3 ´ C4 (20) Figure 17 shows a typical bode plot for transfer function H(s). 16 Submit Documentation Feedback Copyright © 2008–2010, Texas Instruments Incorporated Product Folder Link(s): TPS61175 TPS61175 www.ti.com SLVS892A – DECEMBER 2008 – REVISED OCTOBER 2010 180 90 Phase – ° Gain − dB Phase 0 Kcomp –90 Gain –180 <–fp1 fC fZ f − Frequency − kHz fp2 Figure 17. Bode Plot of Feedback Resistors and Compensated Amplifier Gain and Phase The next step is to choose the loop crossover frequency, fC. The higher in frequency that the loop gain stays above zero before crossing over, the faster the loop response will be and therefore the lower the output voltage will droop during a step load. It is generally accepted that the loop gain cross over no higher than the lower of either 1/5 of the switching frequency, fSW, or 1/3 of the RHPZ frequency, fRHPZ. To approximate a single pole roll-off up to fP2, select R3 so that the compensation gain, KCOMP, at fC on Figure 17 is the reciprocal of the gain, KPW, read at frequency fC from the Figure 16 bode plot or more simply KCOMP(fC) = 20 × log(GEA × R3 × R2/(R2+R1)) = 1/KPW(fC) This makes the total loop gain, T(s) = GPS(s) × HEA(s), zero at the fC. Then, select C4 so that fZ ≅ fC/10 and optional fP2> fC *10. Following this method should lead to a loop with a phase margin near 45 degrees. Lowering R3 while keeping fZ ≅ fC/10 increases the phase margin and therefore increases the time it takes for the output voltage to settle following a step load. In the TPS61175, if the FB pin voltage changes suddenly due to a load step on the output voltage, the error amplifier increases its transconductance for 8-ms in an effort to speed up the IC’s transient response and reduce output voltage droop due to the load step. For example, if the FB voltage decreases 10-mV due to load change, the error amplifier increases its source current through COMP by 5 times; if FB voltage increases 11-mV, the sink current through COMP is increased to 3.5 times normal value. This feature often results in saw tooth ringing on the output voltage, shown as Figure 9. Designing the loop for greater than 45 degrees of phase margin and greater than 10db gain margin minimizes the amplitude of this ringing. This feature is disabled during soft start. LAYOUT CONSIDERATIONS As for all switching power supplies, especially those running at high switching frequency and high currents, layout is an important design step. If layout is not carefully done, the regulator could suffer from instability as well as noise problems. To maximize efficiency, switch rise and fall times are very fast. To prevent radiation of high frequency noise (eg. EMI), proper layout of the high frequency switching path is essential. Minimize the length and area of all traces connected to the SW pin and always use a ground plane under the switching regulator to minimize interplane coupling. The high current path including the switch, Schottky diode, and output capacitor, contains nanosecond rise and fall times and should be kept as short as possible. The input capacitor needs not only to be close to the VIN pin, but also to the GND pin in order to reduce the Iinput supply ripple. Submit Documentation Feedback Copyright © 2008–2010, Texas Instruments Incorporated Product Folder Link(s): TPS61175 17 TPS61175 SLVS892A – DECEMBER 2008 – REVISED OCTOBER 2010 www.ti.com VIN INPUT CAPACITOR VOUT INDUCTOR SCHOTTKEY OUTPUT CAPACITOR SW Minimize the area of SW trace SW PGND SW PGND VIN PGND PGND SS Thermal Pad EN NC FREQ SYNC FB AGND COMP Place enough VIAs around thermal pad to enhance thermal performance AGND FEEDBACK COMPESNATION NETWORK Figure 18. TPS61175 Layout THERMAL CONSIDERATIONS The maximum IC junction temperature should be restricted to 125°C under normal operating conditions. This restriction limits the power dissipation of the TPS61175. Calculate the maximum allowable dissipation, PD(max), and keep the actual dissipation less than or equal to PD(max). The maximum-power-dissipation limit is determined using the following equation: 125 °C - TA PD(max) = R qJA (21) where, TA is the maximum ambient temperature for the application. RqJA is the thermal resistance junction-to-ambient given in Power Dissipation Table. The TPS61175 comes in a thermally enhanced TSSOP package. This package includes a thermal pad that improves the thermal capabilities of the package. The RqJA of the TSSOP package greatly depends on the PCB layout and thermal pad connection. The thermal pad must be soldered to the analog ground on the PCB. Using thermal vias underneath the thermal pad. 18 Submit Documentation Feedback Copyright © 2008–2010, Texas Instruments Incorporated Product Folder Link(s): TPS61175 TPS61175 www.ti.com SLVS892A – DECEMBER 2008 – REVISED OCTOBER 2010 REVISION HISTORY Changes from Original (December 2008) to Revision A • Page Changed the Ordering Information table - Part Number From: TPS61175 To: TPS61175PWP; Removed the Package Marking column ..................................................................................................................................................... 2 Submit Documentation Feedback Copyright © 2008–2010, Texas Instruments Incorporated Product Folder Link(s): TPS61175 19 PACKAGE OPTION ADDENDUM www.ti.com 13-Oct-2010 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/ Ball Finish MSL Peak Temp (3) Samples (Requires Login) TPS61175PWP ACTIVE HTSSOP PWP 14 90 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR Purchase Samples TPS61175PWPR ACTIVE HTSSOP PWP 14 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR Request Free Samples (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. 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