LS3550A MONOLITHIC DUAL PNP TRANSISTOR Linear Systems Monolithic Dual PNP Transistor The LS3550A is a monolithic pair of PNP transistors mounted in a single SOIC package. The monolithic dual chip design reduces parasitics and gives better performance while ensuring extremely tight matching. The 8 Pin SOIC provides ease of manufacturing, and the symmetrical pinout prevents improper orientation. (See Packaging Information). LS3550A Features: Tight matching Low Output Capacitance FEATURES EXCELLENT THERMAL TRACKING TIGHT VBE MATCHING ABSOLUTE MAXIMUM RATINGS 1 @ 25°C (unless otherwise noted) ≤ 3µV/°C |VBE1 – VBE2 | ≤2mV Maximum Temperatures Storage Temperature Operating Junction Temperature Maximum Power Dissipation Continuous Power Dissipation Maximum Currents Collector Current Maximum Voltages Collector to Collector Voltage MATCHING CHARACTERISTICS @ 25°C (unless otherwise stated) SYMBOL CHARACTERISTIC |VBE1 – VBE2 | Base Emitter Voltage Differential ∆|(VBE1 – VBE2)| / ∆T Base Emitter Voltage Differential Change with Temperature |IB1 – IB2 | Base Current Differential |∆ (IB1 – IB2)|/∆T Base Current Differential Change with Temperature hFE1 /hFE2 DC Current Gain Differential ‐65°C to +150°C ‐55°C to +150°C TBD 10mA 80V MIN ‐‐ ‐‐ TYP ‐‐ ‐‐ MAX 2 3 UNITS mV µV/°C ‐‐ ‐‐ ‐‐ ‐‐ 10 0.5 nA nA/°C ‐‐ ‐‐ 10 % CONDITIONS IC = ‐10mA, VCE = ‐5V IC = ‐10mA, VCE = ‐5V TA = ‐40°C to +85°C IC = ‐10µA, VCE = ‐5V IC = ‐10µA, VCE = ‐5V TA = ‐40°C to +85°C IC = 10µA, VCE = 5V Click To Buy ELECTRICAL CHARACTERISTICS @ 25°C (unless otherwise noted) SYMBOL CHARACTERISTICS MIN. BVCBO Collector to Base Voltage ‐45 BVCEO Collector to Emitter Voltage ‐45 BVEBO Emitter‐Base Breakdown Voltage ‐6.2 BVCCO Collector to Collector Voltage ‐80 150 DC Current Gain hFE 120 100 VCE(SAT) Collector Saturation Voltage ‐‐ IEBO Emitter Cutoff Current ‐‐ ICBO Collector Cutoff Current ‐‐ COBO Output Capacitance ‐‐ CC1C2 Collector to Collector Capacitance ‐‐ IC1C2 Collector to Collector Leakage Current ‐‐ fT Current Gain Bandwidth ‐‐ Product(Current) NF Narrow Band Noise Figure ‐‐ TYP. ‐‐ ‐‐ ‐‐ ‐‐ ‐‐ ‐‐ ‐‐ ‐‐ ‐‐ ‐‐ ‐‐ ‐‐ ‐‐ ‐‐ MAX. ‐‐ ‐‐ ‐‐ ‐‐ ‐‐ ‐‐ ‐‐ ‐0.25 ‐0.2 ‐0.2 2 2 ‐1 600 UNITS V V V V V nA nA pF pF nA MHz CONDITIONS IC = 10µA, IE = 0 IC = 10µA, IB = 0 IE = 10µA, IC = 02 IC = 10µA, IE = 0 IC = ‐1mA, VCE = ‐5V IC = ‐10mA, VCE = ‐5V IC = ‐100mA, VCE = ‐5V IC = ‐100mA, IB = ‐10mA IE = 0, VCB = ‐3V IE = 0, VCB = ‐30V IE = 0, VCB = ‐10V VCC = 0V VCC = ±80V IC = ‐1mA, VCE = ‐5V ‐‐ 3 dB IC = ‐100µA, VCE = ‐5V, BW=200Hz, RG= 10Ω, f = 1KHz Notes: 1. Absolute Maximum ratings are limiting values above which serviceability may be impaired 2. The reverse base‐to‐emitter voltage must never exceed 6.2 volts; the reverse base‐to‐emitter current must never exceed 10µA. SOIC (Top View) Available Packages: LS3550A in SOIC LS3550A available as bare die Please contact Micross for full package and die dimensions: Email: [email protected] Web: www.micross.com/distribution.aspx Information furnished by Linear Integrated Systems and Micross Components is believed to be accurate and reliable. However, no responsibility is assumed for its use; nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Linear Integrated Systems.