TI TMS470R1VF45AA

TMS470R1VF45AA
16/32-BIT RISC FLASH MICROCONTROLLER
SPNS086A – AUGUST 2003 – REVISED NOVEMBER 2004
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High-Performance Static CMOS Technology
TMS470R1x 16/32-Bit RISC Core (ARM7TDMI)
– 24-MHz System Clock (60-MHz Pipeline
Mode)
– Independent 16/32-Bit Instruction Set
– Open Architecture With Third-Party Support
– Built-In Debug Module
– Utilizes Big-Endian Format
Integrated Memory
– 512K-Byte Program Flash
– 2 Banks With 14 Contiguous Sectors
– Internal State Machine for Programming
and Erase
– 32K-Byte Static RAM (SRAM)
Operating Features
– Core Supply Voltage (VCC): 1.81 V - 2.05 V
– I/O Supply Voltage (VCCIO): 3.0 V - 3.6 V
– Low-Power Modes: STANDBY and HALT
– Industrial and Automotive Temperature
Ranges
470+ System Module
– 32-Bit Address Space Decoding
– Bus Supervision for Memory and
Peripherals
– Analog Watchdog (AWD) Timer
– Real-Time Interrupt (RTI)
– System Integrity and Failure Detection
– Interrupt Expansion Module (IEM)
Direct Memory Access (DMA) Controller
– 32 Control Packets and 16 Channels
Zero-Pin Phase-Locked Loop (ZPLL)-Based
Clock Module With Prescaler
– Multiply-by-4 or -8 Internal ZPLL Option
– ZPLL Bypass Mode
Seven Communication Interfaces:
– Three Serial Peripheral Interfaces (SPIs)
– 255 Programmable Baud Rates
– Two Serial Communications Interfaces
(SCIs)
– 224 Selectable Baud Rates
– Asynchronous/Isosynchronous Modes
– Two High-End CAN Controllers (HECCs)
– 32-Mailbox Capacity Each
– Fully Compliant With CAN Protocol,
Version 2.0B
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High-End Timer (HET)
– 32 Programmable I/O Channels:
– 24 High-Resolution Pins
– 8 Standard-Resolution Pins
– High-Resolution Share Feature (XOR)
– High-End Timer RAM
– 128-Instruction Capacity
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16-Channel 10-Bit Multi-Buffered ADC
(MibADC)
– 128-Word FIFO Buffer
– Single- or Continuous-Conversion Modes
– 1.55 µs Minimum Sample and Conversion
Time
– Calibration Mode and Self-Test Features
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Eight External Interrupts
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Flexible Interrupt Handling
27 Dedicated GIO Pins,1 Input-Only GIO Pin,
and 59 Additional Peripheral I/Os
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External Clock Prescale (ECP) Module
– Programmable Low-Frequency External
Clock (CLK)
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Compatible ROM Device (Planned)
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On-Chip Scan-Base Emulation Logic,
IEEE Standard 1149.1† (JTAG) Test-Access Port
144-Pin Plastic Low-Profile Quad Flatpack
(PGE Suffix)
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Development System Support Tools Available
– Code Composer Studio Integrated
Development Environment (IDE)
– HET Assembler and Simulator
– Real-Time In-Circuit Emulation
– Flash Programming
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
TexasInstruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Code Composer Studio is a trademark of Texas Instruments.
ARM7TDMI is a trademark of Advanced RISC Machines Limited (ARM).
All trademarks are the property of their respective owners.
† The test-access port is compatible with the IEEE Standard 1149.1-1990, IEEE Standard Test-Access Port and Boundary Scan Architecture
specification. Boundary scan is not supported on this device.
Copyright  2004, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication
date. Products conform to specifications per the Texas
Instruments standard warranty. Production processing does
not necessarily include testing of all parameters.
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251-1443
1
TMS470R1VF45AA
16/32-BIT RISC FLASH MICROCONTROLLER
SPNS086A – AUGUST 2003 – REVISED NOVEMBER 2004
74
73
75
78
77
76
117
118
119
120
121
122
123
124
125
126
127
128
129
130
57
56
55
54
53
52
51
50
131
49
48
47
46
45
44
43
42
41
40
39
38
37
132
133
134
135
136
137
138
139
140
141
142
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36
34
35
32
33
30
31
HET[12]
HET[11]
HET[10]
VSS
VCC
PORRST
GIOA[7]/INT7
GIOA[6]/INT6
GIOA[5]/INT5
GIOA[4]/INT4
22
23
21
18
19
20
24
25
26
27
28
29
HET[13]
SPI1ENA
SPI1SCS
SPI1SIMO
SPI1SOMI
SPI1CLK
1
143
144
† GIOA[0]/INT0 (pin 39) is an input-only GIO pin.
2
82
81
80
79
VCC
VSS
GIOB[7]
CLKOUT
VCCIO
VSSIO
HET[9]
HET[8]
GIOB[6]
GIOB[5]
TCK
TDO
TDI
PLLDIS
85
84
83
86
94
93
92
91
90
89
88
87
95
97
96
99
98
100
102
101
115
116
16
17
HET[4]
HET[5]
HET[6]
HET[7]
GIOC[1]
GIOC[2]
111
112
113
114
GIOC[4]
GIOC[5]
GIOC[6]
GIOC[7]
VSS
OSCOUT
OSCIN
VCC
RST
VSSIO
VCCIO
GIOD[3]
GIOD[2]
GIOD[1]
GIOD[0]
HET[17]
HET[16]
HET[15]
HET[14]
FLTP1
VCCP
VSS
HET[2]
HET[3]
71
70
69
68
67
66
65
64
63
62
61
60
59
58
GIOC[3]
FLTP2
72
109
110
2
3
4
5
6
7
8
9
10
11
12
13
14
15
ADIN[11]
ADIN[14]
ADIN[10]
ADIN[13]
ADIN[9]
ADIN[12]
ADIN[8]
ADREFHI
ADREFLO
VCCAD
VSSAD
TMS
TMS2
GIOC[0]
HET[23]
HET[25]
HET[26]
HET[27]
VSS
VCC
HET[0]
HET[1]
VSS
VCC
106
105
104
103
108
107
ADIN[0]
ADIN[1]
ADIN[2]
ADIN[3]
ADIN[4]
ADIN[15]
ADIN[5]
ADIN[6]
ADIN[7]
ADEVT
SPI3ENA
SPI3SCS
SPI3SIMO
SPI3SOMI
SPI3CLK
VCC
VSS
SCI1RX
SCI1TX
SCI1CLK
CAN1HTX
CAN1HRX
TMS470R1VF45AA 144-PIN PGE PACKAGE (TOP VIEW)
AWD
HET[18]
HET[19]
HET[20]
HET[21]
HET[22]
SPI2SCS
SPI2ENA
SPI2SOMI
SPI2SIMO
SPI2CLK
GIOB[4]
GIOB[3]
GIOB[2]
GIOB[1]
CAN2HRX
CAN2HTX
VCC
VSS
VCCIO
VSSIO
HET[24]
HET[31]
HET[30]
HET[29]
HET[28]
GIOB[0]
SCI2CLK
SCI2TX
SCI2RX
GIOA[3]/INT3
GIOA[2]/INT2
GIOA[1]/INT1/ECLK
GIOA[0]/INT0†
TEST
TRST
TMS470R1VF45AA
16/32-BIT RISC FLASH MICROCONTROLLER
SPNS086A – AUGUST 2003 – REVISED NOVEMBER 2004
description
The TMS470R1VF45AA† device is a member of the Texas Instruments (TI) TMS470R1x family of generalpurpose16/32-bit reduced instruction set computer (RISC) microcontrollers. The VF45AA microcontroller offers
high performance utilizing the high-speed ARM7TDMI 16/32-bit RISC central processing unit (CPU), resulting
in a high instruction throughput while maintaining greater code efficiency. The ARM7TDMI 16/32-bit RISC CPU
views memory as a linear collection of bytes numbered upwards from zero. The TMS470R1VF45AA utilizes
the big-endian format where the most significant byte of a word is stored at the lowest numbered byte and the
least significant byte at the highest numbered byte.
High-end embedded control applications demand more performance from their controllers while maintaining
low costs. The VF45AA RISC core architecture offers solutions to these performance and cost demands while
maintaining low power consumption.
The VF45AA device contains the following:
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ARM7TDMI 16/32-Bit RISC CPU
TMS470R1x system module (SYS) with 470+ enhancements [including an interrupt expansion module
(IEM) and a 16-channel direct-memory access (DMA) controller]
512K-byte Flash
32K-byte SRAM
Zero-pin phase-locked loop (ZPLL) clock module
Analog watchdog (AWD) timer
Real-time interrupt (RTI) module
Three serial peripheral interface (SPI) modules
Two serial communications interface (SCI) modules
Two high-end CAN controller (HECC) modules
10-bit multi-buffered analog-to-digital converter (MibADC) with 16 input channels
High-end timer (HET) controlling 32 I/Os
External clock prescale (ECP) module
Up to 86 I/O pins and 1 input-only pin
The functions performed by the 470+ system module (SYS) include: address decoding; memory protection;
memory and peripherals bus supervision; reset and abort exception management; expanded interrupt capability
with prioritization for all internal interrupt sources; device clock control; direct-memory access and control; and
parallel signature analysis (PSA). This data sheet includes device-specific information such as memory and
peripheral select assignment, interrupt priority, and a device memory map. For a more detailed functional
description of the SYS module, see the TMS470R1x System Module Reference Guide (literature number
SPNU189). For a more detailed functional description of the IEM module, see the TMS470R1x Interrupt Expansion Module (IEM) Reference Guide (literature number SPNU211). And for a more detailed functional
description of the DMA module, see the TMS470R1x Direct Memory Access (DMA) Controller Reference Guide
(literature number SPNU194).
The VF45AA memory includes general-purpose SRAM supporting single-cycle read/write accesses in byte,
half-word, and word modes.
The Flash memory on this device is a nonvolatile, electrically erasable and programmable memory implemented
with a 32-bit-wide data bus interface.The Flash operates with a system clock frequency of up to 24 MHz. When
in pipeline mode, the Flash operates with a system clock frequency of up to 60 MHz. For more detailed
information on the F05 devices Flash, see the F05 Flash section of this data sheet and the TMS470R1x F05
Flash Reference Guide (literature number SPNU213).
† The TMS470R1VF45AA device name shall be referred to as either the full device name or as VF45AA throughout the remainder of this document.
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3
TMS470R1VF45AA
16/32-BIT RISC FLASH MICROCONTROLLER
SPNS086A – AUGUST 2003 – REVISED NOVEMBER 2004
description (continued)
The VF45AA device has seven communication interfaces: three SPIs, two SCIs, and two HECCs. The SPI
provides a convenient method of serial interaction for high-speed communications between similar shift-register
type devices. The SCI is a full-duplex, serial I/O interface intended for asynchronous communication between
the CPU and other peripherals using the standard Non-Return-to-Zero (NRZ) format. The HECC uses a serial,
multimaster communication protocol that efficiently supports distributed real-time control with robust
communication rates of up to 1 megabit per second (Mbps). The HECC is ideal for applications operating in
noisy and harsh environments (e.g., automotive and industrial fields) that require reliable serial communication
or multiplexed wiring. For more detailed functional information on the SPI, SCI, and HECC peripherals, see the
specific Reference Guides (literature numbers SPNU195, SPNU196, and SPNU197, respectively).
The HET is an advanced intelligent timer that provides sophisticated timing functions for real-time applications.
The timer is software-controlled, using a reduced instruction set, with a specialized timer micromachine and
an attached I/O port. The HET can be used for compare, capture, or general-purpose I/O. It is especially well
suited for applications requiring multiple sensor information and drive actuators with complex and accurate
time pulses. For more detailed functional information on the HET, see the TMS470R1x High-End Timer (HET)
Reference Guide (literature number SPNU199).
The VF45AA device has a 10-bit-resolution, 16-channel sample-and-hold MibADC. The MibADC channels can
be converted individually or can be grouped by software for sequential conversion sequences. There are three
separate groupings, two of which can be triggered by an external event. Each sequence can be converted once
when triggered or configured for continuous conversion mode. For more detailed functional information on the
MibADC, see the TMS470R1x Multi-Buffered Analog-to-Digital Converter (MibADC) Reference Guide (literature
number SPNU206).
The zero-pin phase-locked loop (ZPLL) clock module contains a phase-locked loop, a clock-monitor circuit, a
clock-enable circuit, and a prescaler (with prescale values of 1–8). The function of the ZPLL is to multiply the
external frequency reference to a higher frequency for internal use. The ZPLL provides ACLK† to the system
(SYS) module. The SYS module subsequently provides system clock (SYSCLK), real-time interrupt clock
(RTICLK), CPU clock (MCLK), and peripheral interface clock (ICLK) to all other VF45AA device modules. For
more detailed functional information on the ZPLL, see the TMS470R1x Zero-Pin Phase-Locked Loop (ZPLL)
Clock Module Reference Guide (literature number SPNU212).
The VF45AA device also has an external clock prescaler (ECP) module that when enabled, outputs a continuous
external clock (ECLK) on a specified GIO pin. The ECLK frequency is a user-programmable ratio of the peripheral interface clock (ICLK) frequency. For more detailed functional information on the ECP, see the
TMS470R1x External Clock Prescaler (ECP) Reference Guide (literature number SPNU202).
† ACLK should not be confused with the MibADC internal clock, ADCLK. ACLK is the continuous system clock from an external resonator/crystal
reference.
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TMS470R1VF45AA
16/32-BIT RISC FLASH MICROCONTROLLER
SPNS086A – AUGUST 2003 – REVISED NOVEMBER 2004
device characteristics
The TMS470R1VF45AA device is a derivative of the F05 system emulation device SE470R1VB8AD. Table 1
identifies all the characteristics of the TMS470R1VF45AA device except the SYSTEM and CPU, which are
generic. The COMMENTS column aids the user in software-programming and references device-specific information.
Table 1. Device Characteristics
CHARACTERISTICS
DEVICE DESCRIPTION
TMS470R1VF45AA
COMMENTS FOR VF45AA
MEMORY
For the number of memory selects on this device, see the Memory Selection Assignment table (Table 2).
Pipeline/Non-Pipeline
INTERNAL
MEMORY
512K-Byte Flash
32K-Byte SRAM
Flash is pipeline-capable
The VF45AA RAM is implemented in one 32K array selected by two memoryselect signals (see the Memory Selection Assignment table, Table 2).
PERIPHERALS
For the device-specific interrupt priority configurations, see the Interrupt Priority (IEM and CIM) table (Table 6). And for the 1K peripheral
address ranges and their peripheral selects, see the VF45AA Peripherals, System Module, and Flash Base Addresses table (Table 4).
CLOCK
ZPLL
GENERAL-PURPOSE
I/Os
27 I/O
1 Input only
Zero-pin PLL has no external loop filter pins.
Ports A, B, and C each have eight (8) external pins.
Port D has four (4) external pins.
ECP
YES
SCI
2 (3-pin)
SCI1 and SCI2
CAN
(HECC and/or SCC)
2 HECCs
Two high-end CAN controller modules (HECC1 and HECC2)
SPI
(5-pin, 4-pin or 3-pin)
3 (5-pin)
SPI1, SPI2, and SPI3
The VF45AA device has both the logic and registers for a full 32-I/O HET
implemented and all 32 pins are available externally.
HET with
XOR Share
32 I/O
HET RAM
128-Instruction Capacity
MibADC
10-bit, 16-channel
128-word FIFO
CORE VOLTAGE
1.81 - 2.05 V
I/O VOLTAGE
3.0 - 3.6 V
PINS
144
PACKAGE
PGE
The high-resolution (HR) SHARE feature allows even HR pins to share the
next higher odd HR pin structures. This HR sharing is independent of whether
or not the odd pin is available externally. If an odd pin is available externally
and shared, then the odd pin can only be used as a general-purpose I/O. For
more information on HR SHARE, see the TMS470R1x High-End Timer (HET)
Reference Guide (literature number SPNU199).
The VF45AA device has both the logic and registers for a full 16-channel
MibADC implemented and all 16 pins are available externally.
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5
TMS470R1VF45AA
16/32-BIT RISC FLASH MICROCONTROLLER
SPNS086A – AUGUST 2003 – REVISED NOVEMBER 2004
functional block diagram
External Pins
VCCP
FLTP1
FLTP2
OSCIN
FLASH
(512K Bytes)
14 Sectors
RAM
(32K Bytes)
ZPLL
OSCOUT
PLLDIS
ADIN[15:0]
CPU Address/Data Bus
ADEVT
MibADC
with
128 -Word
FIFO
TRST
TMS470R1x
CPU
TCK
ADREFHI
ADREFLO
VCCAD
VSSAD
TDI
TDO
Expansion Address/Data Bus
TMS
TMS470R1x 470+ SYSTEM MODULE
TMS2
RST
AWD
DMA Controller
16 Channels
TEST
IEM
PORRST
HET with
XOR Share
(128 -Word)
HECC1
HECC2
HET [31:24]
HET[23:0]
CAN1HTX
CAN1HRX
CAN2HTX
CAN2HRX
SCI1CLK
SCI1
SCI1TX
SCI1RX
CLKOUT
SCI2CLK
SCI2
SCI2TX
SPI2
SPI1
SPI1SCS
SPI1ENA
SPI1SIMO
SPI1SOMI
SPI1CLK
GIOA[0]/INT0†
GIOA[2:7]/
INT[2:7]
GIOB[0:7]
GIOC[0:7]
GIOD[0:3]
SPI3
SPI2SCS
SPI2ENA
SPI2SIMO
SPI2SOMI
SPI2CLK
GIO
SPI3SCS
SPI3ENA
SPI3SIMO
SPI3SOMI
SPI3CLK
ECP
GIOA[1]/INT1/
ECLK
SCI2RX
† GIOA[0]/INT0 is an input-only GIO pin.
6
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Crystal
External Pins
TMS470R1VF45AA
16/32-BIT RISC FLASH MICROCONTROLLER
SPNS086A – AUGUST 2003 – REVISED NOVEMBER 2004
Terminal Functions
TERMINAL
NAME
NO.
TYPE†‡
INTERNAL
PULLUP/
PULLDOWN§
DESCRIPTION
HIGH-END TIMER (HET)
HET[0]
129
HET[1]
130
HET[2]
137
HET[3]
138
HET[4]
139
HET[5]
140
HET[6]
141
HET[7]
142
HET[8]
79
HET[9]
80
HET[10]
29
HET[11]
28
HET[12]
27
HET[13]
26
HET[14]
25
HET[15]
24
HET[16]
23
HET[17]
22
HET[18]
71
HET[19]
70
HET[20]
69
HET[21]
68
HET[22]
67
HET[23]
123
The VF45AA device has both the logic and registers for a full 32-I/O HET implemented
and all 32 pins are available externally.
Timer input capture or output compare. The HET[31:0] applicable pins can be
programmed as general-purpose input/output (GIO) pins. HET[23:0] are highresolution pins and HET[31:24] are standard-resolution pins.
3.3-V I/O
IPD
IPU
HET[24]
51
HET[25]
124
HET[26]
125
HET[27]
126
HET[28]
47
HET[29]
48
HET[30]
49
HET[31]
50
CAN1HTX
88
3.3-V I/O
CAN1HRX
87
3.3-V I/O
The high-resolution (HR) SHARE feature allows even HR pins to share the next higher
odd HR pin structures. This HR sharing is independent of whether or not the odd pin
is available externally. If an odd pin is available externally and shared, then the odd
pin can only be used as a general-purpose I/O. For more information on HR SHARE,
see the TMS470R1x High-End Timer (HET) Reference Guide (literature number
SPNU199).
HIGH-END CAN CONTROLLER 1 (HECC1)
HECC1 transmit pin or GIO pin
HECC1 receive pin or GIO pin
HIGH-END CAN CONTROLLER 2 (HECC2)
CAN2HTX
56
3.3-V I/O
CAN2HRX
57
3.3-V I/O
IPU
HECC2 transmit pin or GIO pin
HECC2 receive pin or GIO pin
† I = input, O = output, PWR = power, GND = ground, REF = reference voltage, NC = no connect
‡ All I/O pins, except RST, are configured as inputs while PORRST is low and immediately after PORRST goes high.
§ IPD = internal pulldown, IPU = internal pullup (all internal pullups and pulldowns are active on input pins, independent of the PORRST state.)
POST OFFICE BOX 1443
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7
TMS470R1VF45AA
16/32-BIT RISC FLASH MICROCONTROLLER
SPNS086A – AUGUST 2003 – REVISED NOVEMBER 2004
Terminal Functions (Continued)
TERMINAL
NAME
NO.
TYPE†‡
INTERNAL
PULLUP/
PULLDOWN§
DESCRIPTION
GENERAL-PURPOSE I/O (GIO)
GIOA[0]/INT0
39
GIOA[1]/INT1/
ECLK
40
GIOA[2]/INT2
41
GIOA[3]/INT3
42
GIOA[4]/INT4
36
GIOA[5]/INT5
35
GIOA[6]/INT6
34
GIOA[7]/INT7
33
GIOB[0]
46
GIOB[1]
58
GIOB[2]
59
GIOB[3]
60
GIOB[4]
61
GIOB[5]
77
GIOB[6]
78
GIOB[7]
84
GIOC[0]
122
GIOC[1]
143
GIOC[2]
144
GIOC[3]
6
GIOC[4]
7
GIOC[5]
8
GIOC[6]
9
GIOC[7]
10
GIOD[0]
21
GIOD[1]
20
GIOD[2]
19
GIOD[3]
18
ADEVT
99
ADIN[0]
108
ADIN[1]
107
ADIN[2]
106
ADIN[3]
105
ADIN[4]
104
ADIN[5]
102
ADIN[6]
101
ADIN[7]
100
ADIN[8]
115
ADIN[9]
113
3.3-V I
General-purpose input/output pins.
GIOA[0]/INT0 is an input-only pin. GIOA[7:0]/INT[7:0] are interrupt-capable pins.
3.3-V I/O
IPD
The GIOA[1]/INT1/ECLK pin is multiplexed with the external clock-out function of the
external clock prescale (ECP) module.
MULTI-BUFFERED ANALOG-TO-DIGITAL CONVERTER (MibADC)
ADIN[10]
111
ADIN[11]
109
3.3-V I/O
3.3-V I
IPD
MibADC event input. ADEVT can be programmed as a GIO pin.
MibADC analog input pins
ADIN[12]
114
† I = input, O = output, PWR = power, GND = ground, REF = reference voltage, NC = no connect
‡ All I/O pins, except RST, are configured as inputs while PORRST is low and immediately after PORRST goes high.
§ IPD = internal pulldown, IPU = internal pullup (all internal pullups and pulldowns are active on input pins, independent of the PORRST state.)
8
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TMS470R1VF45AA
16/32-BIT RISC FLASH MICROCONTROLLER
SPNS086A – AUGUST 2003 – REVISED NOVEMBER 2004
Terminal Functions (Continued)
TERMINAL
NAME
NO.
TYPE†‡
INTERNAL
PULLUP/
PULLDOWN§
DESCRIPTION
MULTI-BUFFERED ANALOG-TO-DIGITAL CONVERTER (MibADC) (CONTINUED)
ADIN[13]
112
ADIN[14]
110
ADIN[15]
103
3.3-V I
MibADC analog input pins
ADREFHI
116
3.3-V
REF I
MibADC module high-voltage reference input
ADREFLO
117
GND
REF I
MibADC module low-voltage reference input
VCCAD
118
3.3-V
PWR
MibADC analog supply voltage
VSSAD
119
GND
MibADC analog ground reference
SERIAL PERIPHERAL INTERFACE 1 (SPI1)
SPI1CLK
5
SPI1 clock. SPI1CLK can be programmed as a GIO pin.
SPI1ENA
1
SPI1 chip enable. SPI1ENA can be programmed as a GIO pin.
SPI1SCS
2
3.3-V I/O
IPD
SPI1 slave chip select. SPI1SCS can be programmed as a GIO pin.
SPI1SIMO
3
SPI1 data stream. Slave in/master out. SPI1SIMO can be programmed as a GIO pin.
SPI1SOMI
4
SPI1 data stream. Slave out/master in. SPI1SOMI can be programmed as a GIO pin.
SPI2CLK
62
SPI2 clock. SPI2CLK can be programmed as a GIO pin.
SPI2ENA
65
SPI2 chip enable. SPI2ENA can be programmed as a GIO pin.
SERIAL PERIPHERAL INTERFACE 2 (SPI2)
SPI2SCS
66
SPI2SIMO
63
SPI2SOMI
64
3.3-V I/O
IPD
SPI2 slave chip select. SPI2SCS can be programmed as a GIO pin.
SPI2 data stream. Slave in/master out. SPI2SIMO can be programmed as a GIO pin.
SPI2 data stream. Slave out/master in. SPI2SOMI can be programmed as a GIO pin.
SERIAL PERIPHERAL INTERFACE 3 (SPI3)
SPI3CLK
94
SPI3ENA
98
SPI3SCS
97
SPI3SIMO
96
SPI3SOMI
95
SPI3 clock. SPI3CLK can be programmed as a GIO pin.
SPI3 chip enable. SPI3ENA can be programmed as a GIO pin.
3.3-V I/O
IPD
SPI3 slave chip select. SPI3SCS can be programmed as a GIO pin.
SPI3 data stream. Slave in/master out. SPI3SIMO can be programmed as a GIO pin.
SP3 data stream. Slave out/master in. SPI3SOMI can be programmed as a GIO pin.
ZERO-PIN PHASE-LOCKED LOOP (ZPLL)
OSCIN
13
1.8-V I
Crystal connection pin or external clock input
OSCOUT
12
1.8-V O
External crystal connection pin
PLLDIS
73
3.3-V I
SCI1CLK
89
3.3-V I/O
SCI1RX
91
3.3-V I/O
IPU
SCI1 data receive. SCI1RX can be programmed as a GIO pin.
SCI1TX
90
3.3-V I/O
IPU
SCI1 data transmit. SCI1TX can be programmed as a GIO pin.
SCI2CLK
45
3.3-V I/O
IPD
SCI2 clock. SCI2CLK can be programmed as a GIO pin.
SCI2RX
43
3.3-V I/O
IPU
SCI2 data receive. SCI2RX can be programmed as a GIO pin.
IPD
Enable/disable the ZPLL. The ZPLL can be bypassed and the oscillator becomes the
system clock. If not in bypass mode, TI recommends that this pin be connected to
ground or pulled down to ground by an external resistor.
SERIAL COMMUNICATIONS INTERFACE 1 (SCI1)
IPD
SCI1 clock. SCI1CLK can be programmed as a GIO pin.
SERIAL COMMUNICATIONS INTERFACE 2 (SCI2)
SCI2TX
44
3.3-V I/O
IPU
SCI2 data transmit. SCI2TX can be programmed as a GIO pin.
† I = input, O = output, PWR = power, GND = ground, REF = reference voltage, NC = no connect
‡ All I/O pins, except RST, are configured as inputs while PORRST is low and immediately after PORRST goes high.
§ IPD = internal pulldown, IPU = internal pullup (all internal pullups and pulldowns are active on input pins, independent of the PORRST state.)
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9
TMS470R1VF45AA
16/32-BIT RISC FLASH MICROCONTROLLER
SPNS086A – AUGUST 2003 – REVISED NOVEMBER 2004
Terminal Functions (Continued)
TERMINAL
NAME
NO.
TYPE†‡
CLKOUT
83
3.3-V I/O
PORRST
32
3.3-V I
RST
15
3.3-V I/O
AWD
72
3.3-V I/O
INTERNAL
PULLUP/
PULLDOWN§
DESCRIPTION
SYSTEM MODULE (SYS)
Bidirectional pin. CLKOUT can be programmed as a GIO pin or the output of SYSCLK,
IPD
ICLK, or MCLK.
Input master chip power-up reset. External VCC monitor circuitry must assert a powerIPD
on reset.
Bidirectional reset. The internal circuitry can assert a reset, and an external system
reset can assert a device reset.
On this pin, the output buffer is implemented as an open drain (drives low only).
IPU
To ensure an external reset is not arbitrarily generated, TI recommends that an
external pullup resistor be connected to this pin.
WATCHDOG/REAL-TIME INTERRUPT (WD/RTI)
Analog watchdog reset. The AWD pin provides a system reset if the WD KEY is not
written in time by the system, providing an external RC network circuit is connected.
IPD
TCK
76
3.3-V I
IPD
TDI
74
3.3-V I
IPU
TDO
75
3.3-V O
IPD
TEST
38
3.3-V I
IPD
TMS
120
3.3-V I
IPU
TMS2
121
3.3-V I
IPU
TRST
37
3.3-V I
IPD
FLTP1
134
NC
FLTP2
133
NC
VCCP
135
3.3-V
PWR
VCC
14
31
55
86
93
128
132
1.8-V
PWR
If the user is not using AWD, TI recommends that this pin be connected to ground or
pulled down to ground by an external resistor.
For more details on the external RC network circuit, see the TMS470R1x System
Module Reference Guide (literature number SPNU189) and the application note
Analog Watchdog Resistor, Capacitor and Discharge Interval Selection Constraints
(literature number SPNA005).
TEST/DEBUG (T/D)
Test clock. TCK controls the test hardware (JTAG)
Test data in. TDI inputs serial data to the test instruction register, test data register,
and programmable test address (JTAG).
Test data out. TDO outputs serial data from the test instruction register, test data
register, identification register, and programmable test address (JTAG).
Test enable. Reserved for internal use only. TI recommends that this pin be connected
to ground or pulled down to ground by an external resistor.
Serial input for controlling the state of the CPU test access port (TAP) controller (JTAG)
Serial input for controlling the second TAP. TI recommends that this pin be connected
to VCCIO or pulled up to VCCIO by an external resistor.
Test hardware reset to TAP1 and TAP2. IEEE Standard 1149-1 (JTAG) BoundaryScan Logic. TI recommends that this pin be pulled down to ground by an external
resistor.
FLASH
Flash test pad 1. For proper operation, this pin must not be connected [no
connect (NC)].
Flash test pad 2. For proper operation, this pin must not be connected [no
connect (NC)].
Flash external pump voltage (3.3 V). This pin is required for both Flash read and Flash
program and erase operations.
SUPPLY VOLTAGE CORE (1.8 V)
Core logic supply voltage
† I = input, O = output, PWR = power, GND = ground, REF = reference voltage, NC = no connect
‡ All I/O pins, except RST, are configured as inputs while PORRST is low and immediately after PORRST goes high.
§ IPD = internal pulldown, IPU = internal pullup (all internal pullups and pulldowns are active on input pins, independent of the PORRST state.)
10
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TMS470R1VF45AA
16/32-BIT RISC FLASH MICROCONTROLLER
SPNS086A – AUGUST 2003 – REVISED NOVEMBER 2004
Terminal Functions (Continued)
TERMINAL
NAME
NO.
TYPE†‡
INTERNAL
PULLUP/
PULLDOWN§
DESCRIPTION
SUPPLY VOLTAGE DIGITAL I/O (3.3 V)
17
VCCIO
53
3.3-V
PWR
Digital I/O supply voltage
82
SUPPLY GROUND CORE
11
30
54
VSS
85
92
GND
Core supply ground reference
127
131
136
SUPPLY GROUND DIGITAL I/O
16
VSSIO
52
GND
Digital I/O supply ground reference
81
† I = input, O = output, PWR = power, GND = ground, REF = reference voltage, NC = no connect
‡ All I/O pins, except RST, are configured as inputs while PORRST is low and immediately after PORRST goes high.
§ IPD = internal pulldown, IPU = internal pullup (all internal pullups and pulldowns are active on input pins, independent of the PORRST state.)
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11
TMS470R1VF45AA
16/32-BIT RISC FLASH MICROCONTROLLER
SPNS086A – AUGUST 2003 – REVISED NOVEMBER 2004
VF45AA DEVICE-SPECIFIC INFORMATION
memory
Figure 1 shows the memory map of the VF45AA device.
Memory (4G Bytes)
0xFFFF_FFFF
0xFFFF_FFFF
SYSTEM with PSA, CIM, RTI, DEC,
DMA, MMC
System Module Control Registers
(512K Bytes)
IEM
0xFFF8_0000
0xFFF7_FFFF
Reserved
Peripheral Control Registers
(512K Bytes)
0xFFF0_0000
0xFFEF_FFFF
0xFFE8_C000
0xFFE8_BFFF
0xFFE8_8000
0xFFE8_7FFF
0xFFE8_4024
0xFFE8_4023
0xFFE8_4000
0xFFE8_3FFF
HET
Reserved
SPI1
Flash Control Registers
SCI2
Reserved
SCI1
MPU Control Registers
MibADC
GIO/ECP
Reserved
0xFFE0_0000
HECC1/HECC2
HECC1/2 RAM
Reserved
RAM
(32K Bytes)
Program
and
Data Area
FLASH
(512K Bytes)
14 Sectors
SPI2/SPI3
Reserved
Reserved
Reserved
Data Abort
Prefetch Abort
Software Interrupt
0x0000_0000
Undefined Instruction
Exception, Interrupt, and
Reset Vectors
0xFFFF_FC00
0xFFF8_0000
0xFFF7_FC00
0xFFF7_F800
0xFFF7_F500
0xFFF7_F400
0xFFF7_F000
0xFFF7_EC00
0xFFF7_E800
0xFFF7_E400
0xFFF7_D800
0xFFF7_D400
0xFFF7_C000
0xFFF0_0000
0x0000_001F
FIQ
IRQ
0x0000_0020
0x0000_001F
0xFFFF_FD00
Reset
0x0000_001C
0x0000_0018
0x0000_0014
0x0000_0010
0x0000_000C
0x0000_0008
0x0000_0004
0x0000_0000
NOTES: A. Memory addresses are configurable by the system (SYS) module within the range of 0x0000_0000 to 0xFFE0_0000.
B. The CPU registers are not a part of the memory map.
Figure 1. Memory Map
12
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TMS470R1VF45AA
16/32-BIT RISC FLASH MICROCONTROLLER
SPNS086A – AUGUST 2003 – REVISED NOVEMBER 2004
memory selects
Memory selects allow the user to address memory arrays (i.e., Flash, RAM, and HET RAM) at user-defined
addresses. Each memory select has its own set (low and high) of memory base address registers (MFBAHRx
and MFBALRx) that, together, define the array’s starting (base) address, block size, and protection.
The base address of each memory select is configurable to any memory address boundary that is a multiple
of the decoded block size. For more information on how to control and configure these memory select registers,
see the bus structure and memory sections of the TMS470R1x System Module Reference Guide (literature
number SPNU189).
For the memory selection assignments and the memory selected, see Table 2.
Table 2. Memory Selection Assignment
MEMORY
SELECT
MEMORY SELECTED
(ALL INTERNAL)
0 (fine)
FLASH
1 (fine)
FLASH
2 (fine)
RAM
3 (fine)
RAM
4 (fine)
HET RAM
MEMORY
SIZE
512K
32K†
1.5K
MPU
MEMORY BASE ADDRESS REGISTER
NO
MFBAHR0 and MFBALR0
NO
MFBAHR1 and MFBALR1
YES
MFBAHR2 and MFBALR2
YES
MFBAHR3 and MFBALR3
MFBAHR4 and MFBALR4
STATIC MEM
CTL REGISTER
SMCR1
† The starting addresses for both RAM memory-select signals cannot be offset from each other by a multiple of the user-defined block size in the
memory-base address register.
RAM
The VF45AA device contains 32K bytes of internal static RAM configurable by the SYS module to be addressed
within the range of 0x0000_0000 to 0xFFE0_0000. This VF45AA RAM is implemented in one 32K array selected
by two memory-select signals. This VF45AA configuration imposes an additional constraint on the memory
map for RAM; the starting addresses for both RAM memory selects cannot be offset from each other by the
multiples of the size of the physical RAM (i.e., 32K for the VF45AA device). The VF45AA RAM is addressed
through memory selects 2 and 3.
The RAM can be protected by the memory protection unit (MPU) portion of the SYS module, allowing the user
finer blocks of memory protection than is allowed by the memory selects. The MPU is ideal for protecting an
operating system while allowing access to the current task. For more detailed information on the MPU portion
of the SYS module and memory protection, see the memory section of the TMS470R1x System Module
Reference Guide (literature number SPNU189).
F05 Flash
The F05 Flash memory is a nonvolatile electrically erasable and programmable memory implemented with a
32-bit-wide data bus interface. The F05 Flash has an external state machine for program and erase functions.
See the Flash read and Flash program and erase sections below. For more detailed functional information on
the F05 Flash module, see the TMS470R1x F05 Flash Reference Guide (literature number SPNU213).
flash protection keys
The VF45AA device provides Flash protection keys. These four 32-bit protection keys prevent program/erase/
compaction operations from occurring until after the four protection keys have been matched by the CPU loading
the correct user keys into the FMPKEY control register. The protection keys on the VF45AA are located in the
last 4 words of the first 16K sector. For more detailed information on the Flash protection keys and the FMPKEY
control register, see the Optional Quadruple Protection Keys and Programming the Protection Keys portions
of the TMS470R1x F05 Flash Reference Guide (literature number SPNU213).
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13
TMS470R1VF45AA
16/32-BIT RISC FLASH MICROCONTROLLER
SPNS086A – AUGUST 2003 – REVISED NOVEMBER 2004
Flash read
The VF45AA Flash memory is configurable by the SYS module to be addressed within the range of
0x0000_0000 to 0xFFE0_0000. The Flash is addressed through memory selects 0 and 1.
Note: The Flash external pump voltage (VCCP) is required for all operations (program, erase, and read).
Flash pipeline mode
When in pipeline mode, the Flash operates with a system clock frequency of up to 60 MHz (versus a system
clock in normal mode of up to 24 MHz). Flash in pipeline mode is capable of accessing 64-bit words and provides
two 32-bit pipelined words to the CPU. Also in pipeline mode, the Flash can be read with no wait states when
memory addresses are contiguous (after the initial 1-or 2-wait-state reads).
Note: After a system reset, pipeline mode is disabled (ENPIPE bit [FMREGOPT.0] is a "0"). In other words,
the VF45AA device powers up and comes out of reset in non-pipeline mode. Furthermore, setting the Flash
configuration mode bit (GLBCTRL.4) will override pipeline mode.
Flash program and erase
The VF45AA device Flash contains two 256K-byte memory arrays (or banks) for a total of 512K bytes of Flash
and consists of fourteen sectors. These fourteen sectors are sized as follows:
Table 3. VF45AA Flash Memory Banks and Sectors
SECTOR
NO.
SEGMENT
LOW ADDRESS
HIGH ADDRESS
0
16K Bytes
0x00000000
0x00003FFF
1
16K Bytes
0x00004000
0x00007FFF
2
32K Bytes
0x00008000
0x0000FFFF
3
32K Bytes
0x00010000
0x00017FFF
4
32K Bytes
0x00018000
0x0001FFFF
5
32K Bytes
0x00020000
0x00027FFF
6
32K Bytes
0x00028000
0x0002FFFF
7
32K Bytes
0x00030000
0x00037FFF
8
16K Bytes
0x00038000
0x0003BFFF
9
16K Bytes
0x0003C000
0x0003FFFF
0
64K Bytes
0x00040000
0x0004FFFF
1
64K Bytes
0x00050000
0x0005FFFF
2
64K Bytes
0x00060000
0x0006FFFF
3
64K Bytes
0x00070000
0x0007FFFF
MEMORY ARRAYS
(OR BANKS)
BANK0
(256K Bytes)
BANK1
(256K Bytes)
The minimum size for an erase operation is one sector. The maximum size for a program operation is one
16-bit word.
Note: The Flash external pump voltage (VCCP) is required for all operations (program, erase, and read).
For more detailed information on Flash program and erase operations, see the TMS470R1x F05 Flash Reference Guide (literature number SPNU213).
14
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TMS470R1VF45AA
16/32-BIT RISC FLASH MICROCONTROLLER
SPNS086A – AUGUST 2003 – REVISED NOVEMBER 2004
HET RAM
The VF45AA device contains HET RAM. The HET RAM has a 128-instruction capability. The HET RAM is
configurable by the SYS module to be addressed within the range of 0x0000_0000 to 0xFFE0_0000. The HET
RAM is addressed through memory select 4.
XOR share
The VF45AA HET peripheral contains the XOR-share feature. This feature allows two adjacent HET highresolution channels to be XORed together, making it possible to output smaller pulses than a standard HET.
For more detailed information on the HET XOR-share feature, see the TMS470R1x High-End Timer (HET)
Reference Guide (literature number SPNU199).
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15
TMS470R1VF45AA
16/32-BIT RISC FLASH MICROCONTROLLER
SPNS086A – AUGUST 2003 – REVISED NOVEMBER 2004
peripheral selects and base addresses
The VF45AA device uses eight of the sixteen peripheral selects to decode the base addresses of the peripherals.
These peripheral selects are fixed and transparent to the user since they are part of the decoding scheme used
by the SYS module.
Control registers for the peripherals, SYS module, and Flash begin at the base addresses shown in Table 4.
Table 4. VF45AA Peripherals, System Module, and Flash Base Addresses
CONNECTING MODULE
16
ADDRESS RANGE
BASE ADDRESS
ENDING ADDRESS
PERIPHERAL SELECTS
SYSTEM
0xFFFF_FFD0
0xFFFF_FFFF
N/A
RESERVED
0xFFFF_FF60
0xFFFF_FFCF
N/A
PSA
0xFFFF_FF40
0xFFFF_FF5F
N/A
CIM
0xFFFF_FF20
0xFFFF_FF3F
N/A
RTI
0xFFFF_FF00
0xFFFF_FF1F
N/A
DMA
0xFFFF_FE80
0xFFFF_FEFF
N/A
DEC
0xFFFF_FE00
0xFFFF_FE7F
N/A
MMC
0xFFFF_FD00
0xFFFF_FD7F
N/A
IEM
0xFFFF_FC00
0xFFFF_FCFF
N/A
RESERVED
0xFFFF_FB00
0xFFFF_FBFF
N/A
RESERVED
0xFFFF_FA00
0xFFFF_FAFF
N/A
DMA CMD BUFFER
0xFFFF_F800
0xFFFF_F9FF
N/A
RESERVED
0xFFF8_0000
0xFFFF_F7FF
N/A
RESERVED
0xFFF7_FD00
0xFFF7_FFFF
HET
0xFFF7_FC00
0xFFF7_FCFF
RESERVED
0xFFF7_F900
0xFFF7_FBFF
SPI1
0xFFF7_F800
0xFFF7_F8FF
RESERVED
0xFFF7_F600
0xFFF7_F7FF
SCI2
0xFFF7_F500
0xFFF7_F5FF
SCI1
0xFFF7_F400
0xFFF7_F4FF
RESERVED
0xFFF7_F100
0xFFF7_F3FF
MibADC
0xFFF7_F000
0xFFF7_F0FF
ECP
0xFFF7_EF00
0xFFF7_EFFF
RESERVED
0xFFF7_ED00
0xFFF7_EEFF
GIO
0xFFF7_EC00
0xFFF7_ECFF
HECC2
0xFFF7_EA00
0xFFF7_EBFF
HECC1
0xFFF7_E800
0xFFF7_E9FF
HECC2 RAM
0xFFF7_E600
0xFFF7_E7FF
HECC1 RAM
0xFFF7_E400
0xFFF7_E5FF
PS[0]
PS[1]
PS[2]
PS[3]
PS[4]
PS[5]
PS[6]
RESERVED
0xFFF7_E000
0xFFF7_E3FF
PS[7]
RESERVED
0xFFF7_DC00
0xFFF7_DFFF
PS[8]
RESERVED
0xFFF7_D800
0xFFF7_DBFF
PS[9]
RESERVED
0xFFF7_D600
0xFFF7_D7FF
SPI3
0xFFF7_D500
0xFFF7_D5FF
SPI2
0xFFF7_D400
0xFFF7_D4FF
RESERVED
0xFFF7_C000
0xFFF7_D3FF
PS[11] - PS[15]
RESERVED
0xFFF0_0000
0xFFF7_BFFF
N/A
FLASH CONTROL REGISTERS
0xFFE8_8000
0xFFE8_BFFF
N/A
MPU CONTROL REGISTERS
0xFFE8_4000
0xFFE8_4023
N/A
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PS[10]
TMS470R1VF45AA
16/32-BIT RISC FLASH MICROCONTROLLER
SPNS086A – AUGUST 2003 – REVISED NOVEMBER 2004
direct-memory access (DMA)
The direct-memory access (DMA) controller transfers data to and from any specified location in the VF45AA
memory map (except for restricted memory locations like the system control registers area). The DMA manages
up to 16 channels, and supports data transfer for both on-chip and off-chip memories and peripherals. The
DMA controller is connected to both the CPU and Peripheral busses, enabling these data transfers to occur in
parallel with CPU activity and thus, maximizing overall system performance.
Although the DMA controller has two possible configurations, for the VF45AA device, the DMA controller
configuration is 32 control packets and 16 channels.
For the VF45AA DMA request hardwired configuration, see Table 5.
Table 5. DMA Request Lines Connections
MODULES
DMA REQUEST INTERRUPT SOURCES
RESERVED
DMA CHANNEL
DMAREQ[0]
SPI1
SPI1 end-receive
SPI1DMA0
DMAREQ[1]
SPI1
SPI1 end-transmit
SPI1DMA1
DMAREQ[2]
DMAREQ[3]
†
MibADC event
MibADCDMA0
MibADC†/SCI1
MibADC G1/SCI1 end-receive
MibADCDMA1/SCI1DMA0
DMAREQ[4]
MibADC†/SCI1
MibADC G2/SCI1 end-transmit
MibADCDMA2/SCI1DMA1
DMAREQ[5]
SPI2
SPI2 end-receive
SPI2DMA0
SPI2
SPI2 end-transmit
SPI2DMA1
MibADC
RESERVED
DMAREQ[6]
DMAREQ[7]
DMAREQ[8]
RESERVED
DMAREQ[9]
RESERVED
DMAREQ[10]
RESERVED
DMAREQ[11]
RESERVED
DMAREQ[12]
RESERVED
DMAREQ[13]
SCI2/SPI3
SCI2 end-receive/SPI3 end-receive SCI2DMA0/SPI3DMA0
DMAREQ[14]
SCI2/SPI3
SCI2 end-transmit/SPI3
end-transmit
DMAREQ[15]
SCI2DMA1/SPI3DMA1
† The MibADC is capable of being serviced by the DMA when the device is in buffered mode. For more information on buffered mode, see the
MibADC section of this data sheet and the TMS470R1x Multi-Buffered Analog-to-Digital Converter (MibADC) Reference Guide (literature number
SPNU206).
Each channel has two control packets attached to it, allowing the DMA to continuously load RAM and generate
periodic interrupts so that the data can be read by the CPU. The control packets allow for the interrupt enable,
and the channels determine the priority level of the interrupt.
DMA transfers occur in one of two modes:
●
Non-request mode (used when transferring from memory to memory)
●
Request mode (used when transferring from memory to peripheral)
For more detailed functional information on the DMA controller, see the TMS470R1x Direct Memory Access
(DMA) Controller Reference Guide (literature number SPNU194).
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17
TMS470R1VF45AA
16/32-BIT RISC FLASH MICROCONTROLLER
SPNS086A – AUGUST 2003 – REVISED NOVEMBER 2004
interrupt priority (IEM to CIM)
Interrupt requests originating from the VF45AA peripheral modules (i.e., SPI1, SPI2, or SPI3; SCI1 or SCI2;
HECC1 or HECC2; RTI; etc.) are assigned to channels within the 48-channel interrupt expansion module (IEM)
where, via programmable register mapping, these channels are then mapped to the 32-channel central interrupt
manager (CIM) portion of the SYS module.
Programming multiple interrupt sources in the IEM to the same CIM channel effectively shares the CIM channel
between sources.
The CIM request channels are maskable so that individual channels can be selectively disabled. All interrupt
requests can be programmed in the CIM to be of either type:
●
Fast interrupt request (FIQ)
●
Normal interrupt request (IRQ)
The CIM prioritizes interrupts. The precedences of request channels decrease with ascending channel order
in the CIM (0 [highest] and 31 [lowest] priority). For IEM-to-CIM default mapping, channel priorities, and their
associated modules, see Table 6.
Table 6. Interrupt Priority (IEM and CIM)
MODULES
INTERRUPT SOURCES
DEFAULT CIM
INTERRUPT LEVEL/
CHANNEL
IEM
CHANNEL
SPI1
SPI1 end-transfer/overrun
0
0
RTI
COMP2 interrupt
1
1
RTI
COMP1 interrupt
2
2
RTI
TAP interrupt
3
3
SPI2
SPI2 end-transfer/overrun
4
4
GIO
GIO interrupt A
5
5
Reserved
HET
6
6
HET interrupt 1
7
7
8
8
SCI1 or SCI2 error interrupt
9
9
SCI1 receive interrupt
10
10
RESERVED
SCI1/SCI2
SCI1
RESERVED
11
11
RESERVED
12
12
13
13
HECC1
HECC1 interrupt A
RESERVED
SPI3
MibADC
14
14
SPI3 end-transfer/overrun
15
15
16
MibADC end event conversion
16
SCI2
SCI2 receive interrupt
17
17
DMA
DMA interrupt 0
18
18
19
19
RESERVED
SCI1
System
SCI1 transmit interrupt
20
20
SW interrupt (SSI)
21
21
22
22
HET interrupt 2
23
23
HECC1 interrupt B
24
24
25
25
RESERVED
HET
HECC1
RESERVED
18
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16/32-BIT RISC FLASH MICROCONTROLLER
SPNS086A – AUGUST 2003 – REVISED NOVEMBER 2004
interrupt priority (IEM to CIM) (continued)
Table 6. Interrupt Priority (IEM and CIM) (Continued)
MODULES
SCI2
INTERRUPT SOURCES
DEFAULT CIM
INTERRUPT LEVEL/
CHANNEL
IEM
CHANNEL
SCI2 transmit interrupt
26
26
MibADC end Group 1 conversion
27
27
DMA
DMA interrupt 1
28
28
GIO
GIO interrupt B
29
29
MibADC end Group 2 conversion
30
30
RESERVED
31
31
RESERVED
31
32
RESERVED
31
33
RESERVED
31
34
RESERVED
31
35
RESERVED
31
36
RESERVED
31
37
MibADC
MibADC
HECC2
HECC2 interrupt A
31
38
HECC2
HECC2 interrupt B
31
39
RESERVED
31
40
RESERVED
31
41
RESERVED
31
42
RESERVED
31
43
RESERVED
31
44
RESERVED
31
45
RESERVED
31
46
RESERVED
31
47
For more detailed functional information on the IEM, see the TMS470R1x Interrupt Expansion Module (IEM)
Reference Guide (literature number SPNU211). For more detailed functional information on the CIM, see the
TMS470R1x System Module Reference Guide (literature number SPNU189).
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TMS470R1VF45AA
16/32-BIT RISC FLASH MICROCONTROLLER
SPNS086A – AUGUST 2003 – REVISED NOVEMBER 2004
MibADC
The multi-buffered analog-to-digital converter (MibADC) accepts an analog signal and converts the signal to a
10-bit digital value.
The VF45AA MibADC module can function in two modes: compatibility mode, where it’s programmer’s model
is compatible with the TMS470R1x ADC module and its digital results are stored in digital result registers; or
in buffered mode, where the digital result registers are replaced with three FIFO buffers, one for each conversion
group [event, group1 (G1), and group2 (G2)]. In buffered mode, the MibADC buffers can be serviced by interrupts
or by the DMA.
MibADC event trigger enhancements
The MibADC includes two major enhancements over the event-triggering capability of the TMS470R1x ADC.
●
Both group1 and the event group can be configured for event-triggered operation, providing up to two eventtriggered groups.
●
The trigger source and polarity can be selected individually for both group 1 and the event group from the
three options identified in Table 7.
Table 7. MibADC Event Hookup Configuration
EVENT #
SOURCE SELECT BITS FOR G1 OR EVENT
(G1SRC[1:0] or EVSRC[1:0])
SIGNAL PIN NAME
EVENT1
00
ADEVT
EVENT2
01
HET18
EVENT3
10
HET19
EVENT4
11
RESERVED
For group 1, these event-triggered selections are configured via the group 1 source select bits (G1SRC[1:0])
in the AD event source register (ADEVTSRC.[5:4]). For the event group, these event-triggered selections are
configured via the event group source select bits (EVSRC[1:0]) in the AD event source register
(ADEVTSRC.[1:0]).
For more detailed functional information on the MibADC, see the TMS470R1x Multi-Buffered Analog-to-Digital
Converter (MibADC) Reference Guide (literature number SPNU206).
20
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development system support
Texas Instruments provides extensive hardware and software development support tools for the TMS470R1x
family. These support tools include:
●
Code Composer Studio IDE
–
–
–
●
Optimizing C compiler
–
–
–
–
–
–
–
●
Provides extensive macro capability
Allows high-speed operation
Allows extensive control of the assembly process using assembler directives
Automatically resolves memory references as C and assembly modules are combined
TMS470R1x CPU Simulator
–
–
–
●
Supports high-level language programming
Full implementation of the standard ANSI C language
Powerful optimizer that improves code-execution speed and reduces code size
Extensive run-time support library included
TMS470R1x control registers easily accessible from the C program
Interfaces C functions and assembly functions easily
Establishes comprehensive, easy-to-use tool set for the development of high-performance
microcontroller applications in C/C++
Assembly language tools (assembler and linker)
–
–
–
–
●
Fully integrated suite of software development tools
Includes Compiler/Assembler/Linker, Debugger, and Simulator
Supports Real-Time analysis, data visualization, and open API
Provides capability to simulate CPU operation without emulation hardware
Allows inspection and modifications of memory locations
Allows debugging programs in C or assembly language
XDS emulation communication kits
–
Allow high-speed JTAG communication to the TMS470R1x emulator or target board
For information on pricing and availability, contact the nearest TI field sales office or authorized distributor.
Code Composer Studio is a trademark of Texas Instruments.
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TMS470R1VF45AA
16/32-BIT RISC FLASH MICROCONTROLLER
SPNS086A – AUGUST 2003 – REVISED NOVEMBER 2004
documentation support
Extensive documentation supports all of the TMS470 microcontroller family generation of devices. The types
of documentation available include: data sheets with design specifications; complete user’s guides for all
devices and development support tools; and hardware and software applications. Useful reference documentation includes:
●
●
22
User’s Guides
–
TMS470R1x 32-Bit RISC Microcontroller Family User’s Guide (literature number SPNU134)
–
TMS470R1x C/C++ Compiler User’s Guide (literature number SPNU151)
–
TMS470R1x Code Generation Tools Getting Started Guide (literature number SPNU117)
–
TMS470R1x C Source Debugger User’s Guide (literature number SPNU124)
–
TMS470R1x Assembly Language Tools User’s Guide (literature number SPNU118)
–
TMS470R1x System Module Reference Guide (literature number SPNU189)
–
TMS470R1x Serial Peripheral Interface (SPI) Reference Guide (literature number SPNU195)
–
TMS470R1x Serial Communication Interface (SCI) Reference Guide (literature number SPNU196)
–
TMS470R1x Controller Area Network (CAN) Reference Guide (literature number SPNU197)
–
TMS470R1x High-End Timer (HET) Reference Guide (literature number SPNU199)
–
TMS470R1x External Clock Prescale (ECP) Reference Guide (literature number SPNU202)
–
TMS470R1x Multi-Buffered Analog-to-Digital Converter (MibADC) Reference Guide
(literature number SPNU206)
–
TMS470R1x Zero-Pin Phase-Locked Loop (ZPLL) Clock Module Reference Guide
(literature number SPNU212)
–
TMS470R1x F05 Flash Reference Guide (literature number SPNU213)
Application Reports:
–
Analog Watchdog Resistor, Capacitor and Discharge Interval Selection Constraints
(literature number SPNA005)
–
F05/C05 Power Up Reset and Power Sequencing Requirements (literature number SPNA009)
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SPNS086A – AUGUST 2003 – REVISED NOVEMBER 2004
device numbering conventions
Figure 2 illustrates the numbering and symbol nomenclature for the TMS470R1x family.
TMS 470 R1 V F 45 A A PGE A
Prefix: TMS = Standard Prefix for Fully Qualified Devices
Family:
470 = TMS470 RISC-Embedded Microcontroller Family
V = 1.8-V Core Voltage
Program Memory Types:
CPU Type:
Device Type:
Program Memory Size
C
F
L
B
R
=
=
=
=
=
Masked ROM
Flash
ROM-less
System Emulator for Development Tools
RAM
R1 = ARM7TDMI CPU
45 = ’45 Devices Contain the Following Modules:
– ZPLL Clock
– 32K-Byte Static RAM
– 1.5 K-Byte HET RAM (128 Instructions)
– Analog Watchdog (AWD)
– Real-Time Interrupt (RTI)
– 16-Channel Direct Memory Access (DMA) Controller
– Interrupt Expansion Module
– 10-Bit, 16-Input Multi-buffered Analog-to-Digital
Converter (MibADC) with 128-Word FIFO Buffer
– Three Serial Peripheral Interface (SPI) Modules
– Two Serial Communications Interface (SCI) Modules
– Two High-End CAN Controller (HECC) Modules
– High-End Timer (HET)
– External Clock Prescaler (ECP)
A = 0
– No on-chip program memory
1–5 – 1 to < 128K Bytes
6–B – 128K Bytes to < 1M Bytes
C–F – > 1M Bytes
Operating Free-Air
Temperature Ranges:
A =
T =
–40°C to 85°C
–40°C to 105°C
Q =
–40°C to 125°C
Silicon Version: Blank = Version 1.0
A = Version 2.0
B = Version 3.0
Package: PGE = 144-Pin Plastic Low-Profile Quad Flatpack (LQFP)
Figure 2. TMS470R1x Family Nomenclature
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TMS470R1VF45AA
16/32-BIT RISC FLASH MICROCONTROLLER
SPNS086A – AUGUST 2003 – REVISED NOVEMBER 2004
device identification code register
The device identification code register identifies the silicon version, the technology family (TF), a ROM or Flash
device, and an assigned device-specific part number (see Table 8). The VF45AA device identification code
register value is 0x292Fh.
Table 8. TMS470 Device ID Bit Allocation Register
BIT 31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
BIT 16
6
5
4
3
2
1
BIT 0
Reserved
FFFF_FFF0
BIT 15
LEGEND:
For bits 3–15:
For bits 0–2:
14
13
12
11
10
9
8
7
VERSION
TF
R/F
PART NUMBER
1
1
1
R-K
R-K
R-K
R-K
R-1
R-1
R-1
R = Read only, -K = Value constant after RST
R = Read only, -1 = Value after RST
Bits 31:16
Reserved. Reads are undefined and writes have no effect.
Bits 15:12
VERSION. Silicon version (revision) bits
These bits identify what version of silicon the device is. Initial device version numbers
start at "0000" ("0010" is the current revision for the VF45AA device).
Bit 11
TF. Technology Family (TF) bit
This bit distinguishes the technology family core power supply:
0 = 3.3 V for F10/C10 devices
1 = 1.8 V for F05/C05 devices
Bit 10
R/F. ROM/Flash bit
This bit distinguishes between ROM and Flash devices:
0 = Flash device
1 = ROM device
Bits 9:3
PART NUMBER. Device-specific part number bits
These bits identify the assigned device-specific part number.
The assigned device-specific part number for the VF45AA device is: 0100101.
Bits 2:0
24
"1" Mandatory High. Bits 2,1, and 0 are tied high by default.
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SPNS086A – AUGUST 2003 – REVISED NOVEMBER 2004
device part numbers
Table 9 lists all the available TMS470R1VF45AA devices.
Table 9. Device Part Numbers†
DEVICE PART
NUMBER
PROGRAM MEMORY
PACKAGE TYPE
TEMPERATURE RANGES
FLASH
EEPROM
144-PIN
LQFP
−40°C TO 85°C
TMS470R1VF45AAPGEA
X
X
X
TMS470R1VF45AAPGET
X
X
TMS470R1VF45AAPGEQ
X
X
TMS470R1VF45ACPGEA
X
X
TMS470R1VF45ACPGET
X
X
TMS470R1VF45ACPGEQ
X
X
TMS470R1VF45AEPGEA
X
X
TMS470R1VF45AEPGET
X
X
TMS470R1VF45AEPGEQ
X
X
ROM
−40°C TO 105°C
−40°C TO 125°C
X
X
X
X
X
X
X
X
† The various part numbers listed in this table differ due to differences in either electrical specifications or functional errata. Electrical differences
will be noted in this datasheet. For functional errata, see the errata document for the specific part number you are using.
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TMS470R1VF45AA
16/32-BIT RISC FLASH MICROCONTROLLER
SPNS086A – AUGUST 2003 – REVISED NOVEMBER 2004
DEVICE ELECTRICAL SPECIFICATIONS AND TIMING PARAMETERS
absolute maximum ratings over operating free-air temperature range, Q version
(unless otherwise noted)†
Supply voltage range, VCC (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to 2.5 V
Supply voltage range: VCCIO , VCCAD , VCCP (Flash pump) (see Note 1) . . . . . . . . . . . . . . . . . . . .−0.3 V to 4.1V
Input voltage range: All input pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to 4.1 V
Input clamp current: IIK (VI < 0 or VI > VCCIO)
All pins except ADIN[0:15], PORRST, TRST, TEST, and TCK . . . . . . . . . . . . . . ±20 mA
IIK (VI < 0 or VI > VCCAD)
ADIN[0:15] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±10 mA
Operating free-air temperature ranges, TA: A version . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −40°C to 85°C
T version . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −40°C to 105°C
Q version . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −40°C to 125°C
Operating junction temperature range, TJ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −40°C to 150°C
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only,
and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is
not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: All voltage values are with respect to their associated grounds.
device recommended operating conditions‡
MIN
NOM
MAX
UNIT
2.05
V
VCC
Digital logic supply voltage (Core)
VCCIO
Digital logic supply voltage (I/O)
3
3.3
3.6
V
VCCAD
MibADC supply voltage
3
3.3
3.6
V
VCCP
Flash pump supply voltage
3
3.3
3.6
V
VSS
Digital logic supply ground
VSSAD
MibADC supply ground
1.81
0
A version
TA
TJ
Operating free-air temperature
− 0.1
0.1
V
− 40
85
°C
T version
− 40
105
°C
Q version
− 40
125
°C
− 40
150
°C
Operating junction temperature
‡ All voltages are with respect to VSS, except VCCAD, which is with respect to VSSAD.
26
V
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16/32-BIT RISC FLASH MICROCONTROLLER
SPNS086A – AUGUST 2003 – REVISED NOVEMBER 2004
electrical characteristics over recommended operating free-air temperature range, Q version
(unless otherwise noted)†
PARAMETER
Vhys
TEST CONDITIONS
Input hysteresis
‡
VIL
VIH
Low-level input voltage
High-level input voltage
Input threshold voltage
0.8
OSCIN only
− 0.3
0.35 VCC
All inputs except
OSCIN
2
0.65 VCC
AWD only
Drain to source on
resistance
VOL
Low-level output voltage¶
VOH
High-level output voltage¶
IIC
Input clamp current (I/O pins)#
Input current (I/O pins)
AWD only
1.35
IOL = IOL MAX
IOH = IOH MIN
IOH = 50 µA
IOL
45
Ω
0.8 VCCIO
V I < VSSIO − 0.3 or VI > VCCIO + 0.3
−2
2
−1
1
IIL Pulldown
VI = VSS
VI = VCCIO
5
40
IIL Pullup
VI = VSS
−40
−5
IIH Pullup
VI = VCCIO
−1
1
All other pins
No pullup or pulldown
−1
1
mA
µA
8
4
VOL = VOL MAX
mA
2
−8
CLKOUT,TDO
RST, SPInCLK,
SPInSOMI,
SPInSIMO
V
V
VCCIO − 0.2
output pins||
High-level output
current
V
0.2
All other
IOH
V
1.8
IIH Pulldown
RST, SPInCLK,
SPInSOMI,
SPInSIMO
V
VCC + 0.3
0.2 VCCIO
IOL = 50 µA
CLKOUT, AWD, TDO
Low-level output
current
VCCIO + 0.3
§
VOL = 0.35V @ IOL = 8mA
UNIT
V
− 0.3
RDSON
II
MAX
All inputs except
OSCIN
OSCIN only
Vth
MIN
0.15
VOH = VOH MIN
All other output pins
−4
mA
−2
except RST||
† Source currents (out of the device) are negative while sink currents (into the device) are positive.
‡ This does not apply to the PORRST pin. For PORRST exceptions, see the RST and PORRST timings section on page 34.
§ These values help to determine the external RC network circuit. For more details, see the TMS470R1x System Module Reference Guide
(literature number SPNU189).
¶ VOL and VOH are linear with respect to the amount of load current (IOL/IOH) applied.
# Parameter does not apply to input-only or output-only pins.
||
The 2 mA buffers on this device are called zero-dominant buffers. If two of these buffers are shorted together and one is outputting a low level
and the other is outputting a high level, the resulting value will always be low.
✩ For Flash pumps/banks in sleep mode.
❏ I/O pins configured as inputs or outputs with no load. All pulldown inputs ≤ 0.2 V. All pullup inputs ≥ VCCIO − 0.2 V.
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TMS470R1VF45AA
16/32-BIT RISC FLASH MICROCONTROLLER
SPNS086A – AUGUST 2003 – REVISED NOVEMBER 2004
electrical characteristics over recommended operating free-air temperature range, Q version
(unless otherwise noted) (continued)†
PARAMETER
ICCP
MAX UNIT
mA
SYSCLK = 24 MHz,
ICLK = 12 MHz, VCC = 2.05 V
85
mA
VCC Digital supply current (standby mode)✫
OSCIN = 6 MHz, VCC = 2.05 V
4.0
mA
VCC Digital supply current (halt mode)✫
All frequencies, VCC = 2.05 V
2.0
mA
VCCIO Digital supply current (operating mode)
No DC load, VCCIO = 3.6 V❏
10
mA
VCCIO Digital supply current (standby mode)
No DC load, VCCIO = 3.6 V❏
300
µA
VCCIO Digital supply current (halt mode)
No DC load, VCCIO = 3.6 V❏
300
µA
VCCAD supply current (operating mode)
All frequencies, VCCAD = 3.6 V
15
mA
VCCAD supply current (standby mode)
All frequencies, VCCAD = 3.6 V
20
µA
VCCAD supply current (halt mode)
All frequencies, VCCAD = 3.6 V
20
µA
VCCP = 3.6 V read operation
55
mA
VCCP = 3.6 V program and erase
70
mA
20
µA
20
µA
ICC
ICCAD
TYP
125
VCC Digital supply current (operating mode)
ICCIO
MIN
TEST CONDITIONS
SYSCLK = 60 MHz,
ICLK = 20 MHz, VCC = 2.05 V
VCCP pump supply current
VCCP
= 3.6 V standby mode operation✫
✫
VCCP = 3.6 V halt mode operation
CI
Input capacitance
2
pF
CO
Output capacitance
3
pF
† Source currents (out of the device) are negative while sink currents (into the device) are positive.
‡ This does not apply to the PORRST pin. For PORRST exceptions, see the RST and PORRST timings section on page 34.
§ These values help to determine the external RC network circuit. For more details, see the TMS470R1x System Module Reference Guide
(literature number SPNU189).
¶ VOL and VOH are linear with respect to the amount of load current (IOL/IOH) applied.
# Parameter does not apply to input-only or output-only pins.
||
The 2 mA buffers on this device are called zero-dominant buffers. If two of these buffers are shorted together and one is outputting a low level
and the other is outputting a high level, the resulting value will always be low.
✩ For Flash pumps/banks in sleep mode.
❏ I/O pins configured as inputs or outputs with no load. All pulldown inputs ≤ 0.2 V. All pullup inputs ≥ VCCIO − 0.2 V.
28
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16/32-BIT RISC FLASH MICROCONTROLLER
SPNS086A – AUGUST 2003 – REVISED NOVEMBER 2004
PARAMETER MEASUREMENT INFORMATION
IOL
Tester Pin
Electronics
50 Ω
VLOAD
Output
Under
Test
CL
IOH
Where: IOL
= IOL MAX for the respective pin (see Note A)
= IOH MIN for the respective pin (see Note A)
IOH
VLOAD = 1.5 V
= 150-pF typical load-circuit capacitance (see Note B)
CL
NOTES: A. For these values, see the electrical characteristics over recommended operating free-air temperature range table.
B. All timing parameters measured using an external load capacitance of 150 pF unless otherwise noted.
Figure 3. Test Load Circuit
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TMS470R1VF45AA
16/32-BIT RISC FLASH MICROCONTROLLER
SPNS086A – AUGUST 2003 – REVISED NOVEMBER 2004
timing parameter symbology
Timing parameter symbols have been created in accordance with JEDEC Standard 100. In order to shorten
the symbols, some of the pin names and other related terminology have been abbreviated as follows:
CM
CO
ER
ICLK
M
OSC, OSCI
OSCO
P
R
R0
R1
Compaction, CMPCT
CLKOUT
Erase
Interface clock
Master mode
OSCIN
OSCOUT
Program, PROG
Ready
Read margin 0, RDMRGN0
Read margin 1, RDMRGN1
RD
RST
RX
S
SCC
SIMO
SOMI
SPC
SYS
TX
Read
Reset, RST
SCInRX
Slave mode
SCInCLK
SPInSIMO
SPInSOMI
SPInCLK
System clock
SCInTX
r
su
t
v
w
rise time
setup time
transition time
valid time
pulse duration (width)
Lowercase subscripts and their meanings are:
a
c
d
f
h
access time
cycle time (period)
delay time
fall time
hold time
The following additional letters are used with these meanings:
30
H
High
X
L
V
Low
Valid
Z
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SPNS086A – AUGUST 2003 – REVISED NOVEMBER 2004
external reference resonator/crystal oscillator clock option
The oscillator is enabled by connecting the appropriate fundamental 4–20 MHz resonator/crystal and load
capacitors across the external OSCIN and OSCOUT pins as shown in Figure 4a. The oscillator is a singlestage inverter held in bias by an integrated bias resistor. This resistor is disabled during leakage test measurement and HALT mode. TI strongly encourages each customer to submit samples of the device to the
resonator/crystal vendors for validation. The vendors are equipped to determine what load capacitors will
best tune their resonator/crystal to the microcontroller device for optimum start-up and operation over temperature/voltage extremes.
An external oscillator source can be used by connecting a 1.8V clock signal to the OSCIN pin and leaving the
OSCOUT pin unconnected (open) as shown in Figure 4b.
OSCIN
C1
(see Note A)
OSCOUT
Crystal
OSCIN
C2
(see Note A)
OSCOUT
External
Clock Signal
(toggling 0– 1.8 V)
(a)
(b)
NOTE A: The values of C1 and C2 should be provided by the resonator/crystal vendor.
Figure 4. Crystal/Clock Connection
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TMS470R1VF45AA
16/32-BIT RISC FLASH MICROCONTROLLER
SPNS086A – AUGUST 2003 – REVISED NOVEMBER 2004
ZPLL and clock specifications
timing requirements for ZPLL circuits enabled or disabled
MIN
MAX
UNIT
4
20
MHz
f(OSC)
Input clock frequency
tc(OSC)
Cycle time, OSCIN
50
ns
tw(OSCIL)
Pulse duration, OSCIN low
15
ns
tw(OSCIH)
Pulse duration, OSCIN high
15
ns
f(OSCRST)
OSC FAIL
frequency†
53
kHz
† Causes a device reset (specifically a clock reset) by setting the RST OSC FAIL bit (GLBCTRL.15) and the OSC FAIL flag bit (GLBSTAT.1). For
more detailed information on these bits and device resets, see the TMS470R1x System Module Reference Guide (literature number SPNU189).
switching characteristics over recommended operating conditions for clocks‡§
TEST CONDITIONS¶
PARAMETER
f(SYS)
System clock frequency#
f(CONFIG)
System clock frequency - Flash config mode
f(ICLK)
Interface clock frequency
f(ECLK)
External clock output frequency for ECP Module
tc(SYS)
Cycle time, system clock
tc(CONFIG)
Cycle time, system clock - Flash config mode
tc(ICLK)
tc(ECLK)
MAX
UNIT
Pipeline mode enabled
60
MHz
Pipeline mode disabled
24
MHz
24
MHz
25
MHz
Pipeline mode enabled
25
MHz
Pipeline mode disabled
24
MHz
Pipeline mode enabled
16.7
ns
Pipeline mode disabled
41.6
ns
41.6
ns
40
ns
Pipeline mode enabled
40
ns
Pipeline mode disabled
41.6
ns
Cycle time, interface clock
Cycle time, ECP module external clock output
MIN
‡ When PLLDIS = 0, f(SYS) = M × f(OSC) / R, where M = {4 or 8}, R = {1,2,3,4,5,6,7,8}. R is the system-clock divider determined by the CLKDIVPRE
[2:0] bits in the global control register (GLBCTRL.[2:0]) and M is the PLL multiplier determined by the MULT4 bit (GLBCTRL.3).
When PLLDIS = 1, f(SYS) = f(OSC) / R, where R = {1,2,3,4,5,6,7,8}.
f(ICLK) = f(SYS) / X, where X = {1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16}. X is the interface clock divider ratio determined by the PCR0.[4:1] bits
in the SYS module.
§ f(ECLK) = f(ICLK) / N, where N = {1 to 256}. N is the ECP prescale value defined by the ECPCTRL.[7:0] register bits in the ECP module.
¶ Pipeline mode enabled or disabled is determined by the ENPIPE bit (FMREGOPT.0).
# Flash Vread must be set to 5V to achieve maximum System Clock Frequency.
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ZPLL and clock specifications (continued)
switching characteristics over recommended operating conditions for external clocks
(see Figure 5 and Figure 6)†‡§
NO.
PARAMETER
TEST CONDITIONS
MIN
¶
SYSCLK or MCLK
1
tw(COL)
ICLK, X is even or 1#
Pulse duration, CLKOUT low
0.5tc(ICLK) – tf
ICLK, X is odd and not
1#
tw(COH)
Pulse duration, CLKOUT high ICLK, X is even or
0.5tc(ICLK) – tr
ICLK, X is odd and not 1
3
4
tw(EOH)
Pulse duration, ECLK low
Pulse duration, ECLK high
ns
0.5tc(SYS) – tr
1#
#
tw(EOL)
UNIT
0.5tc(ICLK) + 0.5tc(SYS) – tf
SYSCLK or MCLK¶
2
MAX
0.5tc(SYS) – tf
N is even and X is even or odd
0.5tc(ECLK) – tf
N is odd and X is even
0.5tc(ECLK) – tf
N is odd and X is odd and not 1
0.5tc(ECLK) + 0.5tc(SYS) – tf
N is even and X is even or odd
0.5tc(ECLK) – tr
0.5tc(ECLK) – tr
N is odd and X is even
N is odd and X is odd and not 1
ns
0.5tc(ICLK) – 0.5tc(SYS) – tr
ns
ns
0.5tc(ECLK) – 0.5tc(SYS) – tr
† X = {1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16}. X is the interface clock divider ratio determined by the PCR0.[4:1] bits in the SYS module.
‡ N = {1 to 256}. N is the ECP prescale value defined by the ECPCTRL.[7:0] register bits in the ECP module.
§ CLKOUT/ECLK pulse durations (low/high) are a function of the OSCIN pulse durations when PLLDIS is active.
¶ Clock source bits selected as either SYSCLK (CLKCNTL.[6:5] = 11 binary) or MCLK (CLKCNTL.[6:5] = 10 binary).
# Clock source bits selected as ICLK (CLKCNTL.[6:5] = 01 binary).
2
CLKOUT
1
Figure 5. CLKOUT Timing Diagram
4
ECLK
3
Figure 6. ECLK Timing Diagram
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SPNS086A – AUGUST 2003 – REVISED NOVEMBER 2004
RST and PORRST timings
timing requirements for PORRST† (see Figure 7)
MIN
NO.
MAX UNIT
VCCPORL
VCC low supply level when PORRST must be active during power up
VCCPORH
VCC high supply level when PORRST must remain active during power up and
become active during power down
VCCIOPORL
VCCIO low supply level when PORRST must be active during power up
VCCIOPORH
VCCIO high supply level when PORRST must remain active during power up and
become active during power down
VIL
Low-level input voltage after VCCIO > VCCIOPORH
VIL(PORRST)
Low-level input voltage of PORRST before VCCIO > VCCIOPORL
3
tsu(PORRST)r
Setup time, PORRST active before VCCIO > VCCIOPORL during power up
0
ms
5
tsu(VCCIO)r
Setup time, VCCIO > VCCIOPORL before VCC > VCCPORL
0
ms
6
th(PORRST)r
Hold time, PORRST active after VCC > VCCPORH
1
ms
7
tsu(PORRST)f
Setup time, PORRST active before VCC ≤ VCCPORH during power down
8
µs
8
th(PORRST)rio
Hold time, PORRST active after VCC > VCCIOPORH
1
ms
9
th(PORRST)d
Hold time, PORRST active after VCC < VCCPORL
0
ms
10
tsu(PORRST)fio
Setup time, PORRST active before VCC ≤ VCCIOPORH during power down
0
ns
11
tsu(VCCIO)f
Setup time, VCC < VCCPORE before VCCIO < VCCIOPORL
0
ns
0.6
1.5
V
V
1.1
V
2.75
V
0.2 VCCIO
V
0.5
V
† When the VCC timing requirements for PORRST are satisfied, there are no timing requirements for VCCP.
VCCP/VCCIO
VCCIOPORH
VCCIOPORH
VCCIO
8
VCC
VCC
VCCPORH
6
VCCIOPORL
VCC
VCCP/VCCIO
PORRST
11
VCCPORH
7
6
10
7
VCCPORL
VCCPORL
VCCIOPORL
5
3
9
VIL(PORRST)
VIL
VIL
VIL
VIL
VIL(PORRST)
Figure 7. PORRST Timing Diagram
switching characteristics over recommended operating conditions for RST‡
PARAMETER
tv(RST)
tfsu
MIN
4112tc(OSC)
Valid time, RST active after PORRST inactive
8tc(SYS)
Valid time, RST active (all others)
Flash start up time, from RST inactive to fetch of first instruction from Flash
(Flash pump stabilization time)
716tc(OSC)
MAX
UNIT
ns
ns
‡ Specified values do NOT include rise/fall times. For rise and fall timings, see the switching characteristics for output timings versus load
capacitance table.
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JTAG scan interface timing (JTAG clock specification 10-MHz and 50-pF load on TDO output)
MIN
NO.
MAX
UNIT
1
tc(JTAG)
Cycle time, JTAG low and high period
50
ns
2
tsu(TDI/TMS - TCKr)
Setup time, TDI, TMS before TCK rise (TCKr)
15
ns
3
th(TCKr -TDI/TMS)
Hold time, TDI, TMS after TCKr
15
ns
4
th(TCKf -TDO)
Hold time, TDO after TCKf
10
ns
5
td(TCKf -TDO)
Delay time, TDO valid after TCK fall (TCKf)
45
ns
TCK
1
1
TMS
TDI
2
3
TDO
4
5
Figure 8. JTAG Scan Timing
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TMS470R1VF45AA
16/32-BIT RISC FLASH MICROCONTROLLER
SPNS086A – AUGUST 2003 – REVISED NOVEMBER 2004
output timings
switching characteristics for output timings versus load capacitance (CL) (see Figure 9)
MIN
PARAMETER
tr
tf
tr
tf
tr
tf
Rise time, CLKOUT, AWD, TDO
Fall time, CLKOUT, AWD, TDO
Rise time, SPInCLK, SPInSOMI, SPInSIMO†
Fall time, RST, SPInCLK, SPInSOMI, SPInSIMO†
Rise time, all other output pins
Fall time, all other output pins
0.5
2.50
CL = 50 pF
1.5
5
CL = 100 pF
3
9
CL = 150 pF
4.5
12.5
CL = 15 pF
0.5
2.5
CL = 50 pF
1.5
5
CL = 100 pF
3
9
CL = 150 pF
4.5
12.5
CL = 15 pF
2.5
8
CL = 50 pF
5
14
CL = 100 pF
9
23
CL = 150 pF
13
32
CL = 15 pF
2.5
8
CL= 50 pF
5
14
CL = 100 pF
9
23
CL = 150 pF
13
32
CL = 15 pF
2.5
12
CL = 50 pF
6.0
28
CL = 100 pF
12
50
CL = 150 pF
18
73
CL = 15 pF
3
12
CL = 50 pF
8.5
28
CL = 100 pF
16
50
CL = 150 pF
23
73
†n = 1 – 3
tr
tf
80%
Output
20%
VCC
80%
20%
Figure 9. CMOS-Level Outputs
36
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0
ns
ns
ns
ns
ns
ns
TMS470R1VF45AA
16/32-BIT RISC FLASH MICROCONTROLLER
SPNS086A – AUGUST 2003 – REVISED NOVEMBER 2004
input timings
timing requirements for input timings† (see Figure 10)
MIN
tpw
tc(ICLK) + 10
Input minimum pulse width
MAX
UNIT
ns
† tc(ICLK) = interface clock cycle time = 1/f(ICLK)
tpw
Input
80%
20%
VCC
80%
20%
0
Figure 10. CMOS-Level Inputs Flash Timings
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SPNS086A – AUGUST 2003 – REVISED NOVEMBER 2004
Flash timings
timing requirements for program Flash‡
tprog(16-bit)
Half word (16-bit) programming time
MIN
TYP
MAX
UNIT
4
16
200
µs
4
15
s
time‡
tprog(Total)
512K-byte programming
terase(sector)
Sector erase time
twec
Write/erase cycles at TA = 125°C
tfp(RST)
2
15
s
100
cycles
Flash pump settling time from RST to SLEEP
143tc(SYS)
ns
tfp(SLEEP)
Initial Flash pump settling time from SLEEP to STANDBY
143tc(SYS)
ns
tfp(STDBY)
Initial Flash pump settling time from STANDBY to ACTIVE
72tc(SYS)
ns
† For more detailed information on the Flash core sectors, see the Flash program and erase section of this data sheet.
‡ The 512K-byte programming times include overhead of state machine.
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SPIn master mode timing parameters
SPIn master mode external timing parameters (CLOCK PHASE = 0, SPInCLK = output, SPInSIMO =
output, and SPInSOMI = input)†‡§ (see Figure 11)
NO.
1
2#
3#
MIN
6
7
MAX
UNIT
ns
tc(SPC)M
Cycle time, SPInCLK
100
256tc(ICLK)
tw(SPCH)M
Pulse duration, SPInCLK high (clock polarity = 0)
0.5tc(SPC)M – tr
0.5tc(SPC)M + 5
tw(SPCL)M
Pulse duration, SPInCLK low (clock polarity = 1)
0.5tc(SPC)M – tf
0.5tc(SPC)M + 5
tw(SPCL)M
Pulse duration, SPInCLK low (clock polarity = 0)
0.5tc(SPC)M – tf
0.5tc(SPC)M + 5
tw(SPCH)M
Pulse duration, SPInCLK high (clock polarity = 1)
0.5tc(SPC)M – tr
0.5tc(SPC)M + 5
td(SPCH-SIMO)M
Delay time, SPInCLK high to SPInSIMO valid
(clock polarity = 0)
10
td(SPCL-SIMO)M
Delay time, SPInCLK low to SPInSIMO valid
(clock polarity = 1)
10
tv(SPCL-SIMO)M
Valid time, SPInSIMO data valid after SPInCLK low
(clock polarity = 0)
tc(SPC)M – 5 – tf
tv(SPCH-SIMO)M
Valid time, SPInSIMO data valid after SPInCLK high
(clock polarity = 1)
tc(SPC)M – 5 – tr
tsu(SOMI-SPCL)M
Setup time, SPInSOMI before SPInCLK low
(clock polarity = 0)
6
tsu(SOMI-SPCH)M
Setup time, SPInSOMI before SPInCLK high
(clock polarity = 1)
6
tv(SPCL-SOMI)M
Valid time, SPInSOMI data valid after SPInCLK low
(clock polarity = 0)
4
tv(SPCH-SOMI)M
Valid time, SPInSOMI data valid after SPInCLK high
(clock polarity = 1)
4
4#
5
¶
#
#
#
ns
ns
ns
ns
ns
ns
† The MASTER bit (SPInCTRL2.3) is set and the CLOCK PHASE bit (SPInCTRL2.0) is cleared.
‡ tc(ICLK) = interface clock cycle time = 1/f(ICLK)
§ For rise and fall timings, see the "switching characteristics for output timings versus load capacitance" table.
¶ When the SPI is in Master mode, the following must be true:
For PS values from 1 to 255:
tc(SPC)M ≥ (PS +1)tc(ICLK) ≥ 100 ns, where PS is the prescale value set in the SPInCTL1.[12:5] register bits.
For PS values of 0:
tc(SPC)M = 2tc(ICLK) ≥ 100 ns.
# The active edge of the SPInCLK signal referenced is controlled by the CLOCK POLARITY bit (SPInCTRL2.1).
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SPIn master mode timing parameters (continued)
1
SPInCLK
(clock polarity = 0)
2
3
SPInCLK
(clock polarity = 1)
4
5
SPInSIMO
Master Out Data Is Valid
6
7
SPInSOMI
Master In Data
Must Be Valid
Figure 11. SPIn Master Mode External Timing (CLOCK PHASE = 0)
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SPIn master mode timing parameters (continued)
SPIn master mode external timing parameters (CLOCK PHASE = 1, SPInCLK = output, SPInSIMO =
output, and SPInSOMI = input)†‡§ (see Figure 12)
NO.
1
2#
3#
4
tc(SPC)M
Cycle time, SPInCLK
¶
MIN
MAX
UNIT
100
256tc(ICLK)
ns
tw(SPCH)M
Pulse duration, SPInCLK high (clock polarity = 0)
0.5tc(SPC)M – tr
0.5tc(SPC)M + 5
tw(SPCL)M
Pulse duration, SPInCLK low (clock polarity = 1)
0.5tc(SPC)M – tf
0.5tc(SPC)M + 5
tw(SPCL)M
Pulse duration, SPInCLK low (clock polarity = 0)
0.5tc(SPC)M – tf
0.5tc(SPC)M + 5
tw(SPCH)M
Pulse duration, SPInCLK high (clock polarity = 1)
0.5tc(SPC)M – tr
0.5tc(SPC)M + 5
tv(SIMO-SPCH)M
Valid time, SPInCLK high after SPInSIMO data valid
(clock polarity = 0)
0.5tc(SPC)M – 15
tv(SIMO-SPCL)M
Valid time, SPInCLK low after SPInSIMO data valid
(clock polarity = 1)
0.5tc(SPC)M – 15
tv(SPCH-SIMO)M
Valid time, SPInSIMO data valid after SPInCLK high
(clock polarity = 0)
0.5tc(SPC)M – 5 – tr
tv(SPCL-SIMO)M
Valid time, SPInSIMO data valid after SPInCLK low
(clock polarity = 1)
0.5tc(SPC)M – 5 – tf
tsu(SOMI-SPCH)M
Setup time, SPInSOMI before SPInCLK high
(clock polarity = 0)
6
tsu(SOMI-SPCL)M
Setup time, SPInSOMI before SPInCLK low
(clock polarity = 1)
6
tv(SPCH-SOMI)M
Valid time, SPInSOMI data valid after SPInCLK high
(clock polarity = 0)
4
tv(SPCL-SOMI)M
Valid time, SPInSOMI data valid after SPInCLK low
(clock polarity = 1)
4
#
5#
6#
7#
ns
ns
ns
ns
ns
ns
† The MASTER bit (SPInCTRL2.3) is set and the CLOCK PHASE bit (SPInCTRL2.0) is set.
‡ tc(ICLK) = interface clock cycle time = 1/f(ICLK)
§ For rise and fall timings, see the "switching characteristics for output timings versus load capacitance" table.
¶ When the SPI is in Master mode, the following must be true:
For PS values from 1 to 255:
tc(SPC)M ≥ (PS +1)tc(ICLK) ≥ 100 ns, where PS is the prescale value set in the SPInCTL1.[12:5] register bits.
For PS values of 0:
tc(SPC)M = 2tc(ICLK) ≥ 100 ns.
# The active edge of the SPInCLK signal referenced is controlled by the CLOCK POLARITY bit (SPInCTRL2.1).
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SPIn master mode timing parameters (continued)
1
SPInCLK
(clock polarity = 0)
2
3
SPInCLK
(clock polarity = 1)
4
5
SPInSIMO
Master Out Data Is Valid
Data Valid
6
7
SPInSOMI
Master In Data
Must Be Valid
Figure 12. SPIn Master Mode External Timing (CLOCK PHASE = 1)
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SPIn slave mode timing parameters
SPIn slave mode external timing parameters (CLOCK PHASE = 0, SPInCLK = input, SPInSIMO =
input, and SPInSOMI = output)†‡§¶ (see Figure 13)
NO.
1
4
5
MIN
MAX
UNIT
ns
tc(SPC)S
Cycle time, SPInCLK
100
256tc(ICLK)
tw(SPCH)S
Pulse duration, SPInCLK high
(clock polarity = 0)
0.5tc(SPC)S – 0.25tc(ICLK)
0.5tc(SPC)S + 0.25tc(ICLK)
tw(SPCL)S
Pulse duration, SPInCLK low
(clock polarity = 1)
0.5tc(SPC)S – 0.25tc(ICLK)
0.5tc(SPC)S + 0.25tc(ICLK)
tw(SPCL)S
Pulse duration, SPInCLK low
(clock polarity = 0)
0.5tc(SPC)S – 0.25tc(ICLK)
0.5tc(SPC)S + 0.25tc(ICLK)
tw(SPCH)S
Pulse duration, SPInCLK high
(clock polarity = 1)
0.5tc(SPC)S – 0.25tc(ICLK)
0.5tc(SPC)S + 0.25tc(ICLK)
td(SPCH-SOMI)S
Delay time, SPInCLK high to SPInSOMI valid
(clock polarity = 0)
6 + tr
td(SPCL-SOMI)S
Delay time, SPInCLK low to SPInSOMI valid
(clock polarity = 1)
6 + tf
tv(SPCH-SOMI)S
Valid time, SPInSOMI data valid after
SPInCLK high (clock polarity =0)
tc(SPC)S – 6 – tr
tv(SPCL-SOMI)S
Valid time, SPInSOMI data valid after
SPInCLK low (clock polarity =1)
tc(SPC)S – 6 – tf
tsu(SIMO-SPCL)S
Setup time, SPInSIMO before SPInCLK low
(clock polarity = 0)
6
tsu(SIMO-SPCH)S
Setup time, SPInSIMO before SPInCLK high
(clock polarity = 1)
6
tv(SPCL-SIMO)S
Valid time, SPInSIMO data valid after
SPInCLK low (clock polarity = 0)
6
tv(SPCH-SIMO)S
Valid time, SPInSIMO data valid after
SPInCLK high (clock polarity = 1)
6
2||
3
#
||
||
||
6||
7||
ns
ns
ns
ns
ns
ns
† The MASTER bit (SPInCTRL2.3) is cleared and the CLOCK PHASE bit (SPInCTRL2.0) is cleared.
‡ If the SPI is in slave mode, the following must be true: tc(SPC)S ≥ (PS + 1) tc(ICLK), where PS = prescale value set in SPInCTL1.[12:5].
§ For rise and fall timings, see the "switching characteristics for output timings versus load capacitance" table.
¶ tc(ICLK) = interface clock cycle time = 1/f(ICLK)
# When the SPIn is in Slave mode, the following must be true:
For PS values from 1 to 255:
tc(SPC)S ≥ (PS +1)tc(ICLK) ≥ 100 ns, where PS is the prescale value set in the SPInCTL1.[12:5] register bits.
For PS values of 0:
tc(SPC)S = 2tc(ICLK) ≥ 100 ns.
||
The active edge of the SPInCLK signal referenced is controlled by the CLOCK POLARITY bit (SPInCTRL2.1).
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SPIn slave mode timing parameters (continued)
1
SPInCLK
(clock polarity = 0)
2
3
SPInCLK
(clock polarity = 1)
4
5
SPInSOMI
SPISOMI Data Is Valid
6
7
SPInSIMO
SPISIMO Data
Must Be Valid
Figure 13. SPIn Slave Mode External Timing (CLOCK PHASE = 0)
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SPIn slave mode timing parameters (continued)
SPIn slave mode external timing parameters (CLOCK PHASE = 1, SPInCLK = input, SPInSIMO =
input, and SPInSOMI = output)†‡§¶ (see Figure 14)
NO.
1
2
MIN
MAX
UNIT
100
256tc(ICLK)
ns
Pulse duration, SPInCLK high
(clock polarity = 0)
0.5tc(SPC)S –0.25tc(ICLK)
0.5tc(SPC)S + 0.25tc(ICLK)
tw(SPCL)S
Pulse duration, SPInCLK low
(clock polarity = 1)
0.5tc(SPC)S –0.25tc(ICLK)
0.5tc(SPC)S + 0.25tc(ICLK)
tw(SPCL)S
Pulse duration, SPInCLK low
(clock polarity = 0)
0.5tc(SPC)S –0.25tc(ICLK)
0.5tc(SPC)S + 0.25tc(ICLK)
tw(SPCH)S
Pulse duration, SPInCLK high
(clock polarity = 1)
0.5tc(SPC)S –0.25tc(ICLK)
0.5tc(SPC)S + 0.25tc(ICLK)
tv(SOMI-SPCH)S
Valid time, SPInSOMI data valid before
SPInCLK high (clock polarity = 0)
0.5tc(SPC)S – 6 – tr
tv(SOMI-SPCL)S
Valid time, SPInSOMI data valid before
SPInCLK low (clock polarity = 1)
0.5tc(SPC)S – 6 – tf
tv(SPCH-SOMI)S
Valid time, SPInSOMI data valid after
SPInCLK high (clock polarity =0)
0.5tc(SPC)S – 6 – tr
tv(SPCL-SOMI)S
Valid time, SPInSOMI data valid after
SPInCLK low (clock polarity =1)
0.5tc(SPC)S – 6 – tf
tsu(SIMO-SPCH)S
Setup time, SPInSIMO before SPInCLK
high (clock polarity = 0)
6
tsu(SIMO-SPCL)S
Setup time, SPInSIMO before SPInCLK
low (clock polarity = 1)
6
tv(SPCH-SIMO)S
Valid time, SPInSIMO data valid after
SPInCLK high (clock polarity = 0)
6
tv(SPCL-SIMO)S
Valid time, SPInSIMO data valid after
SPInCLK low (clock polarity = 1)
6
tc(SPC)S
Cycle time, SPInCLK
tw(SPCH)S
||
3||
4||
5||
6||
7||
#
ns
ns
ns
ns
ns
ns
† The MASTER bit (SPInCTRL2.3) is cleared and the CLOCK PHASE bit (SPInCTRL2.0) is set.
‡ If the SPI is in slave mode, the following must be true: tc(SPC)S ≥ (PS + 1) tc(ICLK), where PS = prescale value set in SPInCTL1.[12:5].
§ For rise and fall timings, see the "switching characteristics for output timings versus load capacitance" table.
¶ tc(ICLK) = interface clock cycle time = 1/f(ICLK)
# When the SPIn is in Slave mode, the following must be true:
For PS values from 1 to 255:
tc(SPC)S ≥ (PS +1)tc(ICLK) ≥ 100 ns, where PS is the prescale value set in the SPInCTL1.[12:5] register bits.
For PS values of 0:
tc(SPC)S = 2tc(ICLK) ≥ 100 ns.
||
The active edge of the SPInCLK signal referenced is controlled by the CLOCK POLARITY bit (SPInCTRL2.1).
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TMS470R1VF45AA
16/32-BIT RISC FLASH MICROCONTROLLER
SPNS086A – AUGUST 2003 – REVISED NOVEMBER 2004
SPIn slave mode timing parameters (continued)
1
SPInCLK
(clock polarity = 0)
2
3
SPInCLK
(clock polarity = 1)
4
5
SPInSOMI
SPISOMI Data Is Valid
Data Valid
6
7
SPInSIMO
SPISIMO Data Must
Be Valid
Figure 14. SPIn Slave Mode External Timing (CLOCK PHASE = 1)
46
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TMS470R1VF45AA
16/32-BIT RISC FLASH MICROCONTROLLER
SPNS086A – AUGUST 2003 – REVISED NOVEMBER 2004
SCIn isosynchronous mode timings — internal clock
timing requirements for internal clock SCIn isosynchronous mode†‡§ (see Figure 15)
(BAUD + 1)
IS EVEN OR BAUD = 0
NO.
(BAUD + 1)
IS ODD AND BAUD ≠ 0
UNIT
MIN
MAX
MIN
MAX
2tc(ICLK)
224tc(ICLK)
3tc(ICLK)
(224 –1) tc(ICLK)
1
tc(SCC)
Cycle time, SCInCLK
2
tw(SCCL)
Pulse duration,
SCInCLK low
0.5tc(SCC) – tf
0.5tc(SCC) + 5
0.5tc(SCC) +0.5tc(ICLK) – tf 0.5tc(SCC) +0.5tc(ICLK)
ns
3
tw(SCCH)
Pulse duration,
SCInCLK high
0.5tc(SCC) – tr
0.5tc(SCC) + 5
0.5tc(SCC) –0.5tc(ICLK) – tr 0.5tc(SCC) –0.5tc(ICLK)
ns
4
td(SCCH-TXV)
Delay time, SCInCLK
high to SCInTX valid
5
tv(TX)
Valid time, SCInTX data
after SCInCLK low
6
tsu(RX-SCCL)
Setup time, SCInRX
before SCInCLK low
7
tv(SCCL-RX)
Valid time, SCInRX data
- tc(ICLK) + tf + 20
after SCInCLK low
10
10
ns
ns
tc(SCC) – 10
tc(SCC) – 10
ns
tc(ICLK) + tf + 20
tc(ICLK) + tf + 20
ns
- tc(ICLK) + tf + 20
ns
† BAUD = 24-bit concatenated value formed by the SCI[H,M,L]BAUD registers.
‡ tc(ICLK) = interface clock cycle time = 1/f(ICLK)
§ For rise and fall timings, see the "switching characteristics for output timings versus load capacitance" table.
1
3
2
SCICLK
5
4
SCITX
Data Valid
6
7
SCIRX
Data Valid
NOTE A: Data transmission/reception characteristics for isosynchronous mode with internal clocking are similar to the asynchronous
mode. Data transmission occurs on the SCICLK rising edge, and data reception on the SCICLK falling edge.
Figure 15. SCIn Isosynchronous Mode Timing Diagram for Internal Clock
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TMS470R1VF45AA
16/32-BIT RISC FLASH MICROCONTROLLER
SPNS086A – AUGUST 2003 – REVISED NOVEMBER 2004
SCIn isosynchronous mode timings — external clock
timing requirements for external clock SCIn isosynchronous mode†‡ (see Figure 16)
NO.
MIN
§
MAX
8tc(ICLK)
tc(SCC)
Cycle time, SCInCLK
2
tw(SCCH)
Pulse duration, SCInCLK high
0.5tc(SCC) – 0.25tc(ICLK)
0.5tc(SCC) + 0.25tc(ICLK)
ns
3
tw(SCCL)
Pulse duration, SCInCLK low
0.5tc(SCC) – 0.25tc(ICLK)
0.5tc(SCC) + 0.25tc(ICLK)
ns
4
td(SCCH-TXV)
Delay time, SCInCLK high to SCInTX valid
2tc(ICLK) + 12 + tr
ns
5
tv(TX)
Valid time, SCInTX data after SCInCLK low
6
tsu(RX-SCCL)
Setup time, SCInRX before SCInCLK low
7
tv(SCCL-RX)
Valid time, SCInRX data after SCInCLK low
ns
2tc(SCC)–10
ns
0
ns
2tc(ICLK) + 10
ns
† tc(ICLK) = interface clock cycle time = 1/f(ICLK)
‡ For rise and fall timings, see the "switching characteristics for output timings versus load capacitance" table.
§ When driving an external SCInCLK, the following must be true: tc(SCC) ≥ 8tc(ICLK)
1
2
3
SCICLK
5
4
SCITX
Data Valid
6
7
SCIRX
Data Valid
NOTE A: Data transmission/reception characteristics for isosynchronous mode with external clocking are similar to the asynchronous
mode. Data transmission occurs on the SCICLK rising edge, and data reception on the SCICLK falling edge.
Figure 16. SCIn Isosynchronous Mode Timing Diagram for External Clock
48
UNIT
1
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TMS470R1VF45AA
16/32-BIT RISC FLASH MICROCONTROLLER
SPNS086A – AUGUST 2003 – REVISED NOVEMBER 2004
high-end timer (HET) timings
minimum PWM output pulse width:
This is equal to one High Resolution Clock Period (HRP). The HRP is defined by the 6-bit High Resolution
Prescale Factor (hr) which is user defined, giving prescale factors of 1 to 64, with a linear increment of codes.
Therefore, the minimum PWM output pulse width = HRP(min) = hr(min)/SYSCLK = 1/SYSCLK
For example, for a SYSCLK of 30 MHz, the minimum PWM output pulse width = 1/30 = 33.33ns
minimum input pulses we can capture:
The input pulse width must be greater or equal to the Low Resolution Clock Period (LRP), i.e., the HET loop
(the HET program must fit within the LRP). The LRP is defined by the 3-bit Loop-Resolution Prescale Factor
(lr), which is user defined, with a power of 2 increment of codes. That is, the value of lr can be 1, 2, 4, 8, 16, or 32.
Therefore, the minimum input pulse width = LRP(min) = hr(min) * lr(min)/SYSCLK = 1 * 1/SYSCLK
For example, with a SYSCLK of 30 MHz, the minimum input pulse width = 1 * 1/30 = 33.33 ns
Note: Once the input pulse width is greater than LRP, the resolution of the measurement is still HRP. (That is,
the captured value gives the number of HRP clocks inside the pulse.)
Abbreviations:
High resolution clock period = HRP = hr/SYSCLK
Loop resolution clock period = LRP = hr*lr/SYSCLK
hr = HET high resolution divide rate = 1, 2, 3,...63, 64
lr = HET low resolution divide rate = 1, 2, 4, 8, 16, 32
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TMS470R1VF45AA
16/32-BIT RISC FLASH MICROCONTROLLER
SPNS086A – AUGUST 2003 – REVISED NOVEMBER 2004
high-end CAN controller (HECCn) mode timings
dynamic characteristics for the CANnHTX and CANnHRX pins
MIN
PARAMETER
td(CANnHTX)
Delay time, transmit shift register to CANnHTX pin†
td(CANnHRX)
Delay time, CANnHRX pin to receive shift register
† These values do not include rise/fall times of the output buffer.
50
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MAX
UNIT
15
ns
5
ns
TMS470R1VF45AA
16/32-BIT RISC FLASH MICROCONTROLLER
SPNS086A – AUGUST 2003 – REVISED NOVEMBER 2004
multi-buffered A-to-D converter (MibADC)
The multi-buffered A-to-D converter (MibADC) has a separate power bus for its analog circuitry that enhances
the A-to-D performance by preventing digital switching noise on the logic circuitry which could be present on
VSS and VCC from coupling into the A-to-D analog stage. All A-to-D specifications are given with respect to
ADREFLO unless otherwise noted.
Resolution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 bits (1024 values)
Monotonic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Assured
Output conversion code . . . . . . . . . . . . . . . . . . . . . . . 00h to 3FFh [00 for VAI ≤ADREFLO; 3FF for VAI ≥ ADREFHI]
MibADC recommended operating conditions†
ADREFHI
A-to-D high-voltage reference source
ADREFLO
A-to-D low-voltage reference source
VAI
Analog input voltage
MAX
UNIT
VCCAD
V
VSSAD
VCCAD
V
VSSAD − 0.3
VCCAD + 0.3
V
−2
2
mA
‡
IAIC
MIN
VSSAD
Analog input clamp current
(VAI < VSSAD – 0.3 or VAI > VCCAD + 0.3)
† For VCCAD and VSSAD recommended operating conditions, see the "device recommended operating conditions" table.
‡ Input currents into any ADC input channel outside the specified limits could affect conversion results of other channels.
operating characteristics over full ranges of recommended operating conditions§¶
PARAMETER
TYP
MAX
UNIT
250
500
Ω
Conversion
10
pF
Sampling
30
pF
1
µA
5
mA
DESCRIPTION/CONDITIONS
Ri
Analog input resistance
See Figure 17
Ci
Analog input capacitance
See Figure 17
IAIL
Analog input leakage current
See Figure 17
IADREFHI
ADREFHI input current
ADREFHI = 3.6 V, ADREFLO = VSSAD
CR
Conversion range over which specified
accuracy is maintained
ADREFHI − ADREFLO
EDNL
Differential nonlinearity error
Difference between the actual step width and the
ideal value after offset correction. (See Figure 18)
EINL
ETOT
MIN
–1
3
3.6
V
±1.5
LSB
Integral nonlinearity error
Maximum deviation from the best straight line through
the MibADC. MibADC transfer characteristics,
excluding the quantization error after offset
correction.
(See Figure 19)
±2
LSB
Total error/Absolute accuracy
Maximum value of the difference between an analog
value and the ideal midstep value.
(See Figure 20)
±2
LSB
§ VCCIO = VCCAD = ADREFHI
¶ 1 LSB = (ADREFHI – ADREFLO)/210 for the MibADC
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TMS470R1VF45AA
16/32-BIT RISC FLASH MICROCONTROLLER
SPNS086A – AUGUST 2003 – REVISED NOVEMBER 2004
multi-buffered A-to-D converter (MibADC) (continued)
External
Rs
MibADC
Input Pin
Ri
Sample Switch
Parasitic
Capacitance
Vsrc
Sample
Capacitor
Rleak
Ci
Figure 17. MibADC Input Equivalent Circuit
Multi-Buffer ADC timing requirements
MIN
1
µs
Delay time, conversion time
0.55
µs
Delay time, total sample/hold and conversion time
1.55
µs
td(SH)
Delay time, sample and hold time
td(SHC)
†
UNIT
µs
Cycle time, MibADC clock
td(C)
MAX
0.05
tc(ADCLK)
† This is the minimum sample/hold and conversion time that can be achieved. These parameters are dependent on many factors for more detail,
see the TMS470R1x Multi-Buffered Analog-to-Digital Converter (MibADC) Reference Guide (literature number SPNU206).
52
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multi-buffered A-to-D converter (MibADC) (continued)
The differential nonlinearity error shown in Figure 18 (sometimes referred to as differential linearity) is the
difference between an actual step width and the ideal value of 1 LSB.
0 ... 110
Digital Output Code
0 ... 101
0 ... 100
0 ... 011
Differential
Linearity Error (1/2 LSB)
1 LSB
0 ... 010
0 ... 001
1 LSB
Differential Linearity
Error (–1/2 LSB)
0 ... 000
0
1
2
3
4
Analog Input Value (LSB)
5
NOTE A: 1 LSB = (ADREFHI – ADREFLO)/210
Figure 18. Differential Nonlinearity (DNL)
The integral nonlinearity error shown in Figure 19 (sometimes referred to as linearity error) is the deviation of
the values on the actual transfer function from a straight line.
0 ... 111
Digital Output Code
0 ... 110
Ideal
Transition
0 ... 101
Actual
Transition
0 ... 100
At Transition
011/100
(– 1/2 LSB)
0 ... 011
0 ... 010
End-Point Lin. Error
0 ... 001
At Transition
001/010 (– 1/4 LSB)
0 ... 000
0
1
2
3
4
5
6
Analog Input Value (LSB)
NOTE A: 1 LSB = (ADREFHI – ADREFLO)/210
7
Figure 19. Integral Nonlinearity (INL) Error
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TMS470R1VF45AA
16/32-BIT RISC FLASH MICROCONTROLLER
SPNS086A – AUGUST 2003 – REVISED NOVEMBER 2004
multi-buffer A-to-D converter (MibADC) (continued)
The absolute accuracy or total error of an MibADC as shown in Figure 20 is the maximum value of the difference
between an analog value and the ideal midstep value.
0 ... 111
Digital Output Code
0 ... 110
0 ... 101
0 ... 100
Total Error
At Step 0 ... 101
(–1 1/4 LSB)
0 ... 011
0 ... 010
Total Error
At Step
0 ... 001 (1/2 LSB)
0 ... 001
0 ... 000
0
1
2
3
4
5
6
Analog Input Value (LSB)
NOTE A: 1 LSB = (ADREFHI – ADREFLO)/210
7
Figure 20. Absolute Accuracy (Total) Error
54
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TMS470R1VF45AA
16/32-BIT RISC FLASH MICROCONTROLLER
SPNS086A – AUGUST 2003 – REVISED NOVEMBER 2004
MECHANICAL DATA
PGE (S-PQFP-G144)
PLASTIC QUAD FLATPACK
108
73
109
72
0,27
0,17
0,08 M
0,50
144
0,13 NOM
37
1
36
Gage Plane
17,50 TYP
20,20 SQ
19,80
22,20
SQ
21,80
0,25
0,05 MIN
0°-7°
0,75
0,45
1,45
1,35
Seating Plane
0,08
1,60 MAX
4040147/C 10/96
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Falls within JEDEC MS-026
Thermal Resistance Characteristics
PARAMETER
°C/W
RΘJA
43
RΘJC
6.5
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TMS470R1VF45AA
16/32-BIT RISC FLASH MICROCONTROLLER
SPNS086A – AUGUST 2003 – REVISED NOVEMBER 2004
List of Figures
TMS470R1VF45AA 144-Pin PGE Package (TOP VIEW)
Functional Block Diagram
Figure 1. Memory Map
Figure 2. TMS470R1x Family Nomenclature
Figure 3. Test Load Circuit
Figure 4. Crystal/Clock Connection
Figure 5. CLKOUT Timing Diagram
Figure 6. ECLK Timing Diagram
Figure 7. PORRST Timing Diagram
Figure 8. JTAG Scan Timing
Figure 9. CMOS-Level Outputs
Figure 10. CMOS-Level Inputs Flash Timings
Figure 11. SPIn Master Mode External Timing (CLOCK PHASE = 0)
Figure 12. SPIn Master Mode External Timing (CLOCK PHASE = 1)
Figure 13. SPIn Slave Mode External Timing (CLOCK PHASE = 0)
Figure 14. SPIn Slave Mode External Timing (CLOCK PHASE = 1)
Figure 15. SCIn Isosynchronous Mode Timing Diagram for Internal Clock
Figure 16. SCIn Isosynchronous Mode Timing Diagram for External Clock
Figure 17. MibADC Input Equivalent Circuit
Figure 18. Differential Nonlinearity (DNL)
Figure 19. Integral Nonlinearity (INL) Error
Figure 20. Absolute Accuracy (Total) Error
Mechanical Data
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SPNS086A – AUGUST 2003 – REVISED NOVMEBER 2004
List of Tables
Table 1.
Table 2.
Table 3.
Table 4.
Table 5.
Table 6.
Table 7.
Table 8.
Table 9.
Device Characteristics
Memory Selection Assignment
VF45AA Flash Memory Banks and Sectors
VF45AA Peripherals, System Module, and Flash Base Addresses
DMA Request Lines Connections
Interrupt Priority (IEM and CIM)
MibADC Event Hookup Configuration
TMS470 Device ID Bit Allocation Register
Device Part Numbers†
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TMS470R1VF45AA
16/32-BIT RISC FLASH MICROCONTROLLER
REVISION HISTORY
REVISION HISTORY
REV
A
DATE
11/04
NOTES
Updates:
Page 1, "JTAG Boundary-Scan Logic" changed to "JTAG Test-Access Port"
Page 1, footnote changed to clarify that boundary scan architecture is not supported on this device
Page 13, flash protection keys identified as being in the last four words of the first 16K sector
Page 22, documentation support section added
Page 25, device part numbers for TMS470R1VF45AC and TMS470R1VF45AE added to table
Page 26, footnote modified to indicate that VCCAD voltage is with respect to VSSAD
Page 27, separate VIL and VIH values added for OSCIN
Page 28, operating ICC at 60MHz changed from 115 mA to 125 mA
Page 33, test condition where N is odd and X is even added to parameters #3 and #4
Page 34, tfsu added to the switching characteristics over recommended operating conditions for RST
Page 38, tfp(RST), tfp(SLEEP), and tfp(STDBY) added to the timing requirements for program Flash
Page 39 - 41, SPI timing parameters #6 and #7 (minimum values) updated
Page 43, SPI timing parameters #4 (maximum value) and #5-7 (minimum value) updated
Page 45, SPI timing parameters #5-7 (minimum value) updated
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