TI TMS470R1VF48CPGEA

TMS470R1VF48C/VF48B
16/32-BIT RISC FLASH MICROCONTROLLERS
SPNS093D – MAY 2004 – REVISED FEBRUARY 2006
O
O
O
O
Integrated Memory (VF48C only)
– 1M-Byte Program Flash
–Two Banks With 16 Contiguous Sectors
– 64K-Byte Static RAM (SRAM)
– Memory Security Module (MSM)
– JTAG Security Module
Integrated Memory (VF48B only)
– 768K-Byte Program Flash
– Two Banks With 12 Contiguous Sectors
– 48K-Byte Static RAM (SRAM)
– Memory Security Module (MSM)
– JTAG Security Module
O
Operating Features
– Low-Power Modes: STANDBY and HALT
– Industrial/Automotive Temperature Ranges
O
470+ System Module
– 32-Bit Address Space Decoding
– Bus Supervision for Memory/Peripherals
– Digital Watchdog (DWD) Timer
– Analog Watchdog (AWD) Timer
– Enhanced Real-Time Interrupt (RTI)
– Interrupt Expansion Module (IEM)
– System Integrity and Failure Detection
– ICE Breaker
O
Direct Memory Access (DMA) Controller
– 32 Control Packets and 16 Channels
O
Frequency-Modulated Zero-Pin Phase-Locked
Loop (FMZPLL)-Based Clock Module With
Prescaler
– Multiply-by-8 Internal FMZPLL Option
– ZPLL Bypass Mode
Twelve Communication Interfaces:
– Two Serial Peripheral Interfaces (SPIs)
– 255 Programmable Baud Rates
– Three Serial Communication Interfaces
(SCIs)
– 224 Selectable Baud Rates
– Asynchronous/Isosynchronous Modes
O
– Two High-End CAN Controllers (HECC)
– 32-Mailbox Capacity
– Fully Compliant With CAN Protocol,
Version 2.0B
– Five Inter-Integrated Circuit (I2C) Modules
– Multi-Master and Slave Interfaces
– Up to 400 Kbps (Fast Mode)
– 7- and 10-Bit Address Capability
High-Performance Static CMOS Technology
TMS470R1x 16/32-Bit RISC Core (ARM7TDMI™)
– 60-MHz System Clock (Pipeline Mode)
– Independent 16/32-Bit Instruction Set
– Open Architecture With Third-Party Support
– Built-In Debug Module
O
High-End Timer Lite (HET)
– 12 Programmable I/O Channels:
– 12 High-Resolution Pins
– High-Resolution Share Feature (XOR)
– High-End Timer RAM
– 64-Instruction Capacity
O
External Clock Prescale (ECP) Module
– Programmable Low-Frequency External
Clock (CLK)
O
12-Channel 10-Bit Multi-Buffered ADC
(MibADC)
– 64-Word FIFO Buffer
– Single- or Continuous-Conversion Modes
– 1.55 μs Minimum Sample and Conversion
Time
– Calibration Mode and Self-Test Features
O
Flexible Interrupt Handling
Expansion Bus Module (EBM)
– Supports 8- and 16-Bit Expansion Bus
Memory Interface Mappings
– 42 I/O Expansion Bus Pins
O
O
46 Dedicated General-Purpose I/O (GIO) Pins
and 47 Additional Peripheral I/Os
O
Sixteen External Interrupts
O
Compatible ROM Device (Planned)
On-Chip Scan-Base Emulation Logic,
IEEE Standard 1149.1(1) (JTAG) Test-Access
Port
O
O
144-Pin Plastic Low-Profile Quad Flatpack
(PGE Suffix)
O
Development System Support Tools Available
– Code Composer Studio™ Integrated Development Environment (IDE)
– HET Assembler and Simulator
– Real-Time In-Circuit Emulation
– Flash Programming
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
TexasInstruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Code Composer Studio is a trademark of Texas Instruments.
ARM7TDMI is a trademark of Advanced RISC Machines Limited (ARM).
All trademarks are the property of their respective owners.
1 The test-access port is compatible with the IEEE Standard 1149.1-1990, IEEE Standard Test-Access Port and Boundary Scan Architecture
specification. Boundary scan is not supported on this device.
Copyright © 2006, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication
date. Products conform to specifications per the Texas
Instruments standard warranty. Production processing does
not necessarily include testing of all parameters.
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251-1443
1
TMS470R1VF48C/VF48B
16/32-BIT RISC FLASH MICROCONTROLLERS
SPNS093D – MAY 2004 – REVISED FEBRUARY 2006
74
73
75
78
77
76
82
81
80
79
85
84
83
86
94
93
92
91
90
89
88
87
95
97
96
99
98
100
102
101
72
109
110
71
70
69
68
67
66
65
64
63
62
61
60
59
58
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
57
56
55
54
53
52
51
50
131
49
48
47
46
45
44
43
42
41
40
39
38
37
132
133
134
135
136
137
138
139
140
141
142
36
34
35
32
33
30
31
24
25
26
27
28
29
22
23
21
18
19
20
16
17
SPI1SCS
SPI1ENA
GIOG[4]
SPI1CLK
SPI1SIMO
GIOG[3]
SPI1SOMI
GIOG[2]
HET[6]
GIOG[1]
HET[7]
HET[8]
VCC
VSS
HET[18]
TMS2
TMS
HET[20]
HET[22]
GIOG[0]
SCI3TX
SCI3RX
GIOD[5]
SCI3CLK
VCCIO
VSSIO
GIOD[4]
I2C3SCL
I2C3SDA
GIOD[3]
VCC
OSCOUT
OSCIN
VSS
GIOD[2]
AWD
2
3
4
5
6
7
8
9
10
11
12
13
14
15
143
144
1
ADREFHI
ADREFLO
VCCAD
VSSAD
ADIN[4]
ADIN[3]
ADIN[2]
ADIN[1]
ADIN[0]
PORRST
GIOC[4]
GIOC[3]
RST
VSS
VCC
TEST
GIOH[5]
GIOC[2]
GIOA[4]/INT[4]
GIOC[1]
VSS
VCC
VCCP
FLTP2
GIOA[3]/INT[3]
GIOA[2]/INT[2]
GIOC[0]
GIOA[1]/INT[1]/ECLK
VCCIO
VSSIO
GIOH[0]
GIOG[7]
GIOA[0]/INT[0]
GIOG[6]
GIOG[5]
TRST
106
105
104
103
108
107
ADIN[5]
ADIN[6]
ADIN[7]
ADIN[8]
ADIN[9]
ADIN[10]
ADIN[11]
ADEVT
GIOF[7]/INT[15]
GIOF[6]/INT[14]
GIOA[5]/INT[5]
PLLDIS
GIOF[5]/INT[13]
I2C2SCL
I2C2SDA
GIOF[4]/INT[12]
VCC
VSS
GIOF[3]/INT[11]
GIOF[2]/INT[10]
I2C1SCL
I2C1SDA
VCCIO
VSSIO
CAN1HTX
CAN1HRX
GIOF[1]/INT[9]
CLKOUT
GIOF[0]/INT[8]
GIOA[7]/INT[7]
GIOA[6]/INT[6]
GIOE[7]
TCK
TDO
TDI
HET[0]
TMS470R1VF48C/TMS470R1VF48B 144-PIN PGE PACKAGE (TOP VIEW)
2
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251-1443
HET[1]
HET[2]
GIOE[6]
VCCIO
VSSIO
GIOE[5]
HET[3]
HET[4]
GIOE[4]
HET[5]
SPI2SCS
GIOE[3]
SPI2ENA
SPI2SIMO
GIOE[2]
SPI2SOMI
SPI2CLK
CAN2HTX
CAN2HRX
VCC
VSS
SCI2CLK
SCI2RX
SCI2TX
SCI1CLK
GIOE[1]
SCI1RX
SCI1TX
GIOE[0]
GIOB[0]
GIOD[0]
I2C4SDA
I2C4SCL
GIOD[1]
I2C5SDA
I2C5SCL
TMS470R1VF48C/VF48B
16/32-BIT RISC FLASH MICROCONTROLLERS
SPNS093D – MAY 2004 – REVISED FEBRUARY 2006
description
The VF48x(2) devices are members of the Texas Instruments TMS470R1x family of general-purpose 16/32-bit
reduced instruction set computer (RISCllers. The VF48x microcontroller offers high performance utilizing the
high-speed ARM7TDMI 16/32-bit RISC central processing unit (CPU), resulting in a high instruction throughput
while maintaining greater code efficiency. The ARM7TDMI 16/32-bit RISC CPU views memory as a linear
collection of bytes numbered upwards from zero. The VF48x uses the big-endian format where the most
significant byte of a word is stored at the lowest numbered byte and the least significant byte at the highest
numbered byte.
High-end embedded control applications demand more performance from their controllers while maintaining
low costs. The VF48x RISC core architecture offers solutions to these performance and cost demands while
maintaining low power consumption.
The VF48x devices contain the following:
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
ARM7TDMI 16/32-Bit RISC CPU
TMS470R1x system module (SYS) with 470+ enhancements
1M-byte flash (VF48C only)
768K-byte flash (VF48B only)
64K-byte SRAM (VF48C only)
48K-byte SRAM (VF48B only)
Frequency-modulated zero-pin phase-locked loop (FMZPLL) clock module
Digital watchdog (DWD) timer
Analog watchdog (AWD) timer
Enhanced real-time interrupt (RTI) module
Interrupt expansion module (IEM)
Memory security module (MSM)
JTAG security module
Two serial peripheral interface (SPI) modules
Three serial communications interface (SCI) modules
Two high-end CAN controllers (HECC)
Five inter-integrated circuit (I2C) modules
10-bit multi-buffered analog-to-digital converter (MibADC), with 12 input channels
High-end timer lite (HET) controlling 12 I/Os
External Clock Prescale (ECP)
Expansion Bus Module (EBM)
Up to 93 I/O pins
The functions performed by the 470+ system module (SYS) include:
Address decoding
O
Memory protection
O
Memory and peripherals bus supervision
O
Reset and abort exception management
O
Prioritization for all internal interrupt sources
O
Device clock control
O
Parallel signature analysis (PSA)
O
The enhanced real-time interrupt (RTI) module on the VF48x has the option to be driven by the oscillator clock.
The digital watchdog (DWD) is a 25-bit resettable decrementing counter that provides a system reset when the
watchdog counter expires. This data sheet includes device-specific information such as memory and peripheral
select assignment, interrupt priority, and a device memory map. For a more detailed functional description of
the SYS module, see the TMS470R1x System Module Reference Guide (literature number SPNU189).
2 Throughout the remainder of this document, the TMS470R1VF48C and TMS740R1VF48B device names, where generic, will be referred to
as either VF48C/VF48B or VF48x; and where unique, by either the full device name or VF48C or VF48B.
POST OFFICE BOX 1443
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3
TMS470R1VF48C/VF48B
16/32-BIT RISC FLASH MICROCONTROLLERS
SPNS093D – MAY 2004 – REVISED FEBRUARY 2006
description (continued)
The VF48x memory includes general-purpose SRAM supporting single-cycle read/write accesses in byte,
half-word, and word modes.
The flash memory on this device is a nonvolatile, electrically erasable and programmable memory implemented
with a 32-bit-wide data bus interface. The flash operates with a system clock frequency of up to 24 MHz. When
in pipeline mode, the flash operates with a system clock frequency of up to 60 MHz. For more detailed information
on the flash, see the flash section of this data sheet and the TMS470R1x F05 Flash Reference Guide (literature
number SPNU213).
The memory security module (MSM) and the JTAG security module prevent unauthorized access and visibility
to on-chip memory, thereby preventing reverse engineering or manipulation of proprietary code. For more
detailed information, see the TMS470R1x Memory Security Module Reference Guide (literature number
SPNU246) and the TMS470R1x JTAG Security Module Reference Guide (literature number SPNU245).
The VF48x device has twelve communication interfaces: two SPIs, three SCIs, two HECCs, and five I2Cs. The
SPI provides a convenient method of serial interaction for high-speed communications between similar shiftregister type devices. The SCI is a full-duplex, serial I/O interface intended for asynchronous communication
between the CPU and other peripherals using the standard non-return-to-zero (NRZ) format. The HECC uses
a serial, multimaster communication protocol that efficiently supports distributed real-time control with robust
communication rates of up to 1 megabit per second (Mbps). These CAN peripherals are ideal for applications
operating in noisy and harsh environments (e.g., automotive and industrial fields) that require reliable serial
communication or multiplexed wiring. The I2C module is a multi-master communication module providing an
interface between the VF48x microcontroller and an I2C-compatible device via the I2C serial bus. The I2C
supports both 100 Kbps and 400 Kbps speeds. For more detailed functional information on the SPI, SCI, and
CAN peripherals, see the specific reference guides (literature numbers SPNU195, SPNU196, and SPNU197).
For more detailed functional information on the I2C, see the TMS470R1x Inter-Integrated Circuit (I2C) Reference Guide (literature number SPNU223).
The HET is an advanced intelligent timer that provides sophisticated timing functions for real-time applications.
The timer is software-controlled, using a reduced instruction set, with a specialized timer micromachine and
an attached I/O port. The HET can be used for compare, capture, or general-purpose I/O. It is especially well
suited for applications requiring multiple sensor information and drive actuators with complex and accurate
time pulses. The HET used in this device is the high-end timer lite. It has fewer I/Os than the usual 32 in a
standard HET. For more detailed functional information on the HET, see the TMS470R1x High-End Timer (HET)
Reference Guide (literature number SPNU199). The VF48x HET peripheral contains the XOR-share feature.
This feature allows two adjacent HET high- resolution channels to be XORed together, making it possible to
output smaller pulses than a standard HET. For more detailed information on the HET XOR-share feature, see
the TMS470R1x High-End Timer (HET) Reference Guide (literature number SPNU199).
The VF48x device has one 10-bit-resolution, sample-and-hold MibADC. Each of the MibADC channels can be
converted individually or can be grouped by software for sequential conversion sequences. There are three
separate groupings, two of which can be triggered by an external event. Each sequence can be converted once
when triggered or configured for continuous conversion mode. For more detailed functional information on the
MibADC, see the TMS470R1x Multi-Buffered Analog-to-Digital Converter (MibADC) Reference Guide (literature
number SPNU206).
4
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TMS470R1VF48C/VF48B
16/32-BIT RISC FLASH MICROCONTROLLERS
SPNS093D – MAY 2004 – REVISED FEBRUARY 2006
description (continued)
The frequency-modulated zero-pin phase-locked loop (FMZPLL) clock module contains a phase-locked loop,
a clock-monitor circuit, a clock-enable circuit, and a prescaler (with prescale values of 1–8). The function of the
FMZPLL is to multiply the external frequency reference to a higher frequency for internal use. The FMZPLL
provides ACLK to the system (SYS) module. The SYS module subsequently provides system clock (SYSCLK),
real-time interrupt clock (RTICLK), CPU clock (MCLK), and peripheral interface clock (ICLK) to all other VF48x
device modules. For more detailed functional information on the FMZPLL, see the TMS470R1x FrequencyModulated Phase-Locked Loop (FMPLL) Clock Module Reference Guide (literature number SPNU221).
NOTE
ACLK should not be confused with the MibADC internal clock, ADCLK. ACLK is the continuous system
clock from an external resonator/crystal reference.
The expansion bus module (EBM) is a standalone module that supports the multiplexing of the GIO functions
and the expansion bus interface. For more information on the EBM, see the TMS470R1x Expansion Bus Module
(EBM) Reference Guide (literature number SPNU222).
The VF48x device also has an external clock prescaler (ECP) module that when enabled, outputs a continuous
external clock (ECLK) on a specified GIO pin. The ECLK frequency is a user-programmable ratio of the peripheral interface clock (ICLK) frequency. For more detailed functional information on the ECP, see the
TMS470R1x External Clock Prescaler (ECP) Reference Guide (literature number SPNU202).
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251-1443
5
TMS470R1VF48C/VF48B
16/32-BIT RISC FLASH MICROCONTROLLERS
SPNS093D – MAY 2004 – REVISED FEBRUARY 2006
device characteristics
The VF48x device is a derivative of the F05 system emulation device SE470R1VB8AD. Table 1 identifies all
the characteristics of the VF48x device except the SYSTEM and CPU, which are generic.
Table 1. Device Characteristics
CHARACTERISTICS
DEVICE DESCRIPTION
TMS470R1VF48X
COMMENTS FOR VF48X
MEMORY
For the number of memory selects on this device, see the Memory Selection Assignment table (Table 2).
Flash is pipeline-capable.
Pipeline/Non-Pipeline
INTERNAL
MEMORY
1M-Byte flash (VF48C only)
768K-byte flash (VF48B only)
64K-Byte SRAM (VF48C only)
48K-byte SRAM (VF48B only)
Memory Security Module (MSM)
JTAG Security Module
The VF48C RAM is implemented in one 64K array selected by two
memory-select signals (see the Memory Selection Assignment table,
Table 2).
The VF48B RAM is implemented in one 48K array selected by two
memory-select signals (see the Memory Selection Assignment table,
Table 2).
PERIPHERALS
For the device-specific interrupt priority configurations, see the Interrupt Priority Table (Table 5). And for the 1K peripheral address ranges and
their peripheral selects, see the VF48x Peripherals, System Module, and Flash Base Addresses table (Table 3).
6
CLOCK
FMZPLL
Expansion Bus
EBM
Expansion bus module with 42 pins. Supports 8- and 16-bit memories.
See Table 6 for details.
GENERAL-PURPOSE
I/Os
46 I/O
Port A has 8 external pins, Port B has only 1 external pin, Port C has 5
external pins, Port D has 6 external pins, Ports E, F, and G each have
8 external pins, and Port H has 2 external pins.
ECP
YES
SCI
3 (3-pin)
CAN
(HECC and/or SCC)
2 HECC
SPI
(5-pin, 4-pin or 3-pin)
2 (5-pin)
I2C
5
HET with
XOR Share
12 I/O
HET RAM
64-Instruction Capacity
MibADC
10-bit, 12-channel
64-word FIFO
CORE VOLTAGE
1.8 V
I/O VOLTAGE
3.3 V
PINS
144
PACKAGES
PGE
POST OFFICE BOX 1443
Frequency-modulated zero-pin PLL has no external loop filter pins.
Two high-end CAN controllers
The high-resolution (HR) SHARE feature allows even-numbered HR
pins to share the next higher odd-numbered HR pin structures. This HR
sharing is independent of whether or not the odd pin is available
externally. If an odd pin is available externally and shared, then the odd
pin can only be used as a general-purpose I/O. For more information on
HR SHARE, see theTMS470R1x High-End Timer (HET) Reference
Guide (literature number SPNU199).
Both the logic and registers for a full 16-channel MibADC are present.
• HOUSTON, TEXAS 77251-1443
TMS470R1VF48C/VF48B
16/32-BIT RISC FLASH MICROCONTROLLERS
SPNS093D – MAY 2004 – REVISED FEBRUARY 2006
functional block diagram (VF48C)
External Pins
FLASH
(1M Byte)
2 Banks
16 Sectors
VCCP
FLTP2
OSCIN
Memory
Security
Module
(MSM)
RAM
(64K Bytes)
FMZPLL
OSCOUT
Crystal
External Pins
PLLDIS
ADIN[11:0]
CPU Address/Data Bus
MibADC
64-Word
FIFO
TMS470R1x CPU
TRST
TCK
TDO
TMS2
AWD
Interrupt Expansion
Module (IEM)
TEST
Digital
Watchdog
(DWD)
PORRST
CLKOUT
Analog
Watchdog
(AWD)
HET
64 Words
Expansion Address/Data Bus
TMS470R1x SYSTEM MODULE
with Enhanced RTI Module(A)
DMA Controller
16 Channels
HECC1
HECC2
I2C5SDA
I2C5SCL
I2C5
CAN1HTX
CAN2HTX
CAN2SRX
SCI1CLK
SCI1
SCI1TX
SCI1RX
SCI2CLK
SCI2
I2C4
HET [0:8;18,20,22]
CAN1HRX
SCC
I2C4SDA
I2C4SCL
ADREFLO
VSSAD
TDI
RST
ADREFHI
VCCAD
ICE Breaker
TMS
ADEVT
SCI2TX
SCI2RX
I2C3
I2C3SDA
I2C3SCL
I2C2
I2C2SDA
I2C2SCL
SCI3
SPI2
SPI1
ECP
GIO/EBM†
I2C1
I2C1SDA
A.
GIOA[0]/INT[0]
GIOA[7:2]/INT[7:2]
GIOB[0]
GIOC[4:0]
GIOD[5:0]
GIOE[7:0]/INT[15:8]
GIOF[7:0]
GIOG[7:0]
GIOH[5,0]
GIOA[1]/INT[1]/ECLK
SCI3TX
SCI3RX
SCI3CLK
SPI2SCS
SPI2ENA
SPI2SIMO
SPI2SOMI
SPI2CLK
SPI1SCS
SPI1ENA
SPI1SIMO
SPI1SOMI
SPI1CLK
I2C1SCL
The enhanced RTI module is the system module with two extra bits to disable the FMZPLL while in STANDBY mode.
POST OFFICE BOX 1443
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7
TMS470R1VF48C/VF48B
16/32-BIT RISC FLASH MICROCONTROLLERS
SPNS093D – MAY 2004 – REVISED FEBRUARY 2006
functional block diagram (VF48B)
External Pins
FLASH
(768K Byte)
2 Banks
12 Sectors
VCCP
FLTP2
OSCIN
Memory
Security
Module
(MSM)
RAM
(48K Bytes)
FMZPLL
OSCOUT
Crystal
External Pins
PLLDIS
ADIN[11:0]
CPU Address/Data Bus
MibADC
64-Word
FIFO
TMS470R1x CPU
TRST
TCK
TDO
TMS2
AWD
Interrupt Expansion
Module (IEM)
TEST
Digital
Watchdog
(DWD)
PORRST
CLKOUT
Analog
Watchdog
(AWD)
HET
64 Words
Expansion Address/Data Bus
TMS470R1x SYSTEM MODULE
with Enhanced RTI Module†
DMA Controller
16 Channels
HECC1
HECC2
I2C5SDA
I2C5SCL
I2C5
CAN1HTX
CAN2HTX
CAN2SRX
SCI1CLK
SCI1
SCI1TX
SCI1RX
SCI2CLK
SCI2
I2C4
HET [0:8;18,20,22]
CAN1HRX
SCC
I2C4SDA
I2C4SCL
ADREFLO
VSSAD
TDI
RST
ADREFHI
VCCAD
ICE Breaker
TMS
ADEVT
SCI2TX
SCI2RX
I2C3
I2C3SDA
I2C3SCL
I2C2
I2C2SDA
I2C2SCL
SCI3
SPI2
SPI1
ECP
GIO/EBM†
I2C1
I2C1SDA
A.
8
GIOA[0]/INT[0]
GIOA[7:2]/INT[7:2]
GIOB[0]
GIOC[4:0]
GIOD[5:0]
GIOE[7:0]/INT[15:8]
GIOF[7:0]
GIOG[7:0]
GIOH[5,0]
GIOA[1]/INT[1]/ECLK
SCI3TX
SCI3RX
SCI3CLK
SPI2SCS
SPI2ENA
SPI2SIMO
SPI2SOMI
SPI2CLK
SPI1SCS
SPI1ENA
SPI1SIMO
SPI1SOMI
SPI1CLK
I2C1SCL
The enhanced RTI module is the system module with two extra bits to disable the FMZPLL while in STANDBY mode.
POST OFFICE BOX 1443
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TMS470R1VF48C/VF48B
16/32-BIT RISC FLASH MICROCONTROLLERS
SPNS093D – MAY 2004 – REVISED FEBRUARY 2006
Terminal Functions
TERMINAL
NAME
PIN
NO.
INPUT
VOLTAGE(1)(2)
OUTPUT
CURRENT(1)(2)
INTERNAL
PULLUP/
PULLDOWN(3)
DESCRIPTION
HIGH-END TIMER (HET)
HET[0]
73
HET[1]
72
HET[2]
71
HET[3]
66
HET[4]
65
HET[5]
63
HET[6]
9
Timer input capture or output compare. The HET[8:0,18,20,22] applicable
pins can be programmed as general-purpose input/output (GIO) pins. All
are high-resolution pins.
3.3-V
2mA -z
HET[7]
11
HET[8]
12
HET[18]
15
HET[20]
18
HET[22]
19
CAN1HRX
83
5V tolerant
4mA
CAN1HTX
84
3.3-V
2mA -z
CAN2HRX
54
5V tolerant
4mA
CAN2HTX
55
3.3-V
2mA -z
IPD
(20 μA)
The high-resolution (HR) SHARE feature allows even HR pins to share
the next higher odd HR pin structures. This HR sharing is independent of
whether or not the odd pin is available externally. If an odd pin is available
externally and shared, then the odd pin can only be used as a generalpurpose I/O. For more information on HR SHARE, see the TMS470R1x
High-End Timer (HET) Reference Guide (literature number SPNU199).
HIGH-END CAN CONTROLLER (HECC)
HECC1 receive pin or GIO pin
IPU (20 μA) HECC1 transmit pin or GIO pin
HECC2 receive pin or GIO pin
IPU (20 μA) HECC2 transmit pin or GIO pin
STANDARD CAN CONTROLLER (SCC)
CANSRX
-
5V tolerant
4mA
CANSTX
-
3.3-V
2mA -z
SCC receive pin.The CANSRX signal is only connected to the pad and not
to a package pin. For reduced power consumption in low power mode,
CANSRX should be driven output LOW.
IPU
(20 μA)
SCC transmit pin. The CANSTX signal is only connected to the pad and
not to a package pin. For reduced power consumption in low power
mode, CANSTX should be driven output LOW.
GENERAL-PURPOSE I/O (GIO)
GIOA[0]/INT[0]
141
GIOA[1]/INT[1]/
ECLK
136
GIOA[2]/INT[2]
134
GIOA[3]/INT[3]
133
GIOA[4]/INT[4]
127
GIOA[5]/INT[5]
98
GIOA[6]/INT[6]
78
GIOA[7]/INT[7]
79
GIOB[0]
43
GIOC[0]
135
GIOC[1]
128
GIOC[2]
126
GIOC[3]
120
GIOC[4]
119
General-purpose input/output pins. GIOA[7:0]/INT[7:0] are interruptcapable pins.
5V tolerant
3.3-V
4mA
2mA -z
GIOA[1]/INT[1]/ECLK pin is multiplexed with the external clock-out
function of the external clock prescale (ECP) module.
IPD
(20 μA)
GIOB[0], GIOC[4:0], GIOD[5:0], GIOE[7:0:], GIOF[7:0], GIOG[7:0], AND
GIOH[5,0] are multiplexed with the expansion bus module.
SeeTable 6.
1 PWR = power, GND = ground, REF = reference voltage, NC = no connect
2 All I/O pins, except RST, are configured as inputs while PORRST is low and immediately after PORRST goes high.
3 IPD = internal pulldown, IPU = internal pullup (all internal pullups and pulldowns are active on input pins, independent of the PORRST state.)
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9
TMS470R1VF48C/VF48B
16/32-BIT RISC FLASH MICROCONTROLLERS
SPNS093D – MAY 2004 – REVISED FEBRUARY 2006
Terminal Functions (Continued)
TERMINAL
NAME
PIN
NO.
INPUT
VOLTAGE(1)(2)
OUTPUT
CURRENT(1)(2)
INTERNAL
PULLUP/
PULLDOWN(3)
DESCRIPTION
GENERAL-PURPOSE I/O (GIO) (CONTINUED)
GIOD[0]
42
GIOD[1]
39
GIOD[2]
35
GIOD[3]
30
GIOD[4]
27
GIOD[5]
23
GIOE[0]
44
GIOE[1]
47
GIOE[2]
58
GIOE[3]
61
GIOE[4]
64
GIOE[5]
67
GIOE[6]
70
GIOE[7]
77
GIOF[0]/INT[8]
80
GIOF[1]/INT[9]
82
GIOF[2]/INT[10]
89
GIOF[3]/INT[11]
90
GIOF[4]/INT[12]
93
GIOF[5]/INT[13]
96
GIOF[6]/INT[14]
99
GIOF[7]/INT[15]
100
GIOG[0]
20
GIOG[1]
10
GIOG[2]
8
GIOG[3]
6
GIOG[4]
3
GIOG[5]
143
GIOG[6]
142
GIOG[7]
140
GIOH[0]
139
GIOB[0], GIOC[4:0], GIOD[5:0], GIOE[7:0:], GIOF[7:0], GIOG[7:0],
AND GIOH[5,0] are multiplexed with the expansion bus module.
3.3-V
2mA -z
IPD
(20 μA)
GIOF[7:0]/INT[15:8] are interrupt capable pins.
See Table 6.
GIOH[5]
125
1 PWR = power, GND = ground, REF = reference voltage, NC = no connect
2 All I/O pins, except RST, are configured as inputs while PORRST is low and immediately after PORRST goes high.
3 IPD = internal pulldown, IPU = internal pullup (all internal pullups and pulldowns are active on input pins, independent of the PORRST state.)
10
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TMS470R1VF48C/VF48B
16/32-BIT RISC FLASH MICROCONTROLLERS
SPNS093D – MAY 2004 – REVISED FEBRUARY 2006
Terminal Functions (Continued)
TERMINAL
NAME
PIN
NO.
INPUT
VOLT-
OUTPUT
CURRENT(1)(2)
AGE(1)(2)
INTERNAL
PULLUP/
PULLDOWN(3)
DESCRIPTION
MULTI-BUFFERED ANALOG-TO-DIGITAL CONVERTER (MibADC)
ADEVT
101
ADIN[0]
117
ADIN[1]
116
ADIN[2]
115
ADIN[3]
114
2mA -z
IPD (20 μA) MibADC event input. Can be programmed as a GIO pin.
ADIN[4]
113
ADIN[5]
108
ADIN[6]
107
ADIN[7]
106
ADIN[8]
105
ADIN[9]
104
ADIN[10]
103
ADIN[11]
102
ADREFHI
109
ADREFLO
110
GND REF
MibADC module low-voltage reference input
VCCAD
111
3.3-V PWR
MibADC analog supply voltage
VSSAD
112
GND
3.3-V
MibADC analog input pins
3.3-V REF
MibADC module high-voltage reference input
MibADC analog ground reference
SERIAL PERIPHERAL INTERFACE 1 (SPI1)
SPI1CLK
4
SPI1 clock. SPI1CLK can be programmed as a GIO pin.
SPI1ENA
2
SPI1 chip enable. Can be programmed as a GIO pin.
SPI1SCS
1
SPI1 slave chip select. Can be programmed as a GIO pin.
5V tolerant
4mA
SPI1SIMO
5
SPI1 data stream. Slave in/master out. Can be programmed
as a GIO pin.
SPI1SOMI
7
SPI1 data stream. Slave out/master in. Can be programmed
as a GIO pin.
SPI2CLK
56
SPI2 clock. Can be programmed as a GIO pin.
SPI2ENA
60
SPI2 chip enable. Can be programmed as a GIO pin.
SPI2SCS
62
SERIAL PERIPHERAL INTERFACE 2 (SPI2)
SPI2 slave chip select. Can be programmed as a GIO pin.
5V tolerant
4mA
SPI2SIMO
59
SPI2 data stream. Slave in/master out. Can be programmed
as a GIO pin.
SPI2SOMI
57
SPI2 data stream. Slave out/master in. Can be programmed
as a GIO pin.
I2C1SDA
87
I2C1SCL
88
INTER-INTEGRATED CIRCUIT 1 (I2C1)
5V tolerant
4mA
I2C1 serial data pin or GIO pin
I2C1 serial clock pin or GIO pin
INTER-INTEGRATED CIRCUIT 2 (I2C2)
I2C2SDA
94
I2C2SCL
95
5V tolerant
4mA
I2C2 serial data pin or GIO pin
I2C2 serial clock pin or GIO pin
1 PWR = power, GND = ground, REF = reference voltage, NC = no connect
2 All I/O pins, except RST, are configured as inputs while PORRST is low and immediately after PORRST goes high.
3 IPD = internal pulldown, IPU = internal pullup (all internal pullups and pulldowns are active on input pins, independent of the PORRST state.)
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TMS470R1VF48C/VF48B
16/32-BIT RISC FLASH MICROCONTROLLERS
SPNS093D – MAY 2004 – REVISED FEBRUARY 2006
Terminal Functions (Continued)
TERMINAL
NAME
PIN
NO.
INPUT
VOLTAGE(1)(2)
OUTPUT
CURRENT(1)(2)
INTERNAL
PULLUP/
PULLDOWN(3)
DESCRIPTION
INTER-INTEGRATED CIRCUIT 3 (I2C3)
I2C3SDA
29
I2C3SCL
28
I2C4SDA
41
I2C4SCL
40
I2C5SDA
38
I2C5SCL
37
OSCIN
33
OSCOUT
32
5V tolerant
I2C3 serial data pin or GIO pin
4mA
I2C3 serial clock pin or GIO pin
INTER-INTEGRATED CIRCUIT 4 (I2C4)
5V tolerant
I2C4 serial data pin or GIO pin
4mA
I2C4 serial clock pin or GIO pin
INTER-INTEGRATED CIRCUIT 5 (I2C5)
5V tolerant
I2C5 serial data pin or GIO pin
4mA
I2C5 serial clock pin or GIO pin
FREQUENCY-MODULATED ZERO-PIN PHASE-LOCKED LOOP (FMZPLL)
1.8-V
Crystal connection pin or external clock input
2mA
External crystal connection pin
IPD
(20 μA)
PLLDIS
97
3.3-V
SCI1CLK
48
3.3-V
2mA -z
SCI1RX
46
5V tolerant
4mA
SCI1TX
45
3.3-V
2mA -z
SCI2CLK
51
3.3-V
2mA -z
SCI2RX
50
5V tolerant
4mA
SCI2TX
49
3.3-V
2mA -z
SCI3CLK
24
3.3-V
2mA -z
SCI3RX
22
5V tolerant
4mA
SCI3TX
21
3.3-V
2mA -z
Enable/disable the FMZPLL. The FMZPLL can be bypassed and the
oscillator becomes the system clock. If not in bypass mode, TI
recommends that this pin be connected to ground or pulled down to
ground by an external resistor.
SERIAL COMMUNICATIONS INTERFACE 1 (SCI1)
IPD (20 μA)
SCI1 clock. SCI1CLK can be programmed as a GIO pin.
IPU (20 μA)
SCI1 data transmit. SCI1TX can be programmed as a GIO pin.
SCI1 data receive. SCI1RX can be programmed as a GIO pin.
SERIAL COMMUNICATIONS INTERFACE 2 (SCI2)
IPD(20 μA)
SCI2 clock. SCI2CLK can be programmed as a GIO pin.
IPU (20 μA)
SCI2 data transmit. SCI2TX can be programmed as a GIO pin.
SCI2 data receive. SCI2RX can be programmed as a GIO pin.
SERIAL COMMUNICATIONS INTERFACE 3 (SCI3)
IPD (20 μA)
SCI3 clock. SCI3CLK can be programmed as a GIO pin.
IPU (20 μA)
SCI3 data transmit. SCI3TX can be programmed as a GIO pin.
SCI3 data receive. SCI3RX can be programmed as a GIO pin.
SYSTEM MODULE (SYS)
CLKOUT
81
3.3-V
PORRST
118
3.3-V
RST
121
3.3-V
Bidirectional pin. CLKOUT can be programmed as a GIO pin or the
output of SYSCLK, ICLK, or MCLK.
8mA
4mA
IPD
(20 μA)
Input master chip power-up reset. External VCC monitor circuitry must
assert a power-on reset.
IPU
(20 μA)
Bidirectional reset. The internal circuitry can assert a reset, and an
external system reset can assert a device reset.
On this pin, the output buffer is implemented as an open drain (drives
low only).
To ensure an external reset is not arbitrarily generated, TI recommends
that an external pullup resistor be connected to this pin.
WATCHDOG/REAL-TIME INTERRUPT (WD/RTI)
AWD
36
3.3-V
8mA
Analog watchdog reset. The AWD pin provides a system reset if the WD
KEY is not written in time by the system, providing an external RC
network circuit is connected. If the user is not using AWD, TI
recommends that this pin be connected to ground or pulled down to
ground by an external resistor.
For more details on the external RC network circuit, see the TMS470R1x
System Module Reference Guide (literature number SPNU189).
1 PWR = power, GND = ground, REF = reference voltage, NC = no connect
2 All I/O pins, except RST, are configured as inputs while PORRST is low and immediately after PORRST goes high.
3 IPD = internal pulldown, IPU = internal pullup (all internal pullups and pulldowns are active on input pins, independent of the PORRST state.)
12
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TMS470R1VF48C/VF48B
16/32-BIT RISC FLASH MICROCONTROLLERS
SPNS093D – MAY 2004 – REVISED FEBRUARY 2006
Terminal Functions (Continued)
TERMINAL
NAME
PIN
NO.
INPUT
VOLTAGE(1)(2)
OUTPUT
CURRENT(1)(2)
INTERNAL
PULLUP/
PULLDOWN(3)
DESCRIPTION
TEST/DEBUG (T/D)
TCK
76
3.3-V
IPD
(20 μA)
Test clock. TCK controls the test hardware (JTAG).
TDI
74
8mA
IPU
(20 μA)
Test data in. TDI inputs serial data to the test instruction register, test data
register, and programmable test address (JTAG).
TDO
75
8mA
IPD
(20 μA)
Test data out. TDO outputs serial data from the test instruction register,
test data register, identification register, and programmable test address
(JTAG).
TEST
124
IPD
(20 μA)
Test enable. Reserved for internal use only. TI recommends that this pin
be connected to ground or pulled down to ground by an external resistor.
TMS
17
8mA
IPU
(20 μA)
Serial input for controlling the state of the CPU test access port (TAP)
controller (JTAG).
TMS2
16
8mA
IPU
(20 μA)
Serial input for controlling the second TAP. TI recommends that this pin
be connected to VCCIO or pulled up to VCCIO by an external resistor.
TRST
144
IPD
(20 μA)
Test hardware reset to TAP1 and TAP2. IEEE Standard 1149-1 (JTAG)
Boundary-Scan Logic. TI recommends that this pin be pulled down to
ground by an external resistor.
3.3-V
FLASH
FLTP2
132
NC
VCCP
131
3.3-V PWR
Flash test pad 2. For proper operation, this pin must not be connected
[no connect (NC)].
NC
Flash external pump voltage (3.3 V)
SUPPLY VOLTAGE CORE (1.8 V)
13
31
VCC
53
92
1.8-V
PWR
Core logic supply voltage
123
130
SUPPLY VOLTAGE DIGITAL I/O (3.3 V)
25
VCCIO
69
86
3.3-V
PWR
Digital I/O supply voltage
137
SUPPLY GROUND CORE
14
34
VSS
52
91
GND
Core supply ground reference
122
129
SUPPLY GROUND DIGITAL I/O
26
VSSIO
68
85
GND
Digital I/O supply ground reference
138
1 PWR = power, GND = ground, REF = reference voltage, NC = no connect
2 All I/O pins, except RST, are configured as inputs while PORRST is low and immediately after PORRST goes high.
3 IPD = internal pulldown, IPU = internal pullup (all internal pullups and pulldowns are active on input pins, independent of the PORRST state.)
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TMS470R1VF48C/VF48B
16/32-BIT RISC FLASH MICROCONTROLLERS
SPNS093D – MAY 2004 – REVISED FEBRUARY 2006
VF48X DEVICE-SPECIFIC INFORMATION
memory
Figure 1 shows the memory map of the VF48C device.
Memory (4G Bytes)
SYSTEM with PSA, CIM, RTI, DEC,
DMA, MMC, DWD
IEM
MSM
Reserved
0xFFFF_FFFF
System Module Control Registers
(512K Bytes)
0xFFF8_0000
0xFFF7_FFFF
Peripheral Control Registers
(512K Bytes)
Reserved
HET
Reserved
SPI1
SCI3
SCI2
SCI1
Reserved
MibADC
ECP
Reserved
EBM
GIO
Reserved
HECC2
Reserved
HECC1
Reserved
HECC2 RAM
Reserved
HECC1 RAM
Reserved
SCC
Reserved
SCC RAM
I2C4
I2C3
I2C2
I2C1
I2C5
SPI2
Reserved
0xFFF0_0000
0xFFEF_FFFF
0xFFE8_C000
0xFFE8_BFFF
0xFFE8_8000
0xFFE8_7FFF
0xFFE8_4021
0xFFE8_4020
0xFFE8_4000
Reserved
Flash Control Registers
Reserved
MPU Control Registers
Reserved (1 MByte)
0xFFE0_0000
0x7FFF_FFFF
RAM
(64K Bytes)
Program
and
Data Area
FLASH
(1M Bytes)
2 Banks
16 Sectors
Reserved
FIQ
IRQ
HET RAM
(1K Bytes)
Data Abort
0x0000_0024
0x0000_0023
0x0000_0000
A.
B.
Reserved
Prefetch Abort
Software Interrupt
Exception, Interrupt, and
Reset Vectors
0xFFFF_FD00
0xFFFF_FC00
0xFFFF_F700
0xFFF8_0000
0xFFF7_FC00
0xFFF7_F800
0xFFF7_F600
0xFFF7_F500
0xFFF7_F400
0xFFF7_F000
0xFFF7_EF00
0xFFF7_ED00
0xFFF7_EC00
0xFFF7_EA00
0xFFF7_E800
0xFFF7_E600
0xFFF7_E400
0xFFF7_E000
0xFFF7_DC00
0xFFF7_DB00
0xFFF7_DA00
0xFFF7_D900
0xFFF7_D800
0xFFF7_D500
0xFFF7_D400
0xFFF0_0000
0x0000_0023
0x0000_0020
0x0000_001C
0x0000_0018
0x0000_0014
0x0000_0010
0x0000_000C
0x0000_0008
Undefined Instruction
0x0000_0004
Reset
0x0000_0000
Memory addresses are configurable by the system (SYS) module within the range of 0x0000_0000 to 0xFFE0_0000.
The CPU registers are not a part of the memory map.
Figure 1. TMS470R1VF48C Memory Map
14
0xFFFF_FFFF
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TMS470R1VF48C/VF48B
16/32-BIT RISC FLASH MICROCONTROLLERS
SPNS093D – MAY 2004 – REVISED FEBRUARY 2006
memory (continued)
Figure 2 shows the memory map of the VF48B device.
Memory (4G Bytes)
SYSTEM with PSA, CIM, RTI, DEC,
DMA, MMC, DWD
IEM
MSM
Reserved
0xFFFF_FFFF
System Module Control Registers
(512K Bytes)
0xFFF8_0000
0xFFF7_FFFF
Peripheral Control Registers
(512K Bytes)
Reserved
HET
Reserved
SPI1
SCI3
SCI2
SCI1
Reserved
MibADC
ECP
Reserved
EBM
GIO
Reserved
HECC2
Reserved
HECC1
Reserved
HECC2 RAM
Reserved
HECC1 RAM
Reserved
SCC
Reserved
SCC RAM
I2C4
I2C3
I2C2
I2C1
I2C5
SPI2
Reserved
0xFFF0_0000
0xFFEF_FFFF
0xFFE8_C000
0xFFE8_BFFF
0xFFE8_8000
0xFFE8_7FFF
0xFFE8_4021
0xFFE8_4020
0xFFE8_4000
Reserved
Flash Control Registers
Reserved
MPU Control Registers
Reserved (1 MByte)
0xFFE0_0000
0x7FFF_FFFF
RAM
(48K Bytes)
Program
and
Data Area
FLASH
(768K Bytes)
2 Banks
12 Sectors
Reserved
FIQ
IRQ
HET RAM
(1K Bytes)
Reserved
Data Abort
0x0000_0024
0x0000_0023
0x0000_0000
A.
B.
Prefetch Abort
Exception, Interrupt, and
Reset Vectors
Software Interrupt
0xFFFF_FFFF
0xFFFF_FD00
0xFFFF_FC00
0xFFFF_F700
0xFFF8_0000
0xFFF7_FC00
0xFFF7_F800
0xFFF7_F600
0xFFF7_F500
0xFFF7_F400
0xFFF7_F000
0xFFF7_EF00
0xFFF7_ED00
0xFFF7_EC00
0xFFF7_EA00
0xFFF7_E800
0xFFF7_E600
0xFFF7_E400
0xFFF7_E000
0xFFF7_DC00
0xFFF7_DB00
0xFFF7_DA00
0xFFF7_D900
0xFFF7_D800
0xFFF7_D500
0xFFF7_D400
0xFFF0_0000
0x0000_0023
0x0000_0020
0x0000_001C
0x0000_0018
0x0000_0014
0x0000_0010
0x0000_000C
0x0000_0008
Undefined Instruction
0x0000_0004
Reset
0x0000_0000
Memory addresses are configurable by the system (SYS) module within the range of 0x0000_0000 to 0xFFE0_0000.
The CPU registers are not a part of the memory map.
Figure 2. TMS470R1VF48B Memory Map
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TMS470R1VF48C/VF48B
16/32-BIT RISC FLASH MICROCONTROLLERS
SPNS093D – MAY 2004 – REVISED FEBRUARY 2006
memory selects
Memory selects allow the user to address memory arrays (i.e., flash, RAM, and HET RAM) at user-defined
addresses. Each memory select has its own set (low and high) of memory base address registers (MFBAHRx
and MFBALRx) that, together, define the array’s starting (base) address, size, and protection.
The base address of each memory select is configurable to any memory address boundary that is a multiple
of the decoded block size. The decoded block size for the flash memory on this device is 0x00400000. For
more information on how to control and configure these memory select registers, see the bus structure and
memory sections of the TMS470R1x System Module Reference Guide (literature number SPNU189).
For the memory selection assignments and the memory selected, see Table 2.
Table 2. Memory Selection Assignment
MEMORY
SELECT
MEMORY SELECTED
(ALL INTERNAL)
MEMORY
SIZE(1)
MPU
MSM
MEMORY BASE ADDRESS REGISTER
0 (fine)
FLASH/ROM
NO
YES
MFBAHR0 and MFBALR0
1 (fine)
FLASH/ROM
1M (VF48C)
768 K
(VF48B)
NO
YES
MFBAHR1 and MFBALR1
2 (fine)
RAM
64K(2)
(VF48C)
YES
YES
MFBAHR2 and MFBALR2
3 (fine)
RAM
48K(2)
(VF48B)
YES
YES
MFBAHR3 and MFBALR3
4 (fine)
HET RAM
1K
NO
NO
MFBAHR4 and MFBALR4
SMCR1
5 (coarse)
CS[5]/GIOC[3]
128MB (x8)
1MB (x16)
NO
NO
MCBAHR2 and MCBALR2
SMCR5
6 (coarse)
CS[6]/GIOC[4]
128MB (x8)
1MB (x16)
NO
NO
MCBAHR3 and MCBALR3
SMCR6
STATIC MEM
CTL REGISTER
1 x8 refers to size of memory in 8-bits; x16 refers to size of memory in 16-bits.
2 The starting addresses for both RAM memory-select signals cannot be offset from each other by a multiple of the user-defined block size in
the memory-base address register.
JTAG security module
The VF48x device includes a JTAG security module to provide maximum security to the memory contents. The
visible unlock code can be in the OTP sector or in the first bank of the user-programmable memory. For the
VF48x, the visible unlock code is in the OTP sector at address 0x0000_01F8.
memory security module
The VF48x device also includes a memory security module (MSM) to provide additional security and flexibility
to the memory contents’ protection. The password for unlocking the MSM is located in the four words just before
the flash protection keys (see page 17).
RAM
The VF48C device contains 64K-bytes of internal static RAM configurable by the SYS module to be addressed
within the range of 0x0000_0000 to 0xFFE0_0000. This VF48C RAM is implemented in one 64K array selected
by two memory-select signals. This VF48C configuration imposes an additional constraint on the memory map
for RAM; the starting addresses for both RAM memory selects cannot be offset from each other by the multiples
of the size of the physical RAM (i.e., 64K for the VF48C device). The VF48C RAM is addressed through memory
selects 2 and 3.
The VF48B device contains 48Kbytes of internal static RAM configurable by the SYS module to be addressed
within the range of 0x0000_0000 to 0xFFE0_0000. This VF48B RAM is implemented in one 48K array selected
by two memory-select signals. The VF48B configuration imposes an additional constraint on the memory map
16
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16/32-BIT RISC FLASH MICROCONTROLLERS
SPNS093D – MAY 2004 – REVISED FEBRUARY 2006
for RAM; the starting addresses for both RAM memory selects cannot be offset from each other by the multiples
of the size of the physical RAM (i.e., 48K for the VF48B device). The VF48B RAM is addressed through memory
selects 2 and 3.
RAM (continued)
The RAM can be protected by the memory protection unit (MPU) portion of the SYS module, allowing the user
finer blocks of memory protection than is allowed by the memory selects. The MPU is ideal for protecting an
operating system while allowing access to the current task. For more detailed information on the MPU portion
of the SYS module and memory protection, see the memory section of the TMS470R1x System Module
Reference Guide (literature number SPNU189).
F05 flash
The F05 flash memory is a nonvolatile electrically erasable and programmable memory implemented with a
32-bit-wide data bus interface. The F05 flash has an external state machine for programming and erase
functions. See the flash read and flash program and erase sections following.
flash protection keys
The VF48x device provides flash protection keys. These four 32-bit protection keys prevent program/erase/
compaction operations from occurring until after the four protection keys have been matched by the CPU loading
the correct user keys into the FMPKEY control register. The protection keys on the VF48x are located in the
last 4 words of the first 64K sector. For more detailed information on the flashflash protection keys and the
FMPKEY control register, see the "Optional Quadruple Protection Keys" and "Programming the Protection
Keys" portions of the TMS470R1x F05 Flash Reference Guide (literature number SPNU213).
flash read
The VF48x flash memory is configurable by the SYS module to be addressed within the range of 0x0000_0000
to 0xFFE0_0000. The flash is addressed through memory selects 0 and 1.
NOTE
The flash external pump voltage (VCCP) is required for all operations (program, erase, and read).
flash pipeline mode
When in pipeline mode, the flash operates with a system clock frequency of up to 60 MHz (versus a system
clock frequency of 24 MHz in normal mode). Flash in pipeline mode is capable of accessing 64-bit words and
provides two 32-bit pipelined words to the CPU. Also, in pipeline mode the flash can be read with no wait states
when memory addresses are contiguous (after the initial 1- or 2-wait-state reads).
NOTE
After a system reset, pipeline mode is disabled (ENPIPE bit [FMREGOPT.0] is a 0). In other words, the
VF48x device powers up and comes out of reset in non-pipeline mode. Furthermore, setting the flash
configuration mode bit (GBLCTRL.4) will override pipeline mode.
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17
TMS470R1VF48C/VF48B
16/32-BIT RISC FLASH MICROCONTROLLERS
SPNS093D – MAY 2004 – REVISED FEBRUARY 2006
flash program and erase
The VF48C device flash contains two 512K-byte memory arrays (or banks), for a total of 1M-byte of flash, and
consists of sixteen sectors. These sixteen sectors are sized as follows:
SECTOR
NO.
SEGMENT
LOW ADDRESS
HIGH ADDRESS
OTP
2K Bytes
0x0000_0000
0x0000_07FF
0
64K Bytes
0x0000_0000
0x0000_FFFF
1
64K Bytes
0x0001_0000
0x0001_FFFF
2
64K Bytes
0x0002_0000
0x0002_FFFF
3
64K Bytes
0x0003_0000
0x0003_FFFF
4
64K Bytes
0x0004_0000
0x0004_FFFF
5
64K Bytes
0x0005_0000
0x0005_FFFF
6
64K Bytes
0x0006_0000
0x0006_FFFF
7
64K Bytes
0x0007_0000
0x0007_FFFF
0
64K Bytes
0x0008_0000
0x0008_FFFF
1
64K Bytes
0x0009_0000
0x0009_FFFF
2
64K Bytes
0x000A_0000
0x000A_FFFF
3
64K Bytes
0x000B_0000
0x000B_FFFF
4
64K Bytes
0x000C_0000
0x000C_FFFF
5
64K Bytes
0x000D_0000
0x000D_FFFF
6
64K Bytes
0x000E_0000
0x000E_FFFF
7
64K Bytes
0x000F_0000
0x000F_FFFF
MEMORY ARRAYS
(OR BANKS)
BANK0
(512K Bytes)
BANK1
(512K Bytes)
The VF48B device flash contains one 512K-byte memory array (or bank) and one 256K-byte bank, for a total
of 768K-byte of flash, and consists of twelve sectors. These twelve sectors are sized as follows:
SECTOR
NO.
SEGMENT
LOW ADDRESS
HIGH ADDRESS
OTP
2K Bytes
0x0000_0000
0x0000_007FF
0
64K Bytes
0x0000_0000
0x0000_FFFF
1
64K Bytes
0x0001_0000
0x0001_FFFF
2
64K Bytes
0x0002_0000
0x0002_FFFF
3
64K Bytes
0x0003_0000
0x0003_FFFF
4
64K Bytes
0x0004_0000
0x0004_FFFF
5
64K Bytes
0x0005_0000
0x0005_FFFF
6
64K Bytes
0x0006_0000
0x0006_FFFF
7
64K Bytes
0x0007_0000
0x0007_FFFF
0
64K Bytes
0x0008_0000
0x0008_FFFF
1
64K Bytes
0x0009_0000
0x0009_FFFF
2
64K Bytes
0x000A_0000
0x000A_FFFF
3
64K Bytes
0x000B_0000
0x000B_FFFF
MEMORY ARRAYS
(OR BANKS)
BANK0
(512K Bytes)
BANK1
(256K Bytes)
The minimum size for an erase operation is one sector. The maximum size for a program operation is one
16-bit word.
18
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16/32-BIT RISC FLASH MICROCONTROLLERS
SPNS093D – MAY 2004 – REVISED FEBRUARY 2006
flash program and erase (continued)
NOTE
The flash external pump voltage (VCCP) is required for all operations (program, erase, and read).
Execution can occur from one bank while programming/erasing any or all sectors of another bank. However,
execution cannot occur from any sector within a bank that is being programmed or erased.
NOTE
When the OTP sector is enabled, the rest of Flash memory is disabled. The OTP memory can only be
read or programmed from code executed out of RAM.
For more detailed information on flash program and erase operations, see the TMS470R1x F05 Flash Reference Guide (literature number SPNU213).
HET RAM
The VF48x device contains HET RAM. The HET RAM has a 64-instruction capability. The HET RAM is configurable by the SYS module to be addressed within the range of 0x0000_0000 to 0xFFE0_0000. The HET
RAM is addressed through memory select 4.
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19
TMS470R1VF48C/VF48B
16/32-BIT RISC FLASH MICROCONTROLLERS
SPNS093D – MAY 2004 – REVISED FEBRUARY 2006
peripheral selects and base addresses
The VF48x device uses ten of the sixteen peripheral selects to decode the base addresses of the peripherals.
These peripheral selects are fixed and transparent to the user since they are part of the decoding scheme used
by the SYS module.
Control registers for the peripherals, SYS module, and flash begin at the base addresses shown in Table 3.
Table 3. VF48x Peripherals, System Module, and Flash Base Addresses
CONNECTING MODULE
20
ADDRESS RANGE
BASE ADDRESS
ENDING ADDRESS
PERIPHERAL SELECTS
SYSTEM
0xFFFF_FFCC
0xFFFF_FFFF
N/A
RESERVED
0xFFFF_FF70
0xFFFF_FFCB
N/A
DWD
0xFFFF_FF60
0xFFFF_FF6F
N/A
PSA
0xFFFF_FF40
0xFFFF_FF5F
N/A
CIM
0xFFFF_FF20
0xFFFF_FF3F
N/A
RTI
0xFFFF_FF00
0xFFFF_FF1F
N/A
DMA
0xFFFF_FE80
0xFFFF_FEFF
N/A
DEC
0xFFFF_FE00
0xFFFF_FE7F
N/A
RESERVED
0xFFFF_FD80
0xFFFF_FDFF
N/A
MMC
0xFFFF_FD00
0xFFFF_FD7F
N/A
IEM
0xFFFF_FC00
0xFFFF_FCFF
N/A
RESERVED
0xFFFF_FB00
0xFFFF_FBFF
N/A
RESERVED
0xFFFF_FA00
0xFFFF_FAFF
N/A
DMA CMD BUFFER
0xFFFF_F800
0xFFFF_F9FF
N/A
MSM
0xFFFF_F700
0xFFFF_F7FF
N/A
RESERVED
0xFFF8_0000
0xFFFF_F6FF
N/A
RESERVED
0xFFF7_FD00
0xFFF7_FFFF
HET
0xFFF7_FC00
0xFFF7_FCFF
RESERVED
0xFFF7_F900
0xFFF7_FBFF
SPI1
0xFFF7_F800
0xFFF7_F8FF
RESERVED
0xFFF7_F700
0xFFF7_F7FF
SCI3
0xFFF7_F600
0xFFF7_F6FF
SCI2
0XFFF7_F500
0XFFF7_F5FF
SCI1
0xFFF7_F400
0xFFF7_F4FF
RESERVED
0xFFF7_F100
0xFFF7_F3FF
MibADC
0xFFF7_F000
0xFFF7_F0FF
ECP
0xFFF7_EF00
0xFFF7_EFFF
RESERVED
0xFFF7_EE00
0xFFF7_EEFF
EBM
0xFFF7_ED00
0xFFF7_EDFF
GIO
0xFFF7_EC00
0xFFF7_ECFF
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PS[0]
PS[1]
PS[2]
PS[3]
PS[4]
TMS470R1VF48C/VF48B
16/32-BIT RISC FLASH MICROCONTROLLERS
SPNS093D – MAY 2004 – REVISED FEBRUARY 2006
Table 3. VF48x Peripherals, System Module, and Flash Base Addresses (Continued)
CONNECTING MODULE
ADDRESS RANGE
PERIPHERAL SELECTS
BASE ADDRESS
ENDING ADDRESS
0xFFF7_EB00
0xFFF7_EBFF
0xFFF7_EA00
0xFFF7_EAFF
0xFFF7_E900
0xFFF7_E9FF
0xFFF7_E800
0xFFF7_E8FF
0xFFF7_E700
0xFFF7_E7FF
0xFFF7_E600
0xFFF7_E6FF
0xFFF7_E500
0xFFF7_E5FF
0xFFF7_E400
0xFFF7_E4FF
RESERVED
0xFFF7_E100
0xFFF7_E3FF
SCC
0xFFF7_E000
0xFFF7_E0FF
RESERVED
0xFFF7_DD00
0xFFF7_DFFF
SCC RAM
0xFFF7_DC00
0xFFF7_DCFF
I2C4
0xFFF7_DB00
0xFFF7_DBFF
I2C3
0xFFF7_DA00
0xFFF7_DAFF
I2C2
0xFFF7_D900
0xFFF7_D9FF
I2C1
0xFFF7_D800
0xFFF7_D8FF
RESERVED
0xFFF7_D600
0xFFF7_D7FF
I2C5
0xFFF7_D500
0xFFF7_D5FF
SPI2
0xFFF7_D400
0xFFF7_D4FF
RESERVED
0xFFF7_CC00
0xFFF7_D3FF
RESERVED
0xFFF7_C800
0xFFF7_CBFF
PS[13]
RESERVED
0xFFF7_C000
0xFFF7_C7FF
PS[14] - PS[15]
HECC2
HECC1
HECC2 RAM
HECC1 RAM
PS[5]
PS[6]
PS[7]
PS[8]
PS[9]
PS[10]
PS[11] - PS[12]
RESERVED
0xFFF0_0000
0xFFF7_BFFF
N/A
Flash Control Registers
0xFFE8_8000
0xFFE8_BFFF
N/A
RESERVED
0xFFF8_4024
0xFFF8_7FFF
N/A
MPU CONTROL REGISTERS
0xFFE8_4000
0xFFE8_4023
N/A
RESERVED
0xFFF8_0000
0xFFF8_3FFF
N/A
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21
TMS470R1VF48C/VF48B
16/32-BIT RISC FLASH MICROCONTROLLERS
SPNS093D – MAY 2004 – REVISED FEBRUARY 2006
direct-memory access (DMA)
The direct-memory access (DMA) controller transfers data to and from any specified location in the VF48x
memory map (except for restricted memory locations like the system control registers area). The DMA manages
up to 16 channels, and supports data transfer for both on-chip and off-chip memories and peripherals. The
DMA controller is connected to both the CPU and peripheral buses, enabling these data transfers to occur in
parallel with CPU activity and thus maximizing overall system performance.
Although the DMA controller has two possible configurations, for the VF48x device, the DMA controller configuration is 32 control packets and 16 channels.
For the VF48x DMA request hardwired configuration, see Table 4.
Table 4. DMA Request Lines Connections(1)
MODULES
DMA REQUEST INTERRUPT SOURCES
DMA CHANNEL
EBM
Expansion Bus DMA request
EBDMAREQ[0]
DMAREQ[0]
SPI1/I2C4
SPI1 end-receive/I2C4 read
SPI1DMA0/I2C4DMA0
DMAREQ[1]
SPI1/I2C4
SPI1 end-transmit/I2C4 write
SPI1DMA1/I2C4DMA1
DMAREQ[2]
ADC EV/I2C1 read
MibADCDMA0/I2C1DMA0
DMAREQ[3]
MibADC/SCI1/I2C5
ADC G1/SCI1 end-receive/I2C5
read
MibADCDMA1/SCI1DMA0/I2C5DMA0
DMAREQ[4]
MibADC/SCI1/I2C5
ADC G2/SCI1 end-transmit/I2C5
write
MibADCDMA2/SCI1DMA1/I2C5DMA1
DMAREQ[5]
I2C1 write
I2C1DMA1
MibADC/I2C1
I2C1
DMAREQ[6]
SCI3/SPI2
SCI3 end-receive/SPI2 end-receive SCI3DMA0/SPI2DMA0
DMAREQ[7]
SCI3/SPI2
SCI3 end-transmit/SPI2 endtransmit
SCI3DMA01SPI2DMA1
DMAREQ[8]
I2C2
I2C2 read end-receive
I2C2DMA0
DMAREQ[9]
I2C2
I2C2 write end-transmit
I2C2DMA1
DMAREQ[10]
I2C3
I2C3 read
I2C3DMA0
DMAREQ[11]
I2C3
I2C3 write
I2C3DMA1
DMAREQ[12]
SCI2
SCI2 end-receive
SCI2DMA0
DMAREQ[14]
SCI2
SCI2 end-transmit
SCI2DMA1
DMAREQ[15]
RESERVED
DMAREQ[13]
1 For DMA channels with more than one assigned request source, only one of the sources listed can be the DMA request generator in a given
application. The device has software control to ensure that there are no conflicts between requesting modules.
Each channel has two control packets attached to it, allowing the DMA to continuously load RAM and generate
periodic interrupts so that the data can be read by the CPU. The control packets allow for the interrupt enable,
and the channels determine the priority level of the interrupt.
DMA transfers occur in one of two modes:
O
Non-request mode (used when transferring from memory to memory)
O
Request mode (used when transferring from memory to peripheral)
For more detailed functional information on the DMA controller, see the TMS470R1x Direct Memory Access
(DMA) Controller Reference Guide (literature number SPNU194).
22
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TMS470R1VF48C/VF48B
16/32-BIT RISC FLASH MICROCONTROLLERS
SPNS093D – MAY 2004 – REVISED FEBRUARY 2006
interrupt priority (IEM to CIM)
Interrupt requests originating from the VF48x peripheral modules (i.e., SPI1 or SPI2; SCI1 or SCI2; RTI; etc.)
are assigned to channels within the 48-channel interrupt expansion module (IEM) where, via programmable
register mapping, these channels are then mapped to the 32-channel central interrupt manager (CIM) portion
of the SYS module.
Programming multiple interrupt sources in the IEM to the same CIM channel effectively shares the CIM channel
between sources.
The CIM request channels are maskable so that individual channels can be selectively disabled. All interrupt
requests can be programmed in the CIM to be of either type:
O
Fast interrupt request (FIQ)
O
Normal interrupt request (IRQ)
The CIM prioritizes interrupts. The precedences of request channels decrease with ascending channel order
in the CIM (0 [highest] and 31 [lowest] priority). For IEM-to-CIM default mapping, channel priorities, and their
associated modules, see Table 5.
Table 5. Interrupt Priority (IEM and CIM)
MODULES
INTERRUPT SOURCES
DEFAULT CIM
INTERRUPT LEVEL/
CHANNEL
IEM
CHANNEL
SPI1
SPI1 end-transfer/overrun
0
0
RTI
COMP2 interrupt
1
1
RTI
COMP1 interrupt
2
2
RTI
TAP interrupt
3
3
SPI2
SPI2 end-transfer/overrun
4
4
GIO
GIO interrupt A
5
5
RESERVED
HET
I2C1
SCI1/SCI2
SCI1
HET interrupt 1
HECC1
SCC
7
I2C1 interrupt
8
8
9
9
SCI1 receive interrupt
10
10
11
11
I2C2 interrupt
12
12
HECC1 interrupt A
13
13
SCC interrupt A
14
14
RESERVED
MibADC
6
7
SCI1 or SCI2 error interrupt
RESERVED
I2C2
6
MibADC end event conversion
15
15
16
16
SCI2
SCI2 receive interrupt
17
17
DMA
DMA interrupt 0
18
18
I2C3
I2C3 interrupt
19
19
SCI1
SCI1 transmit interrupt
20
20
SW interrupt (SSI)
21
21
22
22
HET interrupt 2
23
23
HECC1 interrupt B
24
24
SCC interrupt B
25
25
System
RESERVED
HET
HECC1
SCC
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23
TMS470R1VF48C/VF48B
16/32-BIT RISC FLASH MICROCONTROLLERS
SPNS093D – MAY 2004 – REVISED FEBRUARY 2006
interrupt priority (IEM to CIM) (continued)
Table 5. Interrupt Priority (IEM and CIM) (Continued)
MODULES
SCI2
MibADC
INTERRUPT SOURCES
DEFAULT CIM
INTERRUPT LEVEL/
CHANNEL
IEM
CHANNEL
SCI2 transmit interrupt
26
26
MibADC end Group 1 conversion
27
27
DMA
DMA Interrupt 1
28
28
GIO
GIO interrupt B
29
29
MibADC
MibADC end Group 2 conversion
30
30
SCI3 error interrupt
31
31
31
32-37
HECC2
HECC2 interrupt A
31
38
HECC2
HECC2 interrupt B
31
39
SCI3
SCI3 receive interrupt
31
40
SCI3
SCI3 transmit interrupt
31
41
I2C4
I2C4 interrupt
31
42
I2C5
I2C5 interrupt
31
43
31
44-47
SCI3
RESERVED
RESERVED
For more detailed functional information on the IEM, see the TMS470R1x Interrupt Expansion Module (IEM)
Reference Guide (literature number SPNU211). For more detailed functional information on the CIM, see the
TMS470R1x System Module Reference Guide (literature number SPNU189).
24
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TMS470R1VF48C/VF48B
16/32-BIT RISC FLASH MICROCONTROLLERS
SPNS093D – MAY 2004 – REVISED FEBRUARY 2006
expansion bus module (EBM)
The expansion bus module (EBM) is a standalone module used to bond out both general-purpose input/output
pins and expansion bus interface pins. This module supports the multiplexing of the GIO functions and the
expansion bus interface functions. The module also supports 8- and 16- bit expansion bus memory interface
mappings as well as mapping of the following expansion bus signals:
O
27-bit address bus (EBADDR[26:0]) for x8, 19-bit address bus (EBADDR[18:0]) for x16
O
8- or 16-bit data bus (EBDATA[7:0] or EBDATA[15:0])
O
2 write strobes (EBWR[1:0])
O
2 memory chip selects (EBCS[6:5])
O
1 output enable (EBOE)
O
1 external hold signal for interfacing to slow memories (EBHOLD)
O
1 DMA request line (EBDMAREQ[0])
Table 6 shows the multiplexing (muxing) of I/O signals with the expansion bus interface signals. The mapping
of these pins varies depending on the memory mode.
Table 6. Expansion Bus Mux Mapping(1)
EXPANSION BUS MODULE PINS(2)
GIO
X8
X16
GIOB[0]
EBDMAREQ[0]
EBDMAREQ[0]
GIOC[0]
EBOE
EBOE
GIOC[2:1]
EBWR[1:0]
EBWR[1:0]
GIOC[4:3]
EBCS[6:5]
EBCS[6:5]
GIOD[5:0]
EBADDR[5:0]
EBADDR[5:0]
GIOE[7:0]
EBDATA[7:0]
EBDATA[7:0]
GIOF[7:0]
EBADDR[13:6]
EBDATA[15:8]
GIOG[7:0]
EBADDR[21:14]
EBADDR[13:6]
GIOH[5]
EBHOLD
EBHOLD
I2C5SDA
EBADDR[26]
EBADDR[18]
I2C5SCL
EBADDR[25]
EBADDR[17]
I2C4SCL
EBADDR[24]
EBADDR[16]
I2C4SDA
EBADDR[23]
EBADDR[15]
GIOH[0]
EBADDR[22]
EBADDR[14]
1 These mappings are controlled by the EBM mux control registers B–H (EBMXCRB–EBMXCRH) and the EBM control register 1 (EBMCR1).
For more detailed information, see theTMS470R1x Expansion Bus Module (EBM) Reference Guide (literature number SPNU222) and the
TMS470R1x General Purpose Input/Output Reference Guide (literature number SPNU192).
2 X8 refers to size of memory in 8-bits; X16 refers to size of memory in 16-bits.
Table 7 lists the names of the expansion bus interface signals and their functions.
Table 7. Expansion Bus Pins
PIN
DESCRIPTION
EBDMAREQ
EBOE
Expansion bus DMA request
Expansion bus pin enable
Expansion bus write strobe. EBWR[1] controls EBDATA[15:8] and
EBWR[0] controls EBDATA[7:0]
Expansion bus chip select
Expansion bus address pin
Expansion bus data pin
Expansion bus hold. An external device may assert this signal to add
wait states to an expansion bus transaction.
EBWR
EBCS
EBADDR
EBDATA
EBHOLD
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25
TMS470R1VF48C/VF48B
16/32-BIT RISC FLASH MICROCONTROLLERS
SPNS093D – MAY 2004 – REVISED FEBRUARY 2006
MibADC
The multi-buffered analog-to-digital converter (MibADC) accepts an analog signal and converts the signal to a
10-bit digital value.
The VF48x MibADC module can function in two modes: compatibility mode, where its programmer’s model is
compatible with the TMS470R1x ADC module and its digital results are stored in digital result registers; or in
buffered mode, where the digital result registers are replaced with three FIFO buffers, one for each conversion
group [event, group1 (G1), and group2 (G2)]. In buffered mode, the MibADC buffers can be serviced by interrupts
or by the DMA.
MibADC event trigger enhancements
The MibADC includes two major enhancements over the event-triggering capability of the TMS470R1x ADC.
O
Both group 1 and the event group can be configured for event-triggered operation, providing up to two
event-triggered groups.
O
The trigger source and polarity can be selected individually for both group 1 and the event group from the
options identified in Table 8.
Table 8. MibADC Event Hookup Configuration
EVENT #
SOURCE SELECT BITS FOR G1 OR EVENT
(G1SRC[1:0] or EVSRC[1:0])
SIGNAL PIN NAME
EVENT1
00
ADEVT
EVENT2
01
HET18
EVENT3
10
RESERVED
EVENT4
11
RESERVED
For group 1, these event-triggered selections are configured via the group 1 source select bits (G1SRC[1:0])
in the AD event source register (ADEVTSRC.[5:4]). For the event group, these event-triggered selections are
configured via the event group source select bits (EVSRC[1:0]) in the AD event source register
(ADEVTSRC.[1:0]).
For more detailed functional information on the MibADC, see the TMS470R1x Multi-Buffered Analog-to-Digital
Converter (MibADC) Reference Guide (literature number SPNU206).
26
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TMS470R1VF48C/VF48B
16/32-BIT RISC FLASH MICROCONTROLLERS
SPNS093D – MAY 2004 – REVISED FEBRUARY 2006
JTAG interface
There are two main test access ports (TAPs) on the VF748C device:
O
TMS470R1x CPU TAP
O
Device TAP for factory test
Some of the JTAG pins are shared among these two TAPs. The hookup is illustrated in Figure 3.
TSM470R1x CPU
TCK
TCK
TRST
TRST
TMS
TMS
TDI
TDI
TDO
TDO_470
Factory TEST
TCK
TRST
TMS2
TMS
TDI
TDO
Figure 3. JTAG Interface
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27
TMS470R1VF48C/VF48B
16/32-BIT RISC FLASH MICROCONTROLLERS
SPNS093D – MAY 2004 – REVISED FEBRUARY 2006
development system support
Texas Instruments provides extensive hardware and software development support tools for the TMS470R1x
family. These support tools include:
O
Code Composer Studio™ Integrated Development Environment (IDE)
–
–
–
O
Optimizing C compiler
–
–
–
–
–
–
–
O
Provides extensive macro capability
Allows high-speed operation
Allows extensive control of the assembly process using assembler directives
Automatically resolves memory references as C and assembly modules are combined
TMS470R1x CPU Simulator
–
–
–
O
Supports high-level language programming
Full implementation of the standard ANSI C language
Powerful optimizer that improves code-execution speed and reduces code size
Extensive run-time support library included
TMS470R1x control registers easily accessible from the C program
Interfaces C functions and assembly functions easily
Establishes comprehensive, easy-to-use tool set for the development of high-performance
microcontroller applications in C/C++
Assembly language tools (assembler and linker)
–
–
–
–
O
Fully integrated suite of software development tools
Includes Compiler/Assembler/Linker, Debugger, and Simulator
Supports Real-Time analysis, data visualization, and open API
Provides capability to simulate CPU operation without emulation hardware
Allows inspection and modifications of memory locations
Allows debugging programs in C or assembly language
XDS emulation communication kits
–
Allows high-speed JTAG communication to the TMS470R1x emulator or target board
For more information on pricing and availability, contact the nearest TI field sales office or authorized distributor.
Code Composer Studio is a trademark of Texas Instruments.
28
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TMS470R1VF48C/VF48B
16/32-BIT RISC FLASH MICROCONTROLLERS
SPNS093D – MAY 2004 – REVISED FEBRUARY 2006
documentation support
Extensive documentation supports all of the TMS470 microcontroller family generation of devices. The types
of documentation available include: data sheets with design specifications; complete user’s guides for all
devices and development support tools; and hardware and software applications. Useful reference documentation includes:
O
O
User’s Guides
–
TMS470R1x 32-Bit RISC Microcontroller Family User’s Guide (literature number SPNU134)
–
TMS470R1x C/C++ Compiler User’s Guide (literature number SPNU151)
–
TMS470R1x Code Generation Tools Getting Started Guide (literature number SPNU117)
–
TMS470R1x C Source Debugger User’s Guide (literature number SPNU124)
–
TMS470R1x Assembly Language Tools User’s Guide (literature number SPNU118)
–
TMS470R1x System Module Reference Guide (literature number SPNU189)
–
TMS470R1x Direct Memory Access (DMA) Controller Reference Guide (literature number SPNU194)
–
TMS470R1x Serial Peripheral Interface (SPI) Reference Guide (literature number SPNU195)
–
TMS470R1x Serial Communication Interface (SCI) Reference Guide (literature number SPNU196)
–
TMS470R1x Controller Area Network (CAN) Reference Guide (literature number SPNU197)
–
TMS470R1x High-End Timer (HET) Reference Guide (literature number SPNU199)
–
TMS470R1x External Clock Prescale (ECP) Reference Guide (literature number SPNU202)
–
TMS470R1x Multi-Buffered Analog-to-Digital Converter (MibADC) Reference Guide
(literature number SPNU206)
–
TMS470R1x F05 Flash Reference Guide (literature number SPNU213)
–
TMS470R1x Frequency-Modulated Phase-Locked Loop (FMPLL) Clock Module Reference Guide
(literature number SPNU221)
–
TMS470R1x Expansion Bus Module (EBM) Reference Guide (literature number SPNU222)
–
TMS470R1x Inter-Integrated Circuit (I2C) Reference Guide (literature number SPNU223)
–
TMS470R1x JTAG Security Module Reference Guide (literature number SPNU245)
–
TMS470R1x Memory Security Module Reference Guide (literature number SPNU246)
Application Reports:
–
Analog Watchdog Resistor, Capacitor and Discharge Interval Selection Constraints
(literature number SPNA005)
–
F05/C05 Power Up Reset and Power Sequencing Requirements (literature number SPNA009)
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29
TMS470R1VF48C/VF48B
16/32-BIT RISC FLASH MICROCONTROLLERS
SPNS093D – MAY 2004 – REVISED FEBRUARY 2006
device numbering conventions
Figure 4 illustrates the numbering and symbol nomenclature for the TMS470R1x family.
TMS 470 R1 V F 48 C PGE A
Prefix: TMS = Standard Prefix for Fully Qualified Devices
Family:
470 = TMS470 RISC-Embedded Microcontroller Family
V = 1.8-V Core Voltage
Program Memory Types:
CPU Type:
Device Type:
Program Memory Size
C
F
L
B
R
=
=
=
=
=
Masked ROM
Flash
ROM-less
System Emulator for Development Tools
RAM
R1 = ARM7TDMI CPU
48 = ’48 Devices Containing the Following Modules:
– FMZPLL Clock
– 64K-Byte Static RAM
– 1K-Byte HET RAM (64 Instructions)
– Digital Watchdog (DWD)
– Interrupt Expansion Module (IEM)
– Memory Security Module (MSM)
– High-End Lite (HET)
– Real-Time Interrupt (RTI)
– 10-Bit, 12-Input Multi-buffered Analog-to-Digital
Converter (MibADC)
– Two Serial Peripheral Interface (SPI) Modules
– Three Serial Communications Interface (SCI) Modules
– Inter-Integrated Circuit (I2C) Module
– High-End Controller Area Network (CAN) [HECC]
– External Clock Prescaler (ECP)
C = 0
– No on-chip program memory
1–5 – 1 to < 128K Bytes
6–B – 128K Bytes to < 1M Bytes
C–F – > 1M Bytes
Operating Free-Air
Temperature Ranges:
A =
T =
Q =
–40°C to 85°C
–40°C to 105°C
–40°C to 125°C
Package: PGE = 144-Pin Plastic Low-Profile Quad Flatpack (LQFP)
Figure 4. TMS470R1x Family Nomenclature
30
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TMS470R1VF48C/VF48B
16/32-BIT RISC FLASH MICROCONTROLLERS
SPNS093D – MAY 2004 – REVISED FEBRUARY 2006
device identification code register
The device identification code register identifies the silicon version, the technology family (TF), a ROM or flash
device, and an assigned device-specific part number (see Table 9). The VF48x device identification code
register value is 0x0A5F.
Table 9. TMS470 Device ID Bit Allocation Register
31
16
Reserved
FFFF_FFF0
15
LEGEND:
For bits 3–15:
For bits 0–2:
11
10
VERSION
TF
R/F
R-K
R-K
R-K
9
3
2
1
0
PART NUMBER
1
1
1
R-K
R-1
R-1
R-1
R = Read only, -K = Value constant after RESET
R = Read only, -1 = Value after RESET
Transmission Request Reset Register (CANTRR) Field Descriptions
Bit
Name
Value
Description
31–16
Reserved
Reads are undefined and writes have no effect.
15–12
VERSION
Silicon version (revision) bits
These bits identify the silicon version of the device.
11
TF
Technology family bit
This bit distinguishes the technology family core power supply:
10
0
3.3 V for F10/C10 devices
1
1.8 V for F05/C05 devices
ROM/flash bit
This bit distinguishes between ROM and flash devices:
R/F
0
Flash device
1
ROM device
9–3
PART NUMBER
Device-specific part number bits
These bits identify the assigned device-specific part number.
The assigned device-specific part number for the VF48x device is 1001011.
2–0
1 Mandatory
High
Bits 2, 1, and 0 are tied high by default.
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TMS470R1VF48C/VF48B
16/32-BIT RISC FLASH MICROCONTROLLERS
SPNS093D – MAY 2004 – REVISED FEBRUARY 2006
device part numbers
Table 10 lists all the available TMS470R1VF48x devices.
Table 10. Device Part Numbers
DEVICE PART
NUMBER
PROGRAM MEMORY
PACKAGE TYPE
TEMPERATURE RANGES
FLASH
EEPROM
144-PIN
LQFP
−40°C TO 85°C
TMS470R1VF48BPGEA
X
X
X
TMS470R1VF48BPGET
X
X
TMS470R1VF48BPGEQ
X
X
TMS470R1VF48CPGEA
X
X
TMS470R1VF48CPGET
X
X
TMS470R1VF48CPGEQ
X
X
32
ROM
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−40°C TO 105°C
−40°C TO 125°C
X
X
X
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X
X
TMS470R1VF48C/VF48B
16/32-BIT RISC FLASH MICROCONTROLLERS
SPNS093D – MAY 2004 – REVISED FEBRUARY 2006
DEVICE ELECTRICAL SPECIFICATIONS AND TIMING PARAMETERS
absolute maximum ratings over operating free-air temperature range, A version
(unless otherwise noted)(1)
Supply voltage ranges: VCC (2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to 2.5 V
Supply voltage ranges: VCCIO , VCCAD , VCCP (flash pump)(2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to 4.1 V
Input voltage range: All 5 V tolerant input pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to 6.0 V
All other input pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to 4.1 V
Input clamp current: All 5 V tolerant pins, PORRST, TRST, TEST and TCK (VI < 0) . . . . . . . . . . . . . . . −20mA
ADIN[0:11] IIK (VI < 0 or VI > VCCAD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±10 mA
All other pins IIK (VI < 0 or VI > VCCIO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA
Operating free-air temperature ranges, TA: A version . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .−40°C to 85°C
T version . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .−40°C to 105°C
Q version . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .−40°C to 125°C
Operating junction temperature range, TJ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .−40°C to 150°C
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .−40°C to 150°C
1 Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only,
and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is
not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
2 All voltage values are with respect to their associated grounds.
device recommended operating conditions(3)
MIN
NOM
MAX
UNIT
SYSCLK = 48MHz (pipeline mode enabled)
1.71
2.05
SYSCLK = 60MHz (pipeline mode enabled)
1.81
2.05
V
Digital logic supply voltage (I/O)
3
3.6
V
VCCAD
ADC supply voltage
3
3.6
V
VCCP
Flash pump supply voltage
3
3.6
V
VSS
Digital logic supply ground
VCC
Digital logic supply voltage (Core)
VCCIO
VSSAD
ADC supply ground
TA
Operating free-air temperature
TJ
0
− 0.1
(3)
V
0.1
V
°C
A version
− 40
85
T version
− 40
105
Q version
− 40
125
°C
− 40
150
°C
Operating junction temperature
3 All voltages are with respect to VSS, except VCCAD, which is with respect to VSSAD.
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TMS470R1VF48C/VF48B
16/32-BIT RISC FLASH MICROCONTROLLERS
SPNS093D – MAY 2004 – REVISED FEBRUARY 2006
electrical characteristics over recommended operating free-air temperature range, A version
(unless otherwise noted)(1)
PARAMETER
Vhys
TEST CONDITIONS
MIN
Low-level input voltage
All inputs
− 0.3
VIH
High-level input voltage
All inputs
2
Vth
Input threshold voltage
AWD only(3)
(2)
1.35
IOL = IOL MAX
VOL
Low-level output voltage(4)
VOH
High-level output voltage(4)
IIC
Input clamp current (I/O pins)(5)
IOH = IOH MIN
IOH = 50 μA
V
0.2
0.8 VCCIO
2
−1
1
IIH Pulldown
VI = VCCIO
5
40
–40
–5
VI = VCCIO
−1
1
No pullup or pulldown
−1
1
VI = VSS
−1
1
VI = VCCIO
1
5
VI = 5 V
5
25
25
50
VI = 5.5 V
CLKOUT, AWD,
TDI, TDO, TMS,
TMS2
mA
μA
μA
8
VOL = VOL MAX
RST
All other 3.3 V
V
V
VCCIO − 0.2
−2
All other pins
4
I/O(6)
2
mA
4
5 V tolerant
CLKOUT, TDI,
TDO, TMS, TMS2
High-level output
current
1.8
VI < VSSIO − 0.3 or VI > VCCIO + 0.3
Input current (5 V tolerant input pins)
IOH
V
V
VI = VSS
IIH Pullup
Low-level output
current
0.8
VCCIO + 0.3
IIL Pulldown
VI = VSS
UNIT
V
0.2 VCCIO
IOL = 50 μA
Input current (3.3 V input pins) IIL Pullup
IOL
MAX
0.15
Input hysteresis
VIL
II
TYP(7)
RST
−8
VOH = VOH MIN
−4
All other 3.3 V I/O
−2
5 V tolerant
−4
(6)
mA
1 Source currents (out of the device) are negative while sink currents (into the device) are positive.
2 This does not apply to the PORRST pin. For PORRST exceptions, see the RST and PORRST timings section on page 41.
3 These values help to determine the external RC network circuit. For more details, see the TMS470R1x System Module Reference Guide
(literature number SPNU189).
4 VOL and VOH are linear with respect to the amount of load current (IOL/IOH) applied.
5 Parameter does not apply to input-only or output-only pins.
6 Some of the 2 mA buffers on this device are zero-dominant buffers, as indicated by a -z in the Output Current column of the Terminal Functions
table. If two of these buffers are shorted together and one is outputting a low level and the other is outputting a high level, the resulting value
will always be low.
7 The typical values indicated in this table are the expected values during operation under normal operating conditions: nominal VCC, VCCIO,or
VCCAD, room temperature.
8 For flash banks/pumps in sleep mode.
9 For reduced power consumption in low power mode, CANSRX and CANSTX should be driven output LOW.
10 I/O pins configured as inputs or outputs with no load. All pulldown inputs ≤ 0.2 V. All pullup inputs ≥ VCCIO − 0.2 V.
34
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TMS470R1VF48C/VF48B
16/32-BIT RISC FLASH MICROCONTROLLERS
SPNS093D – MAY 2004 – REVISED FEBRUARY 2006
electrical characteristics over recommended operating free-air temperature range, A version (unless otherwise noted)(1) (continued)
MAX
UNIT
125
mA
SYSCLK = 60 MHz, VCC = 2.05 V
125
mA
VCC Digital supply current (standby mode)(8)(9)
OSCIN = 5 MHz, VCC = 2.05 V
1.30
mA
VCC Digital supply current (halt mode)(8)(9)
VCC = 2.05 V
700
μA
VCCIO Digital supply current (operating mode)
No DC load, VCCIO = 3.6 V(10)
15
mA
VCCIO Digital supply current (standby mode)(9)
No DC load, VCCIO = 3.6 V(10)
10
μA
VCCIO Digital supply current (halt mode)(9)
No DC load, VCCIO = 3.6 V(10)
10
μA
VCCAD supply current (operating mode)
All frequencies, VCCAD = 3.6 V
15
mA
VCCAD supply current (standby mode)
No DC load, VCCAD = 3.6 V
10
μA
VCCAD supply current (halt mode)
VCCAD = 3.6 V
10
μA
SYSCLK = 48 MHz, VCCP = 3.6 V
read operation
45
mA
SYSCLK = 60 MHz, VCCP = 3.6 V
read operation
55
TEST CONDITIONS
VCC Digital supply current (operating mode)
ICC
ICCIO
ICCAD
ICCP
TYP(7)
SYSCLK = 48 MHz, VCC = 2.05 V
PARAMETER
VCCP pump supply current
MIN
VCCP = 3.6 V program and erase
70
mA
VCCP = 3.6 V standby mode operation(8)
10
μA
VCCP = 3.6 V halt mode operation(8)
10
μA
CI
Input capacitance
2
pF
CO
Output capacitance
3
pF
1 Source currents (out of the device) are negative while sink currents (into the device) are positive.
2 This does not apply to the PORRST pin. For PORRST exceptions, see the RST and PORRST timings section on page 41.
3 These values help to determine the external RC network circuit. For more details, see the TMS470R1x System Module Reference Guide
(literature number SPNU189).
4 VOL and VOH are linear with respect to the amount of load current (IOL/IOH) applied.
5 Parameter does not apply to input-only or output-only pins.
6 Some of the 2 mA buffers on this device are zero-dominant buffers, as indicated by a -z in the Output Current column of the Terminal Functions
table. If two of these buffers are shorted together and one is outputting a low level and the other is outputting a high level, the resulting value
will always be low.
7 The typical values indicated in this table are the expected values during operation under normal operating conditions: nominal VCC, VCCIO,or
VCCAD, room temperature.
8 For flash banks/pumps in sleep mode.
9 For reduced power consumption in low power mode, CANSRX and CANSTX should be driven output LOW.
10 I/O pins configured as inputs or outputs with no load. All pulldown inputs ≤ 0.2 V. All pullup inputs ≥ VCCIO − 0.2 V.
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TMS470R1VF48C/VF48B
16/32-BIT RISC FLASH MICROCONTROLLERS
SPNS093D – MAY 2004 – REVISED FEBRUARY 2006
PARAMETER MEASUREMENT INFORMATION
IOL
Tester Pin
Electronics
50 Ω
VLOAD
Output
Under
Test
CL
IOH
Where: IOL=IOL MAX for the respective pin(A)
IOH=IOH MIN for the respective pin(A)
VLOAD=1.5 V
CL=150-pF typical load-circuit capacitance(B)
A. For these values, see the "electrical characteristics over recommended operating free-air temperature range" table.
B. All timing parameters measured using an external load capacitance of 150 pF unless otherwise noted.
Figure 5. Test Load Circuit
36
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TMS470R1VF48C/VF48B
16/32-BIT RISC FLASH MICROCONTROLLERS
SPNS093D – MAY 2004 – REVISED FEBRUARY 2006
timing parameter symbology
Timing parameter symbols have been created in accordance with JEDEC Standard 100. To shorten the symbols,
some of the pin names and other related terminology have been abbreviated as follows:
CM
CO
ER
ICLK
M
OSC, OSCI
OSCO
P
R
R0
R1
Compaction, CMPCT
CLKOUT
Erase
Interface clock
Master mode
OSCIN
OSCOUT
Program, PROG
Ready
Read margin 0, RDMRGN0
Read margin 1, RDMRGN1
RD
RST
RX
S
SCC
SIMO
SOMI
SPC
SYS
TX
Read
Reset, RST
SCInRX
Slave mode
SCInCLK
SPInSIMO
SPInSOMI
SPInCLK
System clock
SCInTX
r
su
t
v
w
rise time
setup time
transition time
valid time
pulse duration (width)
Lowercase subscripts and their meanings are:
a
c
d
f
h
access time
cycle time (period)
delay time
fall time
hold time
The following additional letters are used with these meanings:
H
High
X
L
V
Low
Valid
Z
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High impedance
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37
TMS470R1VF48C/VF48B
16/32-BIT RISC FLASH MICROCONTROLLERS
SPNS093D – MAY 2004 – REVISED FEBRUARY 2006
external reference resonator/crystal oscillator clock option
The oscillator is enabled by connecting the appropriate fundamental 4–10 MHz resonator/crystal and load
capacitors across the external OSCIN and OSCOUT pins as shown in Figure 6a. The oscillator is a singlestage inverter held in bias by an integrated bias resistor. This resistor is disabled during leakage test measurement and HALT mode. TI strongly encourages each customer to submit samples of the device to the
resonator/crystal vendors for validation. The vendors are equipped to determine what load capacitors will
best tune their resonator/crystal to the microcontroller device for optimum start-up and operation over temperature/voltage extremes.
An external oscillator source can be used by connecting a 1.8 V clock signal to the OSCIN pin and leaving the
OSCOUT pin unconnected (open) as shown in Figure 6b.
OSCIN
C1(A)
OSCOUT
Crystal
OSCIN
C2(A)
External
Clock Signal
(toggling 0–1.8 V)
(a)
(b)
A. The values of C1 and C2 should be provided by the resonator/crystal vendor.
Figure 6. Crystal/Clock Connection
38
OSCOUT
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TMS470R1VF48C/VF48B
16/32-BIT RISC FLASH MICROCONTROLLERS
SPNS093D – MAY 2004 – REVISED FEBRUARY 2006
FMZPLL and clock specifications
timing requirements for FMZPLL circuits enabled or disabled
MIN
f(OSC)
Input clock frequency
tc(OSC)
Cycle time, OSCIN
tw(OSCIL)
tw(OSCIH)
f(OSCRST)
TYP
4
MAX
UNIT
10
MHz
100
ns
Pulse duration, OSCIN low
15
ns
Pulse duration, OSCIN high
15
ns
OSC FAIL frequency
(1)
53
kHz
1 Causes a device reset (specifically a clock reset) by setting the RST OSC FAIL (GLBCTRL.15) and the OSC FAIL flag (GLBSTAT.1) bits equal
to 1. For more detailed information on these bits and device resets, see the TMS470R1x System Module Reference Guide (literature number
SPNU189).
switching characteristics over recommended operating conditions for clocks(1)(2)(3)
TEST CONDITIONS(4)
PARAMETER
f(SYS)
System clock frequency(5)
f(CONFIG)
System clock frequency - flash config mode
f(ICLK)
Interface clock frequency
f(ECLK)
External clock output frequency for ECP module
tc(SYS)
Cycle time, system clock
tc(CONFIG)
Cycle time, system clock - flash config mode
tc(ICLK)
Cycle time, interface clock
tc(ECLK)
Cycle time, ECP module external clock output
MIN
MAX
UNIT
Pipeline mode enabled
60(6)
MHz
Pipeline mode disabled
24
MHz
24
MHz
Pipeline mode enabled
30
MHz
Pipeline mode disabled
24
MHz
Pipeline mode enabled
30
MHz
Pipeline mode disabled
24
MHz
Pipeline mode enabled
16.7
ns
Pipeline mode disabled
41.6
ns
41.6
ns
Pipeline mode enabled
33.3
ns
Pipeline mode disabled
41.6
ns
Pipeline mode enabled
33.3
ns
Pipeline mode disabled
41.6
ns
1 f(SYS) = M × f(OSC) / R, where M = {8}, R = {1,2,3,4,5,6,7,8} when PLLDIS = 0. R is the system-clock divider determined by the CLKDIVPRE
[2:0] bits in the global control register (GLBCTRL.[2:0]) and M is the PLL multiplier determined by the MULT4 bit also in the GLBCTRL register
(GLBCTRL.3).
f(SYS) = f(OSC) / R, where R = {1,2,3,4,5,6,7,8} when PLLDIS = 1.
f(ICLK) = f(SYS) / X, where X = {1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16}. X is the interface clock divider ratio determined by the PCR0.[4:1] bits
in the SYS module.
2 f(ECLK) = f(ICLK) / N, where N = {1 to 256}. N is the ECP prescale value defined by the ECPCTRL.[7:0] register bits in the ECP module.
3 Only ZPLL mode is available. FM mode must not be turned on.
4 Pipeline mode enabled or disabled is determined by the ENPIPE bit (FMREGOPT.0).
5 Flash Vread must be set to 5V to achieve maximum system clock frequency.
6 Operating VCC range for this system clock frequency is 1.81 to 2.05V.
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TMS470R1VF48C/VF48B
16/32-BIT RISC FLASH MICROCONTROLLERS
SPNS093D – MAY 2004 – REVISED FEBRUARY 2006
FMZPLL and clock specifications (continued)
switching characteristics over recommended operating conditions for external clocks
(see Figure 7 and Figure 8)(1)(2)(3)
NO.
PARAMETER
TEST CONDITIONS
SYSCLK or MCLK
1
tw(COL)
Pulse duration, CLKOUT low
ICLK: X is even or 1(5).
SYSCLK or MCLK
tw(COH)
0.5tc(ICLK) – tf
1.(5)
Pulse duration, CLKOUT high ICLK: X is even or 1.(5)
4
tw(EOH)
Pulse duration, ECLK low
0.5tc(ICLK) – tr
1.(5)
0.5tc(ECLK) – tf
1
2
3
4
5
0.5tc(ECLK) – tf
N is odd and X is odd and not 1.
0.5tc(ECLK) + 0.5tc(SYS) – tf
N is even and X is even or odd.
0.5tc(ECLK) – tr
N is odd and X is even.
0.5tc(ECLK) – tr
N is odd and X is odd and not 1.
ns
ns
0.5tc(ECLK) – 0.5tc(SYS) – tr
X = {1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16}. X is the interface clock divider ratio determined by the PCR0.[4:1] bits in the SYS module.
N = {1 to 256}. N is the ECP prescale value defined by the ECPCTRL.[7:0] register bits in the ECP module.
CLKOUT/ECLK pulse durations (low/high) are a function of the OSCIN pulse durations when PLLDIS is active.
Clock source bits are selected as either SYSCLK (CLKCNTL.[6:5] = 11 binary) or MCLK (CLKCNTL.[6:5] = 10 binary).
Clock source bits are selected as ICLK (CLKCNTL.[6:5] = 01 binary).
2
CLKOUT
1
Figure 7. CLKOUT Timing Diagram
4
ECLK
3
Figure 8. ECLK Timing Diagram
40
ns
0.5tc(ICLK) – 0.5tc(SYS) – tr
N is odd and X is even.
Pulse duration, ECLK high
ns
0.5tc(SYS) – tr
N is even and X is even or odd.
tw(EOL)
UNIT
0.5tc(ICLK) + 0.5tc(SYS) – tf
(4)
ICLK: X is odd and not
3
MAX
0.5tc(SYS) – tf
ICLK: X is odd and not
2
MIN
(4)
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TMS470R1VF48C/VF48B
16/32-BIT RISC FLASH MICROCONTROLLERS
SPNS093D – MAY 2004 – REVISED FEBRUARY 2006
RST and PORRST timings
timing requirements for PORRST(1) (see Figure 9)
MIN
NO.
MAX
UNIT
VCCPORL
VCC low supply level when PORRST must be active during power up
VCCPORH
VCC high supply level when PORRST must remain active during power up and become
active during power down
VCCIOPORL
VCCIO low supply level when PORRST must be active during power up
VCCIOPORH
VCCIO high supply level when PORRST must remain active during power up and become
active during power down
VIL
Low-level input voltage after VCCIO > VCCIOPORH
VIL(PORRST)
Low-level input voltage of PORRST before VCCIO > VCCIOPORL
tsu(PORRST)r
Setup time, PORRST active before VCCIO > VCCIOPORL during power up
0
ms
5
tsu(VCCIO)r
Setup time, VCCIO > VCCIOPORL before VCC > VCCPORL
0
ms
6
th(PORRST)r
Hold time, PORRST active after VCC > VCCPORH
1
ms
7
tsu(PORRST)f
Setup time, PORRST active before VCC ≤ VCCPORH during power down
8
μs
8
th(PORRST)rio
Hold time, PORRST active after VCCIO > VCCIOPORH
1
ms
3
0.6
1.5
V
V
1.1
2.75
V
V
0.2 VCCIO
V
0.5
V
9
th(PORRST)d
Hold time, PORRST active after VCC < VCCPORL
0
ms
10
tsu(PORRST)fio
Setup time, PORRST active before VCCIO ≤ VCCIOPORH during power down
0
ns
11
tsu(VCCIO)f
Setup time, VCC < VCCPORL before VCCIO < VCCIOPORL
0
ns
VCCP/VCCIO
VCCIOPORH
VCCIOPORH
VCCIO
8
VCC
VCC
VCCPORH
6
VCCIOPORL
VCC
VCCP/VCCIO
PORRST
11
VCCPORH
7
6
10
7
VCCPORL
VCCPORL
VCCIOPORL
5
3
VIL(PORRST)
9
VIL
VIL
VIL
VIL(PORRST)
VIL
Figure 9. PORRST Timing Diagram
switching characteristics over recommended operating conditions for RST(1)
PARAMETER
tv(RST)
tfsu
MIN
4112tc(OSC)
Valid time, RST active after PORRST inactive
8tc(SYS)
Valid time, RST active (all others)
Flash start up time, from RST inactive to fetch of first instruction from flash (flash pump
stabilization time)
836tc(OSC)
MAX
UNIT
ns
ns
1 Specified values do NOT include rise/fall times. For rise and fall timings, see the "switching characteristics for output timings versus load
capacitance" table.
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16/32-BIT RISC FLASH MICROCONTROLLERS
SPNS093D – MAY 2004 – REVISED FEBRUARY 2006
JTAG scan interface timing (JTAG clock specification 10-MHz and 50-pF load on TDO output)
MIN
NO.
UNIT
1
Cycle time, JTAG low and high period
50
ns
2
tsu(TDI/TMS - TCKr)
Setup time, TDI, TMS before TCK rise (TCKr)
15
ns
3
th(TCKr -TDI/TMS)
Hold time, TDI, TMS after TCKr
15
ns
4
th(TCKf -TDO)
Hold time, TDO after TCKf
10
ns
5
td(TCKf -TDO)
Delay time, TDO valid after TCK fall (TCKf)
45
TCK
1
1
TMS
TDI
2
3
TDO
4
5
Figure 10. JTAG Scan Timings
42
MAX
tc(JTAG)
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ns
TMS470R1VF48C/VF48B
16/32-BIT RISC FLASH MICROCONTROLLERS
SPNS093D – MAY 2004 – REVISED FEBRUARY 2006
output timings
switching characteristics for output timings versus load capacitance (CL) (see Figure 11)
MIN
PARAMETER
tr
tf
tr
tr
tf
tr
tf
Rise time, AWD, CLKOUT, TDI, TDO, TMS, TMS2
Fall time, AWD, CLKOUT, TDI, TDO, TMS, TMS2
Rise time, RST
0.5
2.5
CL= 50 pF
1.5
5.0
CL = 100 pF
3.0
9.0
CL = 150 pF
4.5
12.5
CL = 15 pF
0.5
2.5
CL= 50 pF
1.5
5.0
CL = 100 pF
3.0
9.0
CL = 150 pF
4.5
12.5
CL = 15 pF
2.5
8
CL = 50 pF
5
14
CL = 100 pF
9
23
CL = 150 pF
13
32
CL = 15 pF
3
10
CL = 50 pF
3.5
12
7
21
CL = 100 pF
Rise time,4mA, 5 V tolerant pins
Fall time, 4mA, 5 V tolerant pins
Rise time, all other output pins
Fall time, all other output pins
CL = 150 pF
9
28
CL = 400 pF
18
40
CL = 15 pF
2
8
CL = 50 pF
2.5
9
CL = 100 pF
8
25
CL = 150 pF
11
35
CL = 400 pF
20
45
CL = 15 pF
2.5
10
CL = 50 pF
6.0
25
CL = 100 pF
12
45
CL = 150 pF
18
65
CL = 15 pF
3
10
CL = 50 pF
8.5
25
CL = 100 pF
16
45
CL = 150 pF
23
65
tr
ns
ns
ns
ns
ns
ns
ns
tf
80%
Output
MAX UNIT
CL = 15 pF
20%
VCC
80%
20%
0
Figure 11. CMOS-Level Outputs
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16/32-BIT RISC FLASH MICROCONTROLLERS
SPNS093D – MAY 2004 – REVISED FEBRUARY 2006
input timings
timing requirements for input timings(1) (see Figure 12)
MIN
tpw
MAX
tc(ICLK) + 10
Input minimum pulse width
UNIT
ns
1 tc(ICLK) = interface clock cycle time = 1/f(ICLK)
tpw
Input
80%
VCC
80%
20%
20%
0
Figure 12. CMOS-Level Inputs
flash timings
timing requirements for program flash(1)
tprog(16-bit)
Half word (16-bit) programming time
MIN
TYP
MAX
UNIT
4
16
200
μs
32
(2)
tprog(Total)
1M-byte programming time
8
terase(sector)
Sector erase time
7
twec
Write/erase cycles at TA = 125°C
tfp(RST)
Flash pump settling time from RST to SLEEP
167tc(SYS)
ns
tfp(SLEEP)
Initial flash pump settling time from SLEEP to STANDBY
167tc(SYS)
ns
tfp(STANDBY)
Initial flash pump settling time from STANDBY to ACTIVE
84tc(SYS)
ns
100
1000
1 For more detailed information on the flash core sectors, see the "flash program and erase" section of this data sheet.
2 The 1M-byte programming time includes overhead of state machine.
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s
s
cycles
TMS470R1VF48C/VF48B
16/32-BIT RISC FLASH MICROCONTROLLERS
SPNS093D – MAY 2004 – REVISED FEBRUARY 2006
SPIn master mode timing parameters
SPIn master mode external timing parameters (CLOCK PHASE = 0, SPInCLK = output, SPInSIMO =
output, and SPInSOMI = input)(1)(2)(3) (see Figure 13)
MIN
MAX
100
256tc(ICLK)
Pulse duration, SPInCLK high (clock polarity = 0)
0.5tc(SPC)M – tr
0.5tc(SPC)M + 5
Pulse duration, SPInCLK low (clock polarity = 1)
0.5tc(SPC)M – tf
0.5tc(SPC)M + 5
Pulse duration, SPInCLK low (clock polarity = 0)
0.5tc(SPC)M – tf
0.5tc(SPC)M + 5
Pulse duration, SPInCLK high (clock polarity = 1)
0.5tc(SPC)M – tr
0.5tc(SPC)M + 5
NO.
1
2(5)
3(5)
4
Cycle time, SPInCLK
tw(SPCH)M
tw(SPCL)M
tw(SPCL)M
tw(SPCH)M
td(SPCH-SIMO)M
Delay time, SPInCLK high to SPInSIMO valid
(clock polarity = 0)
10
td(SPCL-SIMO)M
Delay time, SPInCLK low to SPInSIMO valid
(clock polarity = 1)
10
tv(SPCL-SIMO)M
Valid time, SPInSIMO data valid after SPInCLK low (clock polarity = 0)
tc(SPC)M – 5 – tf
tv(SPCH-SIMO)M
Valid time, SPInSIMO data valid after SPInCLK high (clock polarity = 1)
tc(SPC)M – 5 – tr
tsu(SOMI-SPCL)M
Setup time, SPInSOMI before SPInCLK low
(clock polarity = 0)
6
tsu(SOMI-SPCH)M
Setup time, SPInSOMI before SPInCLK high
(clock polarity = 1)
6
tv(SPCL-SOMI)M
Valid time, SPInSOMI data valid after SPInCLK low (clock polarity = 0)
4
tv(SPCH-SOMI)M
Valid time, SPInSOMI data valid after SPInCLK high (clock polarity = 1)
4
(5)
5(5)
6(5)
7(5)
(4)
tc(SPC)M
UNIT
ns
1
2
3
4
The MASTER bit (SPInCTRL2.3) is set and the CLOCK PHASE bit (SPInCTRL2.0) is cleared.
tc(ICLK) = interface clock cycle time = 1/f(ICLK)
For rise and fall timings, see the "switching characteristics for output timings versus load capacitance" table.
When the SPI is in master mode, the following must be true:
For PS values from 1 to 255: tc(SPC)M ≥ (PS +1)tc(ICLK) ≥ 100 ns, where PS is the prescale value set in the SPInCTL1.[12:5] register bits.
For PS values of 0:
tc(SPC)M = 2tc(ICLK) ≥ 100 ns.
5 The active edge of the SPInCLK signal referenced is controlled by the CLOCK POLARITY bit (SPInCTRL2.1).
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16/32-BIT RISC FLASH MICROCONTROLLERS
SPNS093D – MAY 2004 – REVISED FEBRUARY 2006
SPIn master mode timing parameters (continued)
1
SPInCLK
(clock polarity = 0)
2
3
SPInCLK
(clock polarity = 1)
4
5
SPInSIMO
Master Out Data Is Valid
6
7
SPInSOMI
Master In Data
Must Be Valid
Figure 13. SPIn Master Mode External Timing (CLOCK PHASE = 0)
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16/32-BIT RISC FLASH MICROCONTROLLERS
SPNS093D – MAY 2004 – REVISED FEBRUARY 2006
SPIn master mode timing parameters (continued)
SPIn master mode external timing parameters (CLOCK PHASE = 1, SPInCLK = output, SPInSIMO =
output, and SPInSOMI = input)(1)(2)(3) (see Figure 14)
MIN
NO.
1
2(5)
3(5)
4(5)
5(5)
6(5)
7(5)
(4)
MAX
tc(SPC)M
Cycle time, SPInCLK
100
256tc(ICLK)
tw(SPCH)M
Pulse duration, SPInCLK high (clock polarity = 0)
0.5tc(SPC)M – tr
0.5tc(SPC)M + 5
tw(SPCL)M
Pulse duration, SPInCLK low (clock polarity = 1)
0.5tc(SPC)M – tf
0.5tc(SPC)M + 5
tw(SPCL)M
Pulse duration, SPInCLK low (clock polarity = 0)
0.5tc(SPC)M – tf
0.5tc(SPC)M + 5
tw(SPCH)M
Pulse duration, SPInCLK high (clock polarity = 1)
0.5tc(SPC)M – tr
0.5tc(SPC)M + 5
tv(SIMO-SPCH)M
Valid time, SPInCLK high after SPInSIMO data valid
(clock polarity = 0)
0.5tc(SPC)M – 10
tv(SIMO-SPCL)M
Valid time, SPInCLK low after SPInSIMO data valid (clock polarity = 1)
0.5tc(SPC)M – 10
tv(SPCH-SIMO)M
Valid time, SPInSIMO data valid after SPInCLK high (clock polarity = 0)
0.5tc(SPC)M – 5 – tr
tv(SPCL-SIMO)M
Valid time, SPInSIMO data valid after SPInCLK low (clock polarity = 1)
0.5tc(SPC)M – 5 – tf
tsu(SOMI-SPCH)M Setup time, SPInSOMI before SPInCLK high (clock polarity = 0)
6
tsu(SOMI-SPCL)M
Setup time, SPInSOMI before SPInCLK low (clock polarity = 1)
6
tv(SPCH-SOMI)M
Valid time, SPInSOMI data valid after SPInCLK high (clock polarity = 0)
4
tv(SPCL-SOMI)M
Valid time, SPInSOMI data valid after SPInCLK low (clock polarity = 1)
4
UNIT
ns
1
2
3
4
The MASTER bit (SPInCTRL2.3) is set and the CLOCK PHASE bit (SPInCTRL2.0) is set.
tc(ICLK) = interface clock cycle time = 1/f(ICLK)
For rise and fall timings, see the "switching characteristics for output timings versus load capacitance" table.
When the SPI is in master mode, the following must be true:
For PS values from 1 to 255:
tc(SPC)M ≥ (PS +1)tc(ICLK) ≥ 100 ns, where PS is the prescale value set in the SPInCTL1.[12:5] register bits.
For PS values of 0:
tc(SPC)M = 2tc(ICLK) ≥ 100 ns.
5 The active edge of the SPInCLK signal referenced is controlled by the CLOCK POLARITY bit (SPInCTRL2.1).
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TMS470R1VF48C/VF48B
16/32-BIT RISC FLASH MICROCONTROLLERS
SPNS093D – MAY 2004 – REVISED FEBRUARY 2006
SPIn master mode timing parameters (continued)
1
SPInCLK
(clock polarity = 0)
2
3
SPInCLK
(clock polarity = 1)
4
5
SPInSIMO
Master Out Data Is Valid
Data Valid
6
7
SPInSOMI
Master In Data
Must Be Valid
Figure 14. SPIn Master Mode External Timing (CLOCK PHASE = 1)
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16/32-BIT RISC FLASH MICROCONTROLLERS
SPNS093D – MAY 2004 – REVISED FEBRUARY 2006
SPIn slave mode timing parameters
SPIn slave mode external timing parameters (CLOCK PHASE = 0, SPInCLK = input, SPInSIMO =
input, and SPInSOMI = output)(1)(2)(3)(4) (see Figure 15)
NO
1
2(6)
3(6)
4
5
(5)
MIN
MAX
100
256tc(ICLK)
tc(SPC)S
Cycle time, SPInCLK
tw(SPCH)S
Pulse duration, SPInCLK high (clock polarity = 0)
0.5tc(SPC)S – 0.25tc(ICLK)
0.5tc(SPC)S + 0.25tc(ICLK)
tw(SPCL)S
Pulse duration, SPInCLK low (clock polarity = 1)
0.5tc(SPC)S – 0.25tc(ICLK)
0.5tc(SPC)S + 0.25tc(ICLK)
tw(SPCL)S
Pulse duration, SPInCLK low (clock polarity = 0)
0.5tc(SPC)S – 0.25tc(ICLK)
0.5tc(SPC)S + 0.25tc(ICLK)
tw(SPCH)S
Pulse duration, SPInCLK high (clock polarity = 1)
0.5tc(SPC)S – 0.25tc(ICLK)
0.5tc(SPC)S + 0.25tc(ICLK)
td(SPCH-SOMI)S
Delay time, SPInCLK high to SPInSOMI valid (clock
polarity = 0)
6 + tr
td(SPCL-SOMI)S
Delay time, SPInCLK low to SPInSOMI valid (clock
polarity = 1)
6 + tf
tv(SPCH-SOMI)S
Valid time, SPInSOMI data valid after SPInCLK high
(clock polarity = 0)
tc(SPC)S – 6 – tr
tv(SPCL-SOMI)S
Valid time, SPInSOMI data valid after SPInCLK low (clock
polarity = 1)
tc(SPC)S – 6 – tf
tsu(SIMO-SPCL)S
Setup time, SPInSIMO before SPInCLK low (clock
polarity = 0)
6
tsu(SIMO-SPCH)S
Setup time, SPInSIMO before SPInCLK high (clock
polarity = 1)
6
tv(SPCL-SIMO)S
Valid time, SPInSIMO data valid after SPInCLK low (clock
polarity = 0)
6
tv(SPCH-SIMO)S
Valid time, SPInSIMO data valid after SPInCLK high
(clock polarity = 1)
6
(6)
(6)
6(6)
7(6)
UNIT
ns
1
2
3
4
5
The MASTER bit (SPInCTRL2.3) is cleared and the CLOCK PHASE bit (SPInCTRL2.0) is cleared.
If the SPI is in slave mode, the following must be true: tc(SPC)S ≥ (PS + 1) tc(ICLK), where PS = prescale value set in SPInCTL1.[12:5].
For rise and fall timings, see the "switching characteristics for output timings versus load capacitance" table.
tc(ICLK) = interface clock cycle time = 1/f(ICLK)
When the SPIn is in slave mode, the following must be true:
For PS values from 1 to 255:
tc(SPC)S ≥ (PS +1)tc(ICLK) ≥ 100 ns, where PS is the prescale value set in the SPInCTL1.[12:5] register bits.
For PS values of 0:
tc(SPC)S = 2tc(ICLK) ≥ 100 ns.
6The active edge of the SPInCLK signal referenced is controlled by the CLOCK POLARITY bit (SPInCTRL2.1).
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16/32-BIT RISC FLASH MICROCONTROLLERS
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SPIn slave mode timing parameters (continued)
1
SPInCLK
(clock polarity = 0)
2
3
SPInCLK
(clock polarity = 1)
4
5
SPInSOMI
SPISOMI Data Is Valid
6
7
SPInSIMO
SPISIMO Data
Must Be Valid
Figure 15. SPIn Slave Mode External Timing (CLOCK PHASE = 0)
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SPIn slave mode timing parameters (continued)
SPIn slave mode external timing parameters (CLOCK PHASE = 1, SPInCLK = input, SPInSIMO =
input, and SPInSOMI = output)(1)(2)(3)(4) (see Figure 16)
MIN
NO
1
2(6)
3(6)
MAX
100
256tc(ICLK)
0.5tc(SPC)S –0.25tc(ICLK)
0.5tc(SPC)S + 0.25tc(ICLK)
Pulse duration, SPInCLK low (clock polarity = 1)
0.5tc(SPC)S –0.25tc(ICLK)
0.5tc(SPC)S + 0.25tc(ICLK)
Pulse duration, SPInCLK low (clock polarity = 0)
0.5tc(SPC)S –0.25tc(ICLK)
0.5tc(SPC)S + 0.25tc(ICLK)
tw(SPCH)S
Pulse duration, SPInCLK high (clock polarity = 1)
0.5tc(SPC)S –0.25tc(ICLK)
0.5tc(SPC)S + 0.25tc(ICLK)
tv(SOMI-SPCH)S
Valid time, SPInCLK high after SPInSOMI data valid
(clock polarity = 0)
0.5tc(SPC)S – 6 – tr
tv(SOMI-SPCL)S
Valid time, SPInCLK low after SPInSOMI data valid (clock
polarity = 1)
0.5tc(SPC)S – 6 – tf
tv(SPCH-SOMI)S
Valid time, SPInSOMI data valid after SPInCLK high
(clock polarity = 0)
0.5tc(SPC)S – 6 – tr
tv(SPCL-SOMI)S
Valid time, SPInSOMI data valid after SPInCLK low (clock
polarity = 1)
0.5tc(SPC)S – 6 – tf
tsu(SIMO-SPCH)S
Setup time, SPInSIMO before SPInCLK high (clock
polarity = 0)
6
tsu(SIMO-SPCL)S
Setup time, SPInSIMO before SPInCLK low (clock
polarity = 1)
6
tv(SPCH-SIMO)S
Valid time, SPInSIMO data valid after SPInCLK high
(clock polarity = 0)
6
tv(SPCL-SIMO)S
Valid time, SPInSIMO data valid after SPInCLK low (clock
polarity = 1)
6
tc(SPC)S
Cycle time,
tw(SPCH)S
Pulse duration, SPInCLK high (clock polarity = 0)
tw(SPCL)S
tw(SPCL)S
4(6)
5
SPInCLK(5)
(6)
6(6)
7(6)
UNIT
ns
1
2
3
4
5
The MASTER bit (SPInCTRL2.3) is cleared and the CLOCK PHASE bit (SPInCTRL2.0) is set.
If the SPI is in slave mode, the following must be true: tc(SPC)S ≥ (PS + 1) tc(ICLK), where PS = prescale value set in SPInCTL1.[12:5].
For rise and fall timings, see the "switching characteristics for output timings versus load capacitance" table.
tc(ICLK) = interface clock cycle time = 1/f(ICLK)
When the SPIn is in slave mode, the following must be true:
For PS values from 1 to 255:
tc(SPC)S ≥ (PS +1)tc(ICLK) ≥ 100 ns, where PS is the prescale value set in the SPInCTL1.[12:5] register bits.
For PS values of 0:
tc(SPC)S = 2tc(ICLK) ≥ 100 ns.
6 The active edge of the SPInCLK signal referenced is controlled by the CLOCK POLARITY bit (SPInCTRL2.1).
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16/32-BIT RISC FLASH MICROCONTROLLERS
SPNS093D – MAY 2004 – REVISED FEBRUARY 2006
SPIn slave mode timing parameters (continued)
1
SPInCLK
(clock polarity = 0)
2
3
SPInCLK
(clock polarity = 1)
4
5
SPInSOMI
SPISOMI Data Is Valid
Data Valid
6
7
SPInSIMO
SPISIMO Data Must
Be Valid
Figure 16. SPIn Slave Mode External Timing (CLOCK PHASE = 1)
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16/32-BIT RISC FLASH MICROCONTROLLERS
SPNS093D – MAY 2004 – REVISED FEBRUARY 2006
SCIn isosynchronous mode timings — internal clock
timing requirements for internal clock SCIn isosynchronous mode(1)(2)(3) (see Figure 17)
(BAUD + 1)
IS EVEN OR BAUD = 0
NO.
(BAUD + 1)
IS ODD AND BAUD ≠ 0
UNIT
MIN
MAX
MIN
MAX
2tc(ICLK)
224tc(ICLK)
3tc(ICLK)
(224 –1) tc(ICLK)
1
tc(SCC)
Cycle time, SCInCLK
2
tw(SCCL)
Pulse duration,
SCInCLK low
0.5tc(SCC) – tf
0.5tc(SCC) + 5
0.5tc(SCC) +0.5tc(ICLK) – tf 0.5tc(SCC) +0.5tc(ICLK)
ns
3
tw(SCCH)
Pulse duration,
SCInCLK high
0.5tc(SCC) – tr
0.5tc(SCC) + 5
0.5tc(SCC) –0.5tc(ICLK) – tr 0.5tc(SCC) –0.5tc(ICLK)
ns
4
td(SCCH-TXV)
Delay time, SCInCLK
high to SCInTX valid
5
tv(TX)
Valid time, SCInTX data
after SCInCLK low
6
tsu(RX-SCCL)
Setup time, SCInRX
before SCInCLK low
7
tv(SCCL-RX)
Valid time, SCInRX data
- tc(ICLK) + tf + 20
after SCInCLK low
10
10
ns
ns
tc(SCC) – 10
tc(SCC) – 10
ns
tc(ICLK) + tf + 20
tc(ICLK) + tf + 20
ns
- tc(ICLK) + tf + 20
ns
1 BAUD = 24-bit concatenated value formed by the SCI[H,M,L]BAUD registers.
2 tc(ICLK) = interface clock cycle time = 1/f(ICLK)
3 For rise and fall timings, see the "switching characteristics for output timings versus load capacitance" table.
1
3
2
SCICLK
5
4
SCITX
Data Valid
6
7
SCIRX
NOTE:
Data Valid
Data transmission/reception characteristics for isosynchronous mode with internal clocking are similar to the asynchronous
mode. Data transmission occurs on the SCICLK rising edge, and data reception on the SCICLK falling edge.
Figure 17. SCIn Isosynchronous Mode Timing Diagram for Internal Clock
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TMS470R1VF48C/VF48B
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SPNS093D – MAY 2004 – REVISED FEBRUARY 2006
SCIn isosynchronous mode timings — external clock
timing requirements for external clock SCIn isosynchronous mode(1)(2) (see Figure 18)
MIN
NO.
Cycle time, SCInCLK(3)
1
tc(SCC)
2
tw(SCCH)
3
tw(SCCL)
4
td(SCCH-TXV)
Delay time, SCInCLK high to SCInTX valid
5
tv(TX)
Valid time, SCInTX data after SCInCLK low
6
tsu(RX-SCCL)
Setup time, SCInRX before SCInCLK low
7
tv(SCCL-RX)
Valid time, SCInRX data after SCInCLK low
MAX
8tc(ICLK)
ns
Pulse duration, SCInCLK high
0.5tc(SCC) – 0.25tc(ICLK)
0.5tc(SCC) + 0.25tc(ICLK)
ns
Pulse duration, SCInCLK low
0.5tc(SCC) – 0.25tc(ICLK)
0.5tc(SCC) + 0.25tc(ICLK)
ns
2tc(ICLK) + 12 + tr
2tc(SCC)–10
0
1
2
3
SCICLK
5
4
SCITX
Data Valid
6
7
SCIRX
Data Valid
Data transmission/reception characteristics for isosynchronous mode with external clocking are similar to the asynchronous
mode. Data transmission occurs on the SCICLK rising edge, and data reception on the SCICLK falling edge.
Figure 18. SCIn Isosynchronous Mode Timing Diagram for External Clock
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ns
ns
ns
2tc(ICLK) + 10
1 tc(ICLK) = interface clock cycle time = 1/f(ICLK)
2 For rise and fall timings, see the "switching characteristics for output timings versus load capacitance" table.
3 When driving an external SCInCLK, the following must be true: tc(SCC) ≥ 8tc(ICLK).
NOTE:
UNIT
ns
TMS470R1VF48C/VF48B
16/32-BIT RISC FLASH MICROCONTROLLERS
SPNS093D – MAY 2004 – REVISED FEBRUARY 2006
I2C timing
Table 11 assumes testing over recommended operating conditions.
Table 11. I2C Signals (SDA and SCL) Switching Characteristics(1)
STANDARD
MODE
PARAMETER
MIN
MAX
150
FAST MODE
MIN
MAX
75
150
UNIT
tc(I2CCLK)
Cycle time, I2C module clock
75
tc(SCL)
Cycle time, SCL
10
2.5
μs
tsu(SCLH-SDAL)
Setup time, SCL high before SDA low (for a repeated START condition)
4.7
0.6
μs
th(SCLL-SDAL)
Hold time, SCL low after SDA low (for a repeated START condition)
4
0.6
μs
tw(SCLL)
Pulse duration, SCL low
4.7
1.3
μs
tw(SCLH)
Pulse duration, SCL high
4
0.6
μs
tsu(SDA-SCLH)
Setup time, SDA valid before SCL high
250
100
th(SDA-SCLL)
Hold time, SDA valid after SCL low
tw(SDAH)
Pulse duration, SDA high between STOP and START conditions
For I2C bus devices
tsu(SCLH-SDAH) Setup time, SCL high before SDA high (for STOP condition)
tw(SP)
Cb
0 3.45(2)
4.7
1.3
4.0
0.6
0
Pulse duration, spike (must be suppressed)
(3)
0
400
Capacitive load for each bus line
ns
ns
0.9
μs
μs
μs
50
ns
400
pF
1 The I2C pins SDA and SCL do not feature fail-safe I/O buffers. These pins could potentially draw current when the device is powered down.
2 The maximum th(SDA-SCLL) for I2C bus devices needs only be met if the device does not stretch the low period (tw(SCLL)) of the SCL signal.
3 Cb = The total capacitance of one bus line in pF.
SDA
tsu(SDA-SCLH)
tw(SDAH)
tw(SCLL)
tr(SCL)
tw(SP)
tsu(SCLH-SDAH)
tw(SCLH)
SCL
tc(SCL)
th(SCLL-SDAL)
Stop
tf(SCL)
th(SDA-SCLL)
Start
th(SCLL-SDAL)
tsu(SCLH-SDAL)
Repeated
Start
Stop
NOTE:. A device must internally provide a hold time of at least 300 ns for the SDA signal (referred to the VIHmin of the SCL signal) to
bridge the undefined region of the falling edge of SCL.
NOTE:. The maximum th(SDA-SCLL) needs only be met if the device does not stretch the LOW period (tw(SCLL)) of the SCL signal.
NOTE:. A fast-mode I2C-bus device can be used in a standard-mode I2C-bus system, but the requirement tsu(SDA-SCLH) ≥ 250 ns
must then be met. This will automatically be the case if the device does not stretch the LOW period of the SCL signal. If such a
device does stretch the LOW period of the SCL signal, it must output the next data bit to the SDA line tr max + tsu(SDA-SCLH).
NOTE:. Cb = total capacitance of one bus line in pF. If mixed with fast-mode devices, faster fall-times are allowed.
Figure 19. I2C Timings
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55
TMS470R1VF48C/VF48B
16/32-BIT RISC FLASH MICROCONTROLLERS
SPNS093D – MAY 2004 – REVISED FEBRUARY 2006
standard CAN controller (SCC) mode timings
dynamic characteristics for the CANSTX and CANSRX pins
MIN
PARAMETER
td(CANSTX)
Delay time, transmit shift register to CANSTX pin(1)
td(CANSRX)
Delay time, CANSRX pin to receive shift register
MAX
UNIT
15
ns
5
ns
1 These values do not include the rise/fall times of the output buffer.
expansion bus timing parameters, –40°C ≤ TJ ≤ 150°C, 3.0 V ≤ VCC ≤ 3.6 V
(see figure 20 and figure 21)
NO.
MIN
PARAMETER
MAX UNIT
1
tc(CO)
Cycle time, CLKOUT
2
td(COH-EBADV)
Delay Time, CLKOUT high to EBADDR valid
21.4
ns
3
th(COH-EBADIV)
Hold Time, EBADDR invalid after CLKOUT high
12.4
ns
4
td(COH-EBOE)
Delay Time, CLKOUT high to EBOE fall
11.4
ns
5
th(COH-EBOEH)
Hold Time, EBOE rise after CLKOUT high
11.4
ns
6
td(COL-EBWR)
Delay Time, CLKOUT low to write strobe (EBWR) low
11.3
ns
7
th(COL-EBWRH)
Hold Time, EBWR high after CLKOUT low
11.6
ns
8
tsu(EBRDATV-COH)
Setup time, EBDATA valid before CLKOUT high (READ)(1)
Hold time, EBDATA invalid after CLKOUT high (READ)
20.8
9
th(COH-EBRDATIV)
10
td(COL-EBWDATV)
Delay time, CLKOUT low to EBDATA valid
11
th(COL-EBWDATIV)
Hold time, EBDATA invalid after CLKOUT low (WRITE)
ns
15.2
(WRITE)(2)
ns
(– 14.7)
ns
16.1
ns
14.7
ns
SECONDARY TIMES
12
td(COH-EBCS0)
Delay, CLKOUT high to EBCS0 fall
13.6
ns
13
th(COH-EBCS0H)
Hold, EBCS0 rise after CLKOUT high
13.2
ns
14
tsu(COH-EBHOLDL)
15
tsu(COH-EBHOLDH)
Setup time, EBHOLD low to CLKOUT
high(1)
Setup time, EBHOLD high to CLKOUT
high(1)
1 Setup time is the minimum time under worst case conditions. Data with less setup time will not work.
2 Valid after CLKOUT goes low for write cycles.
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10.9
ns
10.5
ns
TMS470R1VF48C/VF48B
16/32-BIT RISC FLASH MICROCONTROLLERS
SPNS093D – MAY 2004 – REVISED FEBRUARY 2006
expansion bus module timing
1
CLKOUT
3
2
Valid
EBADDR
9
8
Valid
EBDATA
4
5
EBOE
12
13
EBCS0
15
14
EBHOLD
1 Hold State
Figure 20. Expansion Memory Signal Timing—Reads
1
CLKOUT
2
3
Valid
EBADDR
11
10
Valid
EBDATA
6
7
EBWR
12
12
EBCS0
14
15
EBHOLD
1 Hold State
Figure 21. Expansion Memory Signal Timing —Writes
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TMS470R1VF48C/VF48B
16/32-BIT RISC FLASH MICROCONTROLLERS
SPNS093D – MAY 2004 – REVISED FEBRUARY 2006
high-end timer (HET) timings
minimum PWM output pulse width:
This is equal to one high resolution clock period (HRP). The HRP is defined by the 6-bit high resolution prescale
factor (hr), which is user defined, giving prescale factors of 1 to 64, with a linear increment of codes.
Therefore, the minimum PWM output pulse width = HRP(min) = hr(min)/SYSCLK = 1/SYSCLK
For example, for a SYSCLK of 30 MHz, the minimum PWM output pulse width = 1/30 = 33.33ns
minimum input pulses we can capture:
The input pulse width must be greater or equal to the low resolution clock period (LRP), i.e., the HET loop (the
HET program must fit within the LRP). The LRP is defined by the 3-bit loop-resolution prescale factor (lr), which
is user defined, with a power of 2 increment of codes. That is, the value of lr can be 1, 2, 4, 8, 16, or 32.
Therefore, the minimum input pulse width = LRP(min) = hr(min) * lr(min)/SYSCLK = 1 * 1/SYSCLK
For example, with a SYSCLK of 30 MHz, the minimum input pulse width = 1 * 1/30 = 33.33 ns
NOTE
Once the input pulse width is greater than LRP, the resolution of the measurement is still HRP. (That is,
the captured value gives the number of HRP clocks inside the pulse.)
Abbreviations:
hr = HET high resolution divide rate = 1, 2, 3,...63, 64
lr = HET low resolution divide rate = 1, 2, 4, 8, 16, 32
High resolution clock period = HRP = hr/SYSCLK
Loop resolution clock period = LRP = hr*lr/SYSCLK
58
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TMS470R1VF48C/VF48B
16/32-BIT RISC FLASH MICROCONTROLLERS
SPNS093D – MAY 2004 – REVISED FEBRUARY 2006
multi-buffered A-to-D converter (MibADC)
The multi-buffered A-to-D converter (MibADC) has a separate power bus for its analog circuitry that enhances
the A-to-D performance by preventing digital switching noise on the logic circuitry, which could be present on
VSS and VCC, from coupling into the A-to-D analog stage. All A-to-D specifications are given with respect to
ADREFLO unless otherwise noted.
Resolution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 bits (1024 values)
Monotonic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Assured
Output conversion code . . . . . . . . . . . . . . . . . . . . . . . 00h to 3FFh [00 for VAI ≤ADREFLO; 3FF for VAI ≥ ADREFHI]
MibADC recommended operating conditions(1)
MIN
MAX
UNIT
ADREFHI
A-to-D high -voltage reference source
VSSAD
VCCAD
V
ADREFLO
A-to-D low-voltage reference source
VSSAD
VCCAD
V
VAI
Analog input voltage
VSSAD − 0.3
VCCAD + 0.3
V
current(2)
Analog input clamp
(VAI < VSSAD – 0.3 or VAI > VCCAD + 0.3)
IAIC
−2
2
mA
1 For VCCAD and VSSAD recommended operating conditions, see the "device recommended operating conditions" table.
2 Input currents into any ADC input channel outside the specified limits could affect conversion results of other channels.
operating characteristics over full ranges of recommended operating conditions(1)(2)
PARAMETER
Ri
DESCRIPTION/CONDITIONS
Analog input resistance
MIN
See Figure 22.
Conversion
Ci
Analog input capacitance
See Figure 22.
IAIL
Analog input leakage current
See Figure 22.
IADREFHI
ADREFHI input current
ADREFHI = 3.6 V, ADREFLO = VSSAD
CR
Conversion range over which specified
accuracy is maintained
ADREFHI − ADREFLO
EDNL
Differential nonlinearity error
Difference between the actual step width and the
ideal value. See Figure 23.
EINL
ETOT
Sampling
–1
3
TYP
MAX
250
500
Ω
10
pF
UNIT
30
pF
1
μA
5
mA
3.6
V
±1.5
LSB
Integral nonlinearity error
Maximum deviation from the best straight line through
the MibADC. MibADC transfer characteristics,
excluding the quantization error.
See Figure 24.
±2
LSB
Total error/Absolute accuracy
Maximum value of the difference between an analog
value and the ideal midstep value.
See Figure 25.
±2
LSB
1 VCCAD = ADREFHI
2 1 LSB = (ADREFHI – ADREFLO)/210 for the MibADC
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SPNS093D – MAY 2004 – REVISED FEBRUARY 2006
multi-buffered A-to-D converter (MibADC) (continued)
External
Rs
MibADC
Input Pin
Ri
Sample Switch
Parasitic
Capacitance
Vsrc
Sample
Capacitor
Rleak
Ci
Figure 22. MibADC Input Equivalent Circuit
multi-buffer ADC timing requirements
MIN
NOM
MAX
UNIT
μs
tc(ADCLK)
Cycle time, MibADC clock
td(SH)
Delay time, sample and hold time
1
μs
td(C)
Delay time, conversion time
0.55
μs
td(SHC)(1)
Delay time, total sample/hold and conversion time
1.55
μs
0.05
1 This is the minimum sample/hold and conversion time that can be achieved. These parameters are dependent on many factors; for more details,
see the TMS470R1x Multi-Buffered Analog-to-Digital Converter (MibADC) Reference Guide (literature number SPNU206).
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16/32-BIT RISC FLASH MICROCONTROLLERS
SPNS093D – MAY 2004 – REVISED FEBRUARY 2006
multi-buffered A-to-D converter (MibADC) (continued)
The differential nonlinearity error shown in Figure 23 (sometimes referred to as differential linearity) is the
difference between an actual step width and the ideal value of 1 LSB.
0 ... 110
Digital Output Code
0 ... 101
0 ...
0.
.. 100
0 ...
0.
.. 011
Differential
Linearity Error (1/2 LSB)
1 LSB
0 ...
0.
.. 010
0 ...
0.
.. 001
Differential Linearity
Error (–1/2 LSB)
1 LSB
0 ...
0.
.. 000
0
1
2
3
4
5
Analog Input Value (LSB)
NOTE:.1 LSB = (ADREFHI – ADREFLO)/
Figure 23. Differential Nonlinearity (DNL)
The integral nonlinearity error shown in Figure 24 (sometimes referred to as linearity error) is the deviation of
the values on the actual transfer function from a straight line.
0 ... 111
Digital Output Code
0 ... 110
Ideal
Transition
0 ... 101
Actual
Transition
0 ... 100
At Transition
011/100
(– 1/2 LSB)
0 ... 011
0 ... 010
End-Point Lin. Error
0 ... 001
At Transition
001/010 (– 1/4 LSB)
0 ... 000
0
1
2
3
4
5
6
7
Analog Input Value (LSB)
NOTE:.1 LSB = (ADREFHI – ADREFLO)/
Figure 24. Integral Nonlinearity (INL) Error
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TMS470R1VF48C/VF48B
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multi-buffer A-to-D converter (MibADC) (continued)
The absolute accuracy or total error of an MibADC as shown in Figure 25 is the maximum value of the difference
between an analog value and the ideal midstep value.
0 ... 111
Digital Output Code
0 ... 110
0 ... 101
0 ... 100
Total Error
At Step 0 ... 101
(–1 1/4 LSB)
0 ... 011
0 ... 010
Total Error
At Step
0 ... 001 (1/2 LSB)
0 ... 001
0 ... 000
0
1
2
3
4
5
6
7
Analog Input Value (LSB)
NOTE:.1 LSB = (ADREFHI – ADREFLO)/
Figure 25. Absolute Accuracy (Total) Error
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TMS470R1VF48C/VF48B
16/32-BIT RISC FLASH MICROCONTROLLERS
SPNS093D – MAY 2004 – REVISED FEBRUARY 2006
MECHANICAL DATA
PGE (S-PQFP-G144)
PLASTIC QUAD FLATPACK
108
73
109
72
0,27
0,17
0,08 M
0,50
144
0,13 NOM
37
1
36
Gage Plane
17,50 TYP
20,20 SQ
19,80
22,20
SQ
21,80
0,25
0,05 MIN
0°-7°
0,75
0,45
1,45
1,35
Seating Plane
0,08
1,60 MAX
4040147/C 11
NOTE:. All linear dimensions are in millimeters.
NOTE:. This drawing is subject to change without notice.
NOTE:. Falls within JEDEC MS-026.
Thermal Resistance Characteristics
PARAMETER
°C/W
RΘJA
43
RΘJC
5
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TMS470R1VF48C/VF48B
16/32-BIT RISC FLASH MICROCONTROLLER
SPNS093D – MAY 2004 – REVISED FEBRUARY 2006
List of Figures
TMS470R1VF48C/TMS470R1VF48B 144-Pin PGE Package (TOP VIEW)
Functional Block Diagram (VF48C)
Functional Block Diagram (VF48B)
Figure 1. TMS470R1VF48C Memory Map
Figure 2. TMS470R1VF48B Memory Map
Figure 3. JTAG Interface
Figure 4. TMS470R1x Family Nomenclature
Figure 5. Test Load Circuit
Figure 6. Crystal/Clock Connection
Figure 7. CLKOUT Timing Diagram
Figure 8. ECLK Timing Diagram
Figure 9. PORRST Timing Diagram
Figure 10. JTAG Scan Timings
Figure 11. CMOS-Level Outputs
Figure 12. CMOS-Level Inputs
Figure 13. SPIn Master Mode External Timing (CLOCK PHASE = 0)
Figure 14. SPIn Master Mode External Timing (CLOCK PHASE = 1)
Figure 15. SPIn Slave Mode External Timing (CLOCK PHASE = 0)
Figure 16. SPIn Slave Mode External Timing (CLOCK PHASE = 1)
Figure 17. SCIn Isosynchronous Mode Timing Diagram for Internal Clock
Figure 18. SCIn Isosynchronous Mode Timing Diagram for External Clock
Figure 19. I2C Timings
Figure 20. Expansion Memory Signal Timing—Reads
Figure 21. Expansion Memory Signal Timing —Writes
Figure 22. MibADC Input Equivalent Circuit
Figure 23. Differential Nonlinearity (DNL)
Figure 24. Integral Nonlinearity (INL) Error
Figure 25. Absolute Accuracy (Total) Error
Mechanical Data
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TMS470R1VF48C/VF48B
16/32-BIT RISC FLASH MICROCONTROLLER
SPNS093D – MAY 2004 – REVISED FEBRUARY 2006
List of Tables
Table 1.
Table 2.
Table 3.
Table 4.
Table 5.
Table 6.
Table 7.
Table 8.
Table 9.
Table 10.
Table 11.
Device Characteristics
Memory Selection Assignment
VF48x Peripherals, System Module, and Flash Base Addresses
DMA Request Lines Connections
Interrupt Priority (IEM and CIM)
Expansion Bus Mux Mapping
Expansion Bus Pins
MibADC Event Hookup Configuration
TMS470 Device ID Bit Allocation Register
Device Part Numbers
I2C Signals (SDA and SCL) Switching Characteristics
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TMS470R1VF48C/VF48B
16/32-BIT RISC FLASH MICROCONTROLLER
REVISION HISTORY
REVISION HISTORY
REV
D
DATE
2/06
NOTES
Updates:
Page 16, memory size (x16) for memory selects 5 and 6 updated.
Page 35, operating ICC current at 48MHz updated to 125mA.
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66
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