E2L0043-17-Y1 ¡ Semiconductor MSM548128BL ¡ Semiconductor This version: Jan. 1998 MSM548128BL Previous version: Dec. 1996 131,072-Word ¥ 8-Bit High-Speed PSRAM DESCRIPTION The MSM548128BL is a 1-Mbit, high-speed and low power CMOS Pseudo Static RAM organized as 131,072-word ¥ 8-bit. The MSM548128BL is fabricated using silicon gate N well CMOS process. This process, coupled with single-transistor memory storage cells, permits maximum circuit density, minimum chip size, and high speed. MSM548128BL has Self-refresh mode in addition to Address-refresh mode and Auto-refresh mode. In Self-refresh mode the internal refresh timer and address counter refresh the dynamic memory cells automatically. This series allows low power consumption when using standby mode with Self-refresh. The MSM548128BL also features a static RAM-like write function that writes the data into the memory cell at the rising edge of WE. The MSM548128BL is pin compatible with CMOS static RAM and 256K pseudo static RAM. FEATURES • Large capacity • Fast access time • Low power • Refresh free • Pin compatible • Logic compatible • Single power supply • Refresh • Package compatible • Package options: 32-pin 600 mil plastic DIP 32-pin 525 mil plastic SOP : : : : : : : : : 1-Mbit (131,072-word ¥ 8 bits) 70 ns max. 200 µA max. (standby with Self-refresh) Self refresh SRAM, 256K PSRAM SRAM WE pin, no address multiplex 5 V ±10% 512 cycle/8 ms auto-address refresh SRAM standard package (DIP32-P-600-2.54) (Product : MSM548128BL-xxRS) (SOP32-P-525-1.27-K) (Product : MSM548128BL-xxGS-K) xx indicates speed rank. PRODUCT FAMILY Access Time (Max.) Package MSM548128BL-70RS 70 ns MSM548128BL-80RS 80 ns 600 mil 32-pin Plastic DIP MSM548128BL-70GS-K 70 ns MSM548128BL-80GS-K 80 ns Family 525 mil 32-pin Plastic SOP 1/12 ¡ Semiconductor MSM548128BL , PIN CONFIGURATION (TOP VIEW) RFSH 1 32 VCC A16 2 31 A15 A14 3 30 CS A12 4 29 WE A7 5 28 A13 A6 6 27 A8 A5 7 26 A9 A4 8 25 A11 A3 9 24 OE A2 10 23 A10 A1 11 22 CE A0 12 RFSH 1 A16 2 32 VCC 31 A15 A14 3 A12 4 30 CS 29 WE A7 5 A6 6 28 A13 27 A8 A5 7 A4 8 26 A9 25 A11 A3 9 A2 10 24 OE 23 A10 21 I/O7 A1 11 A0 12 22 CE 21 I/O7 I/O0 13 20 I/O6 I/O1 14 19 I/O5 I/O0 13 I/O1 14 20 I/O6 19 I/O5 I/O2 15 18 I/O4 I/O2 15 VSS 16 18 I/O4 17 I/O3 VSS 16 17 I/O3 32-Pin Plastic SOP 32-Pin Plastic DIP Pin Name A0 - A16 I/O0 - I/O7 RFSH Function Address Input Data Input/Output Refresh Input CE Chip Enable Input OE Output Enable Input WE Write Enable Input CS Chip Select Input VCC Power Voltage (5 V) VSS Ground (0 V) 2/12 ¡ Semiconductor MSM548128BL BLOCK DIAGRAM A0 Address Latch Control Row Decoder Memory Matrix (512 ¥ 256) ¥ 8 A8 I/O0 Column I/O Input Data Control I/O7 Column Decoder Address Latch Control A9 RFSH A16 Refresh Control CE CS Timing Pulse Generator OE WE Read/Write Control 3/12 ¡ Semiconductor MSM548128BL FUNCTION TABLE CE CS (CE Low) RFSH OE WE I/O Pin Mode L H X L H Low-Z Read L H X X L High-Z Write L H X H H High-Z — L L X X X High-Z CS Standby H X L X X High-Z Refresh H X H X X High-Z Standby L : Low Level Input H : High Level Input X : Don’t Care ELECTRICAL CHARACTERISTICS Absolute Maximum Ratings Parameter Symbol Rating Voltage on Any Pin from VSS *1 VT –1.0 to 7.0 V Power Dissipation 1.0 W Operating Temperature PD Topr 0 to 70 °C Storage Temperature Tstg –55 to 125 °C Storage Temperature (biased) Tbias –10 to 85 °C Short Circuit Output Current IOS 50 mA *1 Note: Unit To VSS 1. Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to the conditions as detailed in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Recommended Operating Conditions Parameter Power Supply Voltage Input Voltage (Ta = 0°C to 70°C) Symbol Min. Typ. Max. Unit VCC 4.5 5.0 5.5 V VSS 0 0 0 V VIH 2.4 — 6.0 V VIL –0.5 — 0.8 V 4/12 ¡ Semiconductor MSM548128BL DC Characteristics (VCC = 5 V ±10%, VSS = 0 V, Ta = 0°C to 70°C) Symbol Min. Typ. Max. Unit ICC1 — 60 85 mA II/O = Open, tcyc = min. ISB1 — 1 2 mA CE = VIH, RFSH = VIH, VIN ≥ 0 V ISB2 — 100 200 mA ICC2 — 1 2 mA ICC3 — 100 200 mA ILI –10 — 10 mA VCC = 5.5 V, VIN = VSS to VCC Output Leakage Current ILO –10 — 10 mA OE = VIH, VI/O = VSS to VCC Output Low Level VOL — — 0.4 V IOL = 2.1 mA Output High Level VOH 2.4 — — V IOH = –1 mA Parameter Operating Current Condition Standby Current CE ≥ VCC – 0.2 V, RFSH ≥ VCC – 0.2 V, VIN ≥ 0 V CE = VIH, RFSH = VIL, VIN ≥ 0 V Self Refresh Current Input Leakage Current CE ≥ VCC – 0.2 V, VIN ≥ 0 V, RFSH £ 0.2 V Capacitance Parameter Symbol Condition Min. Typ. Max. Unit Input Capacitance CIN VIN = 0 V — — 8 pF I/O Pin Capacitance CI/O VI/O = 0 V — — 10 pF Note: This parameter is periodically sampled and is not 100% tested. 5/12 ¡ Semiconductor AC Characteristics Measurement condition: MSM548128BL Input pulse level ........................... VIH = 2.4 V, VIL = 0.4 V Output reference level .................. VOH = 2.0 V, VOL = 0.8 V Rising and falling time ................. 5 ns Output load .................................... 1 TTL + 100 pF Input timing reference level ........ High = 2.2 V, Low = 0.8 V (VCC = 5 V ±10%, Ta = 0°C to 70°C) MSM548128BL-70 Parameter Symbol MSM548128BL-80 Min. Max. Min. Max. Unit Note tRC 120 — 130 — ns tRWC 170 — 190 — ns CE Access Time tCEA — 70 — 80 ns OE Access Time tOEA — 30 — 30 ns Chip Disable to Output in High-Z tCHZ — 30 — 30 ns CE to Output in Low-Z tCLZ 25 — 25 — ns OE Disable to Output in High-Z tOHZ — 20 — 25 ns OE Output in Low-Z tOLZ 0 — 0 — ns CE Pulse Width tCE 70n 10m 80n 10m s CE Precharge Time tP 40 — 40 — ns Random Read Write Cycle Time Random Read Modify Write Cycle Time 6 6 Address Set-up Time tAS 0 — 0 — ns Address Hold Time tAH 25 — 30 — ns Read Command Set-up Time tRCS 0 — 0 — ns Read Command Hold Time tRCH 0 — 0 — ns RFSH Command Hold Time tRHC 15 — 15 — ns RFSH Delay Time (Standby Mode) tRCD — 5 — 5 ns CS Set-up Time tCSS 0 — 0 — ns CS Hold Time tCSH 25 — 30 — ns Write Command Pulse Width tWP 25 — 30 — ns Chip Enable Time tCW 70 — 80 — ns Input Data Set-up Time tDW 25 — 25 — ns Input Data Hold Time tDH 0 — 0 — ns Output Active from End of Write tOW 5 — 5 — ns Write Enable to Output in High-Z tWHZ — 20 — 25 ns 6 tT 3 50 3 50 ns 11 RFSH Delay Time from CE tRFD 40 — 40 — ns RFSH Precharge Time tFP 30 — 30 — ns RFSH Pulse Width (Auto-refresh) tFAP 30n 8m 30n 8m s Auto-refresh Cycle Time tFC 120 — 130 — ns RFSH Pulse Width (Self-refresh) tFAS 8 — 8 — ms CE Delay Time from RFSH in Self-refresh Mode tRFS 150 — 160 — ns CE Delay Time from RFSH in Auto-refresh Mode tRFA 0 — 0 — ns Refresh Period (512 cycle/8 ms) tREF — 8 — 8 ms Transition Time 6/12 ¡ Semiconductor Notes: MSM548128BL 1. Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. 2. All voltages are referenced to ground. 3. ICC1 depends on output loading. Specified values are obtained with the output open. 4. An initial pause of 100 µs is required after power-up followed by more than 8 initial cycles before proper device operation is achieved. 5. AC measurements assume tT = 5 ns. 6. tCHZ, tWHZ and tOHZ define the time at which the output achieves the open circuit condition and is not referenced to output voltage levels. 7. In write cycles, the input data is latched at the earlier rising point of either CE or WE. Write operation is achieved when both CE and WE are low. 8. The I/O state remains at high impedance after CE goes low if the transition occurs at the same time as or after the falling edge of WE. 9. Use WE or OE or both signals to disable the output before input data is applied during a write cycle when the input is not the same. 10. Data input must be set to floating state before I/O becomes low impedance by WE or OE or both. 11. VIH (Min.) and VIL (Max.) are input timing reference levels for measurement. The transition time is measured between VIL and VIH. 12. 512-cycle refresh must be applied within 15 µs after the end of self refreshing to satisfy 512 cycles/8 ms. 7/12 ¡ Semiconductor MSM548128BL ,,,, , , ,,, TIMING WAVEFORM Read Cycle tRC tCE CE tCSS CS tP tCSH tAS tAH Address A0 - A16 tRCS tRCH WE tCEA OE tRHC tOEA tRCD RFSH tOLZ tOHZ tCLZ DOUT tCHZ Valid Data-out "H" or "L" Write Cycle 1 (OE High) tRC tCE CE tCSS CS tAS tP tCSH tAH Address A0 - A16 tCW tWP WE OE tRHC tRCD RFSH tDW DIN tWHZ tCLZ tOHZ tDH Valid Data-in tOLZ tCHZ tOW DOUT "H" or "L" 8/12 ,,,, , ,,,, , ¡ Semiconductor MSM548128BL Write Cycle 2 (OE Low) tRC tCE CE tCSS CS tAS tP tCSH tAH Address A0 - A16 tCW tWP WE OE tRHC RFSH tRCD tDW DIN Valid Data-in tWHZ tCLZ tDH DOUT "H" or "L" Read Modify Write Cycle tRWC tP CE tCSS CS tAS tCSH tAH Address A0 - A16 tRCH tRCS tWP WE OE tRHC tOHZ tRCD RFSH tOEA DIN tOLZ tDW Valid Data-in tWHZ tCLZ DOUT tDH tCHZ tOW Valid Data-out "H" or "L" 9/12 ¡ Semiconductor MSM548128BL , ,, , ,, , , ,,, Auto Refresh Cycle tRHC tRFD CE tRCD tFC tFAP tFC tFP tFAP tRFA RFSH "H" or "L" Self Refresh Cycle tRFD CE tRCD tFAS tRHC tRFS RFSH "H" or "L" CS Standby Mode tRC tCE CE tP tCSS tCSH CS "H" or "L" 10/12 ¡ Semiconductor MSM548128BL PACKAGE DIMENSIONS (Unit : mm) DIP32-P-600-2.54 Package material Lead frame material Pin treatment Solder plate thickness Package weight (g) Epoxy resin 42 alloy Solder plating 5 mm or more 4.70 TYP. 11/12 ¡ Semiconductor MSM548128BL (Unit : mm) SOP32-P-525-1.27-K Mirror finish Package material Lead frame material Pin treatment Solder plate thickness Package weight (g) Epoxy resin 42 alloy Solder plating 5 mm or more 1.32 TYP. Notes for Mounting the Surface Mount Type Package The SOP, QFP, TSOP, SOJ, QFJ (PLCC), SHP and BGA are surface mount type packages, which are very susceptible to heat in reflow mounting and humidity absorbed in storage. Therefore, before you perform reflow mounting, contact Oki’s responsible sales person for the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times). 12/12