E2L0044-17-Y1 ¡ Semiconductor MSM548512L ¡ Semiconductor This version: Jan. 1998 MSM548512L Previous version: Dec. 1996 524,288-Word ¥ 8-Bit High-Speed PSRAM DESCRIPTION The MSM548512L is fabricated using OKI’s CMOS silicon gate process technology. This process, coupled with single-transister memory storage cells, permits maximum circuit density, minimum chip size and high speed. MSM548512L has Self-refresh mode in addition to Address-refresh mode and Auto-refresh mode. In the Self-refresh mode the internal refresh timer and address counter refresh the dynamic memory cells automatically. This series allows low power consumption when using standby mode with Self-refresh. The MSM548512L also features a static RAM-like write function that writes the data into the memory cell at the rising edge of WE. FEATURES • Large capacity • Fast access time • Low power • Refresh free • Logic compatible • Single power supply • Refresh • Package compatible • Package options: 32-pin 600 mil plastic DIP 32-pin 525 mil plastic SOP : : : : : : : : 4-Mbit (524,288-word ¥ 8 bits) 80 ns max. 200 µA max. (standby with Self-refresh) Self refresh SRAM WE pin, no address multiplex 5 V ±10% 2048 cycle/32 ms auto-address refresh SRAM standard package (DIP32-P-600-2.54) (Product : MSM548512L-xxRS) (SOP32-P-525-1.27-K) (Product : MSM548512L-xxGS-K) xx indicates speed rank. PRODUCT FAMILY Family Access Time (Max.) MSM548512L-80RS 80 ns MSM548512L-10RS 100 ns MSM548512L-12RS 120 ns MSM548512L-80GS-K 80 ns MSM548512L-10GS-K 100 ns MSM548512L-12GS-K 120 ns Package 600 mil 32-pin Plastic DIP 525 mil 32-pin Plastic SOP 1/12 ¡ Semiconductor MSM548512L PIN CONFIGURATION (TOP VIEW) A18 1 32 VCC A16 2 31 A15 A14 3 30 A17 A12 4 29 WE A7 5 28 A13 A6 6 27 A8 A5 7 26 A9 A4 8 25 A11 A3 9 24 OE/RFSH A2 10 23 A10 A1 11 22 CE A0 12 , A18 1 A16 2 32 VCC 31 A15 A14 3 A12 4 30 A17 29 WE A7 5 A6 6 28 A13 27 A8 A5 7 A4 8 26 A9 25 A11 A3 9 A2 10 24 OE/RFSH 23 A10 21 I/O7 A1 11 A0 12 22 CE 21 I/O7 I/O0 13 20 I/O6 I/O1 14 19 I/O5 I/O0 13 I/O1 14 20 I/O6 19 I/O5 I/O2 15 18 I/O4 I/O2 15 VSS 16 18 I/O4 17 I/O3 VSS 16 17 I/O3 32-Pin Plastic SOP 32-Pin Plastic DIP Pin Name A0 - A18 Function Address Input I/O0 - I/O7 Data Input/Output CE Chip Enable Input OE/RFSH Output Enable / Refresh Input WE Write Enable Input VCC Power Voltage (5 V) VSS Ground (0 V) 2/12 ¡ Semiconductor MSM548512L BLOCK DIAGRAM A0 Address Latch Control Row Decoder Memory Matrix (2048 ¥ 256) ¥ 8 A10 I/O0 Column I/O Input Data Control I/O7 Column Decoder Address Latch Control A11 A18 Refresh Control CE Timing Pulse Generator OE/RFSH WE Read/Write Control 3/12 ¡ Semiconductor MSM548512L FUNCTION TABLE CE OE/RFSH WE I/O Pin Mode L L H Low-Z Read L X L High-Z Write L H H High-Z — H L X High-Z Refresh H H X High-Z Standby L : Low Level Input H : High Level Input X : Don’t Care ELECTRICAL CHARACTERISTICS Absolute Maximum Ratings Parameter Symbol Rating Unit Voltage on Any Pin from VSS *1 VT –1.0 to 7.0 V Power Dissipation PD Topr 1.0 W Operating Temperature 0 to 70 °C Storage Temperature Tstg –55 to 125 °C Storage Temperature (biased) Tbias –10 to 85 °C Short Circuit Output Current IOS 50 mA *1 Note: To VSS 1. Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to the conditions as detailed in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Recommended Operating Conditions Parameter Power Supply Voltage Input Voltage (Ta = 0°C to 70°C) Symbol Min. Typ. Max. Unit VCC 4.5 5.0 5.5 V VSS 0 0 0 V VIH 2.4 — 6.0 V VIL –0.5 — 0.8 V 4/12 ¡ Semiconductor MSM548512L DC Characteristics (VCC = 5 V ±10%, VSS = 0 V, Ta = 0°C to 70°C) Symbol Min. Typ. Max. Unit ICC1 — 50 75 mA ISB1 — 1 2 mA ISB2 — 100 200 mA ICC2 — 1 2 mA ICC3 — 100 200 mA ILI –10 — 10 mA VCC = 5.5 V, VIN = VSS to VCC Output Leakage Current ILO –10 — 10 mA OE/RFSH = VIH, VI/O = VSS to VCC Output Low Level VOL — — 0.4 V IOL = 2.1 mA Output High Level VOH 2.4 — — V IOH = –1 mA Parameter Operating Current Condition II/O = Open, tcyc = min. CE = VIH, OE/RFSH = VIH, VIN ≥ 0 V Standby Current CE ≥ VCC – 0.2 V, VIN ≥ 0 V, OE/RFSH ≥ VCC – 0.2 V CE = VIH, OE/RFSH = VIL, VIN ≥ 0 V Self Refresh Current Input Leakage Current CE ≥ VCC – 0.2 V, VIN ≥ 0 V, OE/RFSH £ 0.2 V Capacitance Parameter Symbol Condition Min. Typ. Max. Unit Input Capacitance CIN VIN = 0 V — — 8 pF I/O Pin Capacitance CI/O VI/O = 0 V — — 10 pF Note: This parameter is periodically sampled and is not 100% tested. 5/12 ¡ Semiconductor AC Characteristics Measurement condition: MSM548512L Input pulse level ........................... VIH = 2.4 V, VIL = 0.4 V Output reference level .................. VOH = 2.0 V, VOL = 0.8 V Rising and falling time ................. 5 ns Output load .................................... 1 TTL + 100 pF Input timing reference level ........ High = 2.2 V, Low = 0.8 V (VCC = 5 V ±10%, Ta = 0°C to 70°C) Parameter MSM548512L MSM548512L MSM548512L -80 -10 -12 Symbol Unit Note Min. Max. Min. Max. Min. Max. tRC 160 — 180 — 210 — ns Random Read Modify Write Cycle Time tRWC 220 — 240 — 280 — ns CE Access Time tCEA — 80 — 100 — 120 ns OE Access Time tOEA — 30 — 30 — 50 ns Chip Disable to Output in High-Z tCHZ — 25 — 30 — 30 ns CE to Output in Low-Z tCLZ 20 — 20 — 20 — ns OE Disable to Output in High-Z tOHZ — 25 — 25 — 30 ns OE Output in Low-Z tOLZ 0 — 0 — 0 — ns CE Pulse Width tCE 80n 10m 100n 10m 120n 10m s CE Precharge Time tP 70 — 70 — 80 — ns Address Set-up Time tAS 0 — 0 — 0 — ns Address Hold Time tAH 20 — 25 — 30 — ns Read Command Set-up Time tRCS 0 — 0 — 0 — ns Read Command Hold Time tRCH 0 — 0 — 0 — ns OE Command Hold Time tOHC 15 — 15 — 15 — ns OE Delay Time tOCD 0 — 0 — 0 — ns Write Command Pulse Width tWP 25 — 30 — 35 — ns Chip Enable Time tCW 80 — 100 — 120 — ns Input Data Set Time tDW 20 — 25 — 30 — ns Input Data Hold Time tDH 0 — 0 — 0 — ns Output Active from End of Write tOW 5 — 5 — 5 — ns Write Enable to Output in High-Z tWHZ — 20 — 25 — 30 ns 6 tT 3 50 3 50 3 50 ns 11 RFSH Delay Time from CE tRFD 70 — 70 — 80 — ns RFSH Precharge Time tFP 40 — 40 — 40 — ns RFSH Pulse Width (Auto-refresh) tFAP 80n 8m 80n 8m 80n 8m s Auto-refresh Cycle Time tFC 160 — 180 — 210 — ns RFSH Pulse Width (Self-refresh) tFAS 8 — 8 — 8 — ms CE Delay Time from RFSH in Self-refresh Mode tRFS 600 — 600 — 600 — ns Refresh Period (2048 cycle/32 ms) tREF — 32 — 32 — 32 ms Random Read Write Cycle Time Transition Time 6 6 6/12 ¡ Semiconductor Notes: MSM548512L 1. Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. 2. All voltages are referenced to ground. 3. ICC1 depends on output loading. Specified values are obtained with the output open. 4. An initial pause of 100 µs is required after power-up followed by more than 8 initial cycles before proper device operation is achieved. 5. AC measurements assume tT = 5 ns. 6. tCHZ, tWHZ and tOHZ define the time at which the output achieves the open circuit condition and is not referenced to output voltage levels. 7. In write cycles, the input data is latched at the earlier rising point of either CE or WE. Write operation is achieved when both CE and WE are low. 8. The I/O state remains at high impedance after CE goes low if the transition occurs at the same time as or after the falling edge of WE. 9. Use WE or OE or both signals to disable the output before input data is applied during a write cycle when the input is not the same. 10. Data input must be set to floating state before I/O becomes low impedance by WE or OE or both. 11. VIH (Min.) and VIL (Max.) are input timing reference levels for measurement. The transition time is measured between VIL and VIH. 12. 2048-cycle refresh must be applied within 15 µs after the end of self refreshing to satisfy 2048 cycles/32 ms. 7/12 ¡ Semiconductor MSM548512L ,,, , ,,, TIMING WAVEFORM Read Cycle tRC tCE CE tAS tP tAH Address A0 - A18 tRCS tRCH WE tCEA tOHC OE/RSFH tOEA tOLZ tOHZ DOUT tCHZ Valid Data-out "H" or "L" Write Cycle 1 (OE High) tRC tCE CE tAS tP tAH Address A0 - A18 tCW tWP WE OE/RFSH tOCD tDW DIN tWHZ tCLZ tOHZ tDH Valid Data-in tOLZ tCHZ tOW DOUT "H" or "L" 8/12 ,,, , ,,, , ¡ Semiconductor MSM548512L Write Cycle 2 (OE Low) tRC tCE CE tAS tP tAH Address A0 - A18 tCW WE tWP tOHC OE/RFSH tDW DIN Valid Data-in tWHZ tCLZ tDH DOUT "H" or "L" Read Modify Write tRWC tP CE tAS tAH Address A0 - A18 tCW tRCS WE tRCH tWP tOCD tOHC OE/RFSH tOHZ tOEA DIN tOLZ tDW Valid Data-in tWHZ tCLZ DOUT tDH tCHZ tOW Valid Data-out "H" or "L" 9/12 ,, , , ¡ Semiconductor MSM548512L Auto Refresh Cycle CE tRFD tFC tFP tFAP tFC tFP tFAP OE/RFSH "H" or "L" Self Refresh Cycle CE tRFD tFP tFAS tRFS OE/RFSH "H" or "L" 10/12 ¡ Semiconductor MSM548512L PACKAGE DIMENSIONS (Unit : mm) DIP32-P-600-2.54 Package material Lead frame material Pin treatment Solder plate thickness Package weight (g) Epoxy resin 42 alloy Solder plating 5 mm or more 4.70 TYP. 11/12 ¡ Semiconductor MSM548512L (Unit : mm) SOP32-P-525-1.27-K Mirror finish Package material Lead frame material Pin treatment Solder plate thickness Package weight (g) Epoxy resin 42 alloy Solder plating 5 mm or more 1.32 TYP. Notes for Mounting the Surface Mount Type Package The SOP, QFP, TSOP, SOJ, QFJ (PLCC), SHP and BGA are surface mount type packages, which are very susceptible to heat in reflow mounting and humidity absorbed in storage. Therefore, before you perform reflow mounting, contact Oki’s responsible sales person for the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times). 12/12