Product Folder Sample & Buy Support & Community Tools & Software Technical Documents CSD19533Q5A SLPS486A – DECEMBER 2013 – REVISED MAY 2014 CSD19533Q5A 100 V N-Channel NexFET™ Power MOSFET 1 Features • • • • • • • 1 Product Summary Ultra-Low Qg and Qgd Low Thermal Resistance Avalanche Rated Pb-Free Terminal Plating RoHS Compliant Halogen Free SON 5-mm × 6-mm Plastic Package TA = 25°C TYPICAL VALUE Drain-to-Source Voltage 100 V Qg Gate Charge Total (10 V) 27 nC Qgd Gate Charge Gate to Drain 4.9 RDS(on) Drain-to-Source On Resistance VGS(th) Threshold Voltage nC VGS = 6 V 8.7 mΩ VGS = 10 V 7.8 mΩ 2.8 V . Ordering Information(1) 2 Applications • • • UNIT VDS Primary Side Telecom Secondary Side Synchronous Rectifier Motor Control Device Media Qty Package Ship CSD19533Q5A 13-Inch Reel 2500 CSD19533Q5AT 7-Inch Reel 250 SON 5 x 6 mm Plastic Package Tape and Reel 3 Description (1) For all available packages, see the orderable addendum at the end of the data sheet. This 100 V, 7.8 mΩ, SON 5 mm × 6 mm NexFET™ power MOSFET is designed to minimize losses in power conversion applications. TA = 25°C Top View S 8 1 D Absolute Maximum Ratings VALUE UNIT VDS Drain-to-Source Voltage 100 V VGS Gate-to-Source Voltage ±20 V Continuous Drain Current (Package limited) 100 Continuous Drain Current (Silicon limited), TC = 25°C 75 ID (1) S 7 2 D Continuous Drain Current, TA = 25 °C 13 Pulsed Drain Current, TA = 25 °C(2) 231 Power Dissipation(1) 3.2 Power Dissipation, TC = 25°C 96 TJ, Tstg Operating Junction and Storage Temperature Range –55 to 150 °C EAS Avalanche Energy, single pulse ID = 46 A, L = 0.1 mH, RG = 25 Ω 106 mJ IDM PD S 6 3 D D G 5 4 D RDS(on) vs VGS W Gate Charge 30 10 TC = 25°C, I D = 13A TC = 125°C, I D = 13A 27 VGS - Gate-to-Source Voltage (V) RDS(on) - On-State Resistance (mΩ) A (1) Typical RθJA = 40 °C/W on a 1-inch2, 2-oz. Cu pad on a 0.06-inch thick FR4 PCB. (2) Max RθJC = 1.3°C/W, pulse duration ≤100 μs, duty cycle ≤1% P0093-01 24 21 18 15 12 9 6 3 0 A 0 2 4 6 8 10 12 14 16 VGS - Gate-to- Source Voltage (V) 18 20 G001 ID = 13A VDS = 50V 9 8 7 6 5 4 3 2 1 0 0 3 6 9 12 15 18 21 Qg - Gate Charge (nC) 24 27 30 G001 1 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. CSD19533Q5A SLPS486A – DECEMBER 2013 – REVISED MAY 2014 www.ti.com Table of Contents 1 2 3 4 5 Features .................................................................. Applications ........................................................... Description ............................................................. Revision History..................................................... Specifications......................................................... 1 1 1 2 3 5.1 Electrical Characteristics.......................................... 3 5.2 Thermal Information .................................................. 3 5.3 Typical MOSFET Characteristics.............................. 4 6 Device and Documentation Support.................... 7 6.1 Trademarks ............................................................... 7 6.2 Electrostatic Discharge Caution ................................ 7 6.3 Glossary .................................................................... 7 7 Mechanical, Packaging, and Orderable Information ............................................................. 8 7.1 7.2 7.3 7.4 Q5A Package Dimensions ........................................ 9 Recommended PCB Pattern................................... 10 Recommended Stencil Opening ............................. 11 Q5A Tape and Reel Information ............................. 11 4 Revision History Changes from Original (December 2013) to Revision A Page • Added small reel order number .............................................................................................................................................. 1 • Increased pulsed drain current to 231A ................................................................................................................................ 1 • Added line for max power dissipation with case temperature held to 25°C .......................................................................... 1 • Updated the pulsed drain current conditions ......................................................................................................................... 1 • Fixed y-axis on Figure 1 to state that it is a normalized RθJC curve ...................................................................................... 4 • Updated the safe operating area in Figure 10 ....................................................................................................................... 6 2 Submit Documentation Feedback Copyright © 2013–2014, Texas Instruments Incorporated Product Folder Links: CSD19533Q5A CSD19533Q5A www.ti.com SLPS486A – DECEMBER 2013 – REVISED MAY 2014 5 Specifications 5.1 Electrical Characteristics (TA = 25°C unless otherwise stated) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT STATIC CHARACTERISTICS BVDSS Drain-to-Source Voltage VGS = 0 V, ID = 250 μA IDSS Drain-to-Source Leakage Current VGS = 0 V, VDS = 80 V 1 μA IGSS Gate-to-Source Leakage Current VDS = 0 V, VGS = 20 V 100 nA VGS(th) Gate-to-Source Threshold Voltage VDS = VGS, ID = 250 μA RDS(on) Drain-to-Source On Resistance gfs Transconductance 100 2.2 V 2.8 3.4 V VGS = 6 V, ID = 13 A 8.7 11.1 mΩ VGS = 10 V, ID = 13 A 7.8 9.4 mΩ VDS = 10 V, ID = 13 A 63 S DYNAMIC CHARACTERISTICS Ciss Input Capacitance Coss Output Capacitance 2050 2670 pF 395 514 pF Crss RG Reverse Transfer Capacitance 9.6 12.5 pF Series Gate Resistance 1.2 2.4 Ω Qg Gate Charge Total (10 V) 27 35 nC Qgd Gate Charge Gate to Drain Qgs Gate Charge Gate to Source Qg(th) Gate Charge at Vth Qoss Output Charge td(on) Turn On Delay Time tr Rise Time td(off) Turn Off Delay Time tf Fall Time VGS = 0 V, VDS = 50 V, ƒ = 1 MHz VDS = 50 V, ID = 13 A VDS = 50 V, VGS = 0 V VDS = 50 V, VGS = 10 V, IDS = 13 A, RG = 0 Ω 4.9 nC 7.9 nC 5.7 nC 75 nC 6 ns 6 ns 16 ns 5 ns DIODE CHARACTERISTICS VSD Diode Forward Voltage ISD = 13 A, VGS = 0 V 0.8 1.0 V Qrr Reverse Recovery Charge nC Reverse Recovery Time VDS= 50 V, IF = 13 A, di/dt = 300 A/μs 163 trr 62 ns 5.2 Thermal Information (TA = 25°C unless otherwise stated) THERMAL METRIC MIN TYP MAX RθJC Junction-to-Case Thermal Resistance (1) 1.3 RθJA Junction-to-Ambient Thermal Resistance (1) (2) 50 (1) (2) UNIT °C/W RθJC is determined with the device mounted on a 1-inch2 (6.45-cm2), 2-oz. (0.071-mm thick) Cu pad on a 1.5-inches × 1.5-inches (3.81cm × 3.81-cm), 0.06-inch (1.52-mm) thick FR4 PCB. RθJC is specified by design, whereas RθJA is determined by the user’s board design. Device mounted on FR4 material with 1-inch2 (6.45-cm2), 2-oz. (0.071-mm thick) Cu. Submit Documentation Feedback Copyright © 2013–2014, Texas Instruments Incorporated Product Folder Links: CSD19533Q5A 3 CSD19533Q5A SLPS486A – DECEMBER 2013 – REVISED MAY 2014 GATE www.ti.com GATE Source N-Chan 5x6 QFN TTA MIN Rev3 N-Chan 5x6 QFN TTA MAX Rev3 Max RθJA = 50°C/W when mounted on 1 inch2 (6.45 cm2) of 2-oz. (0.071-mm thick) Cu. Source Max RθJA = 115°C/W when mounted on a minimum pad area of 2-oz. (0.071-mm thick) Cu. DRAIN DRAIN M0137-02 M0137-01 5.3 Typical MOSFET Characteristics (TA = 25°C unless otherwise stated) Figure 1. Transient Thermal Impedance 4 Submit Documentation Feedback Copyright © 2013–2014, Texas Instruments Incorporated Product Folder Links: CSD19533Q5A CSD19533Q5A www.ti.com SLPS486A – DECEMBER 2013 – REVISED MAY 2014 Typical MOSFET Characteristics (continued) (TA = 25°C unless otherwise stated) 120 180 IDS - Drain-to-Source Current (A) IDS - Drain-to-Source Current (A) 200 160 140 120 100 80 60 VGS =10V VGS =8V VGS =6V 40 20 0 0 0.5 1 1.5 2 2.5 3 3.5 4 VDS - Drain-to-Source Voltage (V) 4.5 VDS = 5V 100 80 60 40 0 5 TC = 125°C TC = 25°C TC = −55°C 20 0 1 Figure 2. Saturation Characteristics 6 G001 Figure 3. Transfer Characteristics Ciss = Cgd + Cgs Coss = Cds + Cgd Crss = Cgd ID = 13A VDS = 50V 9 C − Capacitance (pF) 8 7 6 5 4 3 10000 1000 100 2 10 1 0 0 3 6 9 12 15 18 21 Qg - Gate Charge (nC) 24 27 1 30 0 10 20 G001 Figure 4. Gate Charge 30 40 50 60 70 80 VDS - Drain-to-Source Voltage (V) 90 100 G001 Figure 5. Capacitance 3.4 30 ID = 250uA 3.2 RDS(on) - On-State Resistance (mΩ) VGS(th) - Threshold Voltage (V) 5 100000 10 VGS - Gate-to-Source Voltage (V) 2 3 4 VGS - Gate-to-Source Voltage (V) G001 3 2.8 2.6 2.4 2.2 2 1.8 1.6 −75 −25 25 75 125 TC - Case Temperature (ºC) Figure 6. Threshold Voltage vs Temperature 175 TC = 25°C, I D = 13A TC = 125°C, I D = 13A 27 24 21 18 15 12 9 6 3 0 0 2 G001 4 6 8 10 12 14 16 VGS - Gate-to- Source Voltage (V) 18 20 G001 Figure 7. On-State Resistance vs Gate-to-Source Voltage Submit Documentation Feedback Copyright © 2013–2014, Texas Instruments Incorporated Product Folder Links: CSD19533Q5A 5 CSD19533Q5A SLPS486A – DECEMBER 2013 – REVISED MAY 2014 www.ti.com Typical MOSFET Characteristics (continued) (TA = 25°C unless otherwise stated) 2 100 VGS = 6V VGS = 10V ISD − Source-to-Drain Current (A) Normalized On-State Resistance 2.2 1.8 1.6 1.4 1.2 1 0.8 0.6 0.4 −75 TC = 25°C TC = 125°C 10 1 0.1 0.01 0.001 ID = 13A −25 25 75 125 TC - Case Temperature (ºC) 175 0.0001 0 Figure 8. Normalized On-State Resistance vs Temperature 10us 100us 1ms 10ms DC TC = 25ºC TC = 125ºC IAV - Peak Avalanche Current (A) IDS - Drain-to-Source Current (A) G001 100 100 10 1 Single Pulse Max RthetaJC = 1.3ºC/W 0.1 0.1 1 Figure 9. Typical Diode Forward Voltage 5000 1000 0.2 0.4 0.6 0.8 VSD − Source-to-Drain Voltage (V) G001 1 10 100 VDS - Drain-to-Source Voltage (V) 1000 10 0.01 0.1 TAV - Time in Avalanche (mS) G001 Figure 10. Maximum Safe Operating Area 1 G001 Figure 11. Single Pulse Unclamped Inductive Switching IDS - Drain- to- Source Current (A) 100 90 80 70 60 50 40 30 20 10 0 −50 −25 0 25 50 75 100 125 TC - Case Temperature (ºC) 150 175 G001 Figure 12. Maximum Drain Current vs Temperature 6 Submit Documentation Feedback Copyright © 2013–2014, Texas Instruments Incorporated Product Folder Links: CSD19533Q5A CSD19533Q5A www.ti.com SLPS486A – DECEMBER 2013 – REVISED MAY 2014 6 Device and Documentation Support 6.1 Trademarks NexFET is a trademark of Texas Instruments. 6.2 Electrostatic Discharge Caution These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. 6.3 Glossary SLYZ022 — TI Glossary. This glossary lists and explains terms, acronyms and definitions. Submit Documentation Feedback Copyright © 2013–2014, Texas Instruments Incorporated Product Folder Links: CSD19533Q5A 7 CSD19533Q5A SLPS486A – DECEMBER 2013 – REVISED MAY 2014 www.ti.com 7 Mechanical, Packaging, and Orderable Information The following pages include mechanical packaging and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. 8 Submit Documentation Feedback Copyright © 2013–2014, Texas Instruments Incorporated Product Folder Links: CSD19533Q5A CSD19533Q5A www.ti.com SLPS486A – DECEMBER 2013 – REVISED MAY 2014 2 3 4 5 4 5 6 3 6 7 2 7 1 8 1 8 7.1 Q5A Package Dimensions DIM MILLIMETERS MIN NOM MAX A 0.90 1.00 1.10 b 0.33 0.41 0.51 c 0.20 0.25 0.34 D1 4.80 4.90 5.00 D2 3.61 3.81 4.02 E 5.90 6.00 6.10 E1 5.70 5.75 5.80 E2 3.38 3.58 3.78 E3 3.03 3.13 3.23 e 1.17 1.27 1.37 e1 0.27 0.37 0.47 e2 0.15 0.25 0.35 H 0.41 0.56 0.71 K 1.10 – – L 0.51 0.61 0.71 L1 0.06 0.13 0.20 θ 0° – 12° Submit Documentation Feedback Copyright © 2013–2014, Texas Instruments Incorporated Product Folder Links: CSD19533Q5A 9 CSD19533Q5A SLPS486A – DECEMBER 2013 – REVISED MAY 2014 www.ti.com 7.2 Recommended PCB Pattern F1 F7 F3 8 1 F2 F11 F5 F9 5 4 F6 F8 F4 F10 M0139-01 DIM MILLIMETERS INCHES MIN MAX MIN MAX F1 6.205 6.305 0.244 0.248 F2 4.46 4.56 0.176 0.18 F3 4.46 4.56 0.176 0.18 F4 0.65 0.7 0.026 0.028 F5 0.62 0.67 0.024 0.026 F6 0.63 0.68 0.025 0.027 F7 0.7 0.8 0.028 0.031 F8 0.65 0.7 0.026 0.028 F9 0.62 0.67 0.024 0.026 F10 4.9 5 0.193 0.197 F11 4.46 4.56 0.176 0.18 For recommended circuit layout for PCB designs, see application note SLPA005 – Reducing Ringing Through PCB Layout Techniques. 10 Submit Documentation Feedback Copyright © 2013–2014, Texas Instruments Incorporated Product Folder Links: CSD19533Q5A CSD19533Q5A www.ti.com SLPS486A – DECEMBER 2013 – REVISED MAY 2014 7.3 Recommended Stencil Opening (0.020) 8x 0.500 (0.020) 0.500 5 4 0.500 (0.020) 8x 1.585 (0.062) 1.235 (0.049) (0.024) 0.620 (0.170) 4.310 0.385 (0.015) 1.270 (0.050) 1 8 1.570 (0.062) 4x 0.615 (0.024) 1.105 (0.044) 3.020 (0.119) K0 4.00 ±0.10 (See Note 1) 0.30 ±0.05 2.00 ±0.05 +0.10 –0.00 12.00 ±0.30 Ø 1.50 1.75 ±0.10 7.4 Q5A Tape and Reel Information 5.50 ±0.05 B0 R 0.30 MAX A0 8.00 ±0.10 Ø 1.50 MIN A0 = 6.50 ±0.10 B0 = 5.30 ±0.10 K0 = 1.40 ±0.10 R 0.30 TYP M0138-01 Notes: 1. 10-sprocket hole-pitch cumulative tolerance ±0.2 2. Camber not to exceed 1 mm in 100 mm, noncumulative over 250 mm 3. Material: black static-dissipative polystyrene 4. All dimensions are in mm (unless otherwise specified) 5. A0 and B0 measured on a plane 0.3 mm above the bottom of the pocket Submit Documentation Feedback Copyright © 2013–2014, Texas Instruments Incorporated Product Folder Links: CSD19533Q5A 11 PACKAGE OPTION ADDENDUM www.ti.com 28-Aug-2014 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan Lead/Ball Finish MSL Peak Temp (2) (6) (3) CSD19533Q5A ACTIVE VSONP DQJ 8 2500 Pb-Free (RoHS Exempt) CU SN Level-1-260C-UNLIM CSD19533Q5AT ACTIVE VSONP DQJ 8 250 Pb-Free (RoHS Exempt) CU SN Level-1-260C-UNLIM Op Temp (°C) Device Marking (4/5) -55 to 150 CSD19533 CSD19533 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. Addendum-Page 1 Samples PACKAGE OPTION ADDENDUM www.ti.com 28-Aug-2014 In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 2 PACKAGE MATERIALS INFORMATION www.ti.com 28-Aug-2014 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) CSD19533Q5A VSONP DQJ 8 2500 330.0 12.4 CSD19533Q5AT VSONP DQJ 8 250 180.0 12.4 Pack Materials-Page 1 B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant 6.3 5.3 1.2 8.0 12.0 Q1 6.3 5.3 1.2 8.0 12.0 Q1 PACKAGE MATERIALS INFORMATION www.ti.com 28-Aug-2014 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) CSD19533Q5A VSONP DQJ 8 2500 340.0 340.0 38.0 CSD19533Q5AT VSONP DQJ 8 250 190.0 190.0 30.0 Pack Materials-Page 2 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. All semiconductor products (also referred to herein as “components”) are sold subject to TI’s terms and conditions of sale supplied at the time of order acknowledgment. TI warrants performance of its components to the specifications applicable at the time of sale, in accordance with the warranty in TI’s terms and conditions of sale of semiconductor products. Testing and other quality control techniques are used to the extent TI deems necessary to support this warranty. Except where mandated by applicable law, testing of all parameters of each component is not necessarily performed. TI assumes no liability for applications assistance or the design of Buyers’ products. Buyers are responsible for their products and applications using TI components. To minimize the risks associated with Buyers’ products and applications, Buyers should provide adequate design and operating safeguards. TI does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property right relating to any combination, machine, or process in which TI components or services are used. Information published by TI regarding third-party products or services does not constitute a license to use such products or services or a warranty or endorsement thereof. Use of such information may require a license from a third party under the patents or other intellectual property of the third party, or a license from TI under the patents or other intellectual property of TI. Reproduction of significant portions of TI information in TI data books or data sheets is permissible only if reproduction is without alteration and is accompanied by all associated warranties, conditions, limitations, and notices. TI is not responsible or liable for such altered documentation. Information of third parties may be subject to additional restrictions. Resale of TI components or services with statements different from or beyond the parameters stated by TI for that component or service voids all express and any implied warranties for the associated TI component or service and is an unfair and deceptive business practice. TI is not responsible or liable for any such statements. Buyer acknowledges and agrees that it is solely responsible for compliance with all legal, regulatory and safety-related requirements concerning its products, and any use of TI components in its applications, notwithstanding any applications-related information or support that may be provided by TI. Buyer represents and agrees that it has all the necessary expertise to create and implement safeguards which anticipate dangerous consequences of failures, monitor failures and their consequences, lessen the likelihood of failures that might cause harm and take appropriate remedial actions. Buyer will fully indemnify TI and its representatives against any damages arising out of the use of any TI components in safety-critical applications. In some cases, TI components may be promoted specifically to facilitate safety-related applications. With such components, TI’s goal is to help enable customers to design and create their own end-product solutions that meet applicable functional safety standards and requirements. Nonetheless, such components are subject to these terms. No TI components are authorized for use in FDA Class III (or similar life-critical medical equipment) unless authorized officers of the parties have executed a special agreement specifically governing such use. Only those TI components which TI has specifically designated as military grade or “enhanced plastic” are designed and intended for use in military/aerospace applications or environments. Buyer acknowledges and agrees that any military or aerospace use of TI components which have not been so designated is solely at the Buyer's risk, and that Buyer is solely responsible for compliance with all legal and regulatory requirements in connection with such use. TI has specifically designated certain components as meeting ISO/TS16949 requirements, mainly for automotive use. In any case of use of non-designated products, TI will not be responsible for any failure to meet ISO/TS16949. Products Applications Audio www.ti.com/audio Automotive and Transportation www.ti.com/automotive Amplifiers amplifier.ti.com Communications and Telecom www.ti.com/communications Data Converters dataconverter.ti.com Computers and Peripherals www.ti.com/computers DLP® Products www.dlp.com Consumer Electronics www.ti.com/consumer-apps DSP dsp.ti.com Energy and Lighting www.ti.com/energy Clocks and Timers www.ti.com/clocks Industrial www.ti.com/industrial Interface interface.ti.com Medical www.ti.com/medical Logic logic.ti.com Security www.ti.com/security Power Mgmt power.ti.com Space, Avionics and Defense www.ti.com/space-avionics-defense Microcontrollers microcontroller.ti.com Video and Imaging www.ti.com/video RFID www.ti-rfid.com OMAP Applications Processors www.ti.com/omap TI E2E Community e2e.ti.com Wireless Connectivity www.ti.com/wirelessconnectivity Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265 Copyright © 2014, Texas Instruments Incorporated