Preliminary PL623-38 Low Phase Noise XO (for 3 rd O.T.) For 65-130MHz FEATURES 15 14 13 56.5 mil 21 Die ID: C560A-FFFF-FP OECTRL 11 VDDBUF VDDBUF Q 8 Q 5 6 GNDBUF 4 GNDBUF Note: ‘^’ Denotes 60kΩ pull-up resistor DIE SPECIFICATIONS Name Value Size Reverse side 57.5 x 56.5 mil GND Pad dimensions 80 micron x 80 micron Thickness 10 mil OE SELECTION Pad #12 OESEL 1 3rd OT Resistor PL623-38 OESEL (pull down) 9 7 GNDBSHIELD Q 3 GNDASHIELD Q 2 GNDANA OECTRL X 1 GNDOSC BLOCK DIAGRAM (0,0) Y 12 22 GNDOSC PL623-38 is an XO IC specifically designed to work with high frequency 3 rd overtone or fundamental crystals from 65MHz to 135MHz. It requires an external resistor for the 3 rd overtone selection. Its design was optimized to tolerate higher limits of inter-electrodes capacitance and bonding capacitance to improve yield. It achieves very low current into the crystal resulting in better overall stability. It is ideal for XO applications requiring PECL output levels at high frequencies. XOUT VDDBUF 20 VDDANA XIN VDDOSC 19 16 (1460,1435) 10 DESCRIPTION XIN 17 OECTRL XOUT Oscillator Amplifier 18 ^ SEL1 • • • 57.5 mil ^SEL0 • • Input: 65-130MHz 3 rd Overtone or fundamental Crystal Output frequency: Up to 130MHz Selectable /2, /4, /8 output dividers with 60KΩ pull up resistor on the selector pins Available output: PECL Supports 2.5V or 3.3V-Power Supply Available in die form GNDOSC • DIE CONFIGURATION 0 (default) Pad #22 OECTRL 0 1 0 1 State Tri-state Output enabled (default) Output enabled (default) Tri-state Pad #12: Bond to VDD to set to “1” Pad #22: Logical states defined by PECL levels OUTPUT DIVIDER SELECTOR LOGIC SEL 0 SEL1 Output 0 0 No Divider 1 0 Divide by 2 0 1 Divide by 4 1 1 Divide by 8 47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991 www.phaselink.com Rev 05/03/05 Page 1 Preliminary PL623-38 Low Phase Noise XO (for 3 rd O.T.) For 65-130MHz DIE PAD ASSIGNMENT Pad # Name X (µm) Y (µm) Pad Description 1 GNDOSC 329.6 110.1 GND connection for oscillator circuitry. 2 GNDOSC 498.3 110.0 GND connection for oscillator circuitry. 3 GNDANA 696.2 110.0 GND connection for analog circuitry. 4 GNDSHIELD 825.0 110.0 GND shielding connection. 5 GNDSHIELD 973.6 110.0 GND shielding connection. 6 GNDBUF 1150.0 109.1 GND connection for output buffer circuitry. 7 GNDBUF 1183.6 302.2 GND connection for output buffer circuitry. 8 Q 1183.6 452.3 PECL output. 9 QBAR 1183.6 613.5 Complementary PECL output. 10 VDDBUF 1182.4 745.9 VDD connection for output buffer circuitry. VDDBUF should be separately decoupled from other VDDs whenever possible. 11 VDDBUF 1252.4 903.6 VDD connection for output buffer circuitry. VDDBUF should be separately decoupled from other VDDs whenever possible. 12 OESEL 1252.4 1081.3 13 VDDBUF 1058.5 1221.6 14 VDDANA 864.5 1221.6 15 VDDOSC 624.0 1222.7 16 SEL1 467.1 1222.6 17 SEL0 271.1 1222.6 Output Divider Selector pin as presented on the DIVIDER SELECTOR TABLE on page ‘1’. 18 GNDOSC 109.4 1222.9 GND connection for oscillator circuitry. 19 OECTRL 108.9 1062.1 Output Enable input pad. See OE SELECTION TABLE on page 1. 20 XIN 109.0 865.8 Crystal connector pad. This pad is the input of the crystal oscillator circuitry. The crystal should be mounted as close to the IC as possible, with minimum parasitic capacitance. 21 XOUT 108.6 358.4 Crystal connector pad. This pad is the input of the crystal oscillator circuitry. The crystal should be mounted as close to the IC as possible, with minimum parasitic capacitance. 22 OECTRL 108.6 146.5 Output Enable input pad. See OE SELECTION TABLE on page 1. This is the selector input to choose the OE control logic to be applied, as presented on the OE SELECTION TABLE on page ‘1’. VDD connection for output buffer circuitry. VDDBUF should be separately decoupled from other VDDs whenever possible. VDD connection for analog circuitry. VDDANA should be separately decoupled from other VDDs whenever possible. VDD connection for oscillator circuitry. VDDOSC should be separately decoupled from other VDDs whenever possible. Output Divider Selector pin as presented on the DIVIDER SELECTOR TABLE on page ‘1’. 47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991 www.phaselink.com Rev 05/03/05 Page 2 Preliminary PL623-38 Low Phase Noise XO (for 3 rd O.T.) For 65-130MHz EXTERNAL COMPONENT VALUES – 3 RD OVERTONE RESISTOR SELECTIONS This resistor is only required when a third overtone crystal is used. The chart below indicates the calculated and the nearest “E12” resistor values versus frequency for PL623-38. Frequency (MHz) R3OT (Ω) E12 Pick KΩ Frequency (MHz) R3OT (Ω) E12 Pick KΩ 65 67.5 70 75 77.5 80 82.5 85 87.5 90 92.5 95 97.5 2,162 2,082 2,008 1,875 1,815 1,758 1,705 1,654 1,607 1,563 1,520 1,480 1,442 2.2 2.2 2.2 1.8 1.8 1.8 1.8 1.8 1.5 1.5 1.5 1.5 1.5 100 102.5 105 107.5 110 112.5 115 117.5 120 122.5 125 127.5 130 1,406 1,372 1,339 1,308 1,278 1,250 1,223 1,197 1,172 1,148 1,125 1,103 1,082 1.5 1.5 1.2 1.2 1.2 1.2 1.2 1.2 1.2 1.2 1.2 1.2 1.0 ELECTRICAL SPECIFICATIONS 1. Absolute Maximum Ratings PARAMETERS Supply Voltage SYMBOL MIN. V DD MAX. UNITS 4.6 V Input Voltage, dc VI V SS -0.5 V DD +0.5 V Output Voltage, dc VO V SS -0.5 V DD +0.5 V Storage Temperature TS -65 150 °C Ambient Operating Temperature TA -40 +85 °C 2 kV Input Static Discharge Voltage Protection Exposure of the device under conditions beyond the limits specified by Maximum Ratings for extended periods may cause permanent damage to the device and affect product reliability. These conditions represent a stress rating only, and functional operations of the device at these or any other conditions above the operational limits noted in this specification is not implied. 47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991 www.phaselink.com Rev 05/03/05 Page 3 PL623-38 Preliminary Low Phase Noise XO (for 3 rd O.T.) For 65-130MHz 2. Crystal Specifications Name Symbol Conditions Parallel Resonant mode Min. Max. Units N/A 3 rd Overtone Load capacitance (capacitance on built-in on die seen by crystal) CL Inter-electrode capacitance Equivalent Series Resistance Die only, no bond wire, no package 5 pF C0 4 pF ESR 35 Ω 130 MHz 3 rd Overtone Oscillation Frequency 65 3. General Electrical Specifications SYMBO L CONDITIONS Supply Current (Loaded Outputs) I DD PECL Operating Voltage V DD PARAMETERS MIN. 2.25 @ Vdd – 1.3V (PECL) Output Clock Duty Cycle TYP. 45 50 MAX. UNITS 85/55 mA 3.63 V 55 % ±50 Short Circuit Current mA 4. Jitter Specifications PARAMETERS Period jitter RMS at 106.25MHz CONDITIONS MIN. TYP. MAX. 2.0 Period jitter peak-to-peak at 106.25MHz With capacitive decoupling between VDD and GND. Integrated jitter RMS at 106.25MHz Integrated 12 kHz to 20 MHz UNITS ps 17.0 0.3* ps *Measured on Agilent E5500. 5. Phase Noise Specifications PARAMETERS FREQUENCY @10Hz @100Hz @1kHz @10kHz @100kHz UNITS Phase Noise vs. carrier with fund. crystal. 106.25MHz -55 -90 -110 -135 -145 dBc/Hz *: Note: Phase noise to be measured. Based on P520-20 product (fundamental 155MHz VCXO). 47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991 www.phaselink.com Rev 05/03/05 Page 4 Preliminary PL623-38 Low Phase Noise XO (for 3 rd O.T.) For 65-130MHz 8. PECL Electrical Characteristics PARAMETERS SYMBOL CONDITIONS MIN. Output High Voltage V OH V DD – 1.025 Output Low Voltage V OL R L = 50 Ω to (V DD – 2V) (see figure) MAX. UNITS V V DD – 1.620 V 9. PECL Switching Characteristics PARAMETERS SYMBOL CONDITIONS MIN. TYP. MAX. UNITS Clock Rise Time tr @20/80% - PECL 0.2 0.4 ns Clock Fall Time tf @80/20% - PECL 0.2 0.4 ns PECL Levels Test Circuit OUT PECL Output Skew OUT VDD 50Ω 2.0V 50% 50Ω OUT tSKEW OUT PECL Transistion Time Waveform DUTY CYCLE 45 - 55% 55 - 45% OUT 80% 50% 20% OUT tR tF 47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991 www.phaselink.com Rev 05/03/05 Page 5 Preliminary PL623-38 Low Phase Noise XO (for 3 rd O.T.) For 65-130MHz ORDERING INFORMATION For part ordering, please contact our Sales Department: 47745 Fremont Blvd., Fremont, CA 94538, USA Tel: (510) 492-0990 Fax: (510) 492-0991 PART NUMBER The order number for this device is a combination of the following: Device number, Package type and Operating temperature range PL623-38 D X TEMPERATURE PART NUMBER C= COMMERCIAL I= INDUSTRIAL PACKAGE TYPE D=DIE Order Number Marking Package Option PL623-38DC P623-38 Waffle Pack PhaseLink Corporation, reserves the right to make changes in its products or specifications, or both at any time without notice. The information furnished by Phaselink is believed to be accurate and reliable. However, PhaseLink makes no guarantee or warranty concerning the accuracy of said information and shall not be responsible for any loss or damage of whatever nature resulting from the use of, or reliance upon this product. LIFE SUPPORT POLICY: PhaseLink’s products are not authorized for use as critical components in life support devices or systems without the express written approval of the President of PhaseLink Corporation. 47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991 www.phaselink.com Rev 05/03/05 Page 6