APU428
4-Bit Micro-controller With LCD Driver
Features
y Built-in EL-light driver, alarm, frequency or
melody generator (MUX with IOB/ SEG41, 42)
y Built-in R to F converter circuit (MUX with
IOA/SEG37~40)
y Built-in comparator, 6/8-bit PWM output, 4-bit
D/A converter, low-battery detector; this
structure can be used as a 4/6/8-bit full range
ADC
Ϋʳ Port PWM 2 pins (MUX with SEG35, 36)
Ϋʳ Port ADC 4 pins (MUX with IOC)
y 2 6-bit programmable timers with programmable
clock source
y Watchdog timer
y LCD/LED driver output
Ϋʳ 42 LCD/LED driver outputs (up to 168 LCD
segments are drivable)
Ϋʳ Mask option is used to select static, 1/2 bias
1/2 duty, 1/2 bias 1/3 duty, 1/2 bias 1/4 duty,
1/3 bias 1/3 duty and 1/3 bias 1/4 duty drive
modes of the LCD panel
Ϋʳ Mask option is used to select DC output,
and static, 1/2 duty, 1/3 duty and 1/4 duty
drive modes of the LED panel
Ϋʳ Mask option is used to select SEG28~32 as
P open-drain DC outputs
Ϋʳ Single instruction stops all segments that
are either in LCD or LED
y Built-in voltage doubler, halver, tripler charge
pump circuit
y Dual clock operation
y HALT function
y Stop function
y Low power dissipation
y Powerful instruction set (148 instructions)
Ϋʳ Binary addition, subtraction, BCD
adjustment, logical operation in direct
addressing mode and index
Ϋʳ addressing mode
Ϋʳ Single-bit manipulation (set, reset, decision
for branch)
Ϋʳ Various conditional branches
Ϋʳ 16 working registers and manipulation
Ϋʳ LCD driver data transfer
Ϋʳ Look-up table
Ϋʳ Programmable option
Ϋʳ System clock selection
y Memory capacity
Ϋʳ Instruction ROM capacity 2048 x 16 bits
Ϋʳ Index ROM capacity 256 x 8 bits
Ϋʳ Internal RAM capacity 256 x 4 bits
(low-address 128 nibbles can be accessed
by direct addressing, full-range 256 nibbles
can be accessed by index addressing)
y Input/output ports
Ϋʳ Port IOA 4 pins (with internal pull-low,
chattering clock, MUX with CX, RR, RT, RH/
SEG 37~40 by mask option)
Ϋʳ Port IOB 4 pins (MUX with ELC, ELP, BZB,
BZ/SEG41, 42 by mask option)
Ϋʳ Port IOC 4 pins (with internal pull-low,
low-level hold, chattering clock, MUX option
with AN1~4 by mask option)
Ϋʳ Port IOD 4 pins (MUX with PWM1,
2/SEG33~36 by mask option)
y 8-level subroutine nesting
y Interrupt function
Ϋʳ External factor 2 (INT pin & port IOA, IOC
input)
Ϋʳ Internal factor 4 (predivider, 2 timers & RFC)
General Description
APU428 is an embedded high-performance 4-bit
microcomputer with an LCD/LED driver. It contains
all the necessary functions in a single chip: 4-bit
parallel processing ALU, ROM, RAM, I/O ports, timer,
clock generator, dual clock, ADC, RFC, alarm,
EL-light, LCD driver, look-up table and watchdog
timer. The instruction set consists of 148 instructions
which include nibble operation, manipulation,
various conditional branch instructions and LCD
Preliminary
data transfer instructions which are powerful and
easy to follow.
The HALT function stops any internal operations other
than the oscillator, divider and LCD driver in order to
minimize the power dissipation.
The stop function stops all clocks in the chip.
1
Ver. 0.0
APU428
Block Diagram
B1 B4
A1 A4
C1 C4
D1 D4
S E G 41 42
B -P ort
LightA larm
S E G 37 40
A -P ort
R FC
C -P ort
ADC
S E G 33 36
D -P ort
PW M
S E G 1 S E G 42
COM 1 4
VD D 1 3
LC D D river
S egm entP LA
4-B itD ata B us
Index
M ask R O M
128 x 8 B its
P re-D ivider
W atchdog
T im er
O scillator
D ata R A M
(Index (L))
128 x 4 B its
6-B itP reset
T im er
8-Levels S tack
Instruction
D ecoder
C ontrol
C ircuit
11-B itP rogram
C ounter
Index S R A M
(H )
128 x 4 B its
PR O M
2048 x 16-B it
IN T
C F IN
Preliminary
C FO U T
X TO U T
X T IN
CUP 2
A LU
R ESET
CUP 1
F requency
G enerator
2
Ver. 0.0
APU428
Pad Assignment
<
APU428
;
Pad Coordinates
Pad No.
Pad Name
X
Y
Pad No.
Pad Name
X
Y
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
SEG1
SEG2
SEG3
SEG4
SEG5
SEG6
SEG7
SEG8
SEG9
SEG10
SEG11
SEG12
SEG13
SEG14
SEG15
SEG16
SEG17
SEG18
SEG19
560
675
790
905
1020
1135
1250
1365
1480
1595
1710
1840
1970
1970
1970
1970
1970
1970
1970
70
70
70
70
70
70
70
70
70
70
70
70
160
290
420
535
650
765
880
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
SEG34
SEG35
SEG36
SEG37
SEG38
SEG39
SEG40
SEG41
SEG42
IOB3
IOB4
GND
VDD
CFIN
CFOUT
XTIN
XTOUT
TESTA
RESET
1480
1365
1250
1135
1020
905
790
675
560
445
330
200
70
70
70
70
70
70
70
2265
2265
2265
2265
2265
2265
2265
2265
2265
2265
2265
2265
2175
2045
1915
1800
1685
1570
1455
Preliminary
3
Ver. 0.0
APU428
Pad No.
Pad Name
X
Y
Pad No.
Pad Name
20
21
22
23
24
25
26
27
28
29
30
31
32
33
SEG20
SEG21
SEG22
SEG23
SEG24
SEG25
SEG26
SEG27
SEG28
SEG29
SEG30
SEG31
SEG32
SEG33
1970
1970
1970
1970
1970
1970
1970
1970
1970
1970
1970
1840
1710
1595
995
1110
1225
1340
1455
1570
1685
1800
1915
2045
2175
2265
2265
2265
53
54
55
56
57
58
59
60
61
62
63
64
65
66
INT
IOM1
IOM2
IOM3
IOM4
VDD1
VDD2
VDD3
CUP1
CUP2
COM1
COM2
COM3
COM4
X
Y
70
1340
70
1225
70
1110
70
995
70
880
70
765
70
650
70
535
70
420
70
290
70
160
200
70
330
70
445
70
Chip size: 84.65 x 96.45 mil2
Pad Descriptions
Pad Name
I/O
BAK
VDD1
VDD2
VDD3
RESET
I
INT
I
TESTA
I
CUP1
CUP2
O
XIN
XOUT
CFIN
CFOUT
COM1~4
I
O
I
O
O
SEG1~42
O
IOA1~4
I/O
Preliminary
Description
Positive back-up voltage.
In Li mode, connects a 0.1u capacitance to GND.
LCD drives the voltage and positive supply voltage.
While in Ag mode, connects +1.5V to VDD1.
While in Li/ExtV mode, connects +3.0V to VDD2.
Input pin from LSI reset request signal.
Internal pull-down resistor.
Input pin for external INT request signal.
Falling or rising edge triggered by mask option.
Internal pull-down or pull-up resistor or none is selected by mask option.
Test signal input pin.
Switching pins for supplying the LCD driving voltage to the VDD1, 2, 3 pins.
Connects the CUP1 and CUP2 pins with nonpolarized electrolytic capacitor if
1/2 or 1/3 bias mode has been selected.
In the static mode, these pins should be open.
Time-based counter frequency (clock-specified, LCD alternating frequency,
alarm signal frequency) or system clock oscillation. 32kHz crystal oscillator.
Oscillation stops at the execution of STOP instruction.
System clock oscillation.
Connected with ceramic resonator.
Connected with RC oscillation circuit.
Oscillation stops at the execution of STOP or SLOW instruction.
Output pins for supplying voltage to drive the common pins of the LCD or LED
panel.
Output pins for LCD or LED panel segment.
Input/Output port A can use software to define the internal pull-low resistor and
chattering clock in order to reduce input bounce and generate interrupt.
This port shares pins with SEG37~40 and is set by mask option.
This port also shares pins with CC, RR, RT and RH, and is set by mask option.
4
Ver. 0.0
APU428
Pad Name
I/O
IOB1~4
I/O
IOC1~4
I/O
IOD1~4
I/O
RFC
RR
RT
RH
EL
ELP
CC
ALM
Z
BZB
ELC
GND
Preliminary
I
O
O
O
O
O
O
O
Description
I/O Input/Output port B.
IOB1, 2 shares pins with SEG41, 42, or ELC, ELP and is set by mask option.
IOB3, 4 shares pins with BZ, BZB and is set by mask option.
I/O Input/Output port C can use software to define the internal pull-low/
low-level hold resistor and chattering clock in order to reduce input bounce and
generate interrupt. This port shares pins with AN1-4 and is set by mask option.
Input / Output port D.
This port shares pins with SEG33~36 and is set by mask option.
IOD3,4 shares pins with PWM1,2 and is set by mask option.
1 input pin and 3 output pins for RFC application.
This port shares pins with SEG37~40 and is set by mask option.
This port shares pins with IOA1~4 and is set by mask option.
Output port for the EL-light.
These ports share pins with SEG41, 42 and are set by mask option.
These ports share pins with IOB1, 2 and are set by mask option.
Output port for alarm, frequency or melody generator.
This port shares pins with IOB3,4 and is set by mask option.
Negative supply voltage.
5
Ver. 0.0
APU428
Absolute Maximum Rating
Ta = 0 to 70к GND=0V
Name
Maximum Supply Voltage
Maximum Input Voltage
Maximum Output Voltage
Maximum Operating Temperature
Maximum Storage Temperature
Symbol
Rating
Unit
VDD1
VDD2
VDD3
VIN
VOUT1
VOUT2
tOPG
-0.3 ~ +5.5
-0.3 ~ +5.5
-0.3 ~ +8.5
-0.3 to VDD1/2+0.3
-0.3 to VDD1/2+0.3
-0.3 to VDD3+0.3
0 to +70
V
V
V
V
V
V
к
tSTG
-25 to +125
к
Allowable operating conditions
Name
Supply Voltage
Oscillator Start-up Voltage
Oscillator Sustain Voltage
Supply Voltage
Supply Voltage
Symbol
VDD1
VDD2
VDD3
VDDB
VDDB
Input sHs Voltage
VDD1
VDD2
VIH1
Input sLs Voltage
VIL1
Input sHs Voltage
VIH2
Input sLs Voltage
VIL2
Input sHs Voltage
VIH3
Input sLs Voltage
VIL3
Input sHs Voltage
VIH4
Input sLs Voltage
VIL4
Input sHs Voltage
VIH5
Input sLs Voltage
VIL5
Input sHs Voltage
VIH6
Input sLs Voltage
VIL6
Operating Freq.
fOPG1
fOPG2
fOPG3
Preliminary
Ta = 0 to 70к GND=0V
Condition
Crystal Mode
Crystal Mode
Ag Mode
EXT-V, Li Mode
Ag Battery Mode
Li Battery Mode
OSCIN at Ag Battery Mode
OSCIN at Li Battery Mode
CFIN at Li Battery or EXT-V Mode
RC Mode
Crystal Mode
External RC Mode
CF Mode
6
Min.
Max.
Unit
1.2
2.4
2.4
1.3
1.2
5.25
5.25
8.0
V
V
V
V
V
1.2
2.4
VDD1-0.7
1.65
5.25
VDD1+0.7
V
V
V
-0.7
0.7
V
VDD2-0.7
VDD2+0.7
V
-0.7
0.7
V
0.8VDD1
VDD1
V
0
0.2VDD1
V
0.8VDD2
VDD2
V
0
0.2VDD2
V
0.8VDD2
VDD2
V
0
0.2VDD2
V
0.8VDDO
VDDO
V
0
0.2VDDO
V
32
32
1000
3580
1000
3580
kHz
kHz
kHz
Ver. 0.0
APU428
Electrical Characteristics
Ta=0 to 70к
Input resistance
Name
sLs-Level Hold tR
(IOC)
IOC/IOA Pull-Down tR
INT Pull-Up tR
INT Pull-Down tR
RES Pull-Down tR
Symbol
Condition
Min.
Typ.
Max.
Unit
RIIH1
VI=0.2VDD1, #1
10
40
100
k:
RIIH2
VI=0.2VDD2, #2
10
40
100
k:
RIIH3
VI=0.2VDD2, #3
5
20
50
k:
RMSD1
VI=VDD1, #1
200
500
1000
k:
RMSD2
VI=VDD2, #2
200
500
1000
k:
RMSD3
VI=VDD3, #3
100
250
500
k:
RINTU1
VI=VDD1, #1
200
500
1000
k:
RINTU2
VI=VDD2, #2
200
500
1000
k:
RINTU3
VI=VDD3, #3
100
250
500
k:
RINTD1
VI=GND, #1
200
500
1000
k:
RINTD2
VI=GND, #2
200
500
1000
k:
RINTD3
VI=GND, #3
100
250
500
k:
RRES1
VI=GND or VDD1, #1
5
20
50
k:
RRES2
VI=GND or VDD2, #2
5
20
50
k:
RRES3
VI=GND or VDD2, #3
5
20
50
k:
Note: #1: VDD1= 1.2V ( Ag ), #2: VDD2= 2.4V ( Li ), #3: VDD2= 4V (Ext-V).
DC output characteristics
Name
Output sHs Voltage
Output sLs Voltage
Output sHs Voltage
Output sLs Voltage
Symbol
Min.
Typ.
Max.
Unit
IOH=-10PA, #1
0.8
0.9
1.0
V
VOH2 a
IOH=-50PA, #2
1.5
1.8
2.1
V
VOH3 a
IOH=-200PA, #3
2.5
3
3.5
V
VOL1 a
IOL=20PA, #1
0.2
0.3
0.4
V
VOL2 a
IOL=100PA, #2
0.3
0.6
0.9
V
VOL3 a
IOL=400PA, #3
0.5
1.0
1.5
V
VOH1c
IOH=-200PA, #1
IOH=-1mA, #2
IOH=-3mA, #3
VOH1a
VOH2c
VOH3c
VOL1c
VOL2c
VOL3c
Condition
For
SEG1~
SEG32
SEG33~
SEG42,
IOB3~4,
IOC-n
IOL=400PA, #1
IOL=2mA, #2
IOL=6mA, #3
0.8
0.9
1.0
V
1.5
2.5
0.2
1.8
3
0.3
2.1
3.5
0.4
V
V
V
0.3
0.5
0.6
1.0
0.9
1.5
V
V
Note: #1: VDD1= 1.2V ( Ag ), #2: VDD2= 2.4V ( Li ), #3: VDD2= 4V (Ext-V).
Preliminary
7
Ver. 0.0
APU428
Segment driver output characteristics
Name
Static display mode
Output sHs Voltage
Output sLs Voltage
Output sHs Voltage
Output sLs Voltage
Symbol
Condition
For
VOH1d
VOH2d
VOH3d
VOL1d
VOL2d
VOL3d
VOH1e
VOH2e
VOH3e
VOL1e
VOL2e
VOL3e
IOH=-1PA, #1
IOH=-1PA, #2
IOH=-1PA, #3
IOL=1PA, #1
IOL=1PA, #2
IOL=1PA, #3
IOH=-10PA, #1
IOH=-10PA, #2
IOH=-10PA, #3
IOL=10PA, #1
IOL=10PA, #2
IOL=10PA, #3
VOH12f
VOH3f
VOL12f
VOL3f
VOH12g
VOH3g
VOM12g
VOM3g
VOL12g
VOL3g
IOH=-1PA, #1, #2
IOH=-1PA, #3
IOL=1PA, #1, #2
IOL=1PA, #3
IOH=-10PA, #1, #2
IOH=-10PA, #3
IOI/H=r10PA, #1, #2
IOI/H=r10PA, #3
IOL=10PA, #1, #2
IOL=10PA, #3
VOH12i
VOH3i
VOM12i
VOM13i
VOM22i
VOM23i
VOL12i
VOL3i
VOH12j
VOH3j
VOM12j
VOM13j
VOM22j
VOM23j
VOL12j
VOL3j
IOH=-1PA, #1, #2
IOH=-1PA, #3
IOI/H=r10PA, #1, #2
IOI/H=r10PA, #3
IOI/H=r10PA, #1, #2
IOI/H=r10PA, #3
IOL=1PA, #1, #2
IOL=1PA, #3
IOH=-10PA, #1, #2
IOH=-10PA, #3
IOI/H=r10PA, #1, #2
IOI/H=r10PA, #3
IOI/H=r10PA, #1, #2
IOI/H=r10PA, #3
IOL=10PA, #1, #2
IOL=10PA, #3
SEG-n
COM-n
Min.
Typ.
Max.
1.0
2.2
3.8
0.2
0.2
0.2
1.0
2.2
3.8
0.2
0.2
0.2
Unit
V
V
V
V
V
V
V
V
V
V
V
V
1/2 bias display mode
Output sHs Voltage
Output sLs Voltage
Output sHs Voltage
Output sMs Voltage
Output sLs Voltage
SEG-n
COM-n
2.2
3.8
0.2
0.2
2.2
3.8
1.0
1.8
1.4
2.2
0.2
0.2
V
V
V
V
V
V
V
V
V
V
1/3 bias display mode
Output sHs Voltage
Output sM1s Voltage
Output sM2s Voltage
Output sLs Voltage
Output sHs Voltage
Output sM1s Voltage
Output sM2s Voltage
Output sLs Voltage
SEG-n
COM-n
3.4
5.8
1.0
1.8
2.2
3.8
3.4
5.8
1.0
1.8
2.2
3.8
1.4
2.2
2.6
4.2
0.2
0.2
1.4
2.2
2.6
4.2
0.2
0.2
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
Note: #1: VDD1= 1.2V ( Ag ), #2: VDD2= 2.4V ( Li ), #3: VDD2= 4V (Ext-V).
Preliminary
8
Ver. 0.0
APU428
Functional Description
Index SRAM
The 256 X 4 bits index SRAM is used for applications that need more SRAM or need to load addresses by
operation, and data SRAM is included at a lower-half address in the index SRAM.
Index ROM
The 256 X 8 bits index ROM can be used in the 4-bit or 8-bit mode.
I/O ports
The IOA port can be selected by software separately as input or output. It can also be selected with/without
internal pull-low and different chattering clocks for a HALT release / interrupt trigger in order to reduce the
input bounce for the key scan:
PH6: 512Hz, PH8: 128Hz, PH10: 32Hz.
The pull-low of IOA will be masked off for those pins defined as output pins:
The IOA port can be used as a pseudo serial output port.
The IOB port can be selected by software separately as input or output.
Th e IOC port can be selected by software separately as input or output, and with/without internal pull-low and
different chattering clocks for a HALT release /interrupt trigger in order to reduce the bounce of the key scan.
The pull-low of the IOC will be masked off for those pins defined as output pins.
The IOD port can be selected by software separately as input or output.
The IOD port can be used as a pseudo serial output port.
The initial state of all I/O ports is the standard input state, and IOA and C have pull-low.
Before setting the I/O ports from input to output, execute the output function first to ensure the output state.
Resistor to frequency converter
We use an RC oscillation circuit and a 16-bit counter to calculate the relative resistance of temperature and
humidity sensor. The diagram is shown below:
ELP
RTP
TMS
ENX
RT
EHM
RHM
PH9
Timer & R/F
Controller
MRF
RH
FIN
ERR
Rref
Freq.
CL
LD
Freq.
CL
LD
RR
ENX
CX
FIN
CX
16-Bit Counter
4-Bit Data Bus
There are 2 methods for measuring the input frequency. First, set FIN (i.e. CX) as the clock input and use
timer 2 or the software directly as interval control. Second, if the FIN (CX) frequency is too low (either because
of a poor resolution for a fixed interval or a longer interval for better resolution but a longer read-out rate,
ex.10 seconds per read-out), you can switch the measure mode to set FIN (CX) as the interval control. It will
Preliminary
9
Ver. 0.0
APU428
enable the counter from the first FIN rising edge to the next rising edge, then will generate an interrupt. It may
also use FREQ (internal frequency generator output) as clock input, hence counting the CX interval. For
measuring the resistor value of the temperature and humidity sensor, we must first measure the frequency of
Rref, then the frequency of Sensor:
Fref= K / Rref CX and
Fsensor= K / Rsensor CX, hence
Rsensor = Rref * Freq / Fsensor.
The CX input can be used as a clock counter.
Analog-to-Digital converter
The diagram is shown below:
LHCP
ENCP
AN1
ADF1
AN2
ADF2
AN3
ADF3
AN4
2 o 1
Analog Switch
ADF4
2 o 1
Analog Switch
LBR
Low Battery
Reference
ENLBR
DAC
4-Bit Ladder
DAC
ENDAC
MDA
0 1 2 3
MPW1
6 / 8-Bit
PWM DAC
MPW1
0 1 2 3 4 5 6 7
MPW2
6 / 8-Bit
PWM DAC
MPW2
0 1 2 3 4 5 6 7
The use of these blocks is illustrated below:
y Comparator: Sets negative input as AN4, compare with AN1, 2, 3.
y 4-bit ADC: Sets negative input as internal 4-bit DAC, positive input as AN4, software control for AN1, 2, 3,
4 analog value archive.
y Low battery detector: Sets negative input as internal 4-bit DAC, positive input as LBR (low battery
reference). If the DAC level is lower than LBR, it means there is a low-battery condition.
y PWM DAC output: With an external RC network, 6-bit or 8-bit PWM DAC can be used.
y 6-bit/ 8-bit ADC: Sets negative input as AN4, connects from PWM with an external RC network. You can
get analog value from AN1, 2, 3.
y Supply voltage measurement: Sets negative input as AN4, connects from PWM with an external RC
network, positive input is LBR. If comparative data is N, the supply voltage is LBR (about 1.26V) * 255 / N.
Note: The internal 4-bit DAC level is 1/32 VDD for 0, 3/32 for 1, 29/32 for E and 31/32 for F. The level of 6-bit
PWM is 0/63, 1/63, 62/63 and 63/63, and the level of 8-bit PWM is 0/255, 1/255, 254/255 and 255/255.
Preliminary
10
Ver. 0.0
APU428
An example of ADC timing is shown below:
TCK4
IR
SAD 1Bh
SAD 20h
SAD 11h
SAD 28h
SW (LBR/AN4)
LBR
LBR
AN4
AN4
SW (AN4/DAC)
DAC
DAC
DAC
DAC
En LBR
En DAC
LHCP
T1h
ENCP
Note: Power Supply = 1.2V T1h needs 5ms
Power Supply = 2.4V T1h needs 10Ps
EL-light
Sets ELC and ELP clock and duty cycle using ELC X instruction, then turn on and off ELC and ELP output by
SF X and RF X instruction. With external transistor, diode, inductor and resistor, we can pump the EL panel to
AC 100~250V.
L1
D1
R1
ELP
Q1
EL-plane
R2
Q2
ELC
LIT
ELP
ELC
When the EL-light is turned on, the ELC will turn on before ELP, but when the EL-light is off, the ELP and ELC
will turn off after the next falling edge of ELC in order to make sure no voltage is left on the EL plane.
Timer
The 6-bit programmable timer can select PH3/PH9/PH15/FREQ (Timer 2 can also select PH5/PH7/PH11/
PH13 by TM2X instruction) as the clock source. When it underflows, HALT release signals are generated.
Preliminary
11
Ver. 0.0
APU428
Predivider
The predivider is a 15-sage counter that uses PH0 as clock source. The output of T-FF is changed when the
input signal is changed from H to L. PH11~15 are reset to L when PLC 100H instruction is executed,
power-on reset or external reset is used. When PH14 is changed from H to L, the HALT release signal is
generated.
Alarm/frequency/melody
There is an 8-bit programmable counter and an 8-bit envelope control for alarm, frequency or melody output
from BZ/BZB.
The frequency counter can use software to select 1/2 duty, 1/3 duty,1/4 duty drive modes.
Frequency
1/2 Duty Frequency
1/3 Duty Frequency
1/4 Duty Frequency
INT function
The INT pin can be selected by mask option as pull-high/pull-low or none, and as a rising edge/falling edge
trigger.
Watchdog Timer
The watchdog timer automatically generates a device reset when it overflows. The interval of overflow is
8/64/512 x PH10 (set by mask option). You can use software to enable and disable this function. The
watchdog enable flag will be disabled by power on reset or reset pin reset condition, but cannot be disabled
by watchdog reset itself.
HALT function
The HALT instruction disables all clocks except the predivider, timer, frequency counter, PWM, EL-light
generator and chattering clock in order to minimize the operating current.
STOP function
The STOP instruction disables all clocks to minimize the standby current, so only two external factors (INT,
IOA/IOC) can release the stop condition.
Instruction Table
Instruction
Machine Code
Function
NOP
LCT Lz, Ry
0000 0000 0000 0000
0000 001Z ZZZZ YYYY
No Operation
Lz Чʳ { 7SEG Чʳ Ry}
LCB Lz, Ry
0000 010Z ZZZZ YYYY
Lz Чʳ { 7SEG Чʳ Ry}
LCP Lz, Ry
0000 011Z ZZZZ YYYY
Lz Чʳ Ry , AC
LCD Lz, @HL
0000 100Z ZZZZ 0000
Lz Чʳ T@HL
OPA Rx
0000 1010 0XXX XXXX
Port(A) Чʳ Rx
OPAS Rx, D
0000 1011 DXXX XXXX
A1, 2, 3, 4 Чʳ Rx0, Rx1, D, Pulse
OPB Rx
0000 1100 0XXX XXXX
Port(B) Чʳ Rx
Preliminary
12
Flag/Remark
Ver. 0.0
APU428
Instruction
Machine Code
Function
Flag/Remark
OPC Rx
0000 1101 0XXX XXXX
Port(C) Чʳ Rx
OPD Rx
0000 1110 0XXX XXXX
Port(D) Чʳ Rx
OPDS Rx
0000 1111 DXXX XXXX
D1, 2, 3, 4 Чʳ Rx0, Rx1, D, Pulse
FRQ Rx, D
0001 00DD 0XXX XXXX
FRQ D,@HL
0001 01DD 0000 0000
FREQ Чʳ Rx, AC
DD=00: 1/4 Duty
DD=01: 1/3 Duty
DD=10: 1/2 Duty
FREQ Ч T@HL
FRQX D,X
0001 10DD XXXX XXXX
FREQ Ч X
MVL Rx
0001 1100 0XXX XXXX
L Ч Rx
MVH Rx
0001 1101 0XXX XXXX
H Ч Rx
MPW1 Rx
0001 1110 0XXX XXXX
PWM1 Ч Rx , AC
MPW2 Rx
0001 1111 0XXX XXXX
PWM2 Ч Rx , AC
ADC Rx
0010 0000 0XXX XXXX
AC Ч Rx+AC+CF
CF
ADC @HL
0010 0000 1000 0000
AC Ч @HL+AC+CF
CF
ADC* Rx
0010 0001 0XXX XXXX
AC, Rx Ч Rx+AC+CF
CF
ADC* @HL
0010 0001 1000 0000
AC, @HL Ч @HL+AC+CF
CF
SBC Rx
0010 0010 0XXX XXXX
AC Ч Rx+ACB+CF
CF
SBC @HL
0010 0010 1000 0000
AC Ч @HL+ACB+CF
CF
SBC* Rx
0010 0011 0XXX XXXX
AC, Rx Ч Rx+ACB+CF
CF
SBC* @HL
0010 0011 1000 0000
AC, @HL Ч @HL+ACB+CF
CF
ADD Rx
0010 0100 0XXX XXXX
AC Ч Rx+AC
CF
ADD @HL
0010 0100 1000 0000
AC Ч @HL+AC
CF
ADD* Rx
0010 0101 0XXX XXXX
AC,Rx Ч Rx+AC
CF
ADD* @HL
0010 0101 1000 0000
AC, @HL Ч @HL+AC
CF
SUB Rx
0010 0110 0XXX XXXX
AC Ч Rx+ACB+1
CF
SUB @HL
0010 0110 1000 0000
AC Ч @HL+ACB+1
CF
SUB* Rx
0010 0111 0XXX XXXX
AC, Rx Ч Rx+ACB+1
CF
SUB* @HL
0010 0111 1000 0000
AC,@HL Ч @HL+ACB+1
CF
ADN Rx
0010 1000 0XXX XXXX
AC Ч Rx+AC
ADN @HL
0010 1000 1000 0000
AC Ч @HL+AC
ADN* Rx
0010 1001 0XXX XXXX
AC, Rx Ч Rx+AC
ADN* @HL
0010 1001 1000 0000
AC,@HL Ч @HL+AC
AND Rx
0010 1010 0XXX XXXX
AC Ч Rx AND AC
AND @HL
0010 1010 1000 0000
AC Ч @HL AND AC
AND* Rx
0010 1011 0XXX XXXX
AC, Rx Ч Rx AND AC
AND* @HL
0010 1011 1000 0000
AC,@HL Ч @HL AND AC
EOR Rx
0010 1100 0XXX XXXX
AC Ч Rx EXOR AC
EOR @HL
0010 1100 1000 0000
AC Ч @HL EXOR AC
EOR* Rx
0010 1101 0XXX XXXX
AC, Rx Ч Rx EXOR AC
EOR* @HL
0010 1101 1000 0000
AC,@HL Ч @HL EXOR AC
Preliminary
13
Ver. 0.0
APU428
Instruction
Machine Code
Function
Flag/Remark
OR Rx
0010 1110 0XXX XXXX
AC Ч Rx OR AC
OR @HL
0010 1110 1000 0000
AC Ч @HL OR AC
OR* Rx
0010 1111 0XXX XXXX
AC, Rx Ч Rx OR AC
OR* @HL
0010 1111 1000 0000
AC,@HL Ч @HL OR AC
ADCI Ry,D
0011 0000 DDDD YYYY
AC Ч Ry+D+CF CF
ADCI* Ry,D
0011 0001 DDDD YYYY
AC, Ry Ч Ry+D+CF
CF
SBCI Ry,D
0011 0010 DDDD YYYY
AC Ч Ry+DB+CF
CF
SBCI* Ry,D
0011 0011 DDDD YYYY
AC, Ry Ч Ry+DB+CF
CF
ADDI Ry,D
0011 0100 DDDD YYYY
AC Ч Ry+D
CF
ADDI* Ry,D
0011 0101 DDDD YYYY
AC, Ry Ч Ry+D
CF
SUBI Ry,D
0011 0110 DDDD YYYY
AC Ч Ry+DB+1
CF
SUBI* Ry,D
0011 0111 DDDD YYYY
AC, Ry Ч Ry+DB+1
CF
ADNI Ry,D
0011 1000 DDDD YYYY
AC Ч Ry+D
ADNI* Ry,D
0011 1001 DDDD YYYY
AC, Ry Ч Ry+D
ANDI Ry,D
0011 1010 DDDD YYYY
AC Ч Ry AND D
ANDI* Ry,D
0011 1011 DDDD YYYY
AC, Ry Ч Ry AND D
EORI Ry,D
0011 1100 DDDD YYYY
AC Ч Ry EXOR D
EORI* Ry,D
0011 1101 DDDD YYYY
AC, Ry Ч Ry EXOR D
ORI Ry,D
0011 1110 DDDD YYYY
AC Ч Ry OR D
ORI* Ry,D
0011 1111 DDDD YYYY
AC, Ry Ч Ry OR D
INC* Rx
0100 0000 0XXX XXXX
AC, Rx Ч Rx+1
INC* @HL
0100 0000 1000 0000
AC, @HL Ч @HL+1
DEC* Rx
0100 0001 0XXX XXXX
AC, Rx Ч Rx-1
DEC* @HL
0100 0001 1000 0000
AC, @HL Ч @HL-1
IPA Rx
0100 0010 0XXX XXXX
AC, Rx Ч Port(A)
IPB Rx
0100 0100 0XXX XXXX
AC, Rx Ч Port(B)
IPC Rx
0100 0111 0XXX XXXX
AC, Rx Ч Port(C)
IPD Rx
0100 1000 0XXX XXXX
AC, Rx Ч Port(D)
MAF Rx
0100 1010 0XXX XXXX
AC,Rx Ч STS1
MSB Rx
0100 1011 0XXX XXXX
AC,Rx Ч STS2
MSC Rx
0100 1100 0XXX XXXX
AC,Rx Ч STS3
MCX Rx
0100 1101 0XXX XXXX
AC,Rx Ч STS3X
Preliminary
14
B3: CF
B2: AC=0
B1: (No use)
B0: (No use)
B3: (No use)
B2: SCF2(HRx)
B1: SCF1(CPT)
B0: BCF
B3: SCF7(PDV)
B2: PH15
B1: SCF5(TMR1)
B0: SCF4(INT)
B3: SCF9(RFC)
B2: SCF0(APT)
B1: SCF6(TMR2)
B0: (No use)
Ver. 0.0
APU428
Instruction
Machine Code
Function
MSD Rx
0100 1110 0XXX XXXX
AC,Rx Ч STS4
MDX Rx
0100 1111 0XXX XXXX
AC,Rx Ч STS4X
SR0 Rx
0101 0000 0XXX XXXX
ACn, Rxn Ч Rx(n+1)
AC3, Rx3 Ч 0
SR1 Rx
0101 0001 0XXX XXXX
ACn, Rxn Ч Rx(n+1)
AC3, Rx3 Ч 1
SL0 Rx
0101 0010 0XXX XXXX
ACn, Rxn Ч Rx(n-1)
AC0, Rx0 Ч 0
SL1 Rx
0101 0011 0XXX XXXX
Can, Rxn Ч Rx(n-1)
AC0, Rx0 Ч 1
DAA
0101 0100 0000 0000
AC Ч BCD(AC)
DAA* Rx
0101 0101 0XXX XXXX
AC, Rx Ч BCD(AC)
DAA* @HL
0101 0101 1000 0000
AC, @HL Ч BCD(AC)
DAS
0101 0110 0000 0000
AC Ч BCD(AC)
DAS* Rx
0101 0111 0XXX XXXX
AC, Rx Ч BCD(AC)
DAS* @HL
0101 0111 1000 0000
AC, @HL Ч BCD(AC)
LDS Rx,D
0101 1DDD DXXX XXXX AC, Rx Ч D
LDH Rx,@HL
0110 0000 0XXX XXXX
AC, Rx Ч H(T@HL)
LDH* Rx,@HL
0110 0001 0XXX XXXX
AC, Rx Ч H(T@HL)
HL Ч HL + 1
LDL Rx,@HL
0110 0010 0XXX XXXX
AC, Rx Ч L(T@HL)
LDL* Rx,@HL
0110 0011 0XXX XXXX
AC, Rx Ч L(T@HL)
HL Ч @HL + 1
MRF1 Rx
0110 0100 0XXX XXXX
AC,Rx Ч RFC3-0
MRF2 Rx
0110 0101 0XXX XXXX
AC,Rx Ч RFC7-4
MRF3 Rx
0110 0110 0XXX XXXX
AC,Rx Ч RFC11-8
MRF4 Rx
0110 0111 0XXX XXXX
AC,Rx Ч RFC15-12
STA Rx
0110 1000 0XXX XXXX
Rx Ч AC
STA @HL
0110 1000 1000 0000
@HL Ч AC
LDA Rx
0110 1100 0XXX XXXX
AC Ч Rx
LDA @HL
0100 1100 1000 0000
AC Ч @HL
MRA Rx
0110 1101 0XXX XXXX
CF Ч Rx3
MRW @HL,Rx
0110 1110 0XXX XXXX
AC,@HL Ч Rx
MWR Rx,@HL
0110 1111 0XXX XXXX
AC,Rx Ч @HL
MRW Ry,Rx
0111 0YYY YXXX XXXX
AC,Ry Ч Rx
MWR Rx,Ry
0111 1YYY YXXX XXXX
AC,RxҏЧҏRy
JB0 X
1000 0XXX XXXX XXXX
PC Ч X
Preliminary
15
Flag/Remark
B3: (No use)
B2: RFOVF
B1: WDF
B0: CSF
B3: ADF4
B2: ADF3
B1: ADF2
B0: ADF1
CF
if AC0 = 1
Ver. 0.0
APU428
Instruction
Machine Code
Function
Flag/Remark
JB1 X
1000 1XXX XXXX XXXX
PC Ч X
if AC1 = 1
JB2 X
1001 0XXX XXXX XXXX
PC Ч X
if AC2 = 1
JB3 X
1001 1XXX XXXX XXXX
PC Ч X
if AC3 = 1
JNZ X
1010 0XXX XXXX XXXX
PC Ч X
if AC z 0
JNC X
1010 1XXX XXXX XXXX
PC Ч X
if CF = 0
JZ X
1011 0XXX XXXX XXXX
PC Ч X
if AC = 0
JC X
1011 1XXX XXXX XXXX
PC Ч X
if CF = 1
CALL X
1100 0XXX XXXX XXXX
STACK Ч PC+1
PC Ч X
JMP X
1101 0XXX XXXX XXXX
PC Ч X
RTS
1101 1000 0000 0000
PC Ч STACK
SCC X
1101 1001 0X0X 0XXX
SCA X
1101 1010 00XX 0000
SAD X
1101 1011 00XX XXXX
SPA X
1101 1100 000X XXXX
SPB X
1101 1101 0000 XXXX
SPC X
1101 1110 000X XXXX
SPD X
TMS Rx
1101 1111 0000 XXXX
1110 0000 0XXX XXXX
X6 = 1: Cfq = BCLK
X6 = 0: Cfq = PH0
X5 = 1: Cpw = BCLK
X5 = 0: Cpw = PH0
X,4 = 1: Set P(A)
X,4 = 0: Set P(C)
X2,1,0=001: Cch = PH10
X2,1,0=010: Cch = PH8
X2,1,0=100: Cch = PH6
X5: A1-4 Enable (SEF5)
X4: C1-4 Enable (SEF4)
X5: Enable Cmp. output
X4: Latch Data to Cmp.
X3=1: CP4(+) = LBR
X3=0: CP4(+) = AN4
X2=1: CP1~4(-) = AN4
X2=0: CP1~4(-) = DAC
X1: Enable LBR
X0: Enable DAC
X4: Set A4~1 Pull-Low
X3~0: Set A4~1 I/O
X3~0: Set B4~1 I/O
X4: Set C4-1 Pull-Low
/Low-Level-Hold
X3~0: Set C4-1 I/O
X3-0: Set D4~1 I/O
Timer1 Ч Rx, AC
TMS @HL
1110 0001 0000 0000
Timer1 Ч T@HL
TMSX
MDA Rx
X7,6=11: Ctm=FREQ
X7,6=10: Ctm=PH15
X 1110 0010 XXXX XXXX X7,6=01: Ctm=PH3
X7,6=00: Ctm=PH9
X5~0: Set Timer1 Value
1110 0011 0XXX XXXX
DACҏЧҏRx
TM2 Rx
1110 0100 0XXX XXXX
Timer2ҏЧҏRx, AC
TM2 @HL
1110 0101 0000 0000
Timer2ҏЧҏT@HL
Preliminary
16
CALL Return
Ver. 0.0
APU428
Instruction
Machine Code
TM2X X
1110 011X XXXX XXXX
SHE X
1110 1000 0XXX XXX0
SIE* X
1110 1001 0XXX XXXX
PLC X
1110 101X 0XXX XXXX
SRF X
1110 1100 00XX XXXX
SRE X
1110 1101 X0XX 0000
FAST
SLOW
1110 1110 0000 0000
1110 1111 0000 0000
SF X
1111 0000 X00X XXXX
RF X
1111 0100 X00X 0XXX
SF2 X
1111 1000 0000 0XXX
RF2 X
1111 1001 0000 0XXX
Preliminary
Function
X8,7,6=111 : Ctm=PH13
X8,7,6=110 : Ctm=PH11
X8,7,6=101 : Ctm=PH7
X8,7,6=000 : Ctm=PH5
X8,7,6=011 : Ctm=FREQ
X8,7,6=010 : Ctm=PH15
X8,7,6=001 : Ctm=PH3
X8,7,6=000 : Ctm=PH9
X5~0: Set Timer2 Value
X6: Enable HEF6(RFC)
X4: Enable HEF4(TMR2)
X3: Enable HEF3(PDV)
X2: Enable HEF2(INT)
X1: Enable HEF1(TMR1)
X6: Enable IEF6(RFC)
X4: Enable IEF4(TMR2)
X3: Enable IEF3(PDV)
X2: Enable IEF2(INT)
X1: Enable IEF1(TMR1)
X0: Enable IEF0(A,CPT)
X8: Reset PH15~11
X6, 4~0: Reset HRF6, 4~0
X5: Enable Cx Control
X4: Enable Timer2 Control
X3: Enable Counter
X2: Enable RH Output
X1: Enable RT Output
X0: Enable RR Output
X6~4: Enable SRF6~4
SCLK: High Speed Clock
SCLK: Low Speed Clock
X7: Reload Set
X4: WDT Enable
X3: HALT after EL LIGHT
X2: EL LIGHT On
X1: BCF Set
X0: CF Set
X7: Reload Reset
X4: WDT Reset
X2: EL LIGHT Off
X1: BCF Reset
X0: CF Reset
X0: Reload Set
X1: Dis-ENX Set
X2: Close all segments
X0: Reload Reset
X1: Dis-ENX Reset
X2: Release all Segments
17
Flag/Remark
ENX
EHM
ETP
ERR
SRF6 (A Port)
SRF5 (HRF2)
SRF4 (M Port)
RL1
WDF
BCF
CF
RL1
WDF
BCF
CF
RL2
DED
RSOFF
RL2
DED
RSOFF
Ver. 0.0
APU428
Instruction
ALM X
ELC X
HALT
STOP
Machine Code
1111 101X XXXX XXXX
1111 110X XXXX XXXX
1111 1110 0000 0000
1111 1111 0000 0000
Function
X8=1 BCLKX
X8=0 PH0
X7,6=11 BCLK/8
X7,6=10 BCLK/4
X7,6=01 BCLK/2
X7,6=00 BCLK
X5,4=11 1/1
X5,4=10 1/2
X5,4=01 1/3
X5,4=00 1/4
X3,2=11 PH5
X3,2=10 PH6
X3,2=01 PH7
X3,2=00 PH8
X1,0=11 1/1
X1,0=10 1/2
X1,0=01 1/3
X1,0=00 1/4
HALT operation
STOP operation
Symbol description
AC:
Accumulator
ACn:
Accumulator bit-n
X:
Address
Rx:
Memory of address X
WDF:
Watchdog timer enable flag
HL:
Index register
BCLK:
System clock address
IEFn:
Interrupt enable flag
SRFn:
Stop release enable flag
SCFn:
Start condition flag
Cch:
Clock source of chartering detector
TMR:
Timer overflow release flag
SEFn:
Switch enable flag
FREQ:
Frequency generator setting value
ADF:
ADC flag
DAC:
Digital-to-analog converter output signal
LBR:
Low-battery voltage reference
H:
High address of index
HT@HL: High nibble of index ROM
Preliminary
Flag/Remark
X8,7,6=111: FREQ
X8,7,6=100: DC1
X8,7,6=011: PH3
X8,7,6=010: PH4
X8,7,6=001: PH5
X8,7,6=000: DC0
X5~0ҏЧҏPH15~10
D:
PC:
CF:
Rxn:
Ry:
BCF:
@HL:
HRFn:
HEFn:
Cfq:
Ctm:
PDV:
Lz:
T@HL:
CSF:
ELP – CLK
BCLKX
ELP – DUTY
ELC – CLK
ELC – DUTY
Immediate data
Program counter
Carry flag
Memory bit-n of address X
Memory of working register Y
Back-up flag
Memory of index RAM
HALT release flag
HALT release enable flag
Clock source of frequency generator
Clock source of timer
Predivider
LCD latch
Memory of index ROM
Clock source flag
L:
Low address of index
RFOVF: RFC overflow flag
LT@HL: Low nibble of index ROM
18
Ver. 0.0