LM3881 www.ti.com SNVS555C – JANUARY 2008 – REVISED APRIL 2013 LM3881 Power Sequencer Check for Samples: LM3881 FEATURES DESCRIPTION • • • • • • • The LM3881 Power Sequencer offers the easiest method to control power up and power down of multiple power supplies (switching or linear regulators). By staggering the startup sequence, it is possible to avoid latch conditions or large in-rush currents that can affect the reliability of the system. 1 2 Easiest Method to Sequence Rails Power Up and Power Down Control Input Voltage Range of 2.7V to 5.5V Small Footprint VSSOP-8 Package Low Quiescent Current of 80 µA Output Invert Feature Timing Controlled by Small Value External Capacitor Available in VSSOP-8 package, the Power Sequencer contains a precision enable pin and three open drain output flags. Upon enabling the LM3881, the three output flags will sequentially release, after individual time delays, permitting the connected power supplies to startup. The output flags will follow a reverse sequence during power down to avoid latch conditions. Time delays are defined using an external capacitor and the output flag states can be inverted by the user. APPLICATIONS • • • Multiple Supply Sequencing Microprocessor / Microcontroller Sequencing FPGA Sequencing Typical Application Circuit Connection Diagram Input Supply (2.7 V ± 5.5V) VCC LM3881 EN GND VCC EN INV FLAG1 Flag1 FLAG2 Flag2 FLAG3 Flag3 INV 8 2 7 3 FLAG1 LM3881 6 5 4 FLAG2 FLAG3 TADJ Figure 1. Top View VSSOP-8 Package TADJ GND C ADJ 1 PIN DESCRIPTIONS Pin # Name Function 1 VCC Input Supply 2 EN Precision Enable 3 GND Ground 4 INV Output Logic Invert 5 TADJ Timer Adjust 6 FLAG3 Open Drain Output #3 7 FLAG2 Open Drain Output #2 8 FLAG1 Open Drain Output #1 1 2 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. All trademarks are the property of their respective owners. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2008–2013, Texas Instruments Incorporated LM3881 SNVS555C – JANUARY 2008 – REVISED APRIL 2013 www.ti.com These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. Absolute Maximum Ratings (1) (2) VCC, EN, INV, TADJ, FLAG1, FLAG2, FLAG3 to GND -0.3V to +6.0V Storage Temperature Range -65°C to +150°C Junction Temperature 150°C Lead Temperature (Soldering, 5 sec.) Minimum ESD Rating (1) (2) (3) 260°C (3) 2 kV Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is intended to be functional, but does not ensure specific performance limits. For ensured specifications and conditions, see the Electrical Characteristics. If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/Distributors for availability and specifications. The human body model is a 100 pF capacitor discharged through a 1.5 kΩ resistor into each pin. Operating Ratings (1) VCC to GND 2.7V to 5.5V EN, INV, TADJ, FLAG1, FLAG2, FLAG3 to GND -0.3V to VCC + 0.3V Junction Temperature (1) -40°C to +125°C Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is intended to be functional, but does not ensure specific performance limits. For ensured specifications and conditions, see the Electrical Characteristics. Electrical Characteristics Specifications with standard typeface are for TJ = 25°C, and those in bold face type apply over the full Operating Temperature Range (TJ = -40°C to +125°C). Minimum and Maximum limits are ensured through test, design or statistical correlation. Typical values represent the most likely parametric norm at TJ = 25°C and are provided for reference purposes only. VCC = 3.3V, unless otherwise specified. Symbol IQ Parameter Conditions Min (1) Operating Quiescent Current Typ (2) Max (1) Unit 80 110 µA Open Drain Flags IFLAG FLAGx Leakage Current VFLAGx = 3.3V VOL FLAGx Output Voltage Low IFLAGx = 1.2 mA 0.001 1 µA 0.4 V 20 µA Time Delays ITADJ_SRC TADJ Source Current ITADJ_SNK TADJ Sink Current 4 12 4 12 20 µA VHTH High Threshold Level 1.0 1.22 1.4 V VLTH Low Threshold Level 0.3 0.5 0.7 V TCLK Clock Cycle 10 Clock Cycles TD1, TD4 Flag Time Delay TD2, TD3, TD5, TD6 Flag Time Delay CADJ = 10 nF 1.2 9 ms 8 Clock Cycles ENABLE Pin VEN EN Pin Threshold IEN EN Pin Pull-up Current 1.0 VEN = 0V 1.22 1.5 7 V µA INV Pin (1) (2) 2 VIH_INV Invert Pin VIH VIL_INV Invert Pin VIL 90% VCC V 10% VCC V Limits are 100% production tested at 25°C. Limits over the operating temperature range are ensured through correlation using Statistical Quality Control (SQC) methods. The limits are used to calculate TI's Average Outgoing Quality Level (AOQL). Typical numbers are at 25°C and represent the most likely parametric norm. Submit Documentation Feedback Copyright © 2008–2013, Texas Instruments Incorporated Product Folder Links: LM3881 LM3881 www.ti.com SNVS555C – JANUARY 2008 – REVISED APRIL 2013 Typical Performance Characteristics VCC = 3.3V unless otherwise specified. Quiescent Current vs VCC Quiescent Current vs Temperature 82 80.4 80 IQ (PA) IQ (PA) 80.2 80.0 78 79.8 76 79.6 2.5 74 -50 3.0 3.5 4.0 4.5 5.0 5.5 -25 75 Figure 3. Enable Threshold vs Temperature Time Delay vs VIN (CADJ = 10 nF Nominal) 9.56 1.230 9.55 1.225 9.54 TD (ms) VEN (V) 50 Figure 2. 1.235 1.220 9.52 1.210 9.51 0 25 50 100 125 5 5.5 9.53 1.215 -25 25 TEMPERATURE (°C) VCC (V) 1.205 -50 0 75 100 125 9.50 2.5 TEMPERATURE (°C) 3 3.5 4 4.5 VIN (V) Figure 4. Figure 5. Submit Documentation Feedback Copyright © 2008–2013, Texas Instruments Incorporated Product Folder Links: LM3881 3 LM3881 SNVS555C – JANUARY 2008 – REVISED APRIL 2013 www.ti.com Typical Performance Characteristics (continued) VCC = 3.3V unless otherwise specified. Time Delay vs Temperature (CADJ = 10 nF Nominal) VFLAG vs VIN (INV Low, RFLAG = 100 kΩ) 9.75 1 9.70 0.8 VFLAG (V) TD (ms) 9.65 9.60 0.6 0.4 9.55 0.2 9.50 9.45 -50 -25 0 25 50 75 100 0 125 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2 TEMPERATURE (°C) VIN (V) Figure 6. Figure 7. FLAG Voltage vs Current 1 0.8 VFLAG (V) VCC = 3.3V 0.6 VCC = 5V 0.4 0.2 0 0 1 2 3 4 5 IFLAG (mA) Figure 8. 4 Submit Documentation Feedback Copyright © 2008–2013, Texas Instruments Incorporated Product Folder Links: LM3881 LM3881 www.ti.com SNVS555C – JANUARY 2008 – REVISED APRIL 2013 Block Diagram VCC FLAG1 7 PA EN + TD1 - TD2 Timing Delay Generation 1.22V FLAG2 TD3 TD4 Sequence Control TD5 TD6 Clock FLAG3 TADJ GND INV Submit Documentation Feedback Copyright © 2008–2013, Texas Instruments Incorporated Product Folder Links: LM3881 5 LM3881 SNVS555C – JANUARY 2008 – REVISED APRIL 2013 www.ti.com APPLICATION INFORMATION OVERVIEW The LM3881 Power Sequencer provides a simple solution for sequencing multiple rails in a controlled manner. A clock signal is established that facilitates control of the power up and power down of three open drain FET output flags. These flags permit connection to shutdown or enable pins of linear regulators and/or switching regulators to control the power supplies’ operation. This allows a complete power system to be designed without worrying about large in-rush currents or latch-up conditions that can occur during an uncontrolled startup. An invert (INV) pin is provided that reverses the logic of the output flags. This pin should be tied to a logic output high or low and not allowed to remain open circuit. The following discussion assumes the INV pin is held low such that the flag output is active high. A small external timing capacitor is connected to the TADJ pin that establishes the clock waveform. This capacitor is linearly charged/discharged by a fixed current source/sink, denoted ITADJ_SRC / ITADJ_SNK, of magnitude 12 µA between pre-defined voltage threshold levels, denoted VLTH and VHTH, to generate the timing waveform as shown in the following diagram. High Threshold Level, VHTH = 1.22V TADJ Low Threshold Level, VLTH = 0.5V TCLK Figure 9. TADJ Pin Timing Waveform Thus, the clock cycle duration is directly proportional to the timing capacitor value. Considering the TADJ voltage threshold levels and the charge/discharge current magnitude, it can be shown that the timing capacitor-clock period relationship is typically 120 µs/nF. For example, a 10 nF capacitor sets up a clock period of 1.2 ms. The timing sequence of the LM3881 is controlled by the enable (EN) pin. Upon power up, all the flags are held low until the precision enable pin exceeds its threshold. After the EN pin is asserted, the power up sequence will commence and the open-drain flags will be sequentially released. An internal counter will delay the first flag (FLAG1) from rising until a fixed time period, denoted by TD1 in the following timing diagram, elapses. This corresponds to at least nine, maximum ten, clock cycles depending on where EN is asserted relative to the clock signal. Upon release of the first flag, another timer will begin to delay the release of the second flag (FLAG2). This time delay, denoted TD2, corresponds to exactly eight clock periods. Similarly, FLAG3 is released after time delay TD3, again eight clock cycles, has expired. Accordingly, a TADJ capacitor of 10 nF generates typical time delays TD2 and TD3 of 9.6 ms and TD1 of between 10.8 ms and 12.0 ms. The power down sequence is the same as power up, but in reverse order. When the EN pin is de-asserted, a timer will begin that delays the third flag (FLAG3) from pulling low. The second and first flag will then follow in a sequential manner after their appropriate time delays. These time delays, denoted TD4, TD5, TD6, are equal to TD1, TD2, TD3, respectively. For robustness, the pull down FET associated with each flag is designed such that it can sustain a short circuit to VCC. 6 Submit Documentation Feedback Copyright © 2008–2013, Texas Instruments Incorporated Product Folder Links: LM3881 LM3881 www.ti.com SNVS555C – JANUARY 2008 – REVISED APRIL 2013 EN FLAG1 FLAG2 FLAG3 TADJ TD1 TD2 TD3 9 Clock Cycles 8 Clock Cycles 8 Clock Cycles Figure 10. Power Up Sequence, INV Low EN FLAG1 FLAG2 FLAG3 TADJ TD1 TD2 TD3 9 Clock Cycles 8 Clock Cycles 8 Clock Cycles Figure 11. Power Up Sequence, INV High Submit Documentation Feedback Copyright © 2008–2013, Texas Instruments Incorporated Product Folder Links: LM3881 7 LM3881 SNVS555C – JANUARY 2008 – REVISED APRIL 2013 www.ti.com EN FLAG1 FLAG2 FLAG3 TADJ TD4 TD5 TD6 9 Clock Cycles 8 Clock Cycles 8 Clock Cycles Figure 12. Power Down Sequence, INV Low EN FLAG1 FLAG2 FLAG3 TADJ TD4 TD5 TD6 9 Clock Cycles 8 Clock Cycles 8 Clock Cycles Figure 13. Power Down Sequence, INV High 8 Submit Documentation Feedback Copyright © 2008–2013, Texas Instruments Incorporated Product Folder Links: LM3881 LM3881 www.ti.com SNVS555C – JANUARY 2008 – REVISED APRIL 2013 ENABLE CIRCUIT The enable circuit is designed with an internal comparator, referenced to a bandgap voltage (1.22V), to provide a precision threshold. This allows the timing to be set externally using a capacitor as shown in the diagram below. Alternatively, sequencing can be based on a certain event such as a line voltage reaching 90% of its nominal value by employing a resistor divider from VCC to Enable. 7 PA EN 1.22V Enable + - CEN Figure 14. Precision Enable Circuit Using the internal pull-up current source to charge the external capacitor CEN, the time delay while the enable voltage reaches the required threshold, assuming EN is charging from 0V, can be calculated by the equation as follows. Tenable_delay = 1.22V x CEN 7 PA EN 1.22V 0V Tenable delay Figure 15. Enable Delay Timing Submit Documentation Feedback Copyright © 2008–2013, Texas Instruments Incorporated Product Folder Links: LM3881 9 LM3881 SNVS555C – JANUARY 2008 – REVISED APRIL 2013 www.ti.com A resistor divider can also be used to enable the LM3881 based on exceeding a certain VCC supply voltage threshold. Care needs to be taken when sizing the resistor divider to include the effects of the internal EN pull-up current source. The supply voltage for which EN is asserted is given by § REN1 · - 7 PA (R llR ) EN1 EN2 VCCENABLE = 1.22V ¨1 + ¸ © REN2¹ Input Supply (2.7V - 5.5V) LM3881 REN1 VCC EN FLAG1 FLAG2 INV FLAG3 REN2 TADJ CADJ GND Figure 16. Enable Based On Input Supply Level One of the features of the enable pin is that it provides glitch free operation. The timer will start counting at a rising threshold, but will always reset if the enable pin is de-asserted before the first output flag is released. This is illustrated in the timing diagram below, assuming INV is low. EN FLAG1 TD1 Figure 17. Enable Glitch Timing, INV Low If the EN pin remains high for the entire power up sequence, then the part will operate as shown in the standard timing diagrams. However, if the EN signal is de-asserted before the power-up sequence is completed, the part will enter a controlled shutdown. This allows the system to initiate a controlled power sequence, preventing any latch conditions to occur. The following timing diagrams describe the flag sequence if the EN pin is de-asserted after FLAG1 releases, but before the entire power-up sequence is completed. INV is assumed low. 10 Submit Documentation Feedback Copyright © 2008–2013, Texas Instruments Incorporated Product Folder Links: LM3881 LM3881 www.ti.com SNVS555C – JANUARY 2008 – REVISED APRIL 2013 EN FLAG1 FLAG2 FLAG3 TADJ TD4 TD1 9 Clock Cycles < 8 Clock Cycles 9 Clock Cycles EN FLAG1 FLAG2 FLAG3 TADJ TD1 TD2 9 Clock Cycles 8 Clock Cycles < 8 Clock Cycles TD4 TD5 9 Clock Cycles 8 Clock Cycles Figure 18. Incomplete Sequence Timing, INV Low Submit Documentation Feedback Copyright © 2008–2013, Texas Instruments Incorporated Product Folder Links: LM3881 11 LM3881 SNVS555C – JANUARY 2008 – REVISED APRIL 2013 www.ti.com REVISION HISTORY Changes from Revision B (April 2013) to Revision C • 12 Page Changed layout of National Data Sheet to TI format .......................................................................................................... 11 Submit Documentation Feedback Copyright © 2008–2013, Texas Instruments Incorporated Product Folder Links: LM3881 PACKAGE OPTION ADDENDUM www.ti.com 11-Apr-2013 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan Lead/Ball Finish (2) MSL Peak Temp Op Temp (°C) Top-Side Markings (3) (4) LM3881MM/NOPB ACTIVE VSSOP DGK 8 1000 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 125 STBB LM3881MME/NOPB ACTIVE VSSOP DGK 8 250 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 125 STBB LM3881MMX/NOPB ACTIVE VSSOP DGK 8 3500 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 125 STBB (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) Multiple Top-Side Markings will be inside parentheses. Only one Top-Side Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Top-Side Marking for that device. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. 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Addendum-Page 1 Samples PACKAGE MATERIALS INFORMATION www.ti.com 24-Apr-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing LM3881MM/NOPB VSSOP DGK 8 LM3881MME/NOPB VSSOP DGK LM3881MMX/NOPB VSSOP DGK SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant 1000 178.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1 8 250 178.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1 8 3500 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 24-Apr-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) LM3881MM/NOPB VSSOP DGK 8 1000 210.0 185.0 35.0 LM3881MME/NOPB VSSOP DGK 8 250 210.0 185.0 35.0 LM3881MMX/NOPB VSSOP DGK 8 3500 367.0 367.0 35.0 Pack Materials-Page 2 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. 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