DS26LS32MQML www.ti.com SNOSAM6B – OCTOBER 2005 – REVISED APRIL 2013 DS26LS32MQML Quad Differential Line Receivers Check for Samples: DS26LS32MQML FEATURES DESCRIPTION • The DS26LS32 and DS26LS32A are quad differential line receivers designed to meet the RS-422, RS-423 and Federal Standards 1020 and 1030 for balanced and unbalanced digital data transmission. 1 2 • • • • • • High Differential or Common-Mode Input Voltage Ranges of ±7V on the DS26LS32. ±0.2V Sensitivity Over the Input Voltage Range on the DS26LS32. DS26LS32 Meet All Requirements of RS-422 and RS-423 6k Minimum Input Impedance 100 mV Input Hysteresis on the DS26LS32 Operation From a single 5V Supply TRI-STATE Outputs, with Choice of Complementary Output Enables for Receiving Directly onto a Data Bus The DS26LS32 and DS26LS32A have an input sensitivity of 200 mV over the input voltage range of ±7V. The DS26LS33 has an input sensitivity of 500 mV over the input voltage range of ±15V. The DS26LS32A differs in function from the popular DS26LS32 and DS26LS33 in that input pull-up and pull-down resistors are included which prevent output oscillation on unused channels. Each version provides an enable and disable function common to all four receivers and features TRI-STATE outputs with 8 mA sink capability. Constructed using low power Schottky processing, these devices are available over the full military and commercial operating temperature ranges. Logic Diagram 1 2 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. All trademarks are the property of their respective owners. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2005–2013, Texas Instruments Incorporated DS26LS32MQML SNOSAM6B – OCTOBER 2005 – REVISED APRIL 2013 www.ti.com Connection Diagram Top View Figure 1. CDIP Package See Package Numbers NFE0016A, NAD0016A Top View Figure 2. 20-Lead LCCC Package See Package Number NAJ0020A Truth Table (1) ENABLE ENABLE Input Output 0 1 X Hi-Z See Note Below (1) VID ≥ VTH (Max) 1 VID ≤ VTH (Min) 0 Hi-Z = TRI-STATE Note: Input conditions may be any combination not defined for ENABLE and ENABLE . These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. 2 Submit Documentation Feedback Copyright © 2005–2013, Texas Instruments Incorporated Product Folder Links: DS26LS32MQML DS26LS32MQML www.ti.com SNOSAM6B – OCTOBER 2005 – REVISED APRIL 2013 Absolute Maximum Ratings (1) Supply Voltage 7V Common-Mode Range ±25V Differential Input Voltage ±25V Enable Voltage 7V Output Sink Current 50 mA Maximum Power Dissipation at 25°C (2) NFE0016A Package 1666.5 mW NAJ0020A Package 1875 mW NAD0016A Package 967.74 mW Junction Temperature (TJ) +150°C Thermal Resistance, Junction-to-Ambient θJA NFE0016A Package 100°C/W NAJ0020A Package 130°C/W NAD0016A Package 140°C/W Thermal Resistance, Junction-to-Ambient θJC See MIL-STD-1835 −65°C to +165°C Storage Temperature Range Lead Temperature (Soldering, 4 seconds) ESD Tolerance (1) (2) (3) 260°C (3) 500V Absolute Maximum Ratings are those values beyond which the safety of the device cannot be verified. They are not meant to imply that the device should be operated at these limits. The table of “Electrical Characteristics” provides conditions for actual device operation. Derate NFE0016A, package 11.11 mW/°C above 25°C; derate NAJ0020A package 12.5 mW/°C above 25°C; derate NAD0016A Package 6.4516 mW/°C for above 25°C. Human body model, 1.5kΩ in series with 100pF. Recommended Operating Conditions Supply Voltage, VCC 4.5 V to 5.5 V −55°C to +125°C Temperature, TA Quality Conformance Inspection MIL-STD-883, Method 5005 - Group A Subgroup Description Temp ( °C) 1 Static tests at +25 2 Static tests at +125 3 Static tests at -55 4 Dynamic tests at +25 5 Dynamic tests at +125 6 Dynamic tests at -55 7 Functional tests at +25 8A Functional tests at +125 8B Functional tests at -55 9 Switching tests at +25 10 Switching tests at +125 11 Switching tests at -55 Submit Documentation Feedback Copyright © 2005–2013, Texas Instruments Incorporated Product Folder Links: DS26LS32MQML 3 DS26LS32MQML SNOSAM6B – OCTOBER 2005 – REVISED APRIL 2013 www.ti.com DS26LS32M 883 Electrical Characteristics DC Parameters The following conditions apply, unless otherwise specified. VCC = 5V Parameter IIN Input Current IIL Logical "0" ENABLE Current Max Unit Subgroups (1) 2.3 mA 1, 2, 3 (1) -2.8 mA 1, 2, 3 VCC = 5.5V, VIN = 0.4V (1) -360 uA 1, 2, 3 Test Conditions VCC = 5.5V, VIN = 15V (Pin under test), other inputs -15V, ≤ VIN ≤ +15V VCC = 5.5V, VIN = -15V (Pin under test), other inputs -15V, ≤ VIN ≤ +15V Notes Min IIH Logical "1" ENABLE Current VCC = 5.5V, VIN = 2.7V (1) 20 uA 1, 2, 3 II Logical "1" ENABLE Current VCC =5.5V, VIN = 5.5V (1) 100 uA 1, 2, 3 VIC Input Clamp Voltage (ENABLE) VCC = 4.5V, IIN = -18mA (1) -1.5 V 1, 2, 3 VOH Logical "1" Output Voltage VCC = 4.5V, IOH = -440uA, ΔVIN = 1V, V ENABLE = 0.8V (1) V 1, 2, 3 VCC = 4.5V, IOL = 4mA, ΔVIN = -1V, V ENABLE = 0.8V (1) .4 V 1, 2, 3 VCC = 4.5V, IOL = 8mA, ΔVIN = -1V, V ENABLE = 0.8V (1) .45 V 1, 2, 3 mA 1, 2, 3 VOL Logical "0" Output Voltage 2.5 IOS (MIN) Output Short Circuit Current VCC = 5.5V, VO = 0V, ΔVIN = 1V (1) IOS (MAX) Output Short Circuit Current VCC = 5.5V, VO = 0V, ΔVIN = 1V (1) -85 mA 1, 2, 3 ICC Supply Current VCC = 5.5V, All VIN = GND, Outputs Disabled (1) 70 mA 1, 2, 3 Off-State Output Current VCC = 5.5V, VO = 0.4V (1) IO -20 uA 1, 2, 3 VCC = 5.5V, VO = 2.4V (1) 20 uA 1, 2, 3 VTH Differential Input Voltage 0.2 V 1, 2, 3 kohm 1, 2, 3 V 1, 2, 3 V 1, 2, 3 -7V ≤ VCM ≤ 7V -15V ≤ VCM ≤ 15V (1) (2) -0.2 (1) 6 RIN Input Resistance VIL Logical "0" Input Voltage (ENABLE) VCC = 4.5V (1) (2) VIH Logical "1" Input Voltage (ENABLE) VCC = 4.5V (1) (2) (1) (2) -15 0.8 2 For Subgroups 1 and 2, power dissipation must be externally controlled at elevated temperatures. Parameter tested go-no-go only. DS26LS32M 883 Electrical Characteristics AC Parameters - Propagation Delay Time The following conditions apply, unless otherwise specified. VCC = 5V Parameter Test Conditions Notes Min Max Unit Subgroups 9,11, tPLH Propagation Delay Time CL = 15PF (1) 30 nS tPLH Propagation Delay Time CL = 15PF (1) 120 nS 10 tPHL Propagation Delay Time CL = 15PF (1) 30 nS 9,11, tPHL Propagation Delay Time CL = 15PF (1) 120 nS 10 ENABLE CL = 5PF (1) 34 nS 9 ENABLE CL = 5PF (1) 64 nS 10 ENABLE CL = 5PF (1) 27 nS 11 ENABLE CL = 5PF (1) 32 nS 9,11, ENABLE CL = 5PF (1) 35 nS 10 ENABLE CL = 15PF (1) 34 nS 9 ENABLE CL = 15PF (1) 65 nS 10 ENABLE CL = 15PF (1) 27 nS 11 tPLZ tPHZ tPZL (1) 4 Enable to Output Enable to Output Enable to Output Tested at 25°C, specified but not tested at +125°C & −55°C Submit Documentation Feedback Copyright © 2005–2013, Texas Instruments Incorporated Product Folder Links: DS26LS32MQML DS26LS32MQML www.ti.com SNOSAM6B – OCTOBER 2005 – REVISED APRIL 2013 DS26LS32M 883 Electrical Characteristics AC Parameters - Propagation Delay Time (continued) The following conditions apply, unless otherwise specified. VCC = 5V Parameter tPZH Test Conditions Enable to Output Notes Min Max Unit Subgroups ENABLE CL = 15PF (1) 35 nS 9, 11 ENABLE CL = 15PF (1) 65 nS 10 AC TEST CIRCUIT AND SWITCHING TIME WAVEFORMS Figure 3. Load Test Circuit for TRI-STATE Outputs (1) Diagram shown for ENABLE low. (2) Pulse generator for all pulses: Rate = 1.0 MHz; ZO = 50Ω; tr ≤ 6 ns; tf ≤ 6.0 ns. Figure 4. Propagation Delay (1) S1 and S2 of load circuit are closed except where shown. (2) Pulse generator for all pulses: Rate = 1.0 MHz; ZO = 50Ω; tr ≤ 6 ns; tf ≤ 6.0 ns. Figure 5. Enable and Disable Times TYPICAL APPLICATIONS Figure 6. Two-Wire Balanced Interface—RS-422 Submit Documentation Feedback Copyright © 2005–2013, Texas Instruments Incorporated Product Folder Links: DS26LS32MQML 5 DS26LS32MQML SNOSAM6B – OCTOBER 2005 – REVISED APRIL 2013 www.ti.com Figure 7. Single Wire with Driver Ground Reference—RS-423 6 Submit Documentation Feedback Copyright © 2005–2013, Texas Instruments Incorporated Product Folder Links: DS26LS32MQML DS26LS32MQML www.ti.com SNOSAM6B – OCTOBER 2005 – REVISED APRIL 2013 REVISION HISTORY Date Released Revision Section Originator Changes 10/20/05 A New Release, Corporate format. Changes made in conversion: Ordering Info. Table, Absolute Ratings, Maximum Operating Conditions, Typos in QMLV & RH, 883 AC Electrical Characteristics Parameters Column. R. Malone 1 MDS data sheet converted into Corporate data sheet format. Added: SMD reference for 883 NSID's, Juction temp., Thermal Resistance θJA and θJC. Changed: Maximum Operating Conditions to Recommended Operating Conditions, Enable and Disable Time to Enable to Output. Deleted max limit: 27nS for tPZH and added subgroup 11 to max limit 35nS. MDS data sheet MNDS26LS32–X, Rev. 2B0 will be Archived. 4/15/2013 B TIS Changed layout of National Data Sheet to TI format Submit Documentation Feedback Copyright © 2005–2013, Texas Instruments Incorporated Product Folder Links: DS26LS32MQML 7 PACKAGE OPTION ADDENDUM www.ti.com 15-Apr-2013 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan Lead/Ball Finish (2) MSL Peak Temp Op Temp (°C) (3) Top-Side Markings (4) 5962-7802006QEA ACTIVE CDIP NFE 16 25 TBD Call TI Call TI -55 to 125 (DS26C32AMJ/883 ~ DS26LS32MJ/883 ) (5962-7802006QEA Q ~ 5962-916400 1MEA Q) AM26LS32DMB ACTIVE CDIP NFE 16 25 TBD Call TI Call TI -55 to 125 (DS26C32AMJ/883 ~ DS26LS32MJ/883 ) (5962-7802006QEA Q ~ 5962-916400 1MEA Q) DS26LS32MJ/883 ACTIVE CDIP NFE 16 25 TBD Call TI Call TI -55 to 125 (DS26C32AMJ/883 ~ DS26LS32MJ/883 ) (5962-7802006QEA Q ~ 5962-916400 1MEA Q) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Addendum-Page 1 Samples PACKAGE OPTION ADDENDUM www.ti.com 15-Apr-2013 (4) Multiple Top-Side Markings will be inside parentheses. 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