TLC32040M ANALOG INTERFACE CIRCUIT SGLS031 – MAY 1990 • • • • • • • Advanced LinCMOS Silicon-Gate Process Technology 14-Bit Dynamic Range ADC and DAC Variable ADC and DAC Sampling Rate up to 19 200 Samples Per Second Switched-Capacitor Antialiasing Input Filter and Output-Reconstruction Filter Serial Port for Direct Interface to SMJ320E14, SMJ32020, SMJ320C25, and SMJ320C30 Digital Processors Synchronous or Asynchronous ADC and DAC Conversion Rates With Programmable Incremental ADC and DAC Conversion Timing Adjustments Serial Port Interface to SN54299 Serial-to-Parallel Shift Register for Parallel Interface to SMJ320C10, SMJ320C15, SMJ320E15, or Other Digital Processors J PACKAGE (TOP VIEW) NU RESET EODR FSR DR MSTR CLK VDD REF DGTL GND SHIFT CLK EODX DX WORD/BYTE FSX 1 28 2 27 3 26 4 25 5 24 6 23 7 22 8 21 9 20 10 19 11 18 12 17 13 16 14 15 NU NU IN + IN – AUX IN + AUX IN – OUT + OUT – VCC + VCC – ANLG GND ANLG GND NU NU FK PACKAGE (TOP VIEW) DR MSTR CLK VDD REF DGTL GND SHIFT CLK EODX 5 4 3 2 1 28 27 26 25 6 24 7 23 8 22 9 21 10 20 11 19 12 13 14 15 16 17 18 IN – AUX IN + AUX IN – OUT + OUT – VCC + VCC – DX WORD/BYTE FSX NU NU ANLG GND ANLG GND The TLC32040M interface circuit is a complete analog-to-digital and digital-to-analog input/ output system on a single monolithic CMOS chip. This device integrates a band-pass switched-capacitor antialiasing input filter, a 14-bit-resolution A/D converter, four microprocessor-compatible serial port modes, a 14-bit-resolution D/A converter, and a low-pass switched-capacitor output reconstruction filter. The device offers numerous combinations of master clock input frequencies and conversion/ sampling rates, which can be changed via digital processor control. FSR EODR RESET NU NU NU IN+ description Typical applications for this integrated circuit include modems (7.2-, 8-, 9.6-, 14.4-, and 19.2-kHz sampling rate), analog interface for digital signal processors (DSPs), speech recognition/storage systems,noindustrial processshould control, biomedical NU – Nonusable; external connection be made to these pins. instrumentation, acoustical signal processing, spectral analysis, data acquisition, and instrumentation recorders. Four serial modes, which allow direct interface to the SMJ320E14, SMJ32020, SMJ320C25, and SMJ320C30 digital signal processors, are provided. Also, when the transmit and receive sections of the analog interface circuit (AIC) are operating synchronously, it will interface to two SN54299 serial-to-parallel shift registers.These serial-to-parallel shift registers can then interface in parallel to the SMJ320C10, SMJ320C15, SMJ320E15, other digital signal processors, or external FIFO circuitry. Output data pulses are emitted to inform the processor that data transmission is complete or to allow the DSP to differentiate between two transmitted bytes. A flexible control scheme is provided so that the functions of the integrated circuit can be selected and adjusted coincidentally with signal processing via software control. Advanced LinCMOS is a trademark of Texas Instruments Incorporated. Copyright 1990, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 4–1 TLC32040M ANALOG INTERFACE CIRCUIT description (continued) The antialiasing input filter comprises seventh-order and fourth-order CC-type (Chebyshev/elliptic transitional) low-pass and high-pass filters, respectively, and a fourth-order equalizer. The input filter is implemented in switched-capacitor technology and is preceded by a continuous time filter to eliminate any possibility of aliasing caused by sampled data filtering. When no filtering is desired, the entire composite filter can be switched out of the signal path. A selectable, auxiliary, differential analog input is provided for applications where more than one analog input is required. The A/D and D/A converters each have 14 bits of resolution. The A/D and D/A architectures ensure no missing codes and monotonic operation. An internal voltage reference is provided on the TLC32040M to ease the design task and to provide complete control over the performance of the integrated circuit. The internal voltage reference is brought out to a pin and is available to the designer. Separate analog and digital voltage supplies and grounds are provided to minimize noise and ensure a wide dynamic range. Also, the analog circuit path contains only differential circuitry to keep noise to an absolute minimum. The only exception is the DAC sample and hold, which utilizes pseudo-differential circuitry. The output-reconstruction filter is a seventh-order CC-type (Chebyshev/elliptic transitional low-pass filter with a fourth-order equalizer) and is implemented in switched-capacitor technology. This filter is followed by a continuous-time filter to eliminate images of the digitally encoded signal. The TLC32040M is characterized for operation from – 55°C to 125°C. functional block diagram Band-Pass Filter IN + IN – 26 25 M U X 24 AUX IN + 23 AUX IN – Serial Port M U X 4 5 A/D EODR 6 MSTR CLK Internal Voltage Reference Receive Section 10 13 12 22 14 + + 11 D/A 21 – – OUT– Transmit Section 20 19 9 18 7 VCC + VCC – ANLG DTGL VDD GND GND (DIG) 4–2 DR 3 Low-Pass Filter OUT + FSR POST OFFICE BOX 655303 2 8 REF • DALLAS, TEXAS 75265 RESET SHIFT CLK WORD/BYTE DX FSX EODX TLC32040M ANALOG INTERFACE CIRCUIT Terminal Functions PIN NAME NO. ANLG GND 17, 18 DESCRIPTION I/O Analog ground return for all internal analog circuits. Not internally connected to DGTL GND. AUX IN + 24 I Noninverting auxiliary analog input stage. This input can be switched into the band-pass filter and A/D converter path via software control. If the appropriate bit in the control register is a 1, the auxiliary inputs will replace the IN + and IN – inputs. If the bit is a 0, the IN + and IN – inputs will be used (see the AIC DX data word format section). AUX IN – 23 I Inverting auxiliary analog input (see the above AUX IN + pin description). DGTL GND 9 DR 5 O This pin is used to transmit the ADC output bits from the AIC to the TMS320 serial port. This transmission of bits from the AIC to the TMS320 serial port is synchronized with the SHIFT CLK signal. DX 12 I This pin is used to receive the DAC input bits and timing and control information from the TMS320. This serial transmission from the TMS320 serial port to the AIC is synchronized with the SHIFT CLK signal. EODR 3 O End of data receive.(See the WORD/BYTE pin description and the Serial Port TIming dIagram.) During the word-mode timing, this signal is a low-going pulse that occurs immediately after the 16 bits of A/D information have been transmitted from the AIC to the TMS320 serial port. This signal can be used to interrupt a microprocessor upon completion of serial communications. Also, this signal can be used to strobe and enable external serial-to-parallel shift registers, latches, or external FIFO RAM, and to facilitate parallel data bus communications between the AIC and the serial-to-parallel shift registers. During the byte-mode timing, this signal goes low after the first byte has been transmitted from the AIC to the TMS320 serial port and is kept low until the second byte has been transmitted. The TMS32011 or TMS320C17 can use this low-going signal to differentiate between the two bytes as to which is first and which is second. EODX 11 O End of data transmit. See WORD/BYTE description and Serial Port Timing diagram. During the word-mode timing, this signal is a low-going pulse that occurs immediately after the 16 bits of D/A converter and control or register information have been transmitted from the SMJ320 serial port to the AIC. This signal can be used to interrupt a microprocessor upon the completion of serial communications. Also, this signal can be used to strobe and enable external serial-to-parallel shift registers, latches, or an external FIFO RAM, and to facilitate parallel data-bus communications between the AIC and the serial-to-parallel shift registers. During the byte-mode timing, this signal goes low after the first byte has been transmitted from the SMJ320 serial port to the AIC and is kept low until the second byte has been transmitted. The DSP can use this low-going signal to differentiate between the two bytes as to which is first and which is second. FSR 4 O Frame sync receive. In the serial transmission modes, which are described in the WORD/BYTE description, FSR is held low during bit transmission. When FSR goes low, the SMJ320 serial port will begin receiving bits from the AIC via the DR pin of the AIC. The most significant DR bit will be present on DR before FSR goes low. (See Serial Port Timing and Internal Timing Configuration diagrams.) FSR does not occur after secondary communication. FSX 14 O Frame sync transmit. When this terminal goes low, the SMJ320 serial port will begin transmitting bits to the AIC via DX of the AIC. In all serial transmission modes, which are described in the WORD/BYTE description, FSX is held low during bit transmission (see the Serial Port Timing and Internal Timing Configuration diagrams). IN+ 26 I Noninverting input to analog input amplifier stage IN– 25 I Inverting input to analog input amplifier stage 6 I The master clock signal is used to derive all the key logic signals of the AIC, such as the shift clock, the switched-capacitor filter clocks, and the A/D and D/A timing signals. The Internal Timing Configuration diagram shows how these key signals are derived. The frequencies of these key signals are synchronous submultiples of the master clock frequency to eliminate unwanted aliasing when the sampled analog signals are transferred between the switched-capacitor filters and the A/D and D/A converters (see the Internal Timing Configuration). OUT+ 22 O Noninverting output of analog output power amplifier. Can drive transformer hybrids or high-impedance loads directly in either a differential or a single-ended configuration. OUT– MSTR CLK Digital ground for all internal logic circuits. Not internally connected to ANLG GND. 21 O Inverting output of analog output power amplifier. Functionally identical with and complementary to OUT+. REF 8 I/O The internal voltage reference is brought out on this terminal. Also an external voltage reference can be applied to this terminal. RESET 2 I A reset function is provided to initialize the TA, TA’, TB, RA, RA’, RB, and control registers. This reset function initiates serial communications between the AIC and DSP. The reset function will initialize all AIC registers including the control register. After a negative-going pulse on RESET, the AIC registers will be initialized to provide an 8-kHz data conversion rate for a 5.184-MHz master clock input signal. The conversion rate adjust registers, TA’ and RA’, will be reset to 1. The control register bits will be reset as follows (see AIC DX data word format section). d7 = 1, d6 = 1, d5 = 1, d4 = 0, d3 = 0, d2 = 1 This initialization allows normal serial-port communication to occur between the AIC and the DSP. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 4–3 TLC32040M ANALOG INTERFACE CIRCUIT Terminal Functions (Continued) PIN NAME NO. I/O DESCRIPTION O The shift clock signal is obtained by dividing the master clock signal frequency by four. This signal is used to clock the serial data transfers of the AIC, described in the WORD/BYTE description (see the Serial Port Timing and Internal Timing Configuration diagrams). SHIFT CLK 10 VDD VCC + 20 Positive analog supply voltage, 5 V ± 5% 19 Negative analog supply voltage, – 5 V ± 5% VCC – WORD/BYTE 4–4 Digital supply voltage, 5 V ± 5% 7 13 I This terminal, in conjunction with a bit in the control register, is used to establish one of four serial modes. These four modes are described below. AIC transmit and receive sections are operated asynchronously. The following description applies when the AIC is configured to have asynchronous transmit and receive sections. If the appropriate data bit in the control register is a 0 (see the AIC DX data word format), the transmit and receive sections will be asynchronous. L Serial port directly interfaces with the serial port of the DSP and communicates in two 8-bit bytes. The operation sequence is as follows (see Serial Port Timing diagrams). 1. FSX or FSR is brought low. 2. One 8-bit byte is transmitted or one 8-bit byte is received. 3. EODX or EODR is brought low. 4. FSX or FSR emits a positive frame-sync pulse that is four shift-clock cycles wide. 5. One 8-bit byte is transmitted or one 8-bit byte is received. 6. EODX or EODR is brought high. 7. FSX or FSR is brought high. H Serial port directly interfaces with the serial port of the SMJ32020, SMJ320C25, or SMJ320C30 and communicates in one 16-bit word. The operation sequence is as follows (see Serial Port Timing diagrams): 1. FSX or FSR is brought low. 2. One 16-bit word is transmitted or one 16-bit word is received. 3. FSX or FSR is brought high. 4 EODX or EODR emits a low-going pulse. AIC transmit and receive sections are operated synchronously. If the appropriate data bit in the control register is a 1, the transmit and receive sections will be configured to be synchronous. In this case, the band-pass switched-capacitor filter and the A/D conversion timing will be derived from TX Counter A, TX Counter B, and TA, TA’, and TB registers, rather than the RX Counter A, RX Counter B, and RA, RA’, and RB registers. In this case, the AIC FSX and FSR timing will be identical during primary data communication; however, FSR will not be asserted during secondary data communication since there is no new A/D conversion result. The synchronous operation sequences are as follows (see Serial Port Timing diagrams ). L Serial port directly interfaces with the serial port of the DSP and communicates in two 8-bit bytes. The operation sequence is as follows (see Serial Port Timing diagrams). 1. FSX or FSR are brought low. 2. One 8-bit byte is transmitted and one 8-bit byte is received. 3. EODX and EODR are brought low. 4. FSX and FSR emit positive frame-sync pulse that are four shift-clock cycles wide. 5. One 8-bit byte is transmitted and one 8-bit byte is received. 6. EODX or EODR are brought high. 7. FSX or FSR are brought high. H Serial port directly interfaces with the serial port of the SMJ32020, SMJ320C25, or SMJ320C30 and communicates in one 16-bit word. The operation sequence is as follows (see Serial Port Timing diagrams): 1. FSX and FSR are brought low. 2. One 16-bit word is transmitted and one 16-bit word is received. 3. FSX and FSR are brought high. 4. EODX or EODR emit low-going pulses. Since the transmit and receive sections of the AIC are now synchronous, the AIC serial port, with additional NOR and AND gates, will interface to two SN54299 serial-to-parallel shift registers. Interfacing the AIC to the SN54299 shift register allows the AIC to interface to an external FIFO RAM and facilitates parallel data bus communications between the AIC and the digital signal processor. The operation sequence is the same as the above sequence (see Serial Port Timing diagrams). POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 TLC32040M ANALOG INTERFACE CIRCUIT INTERNAL TIMING CONFIGURATION Master Clock 5.184 MHZ (1) 10.368 MHZ (2) Shift Clock 1.296 MHz (1) 2.592 MHz (2) Divide by 4 20.736 MHz (1) 41.472 MHz (2) XTAL Osc TMS320 DSP TA Register (5 Bits) Optional External Circuitry for Full-Duplex Modems Divide by 135 153.6 kHz Clock (1) Commercial External Front-End Full-Duplex Split-Band Filters TA’ Register (6 Bits) (2s Compl) Divide by 2 Adder / Subtractor (6 Bits) Low-Pass Switched Cap Filter CLK = 288 kHz Square Wave TB Register (6 Bits) d0, d1 = 0,0 d0, d1 = 1, 1‡ d0, d1 = 0,1 d0, d1 = 1,0‡ TX Counter A [TA = 9 (1)] [TA = 18 (2)] (6 Bits) RA Register (5 Bits) 576-kHz Pulses TX Counter B TB = 40, 7.2 kHz TB = 36, 8.0 kHz TB = 30, 9.6 kHz TB = 20, 14.4 kHz TB = 15, 19.2 kHz D/A Conversion Frequency RA’ Register (6 Bits) (2s Compl) Adder / Subtractor (6 Bits) Divide by 2 Band-Pass Switched Cap Filter CLK = 288 kHz Square Wave RB Register (6 Bits) d0, d1 = 0,0 d0, d1 = 0,1 d0, d1 = d0, d1 = 1,0‡ 1,1‡ RX Counter A [TA = 9 (1)] [TA = 18 (2)] 576-kHz (6 Bits) Pulses SCF Clock Frequency = RX Counter B RB = 40, 7.2 kHz RB = 36, 8.0 kHz RB = 30, 9.6 kHz RB = 20, 14.4 kHz RB = 15, 19.2 kHz A/D Conversion Frequency Master Clock Frequency 2 × Contents of Counter A † Split-band filtering can alternatively be performed after the analog input function via software in the SMJ320. ‡ These control bits are described in the AIC DX data word format section. NOTE: Frequency 1, 20.736 MHz is used to show how 153.6 kHz (for a commercially available modem split-band filter clock), popular speech and modem sampling signal frequencies, and an internal 288-kHz switched-capacitor filter clock can be derived synchronously and as submultiples of the crystal oscillator frequency. Since these derived frequencies are synchronous submultiples of the crystal frequency, aliasing does not occur as the sampled analog signal passes between the analog converter and switched-capacitor filter stages. Frequency 2, 41.472 MHz is used to show that the AIC can work with high-frequency signals, which are used by high-speed digital signal processors. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 4–5 TLC32040M ANALOG INTERFACE CIRCUIT explanation of internal timing configuration All of the internal timing of the AIC is derived from the high-frequency clock signal that drives the master clock input. The shift clock signal, which strobes the serial port data between the AIC and DSP, is derived by dividing the master clock input signal frequency by four. SCF Clock Frequency Clock Frequency + 2 Master Contents of Counter A Conversion Frequency SCF Clock Frequency + Contents of Counter B Shift Clock Frequency + Master Clock4 Frequency TX Counter A and TX Counter B, which are driven by the master clock signal, determine the D/A conversion timing. Similarly, RX Counter A and RX Counter B determine the A/D conversion timing. In order for the switched-capacitor low-pass and band-pass filters to meet their transfer function specifications, the frequency of the clock inputs of the switched-capacitor filters must be 288 kHz. If the frequencies of the clock inputs are not 288 kHz , the filter transfer function frequencies are scaled by the ratios of the clock frequencies to 288 kHz. Thus, to obtain the specified filter responses, the combination of master clock frequency and TX Counter A and RX Counter A values must yield 288-kHz switched-capacitor clock signals. These 288-kHz clock signals can then be divided by TX Counter B and RX Counter B to establish the D/A and A/D conversion timings. TX Counter A and TX Counter B are reloaded every D/A conversion period, while RX Counter A and RX Counter B are reloaded every A/D conversion period. TX Counter B and RX Counter B are loaded with the values in the TB and RB Registers, respectively. Via software control, TX Counter A can be loaded with either TA Register, the TA Register less the TA’ Register, or the TA Register plus the TA’ Register. By selecting the TA Register less the TA’ Register option, the upcoming conversion timing will occur earlier by an amount of time that equals TA’ times the signal period of the master clock. By selecting the TA Register plus the TA’ Register option, the upcoming conversion timing will occur later by an amount of time that equals TA’ times the signal period of the master clock. Thus the D/A conversion timing can be advanced or retarded. An identical ability to alter the A/D conversion timing is provided. In this case, however, the RX Counter A can be programmed via software control with the RA Register, the RA Register less the RA’ Register, or the RA Register plus the RA’ Register. The ability to advance or retard conversion timing is particularly useful for modem applications. This feature allows controlled changes in the A/D and D/A conversion timing. This feature can be used to enhance signal-tonoise performance, to perform frequency-tracking functions, and to generate nonstandard modem frequencies. If the transmit and receive sections are configured to be synchronous (see the WORD/BYTE description in the Terminal Functions table), then both the low-pass and band-pass switched-capacitor filter clocks are derived from TX Counter A. Also, both the D/A and A/D conversion timing are derived from TX Counter A and TX Counter B. When the transmit and receive sections are configured to be synchronous, the RX Counter A, RX Counter B, RA Register, RA’ Register, and RB Registers are not used. 4–6 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 TLC32040M ANALOG INTERFACE CIRCUIT AIC DR or DX word bit pattern A/D or D/A MSB, 1st bit sent D15 D14 D13 1st bit sent of 2nd byte D12 D11 D10 D9 D8 D7 D6 A/D or D/A LSB D5 D4 D3 D2 D1 D0 AIC DX data word format section d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d2 d1 d0 → 0 0 COMMENTS Primary DX serial communication protocol ← d15 (MSB) through d2 go to the D/A The TX and RX Counter As are loaded with the TA and RA register values. The TX and RX Counter Bs areloaded with TB and RB register values. converter register ← d15 (MSB) through d2 go to the D/A converter register → ← d15 (MSB) through d2 go to the D/A converter register → ← d15 (MSB) through d2 go to the D/A converter register → 0 1 The TX and Counter As are loaded with the TA + TA’ and RA + RA’ register values. The TX and RX Counter Bs are loaded with the TB and RB register values. NOTE: d1 = 0, d0 = 1 will cause the next D/A and A/D conversion periods to be changed by the addition of TA’ and RA’ master clock cycles, in which TA’ and RA’ can be positive or negative or zero. Please refer to Table 1. AIC Responses to Improper Conditions. 1 0 The TX and Counter As are loaded with the TA - TA’ and RA - RA’ register values. The TX and RX Counter Bs are loaded with the TB and RB register values. NOTE: d1 = 0, d0 = 1 will cause the next D/A and A/D conversion periods to be changed by the subtraction of TA’ and RA’ Master Clock cycles, in which TA’ and RA can be positive or negative or zero. Please refer to Table 1. AIC Responses to Improper Conditions. 1 1 The TX and Counter As are loaded with the TA and RA register values. The TX and RX Counter Bs are loaded with the TB and RB register values. After a delay of four shift-clock cycles, a secondary transmission will immediately follow to program the AIC to operate in the desired configuration. NOTE: Setting the two least significant bits to 1 in the normal transmission of DAC information (Primary Communications) to the AIC will initiate Secondary Communications upon completion of the Primary Communications. Upon completion of the Primary Communication, FSX will remain high for four shift-clock cycles and will then go low and initiate the Secondary Communication. The timing specifications for the Primary and Secondary Communications are identical. in this manner, the Secondary Communication, if initiated, is interleaved between successive Primary Communications. This interleaving prevents the Secondary Communication from interfering with the Primary Communications and DAC timing, thus preventing the AIC from skipping a DAC output. It is important to note that in the synchronous mode, FSR will not be asserted during Secondary Communications. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 4–7 TLC32040M ANALOG INTERFACE CIRCUIT secondary DX serial communication protocol x x | ← to TA register → | x x | ← to RA register → | 0 0 d13 and d6 are MSBs (unsigned binary) x | ← to TA’ register → | x | ← to RA’ register → | 0 1 d14 and d7 are 2s complement sign bits x | ← to TB register → | x | ← to RB register → | 1 0 d14 and d7 are MSBs (unsigned binary) 1 1 x x x x x x x x d7 d6 d5 d4 d3 d2 d2 = 0/1 deletes/inserts the band-pass filter | | Control Register d3 = 0/1 disables/enables the loopback function d4 = 0/1 disables/enables the AUX IN + and AUX IN – terminals d5 = 0/1 asynchronous/synchronous transmit and receive sections d6 = 0/1 gain control bits (see gain control section) d7 = 0/1 gain control bits (see gain control section) reset function A reset function is provided to initiate serial communications between the AIC and DSP. The reset function will initialize all AIC registers, including the control register. After power has been applied to the AIC, a negative-going pulse on RESET will initialize the AIC registers to provide an 8-kHz A/D and D/A conversion rate for a 5.184-MHz master clock input signal. The AIC, except the control register, will be initialized as follows (see AIC DX data word format section): REGISTER INITIALIZED REGISTER VALUE (HEX) TA TA’ 9 1 TB 24 RA 9 RA’ 1 RB 24 The control register bits will be reset as follows (see AIC DX data word format section): d7 = 1, d6 = 1, d5 = 1, d4 = 0, d3 = 0, d2 = 1 This initialization allows normal serial port communications to occur between the AIC and DSP. If the transmit and receive sections are configured to operate synchronously and the user wishes to program different conversion rates, only the TA, TA’, and TB registers need to be programmed, since both transmit and receive timing are synchronously derived from these registers (see the Terminal Functions table and AIC DX data word format section). The circuit shown below provides a reset on power up when power is applied in the sequence given under power-up sequence. The circuit depends on the power supplies’ reaching their recommended values a minimum of 800 ns before the capacitor charges to 0.8 V above DGTL GND. VCC + 5V 200 kΩ RESET 0.5 µF VCC – 4–8 POST OFFICE BOX 655303 –5 V • DALLAS, TEXAS 75265 TLC32040M ANALOG INTERFACE CIRCUIT power-up sequence To ensure proper operation of the AIC and as a safeguard against latch-up, it is recommended that a Schottky diode with a forward voltage less than or equal to 0.4 V be connected from VCC – to ANLG GND (see Figure 16). In the absence of such a diode, power should be applied in the following sequence: ANLG GND and DGTL GND, VCC –, then VCC + and VDD. Also, no input signal should be applied until after power up. AIC responses to improper conditions The AIC has provisions for responding to improper conditions. These improper conditions and the response of the AIC to these conditions are presented in Table 1 below. AIC register constraints The following constraints are placed on the contents of the AIC registers: 1. TA register must be ≥ 4 in WORD mode (WORD/BYTE = high). 2. TA register must be ≥ 5 in BYTE mode (WORD/BYTE = low). 3. TA’ register can be either positive, negative, or zero. 4. RA register must be ≥ 4 in WORD mode (WORD/BYTE = high). 5. RA register must be ≥ 5 in BYTE mode (WORD/BYTE = low). 6. RA’ register can be either positive, negative, or zero. 7. (TA register ± TA’ register) must be > 1. 8. (RA register ± RA’ register) must be > 1. 9. TB register must be > 1. Table 1. AIC Responses to Improper Conditions IMPROPER CONDITION AIC RESPONSE TA register + TA’ register = 0 or 1 TA register – TA’ register = 0 or 1 Reprogram TX Counter A with TA register value TA register + TA’ register < 0 MODULO 64 arithmetic is used to ensure that a positive value is loaded into the TX Counter A, i.e., TA register + TA’ register + 40 HEX is loaded into TX Counter A. RA register + RA’ register = 0 or 1 RA register – RA’ register = 0 or 1 Reprogram RX Counter A with RA register value RA register + RA’ register = 0 or 1 MODULO 64 arithmetic is used to ensure that a positive value is loaded into the RX Counter A, i.e., RA register + RA’ register + 40 HEX is loaded into RX Counter A. TA register = 0 or 1 RA register = 0 or 1 AIC is shutdown. TA register < 4 in WORD mode TA register < 5 in BYTE mode RA register < 4 in WORD mode RA register < 5 in BYTE mode The AIC serial port no longer operates. TB register = 0 or 1 Reprogram TB register with 24 HEX RB register = 0 or 1 Reprogram TB register with 24 HEX AIC and DSP cannot communicate Hold last DAC output POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 4–9 TLC32040M ANALOG INTERFACE CIRCUIT improper operation due to conversion times being too close together If the difference between two successive D/A conversion frame syncs is less than 1/19.2 kHz, the AIC operates improperly. In this situation, the second D/A conversion frame sync occurs too quickly, and there is not enough time for the ongoing conversion to be completed. This situation can occur if the A and B registers are improperly programmed or if the A + A’ register or A – A’ register result is too small. When incrementally adjusting the conversion period via the A + A’ register options, the designer should be careful not to violate this requirement (see following diagram). t1 Frame Sync, FSX, or FSR t2 Ongoing Conversion t2 – t1 ≥ 1/19.2 kHz asynchronous operation – more than one receive frame sync occurring between two transmit frame syncs When incrementally adjusting the conversion period via the A + A’ or A – A’ register options, a specific protocol is followed. The command to use the incremental conversion period adjust option is sent to the AIC during an FSX frame sync. The ongoing conversion period is then adjusted. However, either Receive Conversion Period A or B may be adjusted. For both transmit and receive conversion periods, the incremental conversion period adjustment is performed near the end of the conversion period. Therefore, if there is sufficient time between t1 and t2, the receive conversion period adjustment will be performed during Receive Conversion Period A. Otherwise, the adjustment will be performed during Receive Conversion Period B. The adjustment command only adjusts one transmit conversion period and one receive conversion period. To adjust another pair of transmit and receive conversion periods, another command must be issued during a subsequent FSX frame (see figure below). t1 FSX Transmit Conversion Period t2 FSR Receive Conversion Period A Receive Conversion Period B asynchronous operation – more than one transmit frame sync occurring between two receive frame syncs When incrementally adjusting the conversion period via the A + A’ or A – A’ register options, a specific protocol is followed. For both transmit and receive conversion periods, the incremental conversion period adjustment is performed near the end of the conversion period. The command to use the incremental conversion period adjust options is sent to the AIC during an FSX frame sync. The ongoing transmit conversion period is then adjusted. However, three possibilities exist for the receive conversion period adjustment in the diagram as shown in the figure on the following page. If the adjustment command is issued during Transmit Conversion Period A, Receive Conversion Period A will be adjusted if there is sufficient time between t1 and t2. If there is not sufficient time between t1 and t2, Receive Conversion Period B will be adjusted. The receive portion of an adjustment command may be ignored if the adjustment command is sent during a receive conversion period, which is already being or will be adjusted due to a prior adjustment command. For example, if adjustment 4–10 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 TLC32040M ANALOG INTERFACE CIRCUIT commands are issued during Transmit Conversion Periods A, B, and C, the first two commands may cause Receive Conversion Periods A and B to be adjusted, while the third receive adjustment command is ignored. The third adjustment command is ignored since it was issued during Receive Conversion Period B, which already will be adjusted via the Transmit Conversion Period B adjustment command. t1 FSX Transmit Conversion Period A t2 Transmit Conversion Period B Transmit Conversion Period C FSR Receive Conversion Period B Receive Conversion Period A asynchronous operation – more than one set of primary and secondary DX serial communication occurring between two receive frame sync (see AIC DX data word format section) The TA, TA’, TB, and control register information that is transmitted in the secondary communications is always accepted and is applied during the ongoing transmit conversion period. If there is sufficient time between t1 and t2, the TA, RA’, and RB register information, which is sent during Transmit Conversion Period A, will be applied to Receive Conversion Period A. Otherwise, this information will be applied during Receive Conversion Period B. If RA, RA’, and RB register information has already been received and is being applied during an ongoing conversion period, any subsequent RA, RA’, or RB information that is received during this receive conversion period will be disregarded (see diagram below). Primary t1 Secondary Primary Secondary Primary Secondary FSX Transmit Conversion Period A Transmit Conversion Period B Transmit Conversion Period C t2 FSR Receive Conversion Period A Receive Conversion Period B POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 4–11 TLC32040M ANALOG INTERFACE CIRCUIT absolute maximum ratings over operating free-air temperature range (unless otherwise noted) Supply voltage range, VCC+ (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.3 V to 15 V Supply voltage range, VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.3 V to 15 V Output voltage range, VO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.3 V to 15 V Input voltage range, VI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.3 V to 15 V Digital ground voltage range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.3 V to 15 V Operating free-air temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 55°C to 125°C Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 65°C to 150°C Case temperature for 60 seconds: FK package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C Lead temperature 1,6 mm (1/16 inch) from case for 60 seconds: J package . . . . . . . . . . . . . . . . . . . . . 300°C NOTE 1: Voltage values for maximum ratings are with respect to VCC –. recommended operating conditions PARAMETER MIN NOM MAX UNIT Supply voltage, VCC+ (see Note 2) 4.75 5 5.25 V Supply voltage, VCC– (see Note 2) – 4.75 –5 – 5.25 V 4.75 5 5.25 V Digital supply voltage, VDD (see Note 2) Digital ground voltage with respect to ANLG GND, DGTL GND 0 V Reference input voltage, Vref(ext) (see Note 2) 2 4 V High-level input voltage, VIH 2 VDD+0.3 0.8 V Low-level input voltage, VIL (see Note 3) – 0.3 Maximum peak output voltage swing across RL at OUT+ or OUT– (single ended) (see Note 4) Load resistance at OUT+ and/or OUT–, RL ±3 V Ω 300 Load capacitance at OUT+ and/or OUT–, CL 100 MSTR CLK frequency (see Note 5) 0.075 5 10.368 ± 1.5 Analog input amplifier common-mode input voltage (see Note 6) A/D or D/A conversion rate V 20 pF MHz V kHz Operating free-air temperature, TA – 55 125 °C NOTES: 2. Voltages at analog inputs and outputs, REF, VCC+, and VCC–, are with respect to the ANLG GND terminal. Voltages at digital inputs and outputs and VDD are with respect to the DGTL GND terminal. 3. The algebraic convention, in which the least positive (most negative) value is designated minimum, is used in this data sheet for logic voltage levels and temperature only. 4. This applies when RL ≥ 300 Ω and offset voltage = 0. 5. The band-pass and low-pass switched-capacitor filter response specifications apply only when the switched-capacitor clock frequency is 288 kHz. For switched-capacitor filter clocks at frequencies other than 288 kHz, the filter response is shifted by the ratio of switched-capacitor filter clock frequency to 288 kHz. 6. This range applies when (IN + – IN –) or (AUX IN + – AUX IN –) equals ± 6 V. 4–12 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 TLC32040M ANALOG INTERFACE CIRCUIT electrical characteristics over recommended operating free-air temperature range, VCC+ = 5 V, VCC– = –5 V, VDD = 5 V (unless otherwise noted) total device, MSTR CLK frequency = 5.184 MHz, outputs not loaded PARAMETER VOH VOL High-level output voltage ICC + ICC – Supply current from VCC+ IDD Vref Supply current from VDD αVref ro TEST CONDITIONS VDD = 4.75 V, VDD = 4.75 V, Low-level output voltage IOH = – 300 µA IOL = 2 mA MIN TYP† UNIT V Supply current from VCC– fMSTR CLK = 5.184 MHz Internal reference output voltage MAX 2.4 2.9 0.9 V 40 mA – 40 mA 7 mA 3.3 V Temperature coefficient of internal reference voltage 200 ppm/°C Output resistance at REF 100 kΩ receive amplifier input TYP† MAX A/D converter offset error (filters bypassed) 25 65 mV A/D converter offset error (filters in) 25 65 mV PARAMETER CMRR rI TEST CONDITIONS Common-mode rejection ratio at IN +, IN –, or AUX IN+, AUX IN– See Note 7 MIN 35 Input resistance at IN +, IN – or AUX IN +, AUX IN –, REF UNIT 55 dB 100 kΩ NOTE 7: The test condition is a 0-dBm, 1-kHz input signal with an 8-kHz conversion rate. transmit filter output PARAMETER TEST CONDITIONS VOO Output offset voltage at OUT+ or OUT– (single ended relative to ANLG GND) VOM Maximum peak output voltage swing between OUT+ and OUT– (differential output) RL ≥ 300 Ω MIN TYP† MAX 15 75 ±6 UNIT mV V system distortion specifications, SCF clock frequency = 288 kHz MIN TYP† VI = – 0.5 dB to – 24 dB referred to Vref, Single-ended tested at 25°C, See Note 8 62 70 62 70 VI = – 0.5 dB to – 24 dB referred to Vref, Single-ended tested at 25°C, See Note 8 57 65 57 65 PARAMETER TEST CONDITIONS Attenuation of second harmonic of Single ended A/D input signal Differential Attenuation of third and higher Single ended harmonics of A/D input signal Differential Attenuation of second harmonic of Single ended D/A input signal Differential VI = – 0 dB to – 24 dB referred to Vref, See Note 8 MAX UNIT dB dB 70 62 70 dB Attenuation of third and higher Single ended VI = – 0 dB to – 24 dB referred to Vref, 65 dB harmonics of D/A input signal Differential See Note 8 57 65 † All typical values are at TA = 25°C. NOTE 8: The test condition is a 1-kHz input signal with an 8-kHz conversion rate (0 dB relative to Vref). The load impedance for the DAC is 300 Ω. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 4–13 TLC32040M ANALOG INTERFACE CIRCUIT electrical characteristics over recommended operating free-air temperature range, VCC+ = 5 V, VCC– = –5 V, VDD = 5 V (unless otherwise noted) (continued) A/D channel signal-to-distortion ratio TEST CONDITIONS (see Note 8) PARAMETER AV = 1† MIN MAX AV = 2† MIN MAX >58‡ AV = 4† MIN MAX >58‡ VI = – 6 dB to – 0.5 dB VI = –12 dB to – 6 dB 58 58 58 >58‡ VI = – 18 dB to –12 dB VI = – 24 dB to –18 dB 56 58 58 50 56 58 VI = – 30 dB to – 24 dB VI = – 36 dB to – 30 dB 44 50 56 38 44 50 VI = – 42 dB to – 36 dB VI = – 48 dB to – 42 dB 32 38 44 26 32 38 VI = – 54 dB to – 48 dB † AV is the programmable gain of the input amplifier. ‡ A value > 58 is overrance and signal clipping occurs over range. 20 26 32 A/D channel signal-to-distortion ratio UNIT dB D/A channel signal-to-distortion ratio TEST CONDITIONS (see Note 8) PARAMETER D/A channel signal-to-distortion ratio MIN VI = – 6 dB to 0 dB VI = –12 dB to – 6 dB 58 VI = –18 dB to – 12 dB VI = – 24 dB to – 18 dB 56 VI = – 30 dB to – 24 dB VI = – 36 dB to – 30 dB 44 VI = – 42 dB to – 36 dB VI = – 48 dB to – 42 dB 32 MAX UNIT 58 50 dB 38 26 VI = – 54 dB to – 48 dB 20 NOTE 8: The test condition is a 1-kHz input signal with an 8-kHz conversion rate (0 dB relative to Vref). The load impedance for the DAC is 300 Ω. gain and dynamic range TYP§ MAX UNIT Absolute transmit gain tracking error while transmitting into 300 Ω – 48-dB to 0-dB signal range, See Note 9 ± 0.05 ± 0.15 dB Absolute receive gain tracking error – 48-dB to 0-dB signal range, See Note 9 ± 0.05 ± 0.15 dB Absolute gain of the A/D channel Signal input is a – 0.5 dB, 1-kHz sinewave Absolute gain of the D/A channel Signal input is a 0-dB, 1-kHz sinewave PARAMETER TEST CONDITIONS § All typical values are at TA = 25°C. NOTE 9. Gain tracking is relative to the absolute gain at 1 kHz and 0 dB (0 db relative to Vref). 4–14 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 MIN 0.2 dB – 0.3 dB TLC32040M ANALOG INTERFACE CIRCUIT electrical characteristics over recommended operating free-air temperature range, VCC+ = 5 V, VCC– = –5 V, VDD = 5 V (unless otherwise noted) (continued) power supply rejection and crosstalk attenuation PARAMETER VCC+ or VCC – supply voltage rejection ratio, receive channel TEST CONDITIONS TYP† Idle channel, Supply signal at 200 mV p-p 30 f = 30 kHz to 50 kHz measured at DR (ADC output) 45 Idle channel, Supply signal at 200 mV p-p 30 measured at OUT+ 45 VCC+ or VCC – supply voltage rejection f = 0 to 30 kHz ratio, transmit channel (single ended) f = 30 kHz to 50 kHz Crosstalk attenuation (differential) MIN f = 0 to 30 kHz Transmit-to-receive DX = 00000000000000 70 80 Receive-to-transmit Inputs grounded 70 80 MAX UNIT dB dB dB delay distortion, SCF clock frequency = 288 kHz ± 2%, input (IN+ – IN –) is ± 3-V sinewave Please refer to filter response graphs for delay distortion specifications. band-pass filter transfer function (see curves), SCF clock frequency = 288 kHz ± 2%, input (IN + – IN –) is a ± 3-V sinewave (see Note 9) PARAMETER TEST CONDITIONS MIN f = 100 Hz Filter gain (see Note 10) Input signal reference is 0 dB MAX UNIT – 42 f = 170 Hz – 25 300 Hz ≤ f ≤ 3.4 kHz ± 0.5 f = 4 kHz – 16 f ≥ 4.6 kHz – 58 dB low-pass filter transfer function, SCF clock frequency = 288 kHz ± 2% (see Note 10) PARAMETER TEST CONDITIONS MIN f ≤ 3.4 kHz Output signal reference is 0 dB UNIT ± 0.5 f = 3.6 kHz Filter gain (see Note 11) MAX –4 f = 4 kHz – 30 f ≥ 4.4 kHz – 58 dB serial port PARAMETER VOH VOL High-level output voltage II CI Input current Low-level output voltage TEST CONDITIONS MIN IOH = – 300 µA IOL = 2 mA 2.4 Input capacitance TYP† MAX UNIT V 15 0.4 V ±10 µA pF CO Output capacitance 15 pF † All typical values are at TA = 25°C. NOTES: 9. Gain tracking is relative to the absolute gain at 1 kHz and 0 dB (–0 db relative to Vref). 10. The above filter specifications are for a switched-capacitor filter clock range of 288 kHz ± 2%. For switched-capacitor filter clocks at frequencies other than 288 kHz ± 2 %, the filter response is shifted by the ratio of switched-capacitor filter clock frequency to 288 kHz. 11. The filter gain outside of the pass band is measured with respect to the gain at 1 kHz. The filter gain within the pass band is measured with respect to the average gain within the pass band. The pass bands are 300 to 3400 Hz and 0 to 3400 Hz for the band pass and low-pass filters respectively. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 4–15 TLC32040M ANALOG INTERFACE CIRCUIT operating characteristics over recommended operating free-air temperature range, VCC+ = 5 V, VCC– = –5 V, VDD = 5 V noise (measurement includes low-pass and band-pass switched-capacitor filters) PARAMETER TYP† TEST CONDITIONS Single ended Transmit noise DX input = 00000000000000, constant input code Differential MAX 300 500 20 Receive noise (see Note 12) 300 Inputs grounded, gain = 1 UNIT µV rms 200 µV rms dBrnc0 475 20 µV rms dBrnc0 NOTE 12. This noise is referred to the input with a buffer gain of one. If the buffer gain is two or four, the noise figure will be correspondingly reduced. The noise is computed by statistically evaluating the digital output of the A/D converter. timing requirements serial port recommended input signals PARAMETER tc(MCLK) Master clock cycle time tr(MCLK) Master clock rise time tf(MCLK) tsu(DX) MIN MAX UNIT 100 192 ns 10 ns 10 ns Master clock fall time Master clock duty cycle 42% RESET pulse duration (see Note 13) 800 ns 28 ns DX setup time before SCLK↓ 58% DX hold time before SCLK↓ tc(SCLK)/4 ns th(DX) NOTE 13. RESET pulse duration is the amount of time that the reset pin is held below 0.8 V after the power supplies have reached their recommended values. serial port – AIC output signals PARAMETER MIN Shift clock (SCLK) cycle time TYP† MAX 400 UNIT tc(SCLK) tf(SCLK) Shift clock (SCLK) fall time 50 ns tr(SCLK) Shift clock (SCLK) rise time 50 ns Shift clock (SCLK) duty cycle ns 50% td(CH-FL) td(CH-FH) Delay from SCLK↑ to FSR/FSX↓ 260 ns Delay from SCLK↑ to FSR/FSX↑ 260 ns td(CH-DR) tdw(CH-EL) DR valid after SCLK↑ 316 ns Delay from SCLK↑ to EODX/EODR↓ in WORD mode 280 ns tdw(CH-EH) tf(EODX) Delay from SCLK↑ to EODX/EODR↑ in WORD mode 280 ns EODX fall time 15 ns tf(EODR) tdb(CH-EL) EODR fall time 15 ns Delay from SCLK↑ to EODX/EODR↓ in BYTE mode 100 ns tdb(CH-EH) td(MH-SL) Delay from SCLK↑ to EODX/EODR↑ in BYTE mode 100 ns Delay from MSTR CLK ↑ to SCLK↓ 65 td(MH-SH) Delay from MSTR CLK ↑ to SCLK↓ † All typical values are at TA = 25°C. 65 4–16 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 105 ns ns TLC32040M ANALOG INTERFACE CIRCUIT Table 2. Gain Control Table (Analog Input Signal Required for Full-Scale A/D Conversion) CONTROL REGISTER BITS INPUT CONFIGURATIONS d6 d7 Differential configuration 1 1 Analog input = IN+ – IN– 0 0 1 0 Single-ended configuration 1 1 Analog input = IN+ – ANLG GND 0 0 1 0 = AUX IN+ – AUX IN– = AUX IN+ – ANLG GND A/D CONVERSION ANALOG INPUT† RESULT ±6 V Full scale 0 ±3 V Full scale 1 ± 1.5 V Full scale ±3 V Half scale 0 ±3 V Full scale 1 ± 1.5 V Full scale † In this example, Vref is assumed to be 3 V. In order to minimize distortion, it is recommended that the analog input not exceed 0.1 dB below full scale. Rfb IN + IN – Rfb R – R AUX IN + + R To MUX – R AUX IN – + – + Rfb To MUX – + Rfb Rfb = R for d6 = 1, d7 = 1 d6 = 0, d7 = 0 Rfb = 2R for d6 = 1, d7 = 0 Rfb = 4R for d6 = 0, d7 = 1 Rfb = R for d6 = 1, d7 = 1 d6 = 0, d7 = 0 Rfb = 2R for d6 = 1, d7 = 0 Rfb = 4R for d6 = 0, d7 = 1 Figure 1. IN + and IN – Gain Control Circuitry Figure 2. AUX IN + and AUX IN – Gain Control Circuitry (sin x)/x correction section The AIC does not have (sin x)/x correction circuitry after the digital-to-analog converter. (sin x)/x correction can be accomplished easily and efficiently in digital signal processor (DSP) software. Excellent correction accuracy can be achieved to a band edge of 3000 Hz by using a first-order digital correction filter. The results, which are shown on the next page, are typical of the numerical correction accuracy that can be achieved for sample rates of interest. The filter requires only seven instruction cycles per sample on the SMJ320 DSPs. With a 200-ns instruction cycle, nine instructions per sample represents an overhead factor of 1.4% and 1.7% for sampling rates of 8000 Hz and 9600 Hz, respectively. This correction will add a slight amount of group delay at the upper edge of the 300 – 3000-Hz band. (sin x)/x roll-off for a zero-order hold function The (sin x)/x roll-off for the AIC DAC zero-order hold function at a band-edge frequency of 3000 Hz for the various sampling rates is shown in the following table. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 4–17 TLC32040M ANALOG INTERFACE CIRCUIT Table 3. (sin x)/x Roll-Off f s (Hz) 20 log sin π f/fs π f/fs (f = 3000 Hz) (dB) – 2.64 – 2.11 –1.44 – 0.63 – 0.35 7200 8000 9600 14400 19200 Note that the actual AIC (sin x)/x roll-off will be slightly less than the above figures because the AIC has less than a 100% duty cycle hold interval. correction filter To compensate for the (sin x)/x roll-off of the AIC, a first-order correction filter shown below, is recommended. + u(i + 1) X Σ y(i + 1) + X (1– p1)P2 p1 The difference equation for this correction filter is: Y i ) 1 + p2(1 * p1) (ui ) 1) ) p1 Yi where the constant p1 determines the pole locations. The resulting squared magnitude transfer function is: H (f)2 = 4–18 p22 (1 – p1)2 1 – 2p1 cos(2 π f/fs) + p12 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 Z–1 TLC32040M ANALOG INTERFACE CIRCUIT correction results Table 4 below shows the optimum p values and the corresponding correction results for 8000-Hz and 9600-Hz sampling rates. Table 4. Optimum P Values f (Hz) 300 600 900 1200 1500 1800 2100 2400 2700 3000 ERROR (dB) fs = 8000 Hz p1 = – 0.14813 p2 = 0.9888 – 0.099 – 0.089 – 0.054 – 0.002 0.041 0.079 0.100 0.091 – 0.043 – 0.102 ERROR (dB) fs = 9600 Hz p1 = – 0.1307 p2 = 0.9951 – 0.043 – 0.043 0 0 0 0.043 0.043 0.043 0 – 0.043 SMJ320 software requirements The digital correction filter equation can be written in state variable form as follows: Y = k1Y + k2U where k1 equals p1 (from the preceding page), k2 equals (1 – p1)p2 (from the preceding page), Y is the filter state, and U is the next I/O sample. The coefficients k1 and k2 must be represented as 16-bit integers. The SACH instruction (with the proper shift) will yield the correct result. With the assumption that the SMJ320 processor page pointer and memory configuration are properly initialized, the equation can be executed in seven instructions or seven cycles with the following program: ZAC LT K2 MPY U LTA K1 MPY Y APAC SACH (dma), (shift) POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 4–19 TLC32040M ANALOG INTERFACE CIRCUIT PARAMETER MEASUREMENT INFORMATION tf(SCLK) 2V tc(SCLK) tr(SCLK) 2V 2V 2V 2V 2V 2V SHIFT CLK 0.8 V 0.8 V td(CH-FL) FSR, FSX 2V 0.8 V td(CH-FH) td(CH-FL) td(CH-FH) 2V 0.8 V td(CH-DR) 2V DR D15 D14 tsu(DX) DX D15 D13 D9 D8 D7 D6 D2 D1 D0 D1 D0 0.8 V D14 D13 D9 Don’t Care D8 th(DX) D7 D6 D2 tdb(CH-EH) tdb(CH-EL) EODR, EODX 2V 0.8 V (a) BYTE-MODE TIMING tc(SCLK) 2V 2V 2V 2V SHIFT CLK 0.8 V 0.8 V 0.8 V td(CH-FH) td(CH-FL) FSX, FSR 2V 0.8 V td(CH-DR) DR D15 D14 D13 D12 D11 D2 D1 D0 D13 D12 D11 D2 D1 D0 tsu(DX) DX D15 D14 th(DX) tdw(CH-EL) EODX, EODR tdw(CH-EH) 0.8 V (b) WORD-MODE TIMING MSTR CLK td(MH-SH) td(MH-SL) SHIFT CLK (c) SHIFT-CLOCK TIMING Figure 3. Serial Port Timing 4–20 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 Don’t Care 2V TLC32040M ANALOG INTERFACE CIRCUIT PARAMETER MEASUREMENT INFORMATION SMJ320C10 FSX SN54LS299 S1 DEN A2/PA2 DX G2 G1 A0/PA0 A1/PA1 Q H′ A Y1 S0 D8–D15 CLK G1 Y0 B C A–H SN54LS138 SR SN54LS299 S1 SHIFT CLK Q H′ G2 S0 DO–D15 CLK G1 A–H DO – D15 SN54LS74 C1 SR 1D DR DO–D7 WE MSTR CLK CLK OUT EODX INT Figure 4. SMJ320C10/SMJ320C15/SMJ320E15-TLC32040M Interface Circuit CLK OUT DEN S0, G1 D0 – D15 Valid (a) IN INSTRUCTION TIMING CLK OUT WE SN74LS138 Y1 SN74LS299 CLK D0 – D15 Valid (b) OUT INSTRUCTION TIMING Figure 5. SMJ320C10/SMJ320C15/SMJ320E15-TLC32040M Interface TIming POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 4–21 TLC32040M ANALOG INTERFACE CIRCUIT TYPICAL CHARACTERISTICS AIC TRANSMIT CHANNEL FILTER† ÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎ 10 0.3 Magnitude –10 –20 0.25 0.2 0.15 Magnitude – dB Group Delay –30 0.1 See Note B –40 –50 –60 0.05 0 0.05 See Note A –70 Relative Group Delay – ms 0 0.1 See Note C –80 –90 0.15 0.2 0 0.5 1 1.5 2 2.5 3 Normalized Frequency – kHz × 3.5 4 4.5 5 SCF Clock Frequency 288 kHz † Test conditions are VCC +, VCC –, and VDD within recommended operating conditions, SCF clock f = 288 kHz ± 2%, input = ± 3-V sinewave, and TA = 25°C. NOTES: A. Maximum relative delay (0 Hz to 600 Hz) = 125 µs B. Maximum relative delay (600 Hz to 3000 Hz) = ± 50 µs C. Absolute delay (600 Hz to 3000 Hz) = 700 µs Figure 6 4–22 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 TLC32040M ANALOG INTERFACE CIRCUIT TYPICAL CHARACTERISTICS ÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎ TLC32040 RECEIVE CHANNEL FILTER† Magnitude – dB 0 See Note A 0.35 Magnitude 0.3 –10 0.25 –20 0.2 –30 0.15 –40 ÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎ 0.1 Group Delay –50 –60 –70 0.05 0 Relative Group Delay – ms 10 0.05 See Note B –80 0.1 See Note C –90 0 1 2 0.15 3 Normalized Frequency – kHz × 4 5 SCF Clock Frequency 288 kHz † Test conditions are VCC +, VCC –, and VDD within recommended operating conditions, SCF clock f = 288 kHz ± 2%, input = ± 3-V sinewave, and TA = 25°C. NOTES: A. Maximum relative delay (200 Hz to 600 Hz) = 3350 µs B. Maximum relative delay (600 Hz to 3000 Hz) = ± 50 µs C. Absolute delay (600 Hz to 3000 Hz) = 1230 µs Figure 7 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 4–23 TLC32040M ANALOG INTERFACE CIRCUIT TYPICAL CHARACTERISTICS† A/D SIGNAL-TO-DISTORTION RATIO vs INPUT SIGNAL 80 ÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ 0.5 1-kHz Input Signal With an 8-kHz Conversion Rate 0.4 Gain = 4X 60 50 0.3 ÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎ 1-kHz Input Signal 8-kHz Conversion Rate Gain = 1X Gain Tracking – dB Signal-to-Distortion Ratio – dB 70 A/D GAIN TRACKING (GAIN RELATIVE TO GAIN AT 0-dB INPUT SIGNAL) 40 30 0.2 0.1 0 – 0.1 – 0.2 20 – 0.3 10 – 0.4 0 – 50 – 40 –3 – 20 – 10 0 0 Input Signal Relative to Vref – dB – 0.5 – 50 10 – 40 Figure 8 ÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎ 70 0.4 Gain Tracking – dB Signal-to-Distortion Ratio – dB 0.6 60 50 40 0 – 0.2 – 0.4 20 – 0.6 10 – 0.8 –10 0 10 1-kHz Input Signal into 600 Ω 8-kHz Conversion Rate 0.2 30 –20 –1 – 50 – 40 – 30 – 20 Figure 10 Figure 11 POST OFFICE BOX 655303 –10 Input Signal Relative to Vref – dB Input Signal Relative to Vref – dB 4–24 10 ÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎ 0.8 80 –30 0 1.0 1-kHz Input Signal into 600 Ω 8-kHz Conversion Rate – 40 – 10 D/A GAIN TRACKING (GAIN RELATIVE TO GAIN AT 0-dB INPUT SIGNAL) 100 0 – 50 – 20 Figure 9 D/A CONVERTER SIGNAL-TO-DISTORTION RATIO vs INPUT SIGNAL 90 – 30 Input Signal Relative to Vref – dB • DALLAS, TEXAS 75265 0 10 TLC32040M ANALOG INTERFACE CIRCUIT † Test conditions are VCC +, VCC –, and VDD within recommended operating conditions SCF clock f = 288 kHz ± 2%, and TA = 25°C. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 4–25 TLC32040M ANALOG INTERFACE CIRCUIT TYPICAL CHARACTERISTICS† ATTENUATION OF THIRD HARMONIC OF A/D INPUT vs INPUT SIGNAL 100 100 90 90 Attenuation of Third Harmonic – dB Attenuation of Second Harmonic – dB ATTENUATION OF SECOND HARMONIC OF A/D INPUT vs INPUT SIGNAL 80 70 60 50 40 30 20 10 ÎÎÎÎÎÎ ÎÎÎÎÎÎÎ ÎÎÎÎÎÎ 1-kHz Input Signal 8-kHz Conversion Rate 0 – 50 80 ÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎ 1-kHz Input Signal 8-kHz Conversion Rate 70 60 50 40 30 20 10 – 40 – 30 – 20 – 10 0 Input Signal Relative to Vref – dB 0 – 50 10 – 40 – 30 – 20 – 10 0 Input Signal Relative to Vref – dB Figure 12 Figure 13 ATTENUATION OF SECOND HARMONIC OF D/A INPUT vs INPUT SIGNAL ÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎ 90 100 1-kHz Input Signal into 600 Ω 8-kHz Conversion Rate 90 80 70 60 50 40 30 20 10 0 – 50 ATTENUATION OF THIRD HARMONIC OF D/A INPUT vs INPUT SIGNAL Attenuation of Third Harmonic – dB Attenuation of Second Harmonic – dB 100 80 ÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎ 1-kHz Input Signal into 600 Ω 8-kHz Conversion Rate 70 60 50 40 30 20 10 – 40 – 30 – 20 – 10 0 10 0 – 50 – 40 Input Signal Relative to Vref – dB – 30 – 20 – 10 0 Input Signal Relative to Vref – dB Figure 14 Figure 15 † Test conditions are VCC +, VCC –, and VDD within recommended operating conditions SCF clock f = 288 kHz ± 2%, and TA = 25°C. 4–26 10 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 10 TLC32040M ANALOG INTERFACE CIRCUIT APPLICATION INFORMATION C = 0.2 µF, Ceramic CLKOUT FSX FSX DX DX TMS32020/C25 FSR DR CLKR 5V VCC+ MSTR CLK REF C C ANLG GND FSR DR SHIFT CLK TLC32040/TLC32041 / TLC32042 CLKX BAT 42† C VCC – –5 V VDD 5V 0.1 µF DGTL GND † Thomson Semiconductors Figure 16. AIC Interface to SMJ32020/C25 Showing Decoupling Capacitors and Schottky Diode† PRINCIPLES OF OPERATION analog input Two sets of analog inputs are provided. Normally, the IN + and IN – input set is used; however, the auxiliary input set, AUX IN + and AUX IN –, can be used if a second input is required. Each input set can be operated in either differential or single-ended modes, since sufficient common-mode range and rejection are provided. The gain for the IN +, IN –, AUX IN +, and AUX IN – inputs can be programmed to be either 1, 2, or 4 (see Table 2). Either input circuit can be selected via software control. It is important to note that a wide dynamic range is assured by the differential internal analog architecture and by the separate analog and digital voltage supplies and grounds. A/D band-pass filter, A/D band-pass filter clocking, and A/D conversion timing The A/D band-pass filter can be selected or bypassed via software control. The frequency response of this filter is presented in the following pages. This response results when the switched-capacitor filter clock frequency is 288 kHz. Several possible options can be used to attain a 288-kHz switched-capacitor filter clock. When the filter clock frequency is not 288 kHz, the filter transfer function is frequency scaled by the ratio of the actual clock frequency to 288 kHz. The low-frequency roll-off of the high-pass section is 300 Hz. The internal timing configuration and AIC DX data word format sections of this data sheet indicate the many options for attaining a 288-kHz band-pass switched-capacitor filter clock. These sections indicate that RX Counter A can be programmed to give a 288-kHz band-pass switched-capacitor filter clock for several master clock input frequencies. The A/D conversion rate is then attained by frequency dividing the 288-kHz band-pass switched-capacitor filter clock with RX Counter B. Thus unwanted aliasing is prevented because the A/D conversion rate is an integral submultiple of the band-pass switched-capacitor filter sampling rate, and the two rates are synchronously locked. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 4–27 TLC32040M ANALOG INTERFACE CIRCUIT PRINCIPLES OF OPERATION A/D converter performance specifications Fundamental performance specifications for the A/D converter circuitry are presented in the A/D converter operating characteristics section of this data sheet. The design of the A/D converter circuitry with switchedcapacitor techniques provides an inherent sample and hold. analog output The analog output circuitry is an analog output power amplifier. Both noninverting and inverting amplifier outputs are brought out of the integrated circuit. This amplifier can drive transformer hybrids or low-impedance loads directly in either a differential or single-ended configuration. D/A low-pass filter, D/A low-pass filter clocking, and D/A conversion timing The frequency response of this filter is presented in the following pages. This response results when the low-pass switched-capacitor filter clock frequency is 288 kHz. Like the A/D filter, the transfer function of this filter is frequency scaled when the clock frequency is not 288 kHz. A continuous-time filter is provided on the output of the D/A low-pass filter to greatly attenuate any switched-capacitor clock feedthrough. The D/A conversion rate is then attained by frequency dividing the 288-kHz switched-capacitor filter clock with TX Counter B. Thus, unwanted aliasing is prevented because the D/A conversion rate is an integral submultiple of the switched-capacitor low-pass filter sampling rate, and the two rates are synchronously locked. asynchronous versus synchronous operation If the transmit section of the AIC (low-pass filter and DAC) and receive section (band-pass filter and ADC) are operated asynchronously, the low-pass and band-pass filter clocks are independently generated from the master clock signal. Also, the D/A and A/D conversion rates are independently determined. If the transmit and receive sections are operated synchronously, the low-pass filter clock drives both low-pass and band-pass filters. In synchronous operation, the A/D conversion timing is derived from, and is equal to, the D/A conversion timing. (See description of WORD/BYTE in the Terminal Functions table.) D/A converter performance specifications Fundamental performance specifications for the D/A converter circuitry are presented in the D/A converter operating characteristics section of the data sheet. The D/A converter has a sample and hold that is realized with a switched-capacitor ladder. system frequency response correction (Sin x)/x correction circuitry is performed in digital signal processor software. The system frequency response can be corrected via DSP software to 0.1-dB accuracy to a band-edge of 3000 Hz for all sampling rates. This correction is accomplished with a first-order digital correction filter, which requires only seven SMJ320 instruction cycles. With a 200-ns instruction cycle, seven instructions represent an overhead factor of only 1.1% and 1.3% for sampling rates of 8 and 9.6 kHz, respectively [see the (sin x)/x correction section for more details]. 4–28 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 TLC32040M ANALOG INTERFACE CIRCUIT PRINCIPLES OF OPERATION serial port The serial port has four possible modes that are described in detail in the terminal functions table. These modes are briefly described below and in the description for terminal 13, WORD/BYTE. 1. The transmit and receive sections are operated asynchronously, and the serial port interfaces directly with the DSP in two 8-bit bytes. 2. The transmit and receive sections are operated asynchronously, and the serial port interfaces directly with the SMJ32020, SMJ320C25, and the SMJ320C30. 3. The transmit and receive sections are operated synchronously, and the serial port interfaces directly with the DSP in two 8-bit bytes. 4. The transmit and receive sections are operated synchronously, and the serial port interfaces directly with the SMJ32020, SMJ320C25, SMJ302C30, or two SN54299 serial-to-parallel shift registers, which can then interface in parallel to the SMJ320C10, SMJ320C15, SMJ320E15 to any other digital signal processor, or to external FIFO circuitry. operation with internal voltage reference The internal reference eliminates the need for an external voltage reference and provides overall circuit cost reduction. Thus the internal reference eases the design task and provides complete control over the performance of the integrated circuit. The internal reference is brought out to a pin and is available to the designer. To keep the amount of noise on the reference signal to a minimum, an external capacitor can be connected between REF and ANLG GND. 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