SN74LVC137A 3-LINE TO 8-LINE DECODER/DEMULTIPLEXER WITH ADDRESS LATCHES www.ti.com SCAS340E – MARCH 1994 – REVISED FEBRUARY 2005 FEATURES • • • • • D, DB, OR PW PACKAGE (TOP VIEW) EPIC™ (Enhanced-Performance Implanted CMOS) Submicron Process Typical VOLP (Output Ground Bounce) < 0.8 V at VCC = 3.3 V, TA = 25°C Typical VOHV (Output VOH Undershoot) > 2 V at VCC = 3.3 V, TA = 25°C Inputs Accept Voltages to 5.5 V Package Options Include Plastic Small-Outline (D), Shrink Small-Outline (DB), and Thin Shrink Small-Outline (PW) Packages A B C G2A G2B G1 Y7 GND 1 16 2 15 3 14 4 13 5 12 6 11 7 10 8 9 VCC Y0 Y1 Y2 Y3 Y4 Y5 Y6 DESCRIPTION The SN74LVC137A is designed for high-performance memory-decoding or data-routing applications requiring very short propagation delay times. In high-performance memory systems, this decoder can be used to minimize the effects of system decoding. When employed with high-speed memories utilizing a fast enable circuit, the delay times of this decoder and the enable time of the memory usually are less than the typical access time of the memory. This means that the effective system delay introduced by the decoder is negligible. When the latch-enable (G2A) input is low, the SN74LVC137A acts as a decoder/demultiplexer. When G2A transitions from low to high, the address present at the inputs (A, B, and C) is stored in the latches. Further address changes are ignored, provided G2A remains high. The output-enable (G1 and G2B) inputs control the outputs independently of the select or latch-enable inputs. All of the outputs are forced high if G1 is low or G2B is high. Inputs can be driven from either 3.3-V or 5-V devices. This feature allows the use of these devices as translators in a mixed 3.3-V/5-V system environment. The SN74LVC137A is characterized for operation from –40°C to 85°C. FUNCTION TABLE INPUTS LATCH ENABLE OUTPUT ENABLE OUTPUTS SELECT G2A G1 G2B C B A Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7 X X H X X X H H H H H H H H X L X X X X H H H H H H H H L H L L L L L H H H H H H H L H L L L H H L H H H H H H L H L L H L H H L H H H H H L H L L H H H H H L H H H H L H L H L L H H H H L H H H L H L H L H H H H H H L H H L H L H H L H H H H H H L H L H L H H H H H H H H H H L H H L X X X Outputs corresponding to stored address = L; all other outputs = H Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. EPIC is a trademark of Texas Instruments. PRODUCT PREVIEW information concerns products in the formative or design phase of development. Characteristic data and other specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice. Copyright © 1994–2005, Texas Instruments Incorporated PRODUCT PREVIEW This 3-line to 8-line decoder/demultiplexer, with latches on three address inputs, is designed for 1.65-V to 3.6-V VCC operation. SN74LVC137A 3-LINE TO 8-LINE DECODER/DEMULTIPLEXER WITH ADDRESS LATCHES www.ti.com SCAS340E – MARCH 1994 – REVISED FEBRUARY 2005 LOGIC SYMBOLS (ALTERNATIVES)(1) A B C G1 BIN/OCT 1 0 1 2 2 3 1 4 2 3 & 6 EN 4 G2A 4 5 6 5 7 G2B 15 14 13 12 11 10 9 7 Y0 Y1 Y2 A B C 1 3 G1 Y5 G2A 6 4 0 G 7 2 14 1 13 2 & 12 3 11 4 10 5 Y6 Y7 15 0 2 Y3 Y4 DMUX 0 9 6 5 G2B 7 7 Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7 (1) These symbols are in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12. LOGIC DIAGRAM (POSITIVE LOGIC) A 1 15 PRODUCT PREVIEW 14 13 Select Inputs B 2 12 11 C 9 G2A 4 7 G2B Output Enables 2 G1 Y1 Y2 Y3 Data Outputs Y4 3 10 Latch Enable Y0 5 6 Y5 Y6 Y7 SN74LVC137A 3-LINE TO 8-LINE DECODER/DEMULTIPLEXER WITH ADDRESS LATCHES www.ti.com SCAS340E – MARCH 1994 – REVISED FEBRUARY 2005 Absolute Maximum Ratings (1) over operating free-air temperature range (unless otherwise noted) MIN MAX VCC Supply voltage range –0.5 6.5 V VI Input voltage range (2) –0.5 6.5 V –0.5 VCC + 0.5 range (2) (3) UNIT VO Output voltage IIK Input clamp current VI < 0 –50 mA IOK Output clamp current VO < 0 –50 mA IO Continuous output current ±50 mA ±100 mA Continuous current through VCC or GND Tstg (1) (2) (3) (4) Package thermal impedance (4) 113 DB package 131 PW package 149 Storage temperature range –65 °C/W °C 150 Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed. The value of VCC is provided in the recommended operating conditions table. The package thermal impedance is calculated in accordance with JESD 51. PRODUCT PREVIEW θJA D package V Recommended Operating Conditions (1) VCC Supply voltage VIH High-level input voltage Operating Data retention only VCC = 1.65 V to 1.95 V MIN MAX 1.65 3.6 1.5 UNIT V 0.65 × VCC VCC = 2.3 V to 2.7 V 1.7 VCC = 2.7 V to 3.6 V 2 V 0.35 × VCC VCC = 1.65 V to 1.95 V VIL Low-level input voltage VCC = 2.3 V to 2.7 V 0.7 VI Input voltage 0 5.5 V VO Output voltage 0 VCC V VCC = 2.7 V to 3.6 V 0.8 VCC = 1.65 V IOH High-level output current –4 VCC = 2.3 V –8 VCC = 2.7 V –12 VCC = 3 V –24 VCC = 1.65 V IOL Low-level output current TA (1) Operating free-air temperature mA 4 VCC = 2.3 V 8 VCC = 2.7 V 12 VCC = 3 V ∆t/∆v Input transition rise or fall rate V mA 24 0 10 ns/V –40 85 °C All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004. 3 SN74LVC137A 3-LINE TO 8-LINE DECODER/DEMULTIPLEXER WITH ADDRESS LATCHES www.ti.com SCAS340E – MARCH 1994 – REVISED FEBRUARY 2005 Electrical Characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS IOH = –100 µA VOH 1.65 V to 3.6 V 1.65 V 1.2 IOH = –8 mA 2.3 V 1.7 2.7 V 2.2 3V 2.4 IOH = –24 mA 3V 2.2 IOL = 100 µA 1.65 V to 3.6 V 0.2 IOL = 4 mA 1.65 V 0.45 IOL = 8 mA 2.3 V 0.7 IOL = 12 mA 2.7 V 0.4 3V 0.55 IOL = 24 mA II VI = 5.5 V or GND ICC VI = VCC or GND, ∆ICC PRODUCT PREVIEW (1) V V 3.6 V ±5 µA 3.6 V 10 µA 2.7 V to 3.6 V 500 µA IO = 0 One input at VCC – 0.6 V, Other inputs at VCC or GND UNIT VCC – 0.2 IOH = –4 mA IOH = –12 mA VOL MIN TYP (1) MAX VCC Ci VI = VCC or GND 3.3 V pF Co VO = VCC or GND 3.3 V pF All typical values are at VCC = 3.3 V, TA = 25°C. Switching Characteristics over recommended operating free-air temperature range (unless otherwise noted) (see Figure 1 through Figure 3) PARAMETER FROM (INPUT) TO (OUTPUT) VCC = 1.8 V ± 0.15 V MIN MAX VCC = 2.5 V ± 0.2 V MIN MAX VCC = 2.7 V MIN MAX VCC = 3.3 V ± 0.3 V MIN UNIT MAX A or B or C tpd G2A or G2B Y ns G1 tsk(o) (1) (1) ns Skew between any two outputs of the same package switching in the same direction Operating Characteristics TA = 25°C PARAMETER Cpd 4 Power dissipation capacitance TEST CONDITIONS f = 10 MHz VCC = 1.8 V ± 0.15 V VCC = 2.5 V ± 0.2 V VCC = 3.3 V ± 0.3 V TYP TYP TYP UNIT pF SN74LVC137A 3-LINE TO 8-LINE DECODER/DEMULTIPLEXER WITH ADDRESS LATCHES www.ti.com SCAS340E – MARCH 1994 – REVISED FEBRUARY 2005 PARAMETER MEASUREMENT INFORMATION VCC = 1.8 V ± 0.15 V 2 × VCC S1 1k Ω From Output Under Test Open TEST tpd tPLZ/tPZL tPHZ/tPZH GND CL = 30 pF (see Note A) 1k Ω S1 Open 2 × VCC Open LOAD CIRCUIT tw VCC VCC/2 VCC/2 VCC/2 0V VOLTAGE WAVEFORMS SETUP AND HOLD TIMES VCC/2 VCC/2 0V tPLH Output Control (low-level enabling) VCC/2 VOL VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES tPLZ VCC VCC/2 tPZH VOH VCC/2 0V Output Waveform 1 S1 at 2 × VCC (see Note B) tPHL VCC/2 VCC VCC/2 tPZL VCC Input VOLTAGE WAVEFORMS PULSE DURATION th VCC Data Input VCC/2 0V 0V tsu Output VCC VCC/2 Input PRODUCT PREVIEW Timing Input Output Waveform 2 S1 at Open (see Note B) VOL + 0.15 V VOL tPHZ VCC/2 VOH VOH − 0.15 V 0V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2 ns, tf ≤ 2 ns. D. The outputs are measured one at a time, with one transition per measurement. E. tPLZ and tPHZ are the same as tdis. F. tPZL and tPZH are the same as ten. G. tPLH and tPHL are the same as tpd. Figure 1. Load Circuit and Voltage Waveforms 5 SN74LVC137A 3-LINE TO 8-LINE DECODER/DEMULTIPLEXER WITH ADDRESS LATCHES www.ti.com SCAS340E – MARCH 1994 – REVISED FEBRUARY 2005 PARAMETER MEASUREMENT INFORMATION VCC = 2.5 V ± 0.2 V 2 × VCC S1 500 Ω From Output Under Test Open TEST tpd tPLZ/tPZL tPHZ/tPZH GND CL = 30 pF (see Note A) 500 Ω S1 Open 2 × VCC GND LOAD CIRCUIT tw VCC Timing Input VCC/2 VCC/2 VCC/2 PRODUCT PREVIEW 0V VOLTAGE WAVEFORMS SETUP AND HOLD TIMES VCC/2 VCC/2 0V tPLH Output Control (low-level enabling) VCC/2 VOL VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES tPLZ VCC VCC/2 tPZH VOH VCC/2 0V Output Waveform 1 S1 at 2 × VCC (see Note B) tPHL VCC/2 VCC VCC/2 tPZL VCC Input VOLTAGE WAVEFORMS PULSE DURATION th VCC Data Input VCC/2 0V 0V tsu Output VCC VCC/2 Input Output Waveform 2 S1 at GND (see Note B) VOL + 0.15 V VOL tPHZ VCC/2 VOH VOH − 0.15 V 0V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2 ns, tf ≤ 2 ns. D. The outputs are measured one at a time, with one transition per measurement. E. tPLZ and tPHZ are the same as tdis. F. tPZL and tPZH are the same as ten. G. tPLH and tPHL are the same as tpd. Figure 2. Load Circuit and Voltage Waveforms 6 SN74LVC137A 3-LINE TO 8-LINE DECODER/DEMULTIPLEXER WITH ADDRESS LATCHES www.ti.com SCAS340E – MARCH 1994 – REVISED FEBRUARY 2005 PARAMETER MEASUREMENT INFORMATION VCC = 2.7 V AND 3.3 V ± 0.3 V 6V S1 500 Ω From Output Under Test Open GND CL = 50 pF (see Note A) 500 Ω TEST S1 tpd tPLZ/tPZL tPHZ/tPZH Open 6V GND tw LOAD CIRCUIT 2.7 V 2.7 V Timing Input 0V 0V VOLTAGE WAVEFORMS PULSE DURATION th 1.5 V 1.5 V 0V VOLTAGE WAVEFORMS SETUP AND HOLD TIMES 1.5 V 1.5 V 0V tPLH VOH 1.5 V VOL VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES 1.5 V 1.5 V 0V tPLZ 3V Output Waveform 1 S1 at 6 V (see Note B) 1.5 V tPZH tPHL 1.5 V 2.7 V Output Control (low-level enabling) tPZL 2.7 V PRODUCT PREVIEW 2.7 V Data Input Output 1.5 V 1.5 V tsu Input 1.5 V Input Output Waveform 2 S1 at GND (see Note B) VOL + 0.3 V VOL tPHZ 1.5 V VOH − 0.3 V VOH 0V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2.5 ns, tf ≤ 2.5 ns. D. The outputs are measured one at a time, with one transition per measurement. E. tPLZ and tPHZ are the same as tdis. F. tPZL and tPZH are the same as ten. G. tPLH and tPHL are the same as tpd. Figure 3. Load Circuit and Voltage Waveforms 7 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. 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