TPS84250 www.ti.com SLVSAR6 – AUGUST 2012 7-V to 50-V Input, 2.5-A Step-Down, Integrated Power Solution Check for Samples: TPS84250 FEATURES 1 • • • • • • • • • • • • • • • • • • Complete Integrated Power Solution Allows Small Footprint, Low-Profile Design Wide Input Voltage Range from 7 V to 50 V Output Adjustable from 2.5 V to 15 V 65-V Surge Capability Efficiencies Up To 96% Adjustable Switching Frequency (300 kHz to 1 MHz) Synchronizes to an External Clock Adjustable Slow-Start Output Voltage Sequencing and Tracking Power Good Output Programmable Undervoltage Lockout (UVLO) Output Overcurrent Protection Over Temperature Protection Pre-bias Output Start-up Operating Temperature Range: –40°C to 85°C Enhanced Thermal Performance: 14°C/W Meets EN55022 Class B Emissions For Design Help visit http://www.ti.com/TPS84250 DESCRIPTION The TPS84250 is an easy-to-use integrated power solution that combines a 2.5-A DC/DC converter with an inductor and passives into a low profile, QFN package. This total power solution allows as few as five external components and eliminates the loop compensation and magnetics part selection process. The small 9 mm × 11 mm × 2.8 mm, QFN package is easy to solder onto a printed circuit board and allows a compact point-of-load design with greater than 90% efficiency and excellent power dissipation capability. The TPS84250 offers the flexibility and the featureset of a discrete point-of-load design and is ideal for powering a wide range of ICs and systems. Advanced packaging technology affords a robust and reliable power solution compatible with standard QFN mounting and testing techniques. SIMPLIFIED APPLICATION TPS84250 VIN VOUT VIN VOUT CIN RSET INH/UVLO COUT VADJ APPLICATIONS • • • • PWRGD Industrial and Motor Controls Automated Test Equipment Medical and Imaging Equipment High Density Power Systems RT/CLK SS/TR STSEL 100 AGND PGND Efficiency (%) 95 90 85 80 75 70 VIN = 24 V, VOUT = 15 V, fSW = 1 MHz VIN = 24 V, VOUT = 12 V, fSW = 800 kHz 0 0.5 1 1.5 Output Current (A) 2 2.5 G000 1 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2012, Texas Instruments Incorporated TPS84250 SLVSAR6 – AUGUST 2012 www.ti.com This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. ABSOLUTE MAXIMUM RATINGS (1) over operating temperature range (unless otherwise noted) Input Voltage Output Voltage MIN MAX UNIT VIN –0.3 65 V INH/UVLO –0.3 5 V VADJ –0.3 3 V PWRGD –0.3 6 V SS/TR –0.3 3 V STSEL –0.3 3 V RT/CLK –0.3 3.6 V PH –0.6 65 V –2 65 V –0.6 VIN V ±200 mV RT/CLK 100 µA INH/UVLO 100 µA SS/TRK 200 µA PWRGD 10 mA 105 (2) °C 150 °C 1500 G PH 10ns Transient VOUT VDIFF (GND to exposed thermal pad) Source Current Sink Current Operating Junction Temperature –40 Storage Temperature –65 Mechanical Shock Mil-STD-883D, Method 2002.3, 1 msec, 1/2 sine, mounted Mechanical Vibration (1) Mil-STD-883D, Method 2007.2, 20-2000Hz 20 Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. See the temperature derating curves in the Typical Characteristics section for thermal information. (2) RECOMMENDED OPERATING CONDITIONS over operating free-air temperature range (unless otherwise noted) MIN MAX 7 50 V Output Voltage 2.5 15 V fSW Switching Frequency 400 1000 kHz TA Operating Ambient Temperature -40 85 °C VIN Input Voltage VOUT UNIT PACKAGE SPECIFICATIONS TPS84250 Weight Flammability MTBF Calculated reliability UNIT 0.9 grams Meets UL 94 V-O Per Bellcore TR-332, 50% stress, TA = 40°C, ground benign 31.7 MHrs ORDERING INFORMATION For the most current package and ordering information, see the Package Option Addendum at the end of this datasheet, or see the TI website at www.ti.com. 2 Copyright © 2012, Texas Instruments Incorporated TPS84250 www.ti.com SLVSAR6 – AUGUST 2012 ELECTRICAL CHARACTERISTICS -40°C ≤ TA ≤ +85°C, VIN = 24 V, VOUT = 5.0 V, IOUT = 2.5 A, RT = Open CIN = 2 x 2.2 µF ceramic, COUT = 2 x 47 µF ceramic (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP IOUT Output current Over input voltage and output voltage range VIN Input voltage range Over output current range UVLO VIN Undervoltage lockout No hysteresis, Rising and Falling VOUT(adj) Output voltage adjust range Over output current range Set-point voltage tolerance TA = 25°C; IOUT = 100 mA Temperature variation -40°C ≤ TA ≤ +85°C ±0.5% Line regulation Over input voltage range ±0.1% Load regulation Over output current range ±0.4% Total output voltage variation Includes set-point, line, load, and temperature variation VOUT VIN = 24 V IOUT = 1.5 A η Efficiency Output voltage ripple ILIM VIN = 48 V IOUT = 1.5 A VINH Inhibit threshold voltage IINH INH Input current II(stby) Input standby current Power Good VOUT = 12 V, fSW = 800 kHz 93 % VOUT = 5.0 V, fSW = 500 kHz 84 % VOUT = 3.3 V, fSW = 400 kHz 79 % VOUT = 12 V, fSW = 800 kHz 87 % VOUT = 5.0 V, fSW = 500 kHz 79 % VOUT = 3.3 V, fSW = 400 kHz 74 % 1% I(PWRGD) = 3.5 mA RT/CLK pin OPEN fCLK Synchronization frequency VCLK-H CLK High-Level Threshold VCLK-L CLK Low-Level Threshold DCLK CLK Duty cycle CIN External input capacitance COUT External output capacitance V (4) ±1.0% ±3.0% (4) (3) VOUT 5.1 A Recovery time 400 µs VOUT over/undershoot 90 1.15 1.25 -3.8 Switching frequency (7) ±2.0% INH pin to AGND VOUT falling Thermal Shutdown 15 VINH > 1.36 V PWRGD Thresholds V 2.5 (3) -0.9 PWRGD Low Voltage (5) (6) V VINH < 1.15 V fSW (2) (3) (4) 50 (2) 2.5 No hysteresis VOUT rising (1) A 7.0 (1) 20 MHz bandwith, 0.25 A ≤ IOUT ≤ 2.5 A, VOUT ≥ 3.3V 1.0 A/µs load step from 50 to 100% IOUT(max) UNIT 2.5 Current limit threshold Transient response MAX 0 1.3 Good 94% Fault 109% Fault 91% Good 106% mV 1.36 (5) μA 4 µA 500 kHz 1000 kHz 0.2 300 400 300 1.9 CLK Control 0.5 0.7 25% 50% Thermal shutdown Thermal shutdown hysteresis Ceramic 4.4 (6) Non-ceramic V 2.2 (7) V V 75% 180 °C 15 °C 10 µF 22 100 V μA 430 µF For output voltages ≤ 12 V, the minimum input voltage is 7 V or (VOUT+ 3 V), whichever is greater. For output voltages > 12 V, the minimum input voltage is (1.33 x VOUT). See Figure 27 for more details. The maximum input voltage is 50 V or (15 x VOUT), whichever is less. Output voltages < 3.3 V are subject to reduced VIN(max) specifications and higher ripple magnitudes. The stated limit of the set-point voltage tolerance includes the tolerance of both the internal voltage reference and the internal adjustment resistor. The overall output voltage tolerance is affected by the tolerance of the external RSET resistor. Value when no voltage divider is present at the INH/UVLO pin. A minimum of 4.4µF of ceramic external capacitance is required across the input (VIN and PGND connected) for proper operation. Locate the capacitor close to the device. See Table 1 for more details. The required capacitance must include at least 2 x 47µF ceramic capacitors (or 4 x 22µF). Locate the capacitance close to the device. Adding additional capacitance close to the load improves the response of the regulator to load transients. See Table 1 for more details. Copyright © 2012, Texas Instruments Incorporated 3 TPS84250 SLVSAR6 – AUGUST 2012 www.ti.com THERMAL INFORMATION TPS84250 THERMAL METRIC (1) RKG UNIT 41 PINS Junction-to-ambient thermal resistance (2) θJA 14 (3) ψJT Junction-to-top characterization parameter ψJB Junction-to-board characterization parameter (4) (1) (2) (3) (4) 3.3 °C/W 6.8 For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953. The junction-to-ambient thermal resistance, θJA, applies to devices soldered directly to a 100 mm x 100 mm double-sided, 4-layer PCB with 1 oz. copper and natural convection cooling. Additional airflow reduces θJA. The junction-to-top characterization parameter, ψJT, estimates the junction temperature, TJ, of a device in a real system, using a procedure described in JESD51-2A (sections 6 and 7). TJ = ψJT * Pdis + TT; where Pdis is the power dissipated in the device and TT is the temperature of the top of the device. The junction-to-board characterization parameter, ψJB, estimates the junction temperature, TJ, of a device in a real system, using a procedure described in JESD51-2A (sections 6 and 7). TJ = ψJB * Pdis + TB; where Pdis is the power dissipated in the device and TB is the temperature of the board 1mm from the device. DEVICE INFORMATION FUNCTIONAL BLOCK DIAGRAM TPS84250 Thermal Shutdown PWRGD PWRGD Logic Shutdown Logic VADJ OCP INH/UVLO VIN UVLO VIN PH + + SS/TR VREF STSEL RT/CLK Comp Power Stage and Control Logic VOUT OSC w/PLL PGND AGND 4 Copyright © 2012, Texas Instruments Incorporated TPS84250 www.ti.com SLVSAR6 – AUGUST 2012 PIN DESCRIPTIONS TERMINAL NAME DESCRIPTION NO. 1 4 5 AGND 30 32 33 These pins are connected to the internal analog ground (AGND) of the device. This node should be treated as the zero volt ground reference for the analog control circuitry. Pad 37 should be connected to PCB ground planes using multiple vias for good thermal performance. Not all pins are connected together internally. All pins must be connected together externally with a copper plane or pour directly under the module. Connect AGND to PGND at a single point (GND_PT; pins 8 & 9). See Layout Recommendations. 34 37 2 DNC 3 Do Not Connect. Do not connect these pins to AGND, to another DNC pin, or to any other voltage. These pins are connected to internal circuitry. Each pin must be soldered to an isolated pad. 25 6 7 21 PH 22 23 Phase switch node. Do not place any external component on these pins or tie them to a pin of another function. 24 38 41 GND_PT 8 9 Ground Point. Connect AGND to PGND at these pins as shown in the Layout Considerations. These pins are not connected to internal circuitry, but are connected to each other. 10 11 12 VOUT 13 14 Output voltage. These pins are connected to the internal output inductor. Connect these pins to the output load and connect external bypass capacitors between these pins and PGND. Connect a resistor from these pins to VADJ to set the output voltage. 15 39 16 17 PGND 18 19 This is the return current path for the power stage of the device. Connect these pins to the load and to the bypass capacitors associated with VIN and VOUT. Pad 40 should be connected to PCB ground planes using multiple vias for good thermal performance. 20 40 VIN 26 Input voltage. This pin supplies all power to the converter. Connect this pin to the input supply and connect bypass capacitors between this pin and PGND. INH/UVLO 27 Inhibit and UVLO adjust pin. Use an open drain or open collector logic device to ground this pin to control the INH function. A resistor divider between this pin, AGND, and VIN sets the UVLO voltage. SS/TR 28 Slow-start and tracking pin. Connecting an external capacitor to this pin adjusts the output voltage rise time. A voltage applied to this pin allows for tracking and sequencing control. STSEL 29 Slow-start or track feature select. Connect this pin to AGND to enable the internal SS capacitor. Leave this pin open to enable the TR feature. RT/CLK 31 This pin is connected to an internal frequency setting resistor which sets the default switching frequency. An external resistor can be connected from this pin to AGND to increase the frequency. This pin can also be used to synchronize to an external clock. PWRGD 35 Power Good flag pin. This open drain output asserts low if the output voltage is more than approximately ±6% out of regulation. A pull-up resistor is required. VADJ 36 Connecting a resistor between this pin and VOUT sets the output voltage. Copyright © 2012, Texas Instruments Incorporated 5 TPS84250 SLVSAR6 – AUGUST 2012 www.ti.com DNC AGND AGND AGND RT/CLK AGND 1 PWRGD AGND VADJ RKG PACKAGE (TOP VIEW) 36 35 34 33 32 31 30 2 29 STSEL 28 SS/TR 27 INH/UVLO 26 VIN 25 DNC 24 PH 23 PH 22 PH 21 PH 20 PGND 37 DNC 3 AGND 4 AGND 5 AGND PH PH PH 6 PH 7 38 41 GND_PT 8 VOUT GND_PT 9 PGND VOUT 39 10 6 12 13 14 15 16 17 18 VOUT VOUT PGND PGND PGND 11 VOUT VOUT VOUT 40 19 PGND Copyright © 2012, Texas Instruments Incorporated TPS84250 www.ti.com SLVSAR6 – AUGUST 2012 TYPICAL CHARACTERISTICS (VIN = 12 V) 100 (1) (2) 40 VOUT = 5.0 V, fSW = 500 kHz VOUT = 3.3 V, fSW = 400 kHz VOUT = 2.5 V, fSW = 400 kHz Output Voltage Ripple (mV) 95 90 Efficiency (%) 85 80 75 70 65 VOUT = 5.0 V, fSW = 500 kHz VOUT = 3.3 V, fSW = 400 kHz VOUT = 2.5 V, fSW = 400 kHz 60 55 50 0 0.5 1 1.5 Output Current (A) 2 30 20 10 0 2.5 0 Figure 1. Efficiency vs. Output Current 1 1.5 Output Current (A) 2 2.5 G000 Figure 2. Voltage Ripple vs. Output Current 2.5 90 VOUT = 5.0 V, fSW = 500 kHz VOUT = 3.3 V, fSW = 400 kHz VOUT = 2.5 V, fSW = 400 kHz 80 Ambient Temperature (°C) 2 Power Dissipation (W) 0.5 G000 1.5 1 0.5 70 60 50 40 30 All Output Voltages 0 0.5 1 1.5 Output Current (A) 2 20 2.5 1 1.5 Output Current (A) 2 2.5 G000 120 40 120 30 90 30 90 20 60 20 60 10 30 10 30 0 0 0 0 −30 −10 Gain (dB) 40 −60 −20 Gain Phase −30 −40 1000 10000 Frequency (Hz) 100000 −30 −10 −60 −20 −90 −30 −120 300000 Figure 5. VOUT= 5 V, IOUT= 2 A, COUT1= 44 µF ceramic, COUT2= 56 µF electrolytic, fSW= 500 kHz (2) 0.5 Figure 4. Safe Operating Area Phase (°) Gain (dB) Figure 3. Power Dissipation vs. Output Current (1) 0 G000 Natural Convection −40 1000 G000 Phase (°) 0 Gain Phase −90 10000 Frequency (Hz) 100000 −120 300000 G000 Figure 6. VOUT= 3.3 V, IOUT= 2 A, COUT1= 44 µF ceramic, COUT2= 56 µF electrolytic, fSW= 400 kHz The electrical characteristic data has been developed from actual products tested at 25°C. This data is considered typical for the converter. Applies to Figure 1, Figure 2, and Figure 3. The temperature derating curves represent the conditions at which internal components are at or below the manufacturer's maximum operating temperatures. Derating limits apply to devices soldered directly to a 100 mm × 100 mm double-sided PCB with 1 oz. copper. Applies to Figure 4. Copyright © 2012, Texas Instruments Incorporated 7 TPS84250 SLVSAR6 – AUGUST 2012 www.ti.com TYPICAL CHARACTERISTICS (VIN = 24 V) (1) (2) (3) 60 100 VOUT = 15 V, fSW = 1 MHz VOUT = 12 V, fSW = 800 kHz VOUT = 5.0 V, fSW = 500 kHz VOUT = 3.3 V, fSW = 400 kHz VOUT = 2.5 V, fSW = 400 kHz 95 80 75 70 VOUT = 15 V, fSW = 1 MHz VOUT = 12 V, fSW = 800 kHz VOUT = 5.0 V, fSW = 500 kHz VOUT = 3.3 V, fSW = 400 kHz VOUT = 2.5 V, fSW = 400 kHz 60 55 50 0 0.5 1 1.5 Output Current (A) 2 40 30 20 10 0 2.5 0 Figure 7. Efficiency vs. Output Current 1 1.5 Output Current (A) Ambient Temperature (°C) 2 1.5 1 70 60 50 40 30 All Output Voltages 0 0.5 1 1.5 Output Current (A) 2 20 2.5 2 2.5 G000 Figure 10. Safe Operating Area 40 120 90 30 90 20 60 20 60 10 30 10 30 0 0 0 0 −30 −10 −40 1000 Gain (dB) 120 Phase (°) Gain (dB) 1 1.5 Output Current (A) 30 −30 −60 Gain Phase 10000 Frequency (Hz) 100000 −30 −10 −60 −20 −90 −30 −120 300000 Figure 11. VOUT= 5 V, IOUT= 2 A, COUT1= 44 µF ceramic, COUT2= 56 µF electrolytic, fSW= 500 kHz 8 0.5 Natural Convection 40 −20 (3) 0 G000 Figure 9. Power Dissipation vs. Output Current (2) G000 80 0.5 (1) 2.5 90 VOUT = 15 V, fSW = 1 MHz VOUT = 12 V, fSW = 800 kHz VOUT = 5.0 V, fSW = 500 kHz VOUT = 3.3 V, fSW = 400 kHz VOUT = 2.5 V, fSW = 400 kHz 2.5 0 2 Figure 8. Voltage Ripple vs. Output Current 3 Power Dissipation (W) 0.5 G000 −40 1000 G000 Phase (°) Efficiency (%) 85 65 50 Output Voltage Ripple (mV) 90 Gain Phase −90 10000 Frequency (Hz) 100000 −120 300000 G000 Figure 12. VOUT= 12 V, IOUT= 2 A, COUT1= 44 µF ceramic, COUT2= 56 µF electrolytic, fSW= 800 kHz The electrical characteristic data has been developed from actual products tested at 25°C. This data is considered typical for the converter. Applies to Figure 7, Figure 8, and Figure 9. At light load the output voltage ripple may increase due to pulse skipping. See Light-Load Behavior for more information. Applies to Figure 8. The temperature derating curves represent the conditions at which internal components are at or below the manufacturer's maximum operating temperatures. Derating limits apply to devices soldered directly to a 100 mm × 100 mm double-sided PCB with 1 oz. copper. Applies to Figure 10. Copyright © 2012, Texas Instruments Incorporated TPS84250 www.ti.com SLVSAR6 – AUGUST 2012 TYPICAL CHARACTERISTICS (VIN = 36 V) (1) (2) (3) 60 100 VOUT = 15 V, fSW = 1 MHz VOUT = 12 V, fSW = 800 kHz VOUT = 5.0 V, fSW = 500 kHz VOUT = 3.3 V, fSW = 400 kHz VOUT = 2.5 V, fSW = 400 kHz 95 80 75 70 VOUT = 15 V, fSW = 1 MHz VOUT = 12 V, fSW = 800 kHz VOUT = 5.0 V, fSW = 500 kHz VOUT = 3.3 V, fSW = 400 kHz VOUT = 2.5 V, fSW = 400 kHz 60 55 50 0 0.5 1 1.5 Output Current (A) 2 40 30 20 10 0 2.5 Figure 13. Efficiency vs. Output Current 0.5 1 1.5 Output Current (A) 2 G000 90 VOUT = 15 V, fSW = 1 MHz VOUT = 12 V, fSW = 800 kHz VOUT = 5.0 V, fSW = 500 kHz VOUT = 3.3 V, fSW = 400 kHz VOUT = 2.5 V, fSW = 400 kHz 2.5 80 Ambient Temperature (°C) 3 2 1.5 1 70 60 50 40 0.5 30 0 20 VO = 5 V VO = 12 V VO = 15 V Natural Convection 0 0.5 1 1.5 Output Current (A) 2 2.5 2 2.5 G000 Figure 16. Safe Operating Area 40 120 90 30 90 20 60 20 60 10 30 10 30 0 0 0 0 −30 −10 −40 1000 Gain (dB) 120 Phase (°) Gain (dB) 1 1.5 Output Current (A) 30 −30 −60 Gain Phase 10000 Frequency (Hz) 100000 −30 −10 −60 −20 −90 −30 −120 300000 Figure 17. VOUT= 5 V, IOUT= 2 A, COUT1= 44 µF ceramic, COUT2= 56 µF electrolytic, fSW= 500 kHz (3) 0.5 40 −20 (2) 0 G000 Figure 15. Power Dissipation vs. Output Current (1) 2.5 Figure 14. Voltage Ripple vs. Output Current 4 3.5 Power Dissipation (W) 0 G000 −40 1000 G000 Phase (°) Efficiency (%) 85 65 50 Output Voltage Ripple (mV) 90 Gain Phase −90 10000 Frequency (Hz) 100000 −120 300000 G000 Figure 18. VOUT= 12 V, IOUT= 2 A, COUT1= 44 µF ceramic, COUT2= 56 µF electrolytic, fSW= 800 kHz The electrical characteristic data has been developed from actual products tested at 25°C. This data is considered typical for the converter. Applies to Figure 13, Figure 14, and Figure 15. At light load the output voltage ripple may increase due to pulse skipping. See Light-Load Behavior for more information. Applies to Figure 14. The temperature derating curves represent the conditions at which internal components are at or below the manufacturer's maximum operating temperatures. Derating limits apply to devices soldered directly to a 100 mm × 100 mm double-sided PCB with 1 oz. copper. Applies to Figure 16. Copyright © 2012, Texas Instruments Incorporated 9 TPS84250 SLVSAR6 – AUGUST 2012 www.ti.com TYPICAL CHARACTERISTICS (VIN = 48 V) 70 100 95 80 75 70 65 VOUT = 15 V, fSW = 1 MHz VOUT = 12 V, fSW = 800 kHz VOUT = 5.0 V, fSW = 500 kHz VOUT = 3.3 V, fSW = 400 kHz 60 55 0 0.5 1 1.5 Output Current (A) 2 50 40 30 20 10 0 2.5 Figure 19. Efficiency vs. Output Current 0.5 1 1.5 Output Current (A) 2 G000 90 VOUT = 15 V, fSW = 1 MHz VOUT = 12 V, fSW = 800 kHz VOUT = 5.0 V, fSW = 500 kHz VOUT = 3.3 V, fSW = 400 kHz 80 Ambient Temperature (°C) 5 4 3 2 1 70 60 50 40 VO = 5 V VO = 12 V VO = 15 V 30 Natural Convection 0 0 0.5 1 1.5 Output Current (A) 2 20 2.5 2.5 G000 Figure 22. Safe Operating Area 120 30 90 20 60 20 60 10 30 10 30 0 0 0 0 −30 −10 Gain (dB) 40 90 Phase (°) Gain (dB) 2 120 −40 1000 −60 Gain Phase 10000 Frequency (Hz) 100000 −30 −10 −60 −20 −90 −30 −120 300000 Figure 23. VOUT= 5 V, IOUT= 2 A, COUT1= 44 µF ceramic, COUT2= 56 µF electrolytic, fSW= 500 kHz 10 1 1.5 Output Current (A) 30 −30 (3) 0.5 40 −20 (2) 0 G000 Figure 21. Power Dissipation vs. Output Current (1) 2.5 Figure 20. Voltage Ripple vs. Output Current 6 Power Dissipation (W) 0 G000 −40 1000 G000 Phase (°) Efficiency (%) 85 VOUT = 15 V, fSW = 1 MHz VOUT = 12 V, fSW = 800 kHz VOUT = 5.0 V, fSW = 500 kHz VOUT = 3.3 V, fSW = 400 kHz 60 Output Voltage Ripple (mV) 90 50 (1) (2) (3) Gain Phase −90 10000 Frequency (Hz) 100000 −120 300000 G000 Figure 24. VOUT= 12 V, IOUT= 2 A, COUT1= 44 µF ceramic, COUT2= 56 µF electrolytic, fSW= 800 kHz The electrical characteristic data has been developed from actual products tested at 25°C. This data is considered typical for the converter. Applies to Figure 19, Figure 20, and Figure 21. At light load the output voltage ripple may increase due to pulse skipping. See Light-Load Behavior for more information. Applies to Figure 20. The temperature derating curves represent the conditions at which internal components are at or below the manufacturer's maximum operating temperatures. Derating limits apply to devices soldered directly to a 100 mm × 100 mm double-sided PCB with 1 oz. copper. Applies to Figure 22. Copyright © 2012, Texas Instruments Incorporated TPS84250 www.ti.com SLVSAR6 – AUGUST 2012 CAPACITOR RECOMMENDATIONS FOR THE TPS84250 POWER SUPPLY Capacitor Technologies Electrolytic, Polymer-Electrolytic Capacitors When using electrolytic capacitors, high-quality, computer-grade electrolytic capacitors are recommended. Polymer-electrolytic type capacitors are recommended for applications where the ambient operating temperature is less than 0°C. The Sanyo OS-CON capacitor series is suggested due to the lower ESR, higher rated surge, power dissipation, ripple current capability, and small package size. Aluminum electrolytic capacitors provide adequate decoupling over the frequency range of 2 kHz to 150 kHz, and are suitable when ambient temperatures are above 0°C. Ceramic Capacitors The performance of aluminum electrolytic capacitors is less effective than ceramic capacitors above 150 kHz. Multilayer ceramic capacitors have a low ESR and a resonant frequency higher than the bandwidth of the regulator. They can be used to reduce the reflected ripple current at the input as well as improve the transient response of the output. Tantalum, Polymer-Tantalum Capacitors Polymer-tantalum type capacitors are recommended for applications where the ambient operating temperature is less than 0°C. The Sanyo POSCAP series and Kemet T530 capacitor series are recommended rather than many other tantalum types due to their lower ESR, higher rated surge, power dissipation, ripple current capability, and small package size. Tantalum capacitors that have no stated ESR or surge current rating are not recommended for power applications. Input Capacitor The TPS84250 requires a minimum input capacitance of 4.4 μF of ceramic type. The voltage rating of input capacitors must be greater than the maximum input voltage. The ripple current rating of the capacitor must be at least 450 mArms. Table 1 includes a preferred list of capacitors by vendor. Output Capacitor The output capacitance of the TPS84250 can be comprised of either all ceramic capacitors, or a combination of ceramic and bulk capacitors. The required output capacitance must include at least 100 µF of ceramic type (or 2 x 47 µF). When adding additional non-ceramic bulk capacitors, low-ESR devices like the ones recommended in Table 1 are required. Additional capacitance above the minimum is determined by actual transient deviation requirements. Table 1 includes a preferred list of capacitors by vendor. Table 1. Recommended Input/Output Capacitors (1) CAPACITOR CHARACTERISTICS VENDOR SERIES PART NUMBER WORKING VOLTAGE (V) CAPACITANCE (µF) ESR (2) (mΩ) Murata X5R GRM31CR61H225KA88L 50 4.7 2 TDK X5R C3216X5R1H475K 50 4.7 2 Murata X5R GRM32ER61E226K 16 22 2 TDK X5R C3225X5R0J476K 6.3 47 2 Murata X5R GRM32ER60J476M 6.3 47 2 Sanyo POSCAP 16TQC68M 16 68 50 Sanyo POSCAP 6TPE100MI 6.3 100 25 Kemet T530 T530D227M006ATE006 6.3 220 6 (1) (2) Capacitor Supplier Verification, RoHS, Lead-free and Material Details Consult capacitor suppliers regarding availability, material composition, RoHS and lead-free status, and manufacturing process requirements for any capacitors identified in this table. Maximum ESR @ 100 kHz, 25°C. Copyright © 2012, Texas Instruments Incorporated 11 TPS84250 SLVSAR6 – AUGUST 2012 www.ti.com APPLICATION INFORMATION TPS84250 OPERATION The TPS84250 can operate over a wide input voltage range of 7V to 50V and produce output voltages from 2.5V to 15V. The performance of the device varies over this wide operating range, and there are some important considerations when operated near the boundary limits. This section offers guidance in selecting the optimum components depending on the application and operating conditions. The user must select three primary parameters when designing with the TPS84250. • Output Voltage • UVLO Threshold • Switching Frequency The adjustment of each of these parameters can be made using just one or two resistors. Figure 25 below shows a typical TPS84250 schematic with the key parameter-setting resistors labeled. TPS84250 VIN VIN PWRGD VOUT CIN2 CIN1 RUVLO1 VOUT INH/UVLO COUT1 COUT2 RSET RUVLO2 VADJ COMP RT/CLK RRT SS/TR STSEL AGND PGND Figure 25. TPS84250 Typical Schematic 12 Copyright © 2012, Texas Instruments Incorporated TPS84250 www.ti.com SLVSAR6 – AUGUST 2012 ADJUSTING THE OUTPUT VOLTAGE The TPS84250 is designed to provide output voltages from 2.5V to 15V. The output voltage is determined by the value of RSET, which must be connected between the VOUT node and the VADJ pin (Pin 36). For output voltages greater than 5.0V, improved operating performance can be obtained by increasing the operating frequency. This adjustment requires the addition of RRT between RT/CLK (Pin 31) and AGND (Pin 30). See the Switching Frequency section for more details. Table 2 gives the standard external RSET resistor for a number of common bus voltages and also includes the recommended RRT resistor for output voltages above 5.0V. Table 2. Standard RSET Resistor Values for Common Output Voltages OUTPUT VOLTAGE VOUT (V) RESISTORS 2.5 3.3 5.0 8.0 12.0 15.0 RSET (kΩ) 21.5 31.6 52.3 90.9 140 178 RRT (kΩ) open open 1100 549 267 178 For other output voltages the value of RSET can be calculated using the following formula, or simply selected from the range of values given in Table 3. æV ö RSET = 10 ´ ç OUT - 1÷ (kW ) è 0.798 ø (1) Table 3. Standard RSET and RRT Resistor Values VOUT (V) RSET (kΩ) RRT(kΩ) fSW(kHz) VOUT (V) RSET (kΩ) RRT(kΩ) fSW(kHz) 2.5 21.5 open 400 9.0 102 365 700 3.0 27.4 open 400 9.5 110 365 700 3.3 31.6 open 400 10.0 115 365 700 3.5 34.0 open 400 10.5 121 267 800 4.0 40.2 open 400 11.0 127 267 800 4.5 46.4 open 400 11.5 133 267 800 5.0 52.3 1100 500 12.0 140 267 800 5.5 48.7 1100 500 12.5 147 215 900 6.0 64.9 1100 500 13.0 154 215 900 6.5 71.5 1100 500 13.5 158 215 900 7.0 78.7 549 600 14.0 165 178 1000 7.5 84.5 549 600 14.5 174 178 1000 8.0 90.9 549 600 15.0 178 178 1000 8.5 97.6 365 700 Input Voltage The TPS84250 operates over the input voltage range of 7 V to 50 V. For reliable start-up and operation at light loads, the minimum input voltage depends on the output voltage. For output voltages ≤ 12V, the minimum input voltage is 7V or (VOUT + 3V), whichever is greater. For output voltages > 12V, the minimum input voltage is (1.33 x VOUT). The maximum input voltage is (15 x VOUT) or 50 V, whichever is less. While the device can safely handle input surge voltages up to 65 V, sustained operation at input voltages above 50 V is not recommended. See the Undervoltage Lockout (UVLO) Threshold section of this datasheet for more information. Copyright © 2012, Texas Instruments Incorporated 13 TPS84250 SLVSAR6 – AUGUST 2012 www.ti.com Undervoltage Lockout (UVLO) Threshold At turn-on, the VON UVLO threshold determines the input voltage level where the device begins power conversion. During the power-down sequence, the VOFF UVLO threshold determines the input voltage where power conversion ceases. The turn-on and turn-off thresholds are set by two resistors, RUVLO1 and RUVLO2 as shown in Figure 26. The VON UVLO threshold must be set to at least (VOUT + 3 V) or 7 V whichever is greater to insure proper startup and reduce current surges on the host input supply as the voltage rises. If possible, it is recommended to set the UVLO threshold to appproximantely 80 to 85% of the minimum expected input voltage. Use Equation 2 and Equation 3 to calculate the values of RUVLO1 and RUVLO2. VON is the voltage threshold during power-up when the input voltage is rising. VOFF is the voltage threshold during power-down when the input voltage is decreasing. VOFF should be selected to be at least 500mV less than VON. Table 4 lists standard resistor values for RUVLO1 and RUVLO2 for adjusting the VON UVLO threshold for several input voltages. RUVLO1 = RUVLO2 (VON - VOFF ) 2.9 ´ 10-3 (kW ) (2) 1.25 = æ (VON - 1.25 ) ö -3 çç ÷÷ + 0.9 ´ 10 R UVLO1 è ø (kW ) (3) VIN VIN RUVLO1 INH/UVLO RUVLO2 AGND Figure 26. Adjustable VIN UVLO Table 4. Standard Resistor Values to set VON UVLO Threshold VON THRESHOLD (V) 6.5 10.0 15.0 20.0 25.0 30.0 35.0 40.0 45.0 RUVLO1 (kΩ) 174 174 174 174 174 174 174 174 174 RUVLO2 (kΩ) 40.2 24.3 15.8 11.5 9.09 7.50 6.34 5.62 4.99 Power Good (PWRGD) The PWRGD pin is an open drain output. Once the output voltage is between 94% and 106% of the set voltage, the PWRGD pin pull-down is released and the pin floats. The recommended pull-up resistor value is between 10 kΩ and 100 kΩ to a voltage source that is 5.5 V or less. The PWRGD pin is in a defined state once VIN is greater than 1.0 V, but with reduced current sinking capability. The PWRGD pin achieves full current sinking capability once the VIN pin is above 4.5V. The PWRGD pin is pulled low when the output voltage is lower than 91% or greater than 109% of the nominal set voltage. Also, the PWRGD pin is pulled low if the input UVLO or thermal shutdown is asserted, the INH pin is pulled low, or the SS/TR pin is below 1.4 V. 14 Copyright © 2012, Texas Instruments Incorporated TPS84250 www.ti.com SLVSAR6 – AUGUST 2012 Switching Frequency Nominal switching frequency of the TPS84250 is set from the factory at 400 kHz. This switching frequency is optimum for output voltages below 5.0 V. For output voltages 5.0V and above, better operating performance can be obtained raising the operating frequency. This is easily done by adding a resistor, RRT in , from the RT/CLK pin (Pin 31) to the AGND pin (Pin 30). Raising the operating frequency reduces output voltage ripple, lowers the load current threshold where pulse skipping begins, and improves transient response. The recommended switching frequency for all output voltages is listed in Table 3. For the maximum recommended output voltage value of 15 V, the switching frequency computes to 1000 kHz or 1 MHz. Operation above 1 MHz is not recommended. Use Table 5 below to select the value of the timing resistor for the given values of switching frequencies. Table 5. Standard Resistor Values to set the Switching Frequency fSW (kHz) 400 500 600 700 800 900 1000 RRT(kΩ) OPEN 1100 549 365 267 215 178 It is also possible to synchronize the switching frequency to an external clock signal. See the Synchronization (CLK) section for further details. While it is possible to set the operating frequency higher than 400 kHz when using the device at output voltages of 5 V or less, minimum duty cycle and pulse skipping issues restrict the maximum recommended input voltage under these conditions. The recommended operating conditions for the TPS84250 can be summarized by Figure 27. The graph shows the maximum input voltage vs. output voltage restriction for several operating frequencies. The lower boundary of the graph shows the minimum input voltage as a function of the output voltage. Figure 27. Optimum Operating Range with Switching Frequency Copyright © 2012, Texas Instruments Incorporated 15 TPS84250 SLVSAR6 – AUGUST 2012 www.ti.com Application Schematics VIN 7-36 V TPS84250 VIN 4.7 F 50 V PWRGD 174kΩ VOUT 3.3V @ 2.5A VOUT INH/UVLO 47 F 6.3 V 31.6kΩ 40.2kΩ 47 F 6.3 V VADJ RT/CLK SS/TR STSEL AGND PGND Figure 28. Typical Schematic VIN = 7 V to 36 V, VOUT = 3.3 V VIN 15-50 V TPS84250 VIN 2.2 F 100 V 2.2 F 100 V PWRGD VOUT 12 V @ 2.5 A VOUT 174kΩ INH/UVLO 47 F 16 V 140kΩ 15.4kΩ 47 F 16 V VADJ RT/CLK SS/TR 22 nF 267kΩ STSEL AGND PGND Figure 29. Typical Schematic VIN = 15 V to 50 V, VOUT = 12 V 16 Copyright © 2012, Texas Instruments Incorporated TPS84250 www.ti.com SLVSAR6 – AUGUST 2012 VIN 8-50 V TPS84250 VIN 2.2 F 100 V 2.2 F 100 V 174kΩ PWRGD VOUT 5 V @ 2.5 A VOUT INH/UVLO 52.3kΩ 31.6kΩ 47 F 6.3 V 47 F 6.3 V VADJ RT/CLK SS/TR 1100kΩ STSEL AGND PGND Figure 30. Typical Schematic VIN = 8 V to 50 V, VOUT = 5 V Power-Up Characteristics When configured as shown in the front page schematic, the TPS84250 produces a regulated output voltage following the application of a valid input voltage. During the power-up, internal soft-start circuitry slows the rate that the output voltage rises, thereby limiting the amount of in-rush current that can be drawn from the input source. The soft-start circuitry introduces a short time delay from the point that a valid input voltage is recognized. Figure 31 shows the start-up waveforms for a TPS84250, operating from a 24-V input and the output voltage adjusted to 5 V. The waveform were measured with a 2-A constant current load. Figure 31. Start-Up Sequence Copyright © 2012, Texas Instruments Incorporated 17 TPS84250 SLVSAR6 – AUGUST 2012 www.ti.com Output On/Off Inhibit (INH) The INH pin provides electrical on/off control of the device. Once the INH pin voltage exceeds the threshold voltage, the device starts operation. If the INH pin voltage is pulled below the threshold voltage, the regulator stops switching and enters low quiescent current state. The INH pin has an internal pull-up current source, allowing the user to float the INH pin for enabling the device. If an application requires controlling the INH pin, use an open drain/collector device, or a suitable logic gate to interface with the pin. Figure 32 shows the typical application of the inhibit function. The Inhibit control has its own internal pull-up to VIN potential. An open-collector or open-drain device is recommended to control this input. Turning Q1 on applies a low voltage to the inhibit control (INH) pin and disables the output of the supply, shown in Figure 33. If Q1 is turned off, the supply executes a soft-start power-up sequence, as shown in Figure 34. A regulated output voltage is produced within 5 ms. The waveforms were measured with a 2-A constant current load. VIN VIN RUVLO1 INH/UVLO Q1 INH Control RUVLO2 AGND Figure 32. Typical Inhibit Control Figure 33. Inhibit Turn-Off 18 Figure 34. Inhibit Turn-On Copyright © 2012, Texas Instruments Incorporated TPS84250 www.ti.com SLVSAR6 – AUGUST 2012 Slow Start (SS/TR) For outputs voltages of 5V or less, the slow start capacitance built into the TPS84250 is sufficient to provide for a turn-on ramp rate that does not induce large surge currents while charging the output capacitors. Connecting the STSEL pin (Pin 29) to AGND while leaving SS pin (Pin 28) open enables the internal SS capacitor with a slow start interval of approximately 5 ms. For output voltages greater than 5V, additional slow start capacitance is recommended. For 12V to 15V output voltages, a 22nF capacitor should be connected between the SS/TR pin (Pin 28) and AGND, while connecting the STSEL pin (Pin 29) to AGND as well. Figure 35 shows an additional SS capacitor connected to the SS pin and the STSEL pin connected to AGND. See Table 6 below for SS capacitor values and timing interval. SS/TR CSS (Optional) AGND STSEL Figure 35. Slow Start Capacitor (CSS) and STSEL Connection Table 6. Slow Start Capacitor Values and Slow Start Time CSS (nF) open 4.7 10 15 22 SS Time (msec) 5 7 10 13 17 Copyright © 2012, Texas Instruments Incorporated 19 TPS84250 SLVSAR6 – AUGUST 2012 www.ti.com Overcurrent Protection For protection against load faults, the TPS84250 incorporates cycle-by-cycle current limiting. During an overcurrent condition the output current is limited and the output voltage is reduced, as shown in Figure 36. As the output voltage drops more than 8% below the set point, the PWRGD signal is pulled low. If the output voltage drops more than 25%, the switching frequency is reduced to reduce power dissipation within the device. When the overcurrent condition is removed, the output voltage returns to the established voltage. The TPS84250 is not designed to endure a sustained short circuit condition. The use of an output fuse, voltage supervisor circuit, or other overcurrent protection circuit is recommended. A recommended overcurrent protection circuit is shown in Figure 37. This circuit uses the PWRGD signal as an indication of an overcurrent condition. As PWRGD remains low, the 555 timer operates as a low frequency oscillator, driving the INH/UVLO pin low for approximately 400ms, halting the power conversion of the device. After the inhibit interval, the INH/UVLO pin is released and the TPS84250 restarts. If the overcurrent condition is removed, the PWRGD signal goes high, resetting the oscillator and power conversion resumes, otherwise the inhibit cycle repeats. 3.3V/5V 475kΩ VDD DIS CONT 47.5kΩ To INH/UVLO Pin 27 TLC555 THRS BSS138 TRIG OUT 3.3V/5V 1 F 100kΩ 100kΩ RST From PWRGD Pin 35 Figure 36. Overcurrent Limiting 20 GND BSS138 Figure 37. Over-Current Protection Circuit Copyright © 2012, Texas Instruments Incorporated TPS84250 www.ti.com SLVSAR6 – AUGUST 2012 Light-Load Behavior The TPS84250 is a non-synchronous converter. One of the characteristics of a non-synchronous converter is that as the load current on the output is decreased, a point is reached where the energy delivered by a single switching pulse is more than the load can absorb. This causes the output voltage to rise slightly. This rise in output voltage is sensed by the feedback loop and the device responds by skipping one or more switching cycles until the output voltages falls back to the set point. At very light loads or no load, many switching cycles are skipped. The observed effect during this pulse skipping mode of operation is an increase in the peak to peak ripple voltage, and a decrease in the ripple frequency. The load current where pulse skipping begins is a function of the input voltage, the output voltage, and the switching frequency. A plot of the pulse skipping threshold current as a function of input voltage is given in Figure 38 for a number of popular output voltage and switching frequency combinations. 900 2.5 V, 400 kHz 3.3 V, 400 kHz 5.0 V, 400 kHz 9 V, 600 kHz 12 V, 800 kHz 15 V, 1 MHz Output Current (mA) 800 700 600 500 400 300 200 100 0 10 15 20 25 30 35 Input Voltage (V) 40 45 50 G000 Figure 38. Pulse Skipping Threshold Synchronization (CLK) An internal phase locked loop (PLL) allows synchronization between 400 kHz and 1 MHz, and to easily switch from RT mode to CLK mode. To implement the synchronization feature, connect a square wave clock signal to the RT/CLK pin with a duty cycle between 20% to 80%. The clock signal amplitude must transition lower than 0.8 V and higher than 2.0 V. The start of the switching cycle is synchronized to the falling edge of RT/CLK pin. In applications where both RT mode and CLK mode are needed, the device can be configured as shown in Figure 39. Before the external clock is present, the device works in RT mode where the switching frequency is set by the RRT resistor. When the external clock is present, the CLK mode overrides the RT mode. The first time the CLK pin is pulled above the RT/CLK high threshold (2.0 V), the device switches from RT mode to CLK mode and the RT/CLK pin becomes high impedance as the PLL starts to lock onto the frequency of the external clock. It is not recommended to switch from CLK mode back to RT mode because the internal switching frequency drops to 100 kHz first before returning to the switching frequency set by the RRT resistor . 470 pF 1 kΩ RT/CLK External Clock 300 kHz to 1 MHz RRT AGND Figure 39. CLK/RT Configuration Copyright © 2012, Texas Instruments Incorporated 21 TPS84250 SLVSAR6 – AUGUST 2012 www.ti.com Thermal Shutdown The internal thermal shutdown circuitry forces the device to stop switching if the junction temperature exceeds 180°C typically. The device reinitiates the power up sequence when the junction temperature drops below 165°C typically. Layout Considerations To achieve optimal electrical and thermal performance, an optimized PCB layout is required. Figure 40 and Figure 41 show two layers of a typical PCB layout. Some considerations for an optimized layout are: • Use large copper areas for power planes (VIN, VOUT, and PGND) to minimize conduction loss and thermal stress. • Place ceramic input and output capacitors close to the module pins to minimize high frequency noise. • Locate additional output capacitors between the ceramic capacitor and the load. • Place a dedicated AGND copper area beneath the TPS84250. • Isolate the PH copper area from the VOUT copper area using the PGND copper area. • Connect the AGND and PGND copper area at one point; at pins 8 & 9. • Place RSET, RRT, and CSS as close as possible to their respective pins. • Use multiple vias to connect the power planes to internal layers. • Use a dedicated sense line to connect RSET to VOUT near the load for best regulation. PGND VIN LOAD VOUT sense Via VOUT PGND Plane COUT2 CIN1 Thermal Vias COUT1 PH RSET VOUT sense Via AGND to PGND Connection AGND Figure 40. Typical Top-Layer Recommended Layout 22 Figure 41. Typical PGND-Layer Recommended Layout Copyright © 2012, Texas Instruments Incorporated TPS84250 www.ti.com SLVSAR6 – AUGUST 2012 EMI The TPS84250 is compliant with EN55022 Class B radiated emissions. Figure 42 and Figure 43 show typical examples of radiated emissions plots for the TPS84250 operating from 24 V and 12 V respectively. Both graphs include the plots of the antenna in the horizontal and vertical positions. Figure 42. Radiated Emissions 24-V Input, 5-V Output, 2-A Load (EN55022 Class B) Copyright © 2012, Texas Instruments Incorporated Figure 43. Radiated Emissions 12-V Input, 5-V Output, 2-A Load (EN55022 Class B) 23 PACKAGE OPTION ADDENDUM www.ti.com 28-Sep-2012 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/ Ball Finish MSL Peak Temp (3) TPS84250RKGR ACTIVE B1QFN RKG 41 500 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR TPS84250RKGT ACTIVE B1QFN RKG 41 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR Samples (Requires Login) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 1 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. All semiconductor products (also referred to herein as “components”) are sold subject to TI’s terms and conditions of sale supplied at the time of order acknowledgment. TI warrants performance of its components to the specifications applicable at the time of sale, in accordance with the warranty in TI’s terms and conditions of sale of semiconductor products. Testing and other quality control techniques are used to the extent TI deems necessary to support this warranty. Except where mandated by applicable law, testing of all parameters of each component is not necessarily performed. TI assumes no liability for applications assistance or the design of Buyers’ products. Buyers are responsible for their products and applications using TI components. To minimize the risks associated with Buyers’ products and applications, Buyers should provide adequate design and operating safeguards. TI does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property right relating to any combination, machine, or process in which TI components or services are used. Information published by TI regarding third-party products or services does not constitute a license to use such products or services or a warranty or endorsement thereof. Use of such information may require a license from a third party under the patents or other intellectual property of the third party, or a license from TI under the patents or other intellectual property of TI. Reproduction of significant portions of TI information in TI data books or data sheets is permissible only if reproduction is without alteration and is accompanied by all associated warranties, conditions, limitations, and notices. TI is not responsible or liable for such altered documentation. Information of third parties may be subject to additional restrictions. Resale of TI components or services with statements different from or beyond the parameters stated by TI for that component or service voids all express and any implied warranties for the associated TI component or service and is an unfair and deceptive business practice. TI is not responsible or liable for any such statements. Buyer acknowledges and agrees that it is solely responsible for compliance with all legal, regulatory and safety-related requirements concerning its products, and any use of TI components in its applications, notwithstanding any applications-related information or support that may be provided by TI. Buyer represents and agrees that it has all the necessary expertise to create and implement safeguards which anticipate dangerous consequences of failures, monitor failures and their consequences, lessen the likelihood of failures that might cause harm and take appropriate remedial actions. Buyer will fully indemnify TI and its representatives against any damages arising out of the use of any TI components in safety-critical applications. In some cases, TI components may be promoted specifically to facilitate safety-related applications. With such components, TI’s goal is to help enable customers to design and create their own end-product solutions that meet applicable functional safety standards and requirements. Nonetheless, such components are subject to these terms. No TI components are authorized for use in FDA Class III (or similar life-critical medical equipment) unless authorized officers of the parties have executed a special agreement specifically governing such use. Only those TI components which TI has specifically designated as military grade or “enhanced plastic” are designed and intended for use in military/aerospace applications or environments. Buyer acknowledges and agrees that any military or aerospace use of TI components which have not been so designated is solely at the Buyer's risk, and that Buyer is solely responsible for compliance with all legal and regulatory requirements in connection with such use. TI has specifically designated certain components as meeting ISO/TS16949 requirements, mainly for automotive use. In any case of use of non-designated products, TI will not be responsible for any failure to meet ISO/TS16949. Products Applications Audio www.ti.com/audio Automotive and Transportation www.ti.com/automotive Amplifiers amplifier.ti.com Communications and Telecom www.ti.com/communications Data Converters dataconverter.ti.com Computers and Peripherals www.ti.com/computers DLP® Products www.dlp.com Consumer Electronics www.ti.com/consumer-apps DSP dsp.ti.com Energy and Lighting www.ti.com/energy Clocks and Timers www.ti.com/clocks Industrial www.ti.com/industrial Interface interface.ti.com Medical www.ti.com/medical Logic logic.ti.com Security www.ti.com/security Power Mgmt power.ti.com Space, Avionics and Defense www.ti.com/space-avionics-defense Microcontrollers microcontroller.ti.com Video and Imaging www.ti.com/video RFID www.ti-rfid.com OMAP Applications Processors www.ti.com/omap TI E2E Community e2e.ti.com Wireless Connectivity www.ti.com/wirelessconnectivity Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265 Copyright © 2012, Texas Instruments Incorporated