TRF3040 MODULATOR/SYNTHESIZER SLWS057 – AUGUST 1999 D D D D D D D D D D D 2-GHz Main Synthesizer, Which Incorporates a Dual-Mode 32/33 and 64/65 Prescaler for Fractional-N Operation 200-MHz Auxiliary Synthesizer, Which Incorporates an 8/9 Prescaler Separate Supply Terminals for Main and Auxiliary Charge Pumps Internal Compensation for Fractional Spurs Low Phase Noise Normal and Integral Charge Pump Outputs Fully Programmable Main and Auxiliary Dividers Serial Data Interface D D D D D D Direct I/Q Modulator Control Logic for Power-Down Modes Single-Sideband Suppressed Carrier (SSBSC) Converter to Generate TX Carrier 200-MHz TXIF Synthesizer and Oscillator Variable Gain Amplifier (VGA) With 50 dB of Dynamic Range 900-MHz Power Amplifier (PA) Driver With 9 dBm Typical Output Power Reference and Clock Buffers 158 mA Typical Total Operating Current at 3.75 V Supply 48-Pin Quad Flatpack (LQFP) XTAL+ INA RA PHA VDDA RCLK MCLK PHI RF RN VSS VDDA PT PACKAGE (TOP VIEW) 48 47 46 45 44 43 42 41 40 39 38 37 PHP VDDA RXLO+ RXLO– VSSA VCCP TXLO+ TXLO– VSSP PHSOUT IPEAK TANK+ 1 36 2 35 3 34 4 33 5 32 6 31 7 30 8 29 9 28 10 27 11 26 12 25 XTAL– TXEN DATA CLOCK LOCK STROBE VSSA VDD I I Q Q DUALTX+ VSSA DUALTX– VSSA VDDA GND TANK– VDDA VSSA VSSA VSSA VSSA 13 14 15 16 17 18 19 20 21 22 23 24 These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Copyright 1999, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 TRF3040 MODULATOR/SYNTHESIZER SLWS057 – AUGUST 1999 description The TRF3040 is an integrated transmit modulator/synthesizer circuit suitable for 900-MHz analog and digital cellular telephones. It consists of a transmit intermediate frequency (TXIF) synthesizer and oscillator, a single-sideband suppressed carrier (SSBSC) converter, a direct conversion I/Q modulator, a variable gain amplifier (VGA) with a power amplifier (PA) driver, a main channel fractional-N synthesizer, an auxiliary channel synthesizer, a crystal oscillator reference buffer, and clock buffers in a small surface-mount package. Very few external components are required. The TXIF synthesizer produces the offset signal, TXIF, needed to translate the external local oscillator (TXLO) signal to the correct transmission frequency. The TXIF_VCO (voltage controlled oscillator) can operate from 90 MHz to 200 MHz, depending on the component values chosen for the external tank circuit. The TXLO signal may be differential or single-ended input. The direct conversion I/Q modulator places the modulation signal (π/4-DQPSK, FM) directly on top of the transmit carrier frequency. The VGA has an output range of – 41 dBm to 9 dBm into a 200-Ω differential load. The balanced output signal simplifies the board layout making it easier to meet isolation requirements. 2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 TRF3040 MODULATOR/SYNTHESIZER SLWS057 – AUGUST 1999 functional block diagram Q Q 26 TXLO – 25 TXLO + 8 7 TXLO_Buffer Transmit Intermediate Frequency Synthesizer 20 + 90 TXIF_VCO Buffer 12 TANK+ 13 TANK– Σ TXIF_Buffer + 90 DUALTX+ Σ TXRF + + TXIF TXIF_ VCO + DUALTX VGA BPF DUALTX– 22 PA Driver + + 90 TXIF Phase Detector and Charge Pump 10 PHSOUT 11 IPEAK I/Q Modulator N (N = 6, 7, 8, 9) 28 35 TXIF_LD 36 XTAL – 34 Control Logic XTAL OSC I SSBSC Converter and TXIF Buffer 37 XTAL + – I 27 INR 33 TXEN DATA CLOCK 31 STROBE RXLO + 3 – 4 Main Prescaler ÷ 32/33 Main Divider RXLO Buffer 1 MCLK Main Phase Detector 38 48 PHP PHI MCLK Buffer RCLK Reference Divider 39 RCLK Buffer TXIF_LD Lock Detect 32 LOCK Reference Divider Buffer Auxiliary Phase Detector 41 PHA Auxiliary Synthesizer Input Buffer 43 INA Main Prescaler ÷ 8/9 POST OFFICE BOX 655303 Auxiliary Divider • DALLAS, TEXAS 75265 3 TRF3040 MODULATOR/SYNTHESIZER SLWS057 – AUGUST 1999 Terminal Functions ÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ TERMINAL NAME NO. I/O DESCRIPTION CLOCK 33 I Serial clock input DATA I Serial data input DUALTX + 34 20† O Differential RF power amplifier driver DUALTX – 22† O Differential RF power amplifier driver GND 19 I 28 I Baseband inverting in-phase modulation input I 27 I Baseband noninverting in-phase modulation input INA 43 I Auxiliary synthesizer input IPEAK 11 LOCK 32 38† O Lock detect output O Buffered master clock output O Auxiliary charge pump output PHI 41 48† O Main charge pump integral output PHP 1 O Main charge pump proportional output PHSOUT 10 O TX offset charge pump output Q 25 I Baseband inverting quadrature modulation input Q 26 I Baseband noninverting quadrature modulation input RA RCLK 42 39† O RF 47 RN 46 RXLO + 3 I Differential main synthesizer positive input RXLO – 4 I Differential main synthesizer negative input STROBE 31 I Data strobe input TANK + 12 I Differential TXIF_VCO tank positive input TANK – 13 I Differential TXIF_VCO tank negative input TXEN 35 I Transmit enable TXLO + 7 I Differential transmit LO positive input TXLO – 8 I Differential transmit LO negative input VCCP VDD 6 Main charge pump and bandgap supply voltage 29 Digital supply voltage 2 Main prescaler and bandgap supply voltage MCLK PHA VDDA Substrate (GND) TX offset loop charge pump current setting resistor Auxiliary charge pump current setting resistor Fractional compensation charge pump current setting resistor Main charge pump current setting resistor 14 24† TX offset loop supply voltage 40 Oscillator and buffers supply voltage 44 Auxiliary charge pump supply voltage RF modulator supply voltage 17, 18 VSSA Buffered reference clock output RF modulator ground 5 Main prescaler and bandgap ground 15 TX offset loop ground 16 TX offset loop and charge pump ground 21, 23 PA driver ground 30 Oscillator, MCLK, and RCLK ground VSS VSSP 45 Digital ground XTAL + 37 I Crystal oscillator base input XTAL – 36 O Crystal oscillator emitter input 9 Main charge pump ground † Pins have limited ESD protection 4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 TRF3040 MODULATOR/SYNTHESIZER SLWS057 – AUGUST 1999 absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Power supply voltage range , VCCP, VDD, VDDA (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.3 V to 4.5 V Voltage applied to any other terminal, VIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.3 V to VCC/VDD + 0.3 V Operation junction temperature, TJmax . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150°C Operating temperature, TA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 40°C to 85°C Storage temperature, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 65°C to 150°C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device, at these or any other conditions beyond those indicated under “recommended operating conditions”, is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTE 1: Voltage values are in respect to VSSA (VSSA = VSSP = VSS = GND) recommended operating conditions PARAMETER Supply voltage, VCCP, VDD, VDDA MIN NOM MAX 3.6 3.75 3.9 High-level input voltage, VIH (CLOCK, DATA, STROBE, TXEN) 0.7 × VDD Low-level input voltage, VIL (CLOCK, DATA, STROBE, TXEN) – 0.3 V VDD + 0.3 0.3 × VDD V 2000 MHz Main synthesizer input frequency, fIN(RXLO±) Main synthesizer input power, PIN(RXLO±), (AC coupled, 50-Ω single ended, 100-Ω differential) UNIT –17 dBm Transmit LO input frequency, fIN(TXLO±) 1050 Transmit LO input power, PIN(TXLO±), (AC coupled, 50-Ω single ended, 100-Ω differential) MHz –10 dBm TXIF_VCO tank differential input frequency, fIN(TANK±) Crystal oscillator input frequency, fIN(XTAL+) Auxiliary synthesizer input frequency, fIN(INA) Auxiliary synthesizer input voltage, VIN(INA), (AC coupled) 200 MHz 25 MHz 200 MHz 0.2 In-phase differential input, I/I (quiescent) VPP V VDDA/2 VDDA/2 Quadraphase differential input, Q/Q (quiescent) Operating free-air temperature, TA – 40 V V 25 °C 85 dc electrical characteristics VCCP = VDD = VDDA = 3.75 V, TA = 25°C (unless otherwise noted) supply current I = ICCP + IDD + IDDA PARAMETER TEST CONDITIONS MIN TYP MAX 2 3 UNIT ISLEEP ISTANDBY Sleep mode supply current 22 mA IOPER_ANA Operating supply current – full power analog mode (MODE=0) 142 mA IOPER_DIG Operating supply current – full power digital mode (MODE=1) 158 mA Standby mode supply current mA dc electrical characteristics VCCP = VDD = VDDA = 3.75 V, TA = 25°C (unless otherwise noted) (continued) digital interface PARAMETER VOL VOH TEST CONDITIONS IO = 1 µA IO = 2 mA IO = – 1 µA Output voltage voltage, low Output voltage voltage, high IO = – 2 mA POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 MIN VDD – 0.050 VDD – 0.4 TYP MAX UNIT 0.050 V 0.4 V V V 5 TRF3040 MODULATOR/SYNTHESIZER SLWS057 – AUGUST 1999 charge pump PHA PARAMETER TEST CONDITIONS IPHA ∆IPHA IPHA Output current at PHA ∆IPHA Output current matching PHA (see Figure 1) Relative output current variation (see Figure 1) RA = 100 kΩ, MIN TYP MAX UNIT 200 250 300 µA 2% 10% VPHA = VDDA/2 10% charge pump PHP, normal mode, VRF = VDDA (see Note 2) PARAMETER IPHP ∆IPHP IPHP TEST CONDITIONS Output current at PHP Relative output current variation (see Figure 1) CN = 128, RN = 120 kΩ MIN TYP MAX UNIT ± 250 ± 288 ± 320 µA 2% 10% VPHP = VDDA/2, ∆IPHP Output current matching PHP (see Figure 1) 10% NOTE 2: When a serial input word A is programmed, the main charge pump on the PHP and PHI is in the speed-up mode as long as STROBE is high in standard programming or until the speed-up mode counter reaches its terminal count. When this is not the case, the main charge pumps are in normal mode. charge pump PHP, speed-up mode, VRF = VDDA (see Note 2) PARAMETER IPHP ∆IPHP IPHP TEST CONDITIONS Output current at PHP Relative output current variation (see Figure 1) CN = 128, RN = 120 kΩ MIN TYP MAX UNIT ± 1.2 ± 1.6 ± 1.9 mA 2% 10% VPHP = VDDA/2, ∆IPHP Output current matching PHP (see Figure 1) 10% NOTE 2: When a serial input word A is programmed, the main charge pump on the PHP and PHI is in the speed-up mode as long as STROBE is high in standard programming or until the speed-up mode counter reaches its terminal count. When this is not the case, the main charge pumps are in normal mode. charge pump PHI, speed-up mode, VRF = VDDA (see Note 2) PARAMETER IPHI ∆IPHI IPHI TEST CONDITIONS Output current at PHI Relative output current variation (see Figure 1) CN = 128, 128 CK = 3, CL = 1 RN = 120 kΩ kΩ, VPHA = VDDA/2, MIN TYP MAX UNIT ± 3.3 ±4 ± 4.5 mA 2% 10% ∆IPHI Output current matching PHI (see Figure 1) 10% NOTE 2: When a serial input word A is programmed, the main charge pump on the PHP and PHI is in the speed-up mode as long as STROBE is high in standard programming or until the speed-up mode counter reaches its terminal count. When this is not the case, the main charge pumps are in normal mode. 6 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 TRF3040 MODULATOR/SYNTHESIZER SLWS057 – AUGUST 1999 dc electrical characteristics VCCP = VDD = VDDA = 3.75 V, TA = 25°C (unless otherwise noted) (continued) fractional compensation PHP, normal mode, VRN = VDDA (see Note 2) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT IPHP–FR Output current PHP vs. fractional numerator – 340 – 270 – 170 nA FMOD = 1,, RF = 120 kΩ,, CN = 128, V = V , ∆IPHP–FR PHP DDA/2 Relative output current (see Figure 1) 10% CK = 3, CL = 1 IPHP–FR NOTE 2: When a serial input word A is programmed, the main charge pump on the PHP and PHI is in the speed-up mode as long as STROBE is high in standard programming or until the speed-up mode counter reaches its terminal count. When this is not the case, the main charge pumps are in normal mode. fractional compensation PHP, speed-up mode, VRN = VDDA (see Note 2) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT IPHP–FR Output current PHP vs. fractional numerator – 1.7 – 1.4 – 1.1 µA FMOD = 1,, RF = 120 kΩ, VPHP =VDDA/2, CN = 128, ∆IPHP–FR Relative output current (see Figure 1) 15% CL = 1 CK = 3, IPHP–FR NOTE 2: When a serial input word A is programmed, the main charge pump on the PHP and PHI is in the speed-up mode as long as STROBE is high in standard programming or until the speed-up mode counter reaches its terminal count. When this is not the case, the main charge pumps are in normal mode. fractional compensation PHI, speed-up mode, VRN = VDDA (see Note 2) PARAMETER IPHI–FR ∆IPHI–FR IPHI–FR TEST CONDITIONS Output current PHI vs. fractional numerator Relative output current (see Figure 1) FMOD = 1,, CN = 128, CK = 3, RF = 120 kΩ, VPHI = VDDA/2, CL = 1 MIN TYP MAX UNIT – 5.1 –4 – 2.9 µA 15% NOTE 2: When a serial input word A is programmed, the main charge pump on the PHP and PHI is in the speed-up mode as long as STROBE is high in standard programming or until the speed-up mode counter reaches its terminal count. When this is not the case, the main charge pumps are in normal mode. charge pump leakage currents PARAMETER IPHI IPHA Output leakage current PHI Output leakage current PHA TEST CONDITIONS VRF = VRN = VDDA, POST OFFICE BOX 655303 VPHP = 0 to VDDA • DALLAS, TEXAS 75265 MIN TYP MAX UNIT ± 0.1 ±10 nA ± 0.1 ±10 nA 7 TRF3040 MODULATOR/SYNTHESIZER SLWS057 – AUGUST 1999 ac electrical characteristics VCCP = VDD = VDDA = 3.75 V, TA = 25°C (unless otherwise noted) transmit intermediate frequency synthesizer, SSBSC converter and I/Q modulator PARAMETER TXLO± TEST CONDITIONS Transmit LO input frequency MIN TYP 900 AC coupled; 50-Ω single-ended, 100-Ω differential UNIT 1100 MHz TXLO± Transmit LO input power TANK± TXIF_VCO tank differential input frequency range PHSOUT TXIF_PD charge pump output level IPEAK TXIF_PD charge pump current setting RIPEAK = 13 kΩ 2.3 mA Kφ TXIF_PD phase gain PLL in phase lock 1.46 mA/rad XTAL+ –13 MAX XTAL oscillator input frequency With external capacitors 25 RCLK, MCLK load circuit Output levels 0.7 1 Differential modulation level MHz 1.0 VPEAK kΩ 1.7 2.0 V 820 920 MHz 820 853 MHz 1.65 TX operating frequency range RF output frequency SE = 1, TXEN = 1, AMPS/DAMPS Output power (I/Q set to typical conditions) Open collector, matched to 200 Ω differential impedance Gain flatness Linearity Li it iin DAMPS mode d (I/Q iin phase, h llevels l sett tto nominal conditions Pout set to 8 dBm) Carrier suppression suppression, I & Q in quadrature DUALTX± dB 36 dBc 45 62 dBc 7th order 53 70 dBc VGA set to Pout = 8 dBm 26 40 VGA set to Pout = –38 dBm 33 25 Ar 30 kHz offset Alternate channel noise power At 60 kHz offset POST OFFICE BOX 655303 1 33 dBc –95 dBc/Hz –101 dBc/Hz 21 33 Upper sideband 21 60 TXLO –2×TXIF 15 TXLO ±3×TXIF 36 Harmonics ≤ 10th 21 869 to 894 MHz • DALLAS, TEXAS 75265 dBc 43 TXLO NOTE 3: Parameters may vary depending on external output matching circuit. 8 dBm 5th order Adjacent channel noise power Broadband noise (0-dB VGA or 9-dBm output, whichever is less 9 3rd order Sideband suppression, I & Q in quadrature TXLO conversion products (see Note 3) VPP dBc 1.8 10 DC bias point TXRF 1.4 0.9 0.8 Differential input impedance MHz MHz 10 Differential input frequency V Ω –100 20 Harmonic content I/I Q/Q I/I, MHz VDDA – 0.5 15 XTAL negative resistance dBm 155 0.5 Frequency range RCLK, RCLK MCLK –10 dBc –124 dBc/Hz TRF3040 MODULATOR/SYNTHESIZER SLWS057 – AUGUST 1999 ac electrical characteristics VCCP = VDD = VDDA = 3.75 V, TA = 25°C (unless otherwise noted) (continued) frequency synthesizers main divider PARAMETER TEST CONDITIONS MIN RXLO± Main synthesizer input frequency RXLO± Main synthesizer input power AC coupled, external shunt 50-Ω single-ended, 100 Ω differential RXLO± Main synthesizer input harmonics and subharmonics No multiclocking TYP MAX UNIT 2000 MHz –17 dBm 30 dBc reference divider PARAMETER INR TEST CONDITIONS MIN TYP Operating frequency Harmonics No multiclocking MAX UNIT 25 MHz 10 dBc auxiliary divider PARAMETER TEST CONDITIONS MIN Auxiliary synthesizer input frequency INA MAX 110 Auxiliary synthesizer input signal amplitude No multiclocking Auxiliary synthesizer input in ut im impedance edance UNIT MHz 0.2 VPP 10 dBc Auxiliary synthesizer input harmonics ZINA TYP Resistance 5 100 Capacitance kΩ 3 pF timing requirements, serial data interface (see Figure 6) PARAMETER TEST CONDITIONS DATA Serial data input rate CLOCK Serial data clock input STROBE Serial data strobe input TXEN Transmit enable tsu tk Setup time: Data to CLOCK, CLOCK to STROBE TYP MAX UNIT 10 MHz 10 MHz 10 Transmit enable TXEN=1 Transmit disable TXEN=0 Hold time. CLOCK to DATA CLOCK STROBE (B-G words) tsw MIN Pulse width A-word, PR = 01 A-word, PR = 10 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 Logic 30 ns 30 ns 30 100 1/fVCO × (NM2 × 65) + t w 1/fVCO × (NM2 × 65) + (NM3+1) × 72) + t w ns 9 TRF3040 MODULATOR/SYNTHESIZER SLWS057 – AUGUST 1999 PARAMETER MEASUREMENT INFORMATION charge-pump current output definitions Current I2 ∆ IOUT REL I1 ∆ IOUT MATCH ISINK V1 V2 Voltage ISOURCE I2 ∆ IOUT REL I1 Figure 1. Charge-Pump Output Current Definitions The relative output current variation is defined as the percent difference between charge-pump current output at two charge-pump output voltages and the mean charge-pump current output (see Figure 1): DIOUT Ť I Ť REL OUT MEAN +2 ǒ Ǔ Ťǒ ) ǓŤ I2 – I1 I2 I1 × 100%; with V 1 + 0.7 V, V2 + VDDA–0.8 V. Output current matching is defined as the difference between charge-pump sinking current output and charge-pump sourcing current output at a given charge-pump output (see Figure 1). ∆ IOUT MATCH = ISINK – ISOURCE; with V1 ≤ Voltage ≤ V2. 10 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 TRF3040 MODULATOR/SYNTHESIZER SLWS057 – AUGUST 1999 APPLICATION INFORMATION R2 100kΩ R3 33kΩ R7 Note: DNP = Do Not Place INA 120kΩ AUX_VCC PHA PHI R23 VCC OSC_VCC + 10 C104 15µF C101 .01µF C97 27pF R1 VCC + VCC C1 27pF VCC 10 C8 15µF C17 15µF RCLK P_VCC + + 10 C3 15µF R10 R5 10 C2 .01µF J1 C4 R4 9.1kΩ R6 C5 15pF .01µ F XTAL CP_VCC R8 C9 .01µF 9.1kΩ C18 .01µF C11 4.7kΩ L1 2200nH C50 15pF R9 .01µF C7 15pF C12 4.7kΩ L2 2200nH D_VCC C71 15pF R12 C10 27pF C19 27pF 48 47 46 45 44 43 42 41 40 39 38 37 DNP 1 2 3 4 5 6 7 8 9 10 11 12 PHP C16 RXLO 22pF TXLO PHSOUT 18kΩ TANK 36 35 34 33 32 31 30 29 28 27 26 25 U1 TRF3040 VCC + DNP R11 C13 27pF C14 .01µ F 10 C15 15µF DNP TXEN DATA CLOCK LOCK STROBE 1– J3 R13 C21 DNP 0 1 J4 13 14 15 16 17 18 19 20 21 22 23 24 R14 MCLK J2 C6 R15 RF_VCC TANK– R16 VCC PD_VCC + R17 C23 27pF VCC + 0 J6 C26 15µF DUALTX Q J5 R18 0 Q– J7 R19 L3 12nH PA_VCC C31 DNP R57 5 C32 1.8pF 0 0 C29 DNP 4 2.2pF C33 C111 3.3pF C25 15 µF C28 27pF C30 BALUN1 1 C27 .01µF C24 .01 µF C22 DNP 0 VCC + 10pF C35 3 L4 12nH C34 27pF C98 .01µF C99 15 µF 6 SLT–090G 0 DUALTX– 2.2pF Figure 2. Evaluation Board Schematic POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 11 TRF3040 MODULATOR/SYNTHESIZER SLWS057 – AUGUST 1999 APPLICATION INFORMATION R21 M/CO__VCC PHP 3.9kΩ L10 12nH R20 1.5kΩ L11 12nH C37 1500pF 5dB ATTENUATOR PAD MVCO 5 C103 27pF R24 10 VT 2X 8 R43 7 2X R25 30Ω R42 180 Ω 1 1X VVCO 1X R40 180 Ω + C46 .01µ F C47 27pF RXLO+ 18 Ω L13 1.5nH C49 4.7pF C107 DNP (100µF) C42 R26 18 Ω L12 5.6nH RTL402672 C45 100 µ F PHI C39 .022µ F C36 470pF C102 27pF C38 1500pF R22 5.1kΩ 22pF R28 49.9 C51 1pF TXLO C55 RXLO J9 18 Ω DNP 9dB ATTENUATOR 9 PAD MAIN VCO J8 C48 R30 22pF STRIPLINE R27 TXLO+ R29 100 Ω 62 Ω R31 100 Ω R32 49.9 Ω PHSOUT R61 10 MΩ R35 51 kΩ C56 100 pF R37 1 kΩ R36 360 Ω C57 330 pF C58 3300 pF C59 33 pF VCC TANK+ 1 R38 1 kΩ + C61 1 µF NET00033 3 3 C62 .01 µF C63 27 pF VC1:A KV1470 VC1:B KV1470 2 C60 3 pF L9 82 nH C64 33 pF TANK– R39 1 kΩ TANK CKT C65 100 pF Figure 2. Evaluation Board Schematic (continued) 12 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 TRF3040 MODULATOR/SYNTHESIZER SLWS057 – AUGUST 1999 APPLICATION INFORMATION REF_IN TCXO_VCC J10 C66 .01 µF 3 XTAL R41 10 Ω TCXO 2 OUT VCC GND VCONT 4 C67 27 pF C68 .01 µF + C69 1 µF 1 C70 0.1 µF TCO-980 TOYOCOM AUX_OUT C77 .022 µF J11 R46 18 Ω C78 .022 µF R49 18 Ω R48 18 Ω INA R50 49.9 Ω AVCO_VCC 10 2 R51 1.5 kΩ R52 0Ω R53 6.2 kΩ C84 470 pF OUT VT VCC MOD VCO190-S VARIL PHA C83 1000 pF R47 10 Ω AVCO 14 C79 27 pF C80 .01 µF + C81 1 µF 6 C82 0.1 µF C85 DNP C86 0.015 pF AUXILIARY VCO & REFERENCE TCX0 Figure 2. Evaluation Board Schematic (continued) POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 13 TRF3040 MODULATOR/SYNTHESIZER SLWS057 – AUGUST 1999 APPLICATION INFORMATION POWER OPTO_VCC POWER GND 1 VI 2 VO 3 VO 4 ADJ + C87 1 µF 5V OPTO_VCC_TP VR1 NC 8 1 7 VO 6 VO 5 NC 1 3.75 V SETTING R55 220 Ω + C88 1 µF LM317LD W CCW Tie GNDs together at this point CW R56 220 Ω 5V SETTING + C89 1 µF CW 7 VO 6 VO 5 NC 1 3.75 V SETTING R58 220 Ω + C94 1 µF W CW CCW R63 1 kΩ AVCO_VCC TCXO_TP NC NC 8 LM317LD R60 1 kΩ VR6 MVCO_VCC VR5 1 VI 2 VO 3 VO 4 ADJ 1 7 VO 6 VO 5 NC W CCW TCXO_VCC 8 7 VO 6 VO 5 NC R64 220 Ω 3V SETTING + C100 1 µF W CW NC 8 7 VO 6 VO 5 NC 3 5V SETTING R65 220 Ω + C90 1 µF W CW R67 1 kΩ VCC_TP VR4 LM317MDT 1 LM317LD CCW R80 1 kΩ AVCO_VCC_TP VR3 1 VI 2 VO 3 VO 4 ADJ 1 LM317LD CCW NC 8 LM317LD R59 1 kΩ 1 VI 2 VO 3 VO 4 ADJ 1 VI 2 VO 3 VO 4 ADJ MVCO_VCC 5V_TP VR2 VIN VOUT ADJ + C91 1 µF R79 51 Ω W CCW VCC 3.75 V SETTING R66 220 Ω 1 + C109 10 µF 1 2 CW R68 500 Ω C92 .01 µF + C110 10 µF 5V OPTO_VCC R69 1.8 kΩ C93 0.1 µF R70 1.8 kΩ R71 1.8 kΩ DATA_TP1 CLOCK_TP1 TXEN_TP1 R74 3.6 kΩ R73 3.6 kΩ R72 1.8 kΩ R75 3.6 kΩ R76 3.6 kΩ TXEN DATA 2 CLOCK 3 STROBE_TP1 4 5 STROBE 10 U3 6 5 1 2 4N28S U4 6 5 U5 6 2 4N28S 4 1 5 2 4N28S 4 1 U6 6 19 LD_TP1 R78 2.7 kΩ U7 LOCK 20 5V R77 2 kΩ 6 2 C96 0.1 µF STROBE P1:E TXEN P1:J LD P1:R P1:S P1:T 21 P1:U 22 P1:V 23 24 5 DATA P1:D 4 18 LOCK_DETECT 1 1 CLOCK P1:C 2 4N28S 4 OPTO_VCC C95 0.1 µF 5 P1:B 25 P1:W P1:X P1:Y 4 MOC8030 Figure 2. Evaluation Board Schematic (PC Interface and Evaluation Board DC Supply Circuitry Only) (continued) 14 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 TRF3040 MODULATOR/SYNTHESIZER SLWS057 – AUGUST 1999 APPLICATION INFORMATION Table 1. TRF3040 Evaluation Board Parts List DESIGNATORS DESCRIPTION VALUE QTY SIZE (mm) MANUFACTURER MANUFACTURER P/N C 1, 10, 13, 19, 23, 28, 34, 47, 63, 67,79, 97, 102, 103 Capacitor 27 pF 14 0603 Murata GRM39COG series C 2, 4, 6, 9, 14, 18, 24, 27,46, 62, 66, 68, 80, 92, 98, 101 Capacitor 0.01 µF 16 0603 Murata GRM39COG series Tantalum capacitor 15 µF 8 6032–C Venkel TA010TCM series C 5, 7, 50, 71 Capacitor 15 pF 4 0603 Murata GRM39COG series C 11, 12, 21, 22, 29, 31, 55, 85, 107 Capacitor DNP 9 C 16, 42, 48 Capacitor 22 pF 3 0402 Murata GRM39COG series C 30, 35 Capacitor 2.2 pF 2 0603 Murata GRM39COG series C 32 Capacitor 1.8 pF 1 0603 Murata GRM39COG series C 33 Capacitor 10 pF 1 0603 Murata GRM39COG series C 36, 84 Capacitor 470 pF 2 0603 Murata GRM39COG series C 37, 38 Capacitor 1500 pF 2 0603 Murata GRM39COG series C 39, 77, 78 Capacitor 0.022 µF 3 0603 Murata GRM39COG series C 3, 8, 15, 17, 25, 26, 99, 104 Tantalum capacitor 100 µF 1 6032-C Venkel TA010TCM series C 49, C51 Capacitor 3.9 pF 1 0603 Murata GRM39COG series C 55 Capacitor DNP 1 0402 C 56, 65 Capacitor 100 pF 2 0603 Murata GRM39COG series C 57 Capacitor 330 pF 1 0603 Murata GRM39COG series C 58 Capacitor 3300 pF 1 0603 Murata GRM39COG series C 59, 64 Capacitor 33 pF 2 0603 Murata GRM39COG series C 60 Capacitor 3 pF 1 0603 Panasonic ECU-V1 series C 45 1 µF 10 3216-A Venkel TA010TCM series C 70, 82, 93, 95, 96 Capacitor 0.1 µF 5 0603 Murata GRM39COG series C 83 Capacitor 1000 pF 1 0603 Murata GRM39COG series Capacitor C 61, 69, 81, 87, 88, 89, 90, 91, 94, 100 C 86 C 109, 110 C 111 Tantalum capacitor 0.015 µF 1 0603 Murata GRM39COG series Tantalum capacitor 10 µF 2 3216-A Venkel TA010TCM series Capacitor 3.3 pF 1 0603 Murata GRM39COG series J8 SMA-V L 1, 2 Inductor L 3, 4, 10, 11 L 12, 13 1 EF Johnson 142-0701-201 2200 nH 2 1008 Coilcraft 0603HS series Inductor 12 nH 4 0603 Coilcraft 0603HS series Inductor 4.7 nH 1 0603 Coilcraft 0603HS series L9 Inductor 82 nH 1 0603 Coilcraft 0603HS series R 1, 5, 10, 12, 23, 24, 41, 47 Resistor 10 8 0603 Panasonic ERJ-3GSYJ series R2 Resistor 100K 1 0603 Panasonic ERJ-3GSYJ series R3 Resistor 33K 1 0603 Panasonic ERJ-3GSYJ series R 4, 8 Resistor 9.1K 2 0603 Panasonic ERJ-3GSYJ series R 6, 9 Resistor 4.7K 2 0603 Panasonic ERJ-3GSYJ series R7 Resistor 120K 1 0603 Panasonic ERJ-3GSYJ series R 11 Resistor DNP 1 0603 Panasonic ERJ-3GSYJ series POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 15 TRF3040 MODULATOR/SYNTHESIZER SLWS057 – AUGUST 1999 APPLICATION INFORMATION Table 1. TRF3040 Evaluation Board Parts List (continued) DESIGNATORS DESCRIPTION VALUE QTY SIZE (mm) MANUFACTURER MANUFACTURER P/N R 13, 15, 16, 17, 18, 19, 52, 57 Resistor 0 8 0603 Panasonic ERJ-3GSYJ series R 14 Resistor 18K 1 0603 Panasonic ERS-36SYJ series R 20, 51 Resistor 1.5K 2 0603 Panasonic ERJ-3GSYJ series R 22 Resistor 5.1K 1 0603 Panasonic ERJ-3GSYJ series R 25, 26, 30 Resistor 18 3 0402 Panasonic ERJ-2GEJ series R 27 Resistor 62 1 0402 Panasonic ERJ-2GEJ series R 28, 32 Resistor 49.9 2 0402 Panasonic ERJ-2GEJ series R 29, 31 Resistor 100 2 0402 Panasonic ERJ-2GEJ series R 40, 42 Resistor 430 2 0402 Panasonic ERJ-2GEJ series R 46, 48, 49 Resistor 18 3 0603 Panasonic ERJ-3GSYJ series R 50 Resistor 49.9 1 0603 Panasonic ERJ-3GSYJ series R 35, 79 Resistor 51 2 0603 Panasonic ERJ-3GSYJ series R 36 Resistor 360 1 0603 Panasonic ERJ-3GSYJ series R 37, 38, 39 Resistor 1K 3 0603 Panasonic ERJ-3GSYJ series R 43 Resistor 10 1 0402 Panasonic ERJ-2GEJ series R 53 Resistor 6.2K 1 0603 Panasonic ERJ-3GSYJ series R 55, 56, 58, 64, 65, 66 Resistor 220 6 0603 Panasonic ERJ-3GSYJ series R 59, 60, 63, 67, 80 Trimpot 1K 5 3313J Bourns R 61 Resistor 10M 1 0805 Panasonic R 68 Trimpot 500 1 3313J Bourns R 69, 70, 71, 72 Resistor 1.8K 4 0603 Panasonic ERJ-3GSYJ series R 73, 74, 75, 76 Resistor 3.6K 4 0603 Panasonic ERJ-3GSYJ series R 77 Resistor 2K 1 0603 Panasonic ERJ-3GSYJ series R 78 Resistor 2.7K 1 0603 Panasonic ERJ-3GSYJ series U1 Integrated circuit 1 Texas Instruments U 3, 4, 5, 6 Opto-coupler 4 Motorola 4N28S U7 Opto-coupler 1 Motorola MOC8030 VC 1 3313J-1-102E ERJ-3GSYJ series 3313J-1-102E TRF3040 Varactor 1 Toko VR 1, 2, 3, 5, 6 Voltage regulator 5 Motorola LM317LD VR 4 Voltage regulator 1 Motorola LM317MDT BALUN 1 1 Hitachi SLT-090G DB25M 1 AMP 747238-4 J 1, 2, 6, 9, 10, 11 SMA_H 7 EF Johnson J 3, 4, 5, 7 BNC-90 4 AMP MVCO Voltage-controlled oscillator 1 Panasonic RTL402672 AVCO Voltage-controlled oscillator 1 Vari–L VCO190-S P1 16 Transformer POST OFFICE BOX 655303 4:1 KV1470 • DALLAS, TEXAS 75265 142-0701-831 413631-1 TRF3040 MODULATOR/SYNTHESIZER SLWS057 – AUGUST 1999 APPLICATION INFORMATION Table 1. TRF3040 Evaluation Board Parts List (continued) DESIGNATORS TCXO CLOCK_TP1 DATA_TP1 LD_TP1 TXEN_TP1 STROBE_TP1 MVCO_TP OPTO_VCC_TP +5V_TP AVCO_VCC_TP TXCO_TP VCC_TP POWER GND DESCRIPTION VALUE QTY SIZE (mm) MANUFACTURER MANUFACTURER P/N Temperature-Compensated Crystal Oscillator 1 Toyocom TCO-980 series Test probe connector 13 Components Corporation TP-105-01 series POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 17 TRF3040 MODULATOR/SYNTHESIZER SLWS057 – AUGUST 1999 PRINCIPLES OF OPERATION operational modes The TRF3040 has two separate operational modes: an advanced mobile phone system (AMPS) mode, and a digital advanced mobile phone system (DAMPS) mode, both of which are selected based on which cellular system is in use. In addition, the TRF3040 can be operated in different power-saving mode settings. The power-saving modes disable the circuitry that is not in use at the time in order to reduce power consumption. During sleep mode, only the circuitry required to provide a master clock to the digital portion of the system is active. In standby mode, the main synthesizer, the auxiliary synthesizer, and the master clock circuitries are enabled. In transmit mode, all functions of the device are enabled. Table 2 describes the functions that are enabled during each mode, and Table 3 describes the related programming control bit(s). Table 2. TRF3040 Power-Mode Function Usage FUNCTION ENABLED AMPS/DAMPS ÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ SLEEP STANDBY TRANSMIT X X X Crystal oscillator TXIF phase detector X ÷N X TXIF buffer X TXIF_VCO X TXIF_VCO buffer X SSCSB converter MCLK buffer X RCLK buffer X X X X X TXLO buffer X ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁ RXLO buffer X I/Q modulator X X DUALTX VGA X Control logic X X X Reference divider buffer X X Auxiliary divider buffer X X Main phase detector X X Auxiliary phase detector X X Lock detect X X Table 3. TRF3040 Programming Power-Mode Function FIELD BIT(S) frequency synthesizer SLEEP STANDBY TRANSMIT SM 0:on 1:off 1:off SE 0:off 0:off 1:on EA 0:off 1:on 1:on EM 0:off 1:on 1:on The frequency synthesizer consists of the serial data interface, the main channel synthesizer, and the auxiliary synthesizer. Figure 3 illustrates the functionality of the frequency synthesizer. 18 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 TRF3040 MODULATOR/SYNTHESIZER SLWS057 – AUGUST 1999 PRINCIPLES OF OPERATION DATA CLOCK STROBE 34 33 Serial Input + Program Latches 31 PR EM 2 3 RXLO 2 Divide By 32/33 Prescaler 4 MN1 12 NM2 NM3 8 Main Divider FMOD NF 3 Prescaler Modulus Control Fractional Accumulator 47 Compensation Charge Pump RF EM Main Phase Detector RSM 2 INR CN 8 12 Reference Divider RSA 2 CL 2 Proportional Charge Pump Main Reference Select NR EM + EA CN 8 1 2 4 8 CL 2 1 46 Integral Charge Pump 48 PHI Auxiliary Reference Select 32 Auxiliary Phase Detector Auxiliary Charge Pump EA 43 RN CK 4 EA INA PHP Divide By 8/9 Prescaler Auxiliary Divider 42 41 LOCK RA PHA 13 NA Figure 3. Frequency Synthesizer Functional Block Diagram POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 19 TRF3040 MODULATOR/SYNTHESIZER SLWS057 – AUGUST 1999 PRINCIPLES OF OPERATION serial programming input The TRF3040 operates using CLOCK, DATA, and STROBE pins of the serial data interface. The serial programming data is structured into 24-bit words, of which one or four bits are dedicated address bits. Figure 4 shows the format and the content of each word. Table 4 lists the symbols, number of bits, and the function for each word used in the standard programming mode (ALT = 0). Similarly, the alternate programming mode (ALT = 1) is described in Figure 5 and Table 5. Figure 6 shows the timing diagram for the serial input. When the STROBE goes low, the signal on the DATA input is clocked into a shift register on the positive edges of the CLOCK. When the STROBE goes high, depending on the 1 or 4 address bit(s), data is latched into different working or temporary registers. To fully program the modulator/synthesizer, five words must be sent: G, D, C, B, and A. The E-word is for testing purposes only. The A-word contains new data for the main divider. The A-word is loaded into the working registers only when a main divider synchronization signal is active to avoid phase jumps when reprogramming the main divider. The data for CN and PR is stored by the B-word in temporary registers. The data in these temporary registers is loaded into the work registers together with the A-word. This avoids false main-divider input when the A-word is loaded. The value of the auxiliary divider ratio, NA, is defined by a 13-bit field, and the operational mode of the main synthesizer is determined by the least significant bit (LSB) of the C-word: Standard mode: ALT = 0 Alternate mode: ALT = 1 The content of the D-word defines the operation of the reference divider. The OR function of bits EA and EM enables the buffer/amplifier input stage. The reference divider ratio is determined by the value of NR. The main and auxiliary synthesizer sections can individually select a reference postscaler division of 1, 2, 4, or 8 by selecting fields RSM and RSA, respectively. The G-word programs all other functions: VGA power control, ÷ N (TXIF loop), SE (TXIF synthesizer loop enable), AMPS and DAMPS modes, and sleep mode. The E-word is for testing purposes only and is reset when programming the D-word. 20 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 TRF3040 MODULATOR/SYNTHESIZER SLWS057 – AUGUST 1999 PRINCIPLES OF OPERATION WORD D23 A D0 NM2 0 NF B 1 0 0 0 C 1 0 0 1 NM1 0 0 0 0 NM3 CN CK NA NM2 CL PR 0 0 0 0 0 0 A L T S D 1 0 1 0 F M p RSM E RSA E O a M A D r NR e E 1 1 1 1 S p a r e T S G 1 0 1 1 PC N S M p p O S a a S D E r r M E e e Spare Figure 4. Serial Input Word Format (Standard Programming, ALT = 0) POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 21 TRF3040 MODULATOR/SYNTHESIZER SLWS057 – AUGUST 1999 PRINCIPLES OF OPERATION Table 4. Standard Programming (ALT = 0) Function Table (see Notes 4 and 5) SYMBOL BITS NM1 12 NM2 8 if PR = X1 4 if PR = X0 NM3 4 if PR = X0 0 otherwise FUNCTION Number of main divider cycles when the prescaler is programmed in ratio R1† Number of main divider cycles when the prescaler is programmed in ratio R2† Number of main divider cycles when the prescaler is programmed in ratio R3† PR 2 Main synthesizer prescaler type in use: PR = X1: modulus 2 prescaler (64/65) PR = X0: modulus 3 prescaler (64/65/72) NF 3 Main synthesizer fractional-N increment FMOD 1 Main synthesizer fractional-N modulus selection flag: 1 = modulo 8 0 = modulo 5 CN 8 Current setting factor for main charge pumps CL 2 Acceleration factor for proportional charge pump current CK 4 Acceleration factor for integral charge pump current EM 1 Main divider enable flag (see Table 11) EA 1 Auxiliary divider enable flag (see Table 11) RSM 2 Reference select for main phase detector RSA 2 Reference select for auxiliary phase detector NR 12 Reference divider ratio NA 13 Auxiliary divider ratio N 2 TXIF synthesizer divider ratio, ÷N, N = 6, 7, 8, 9 (see Note 6) PC 7 Variable gain amplifier (VGA) power control function (see Table 14) SE 1 TXIF synthesizer on/off. SE=1, TXIF synthesizer on; SE=0, TXIF synthesizer off SM 1 Sleep mode bit; SM bit shuts down the synthesizers and the modulator section (see Table 3) MODE 1 Mode control: MODE=1, digital (DAMPS); MODE=0, analog (AMPS) (see Note 7) ALT 1 Alternate programming bit; ALT=0, standard (STD) mode; ALT=1, enhanced (ALT) mode (see Note 8) T 19 Test mode connection of internal signals to lock pin: see test modes section † Not including reset cycles and fractional-N effects. R1 = 64, R2 = 65, R3 = 72. NOTES: 4. Data bits are shifted in on the leading clock edge, with the least significant bit (LSB) first in and the most significant bit (MSB) last. 5. On the rising edge of the strobe and with the address decoder output = 1, the contents of the input shift register are transferred to the working registers. The strobe rising edge comes one-half clock period after the clock edge on which the MSB of a word is shifted in. 6. Field bits setting for the TXIF synthesizer divider ratio N1 N0 BN 0 0 6 0 1 7 1 0 8 1 1 9 FIELD BIT 7. The MODE bit allows a reduction in current for the DUALTX output driver while in AMPS mode. 8. The ALT programming bit allows the user to specify an enhanced programming scheme which allows for a fully programmable fractional modulus of 1 to 16 for the main synthesizer. 22 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 TRF3040 MODULATOR/SYNTHESIZER SLWS057 – AUGUST 1999 PRINCIPLES OF OPERATION MSB LSB D23 D0 WORD A0 0 B 1 0 0 0 C 1 0 0 1 D NF G CN CK NA 1 0 1 0 1 1 1 1 E 0 NM FMOD RSM E RSA E M A NR S p a r e 1 0 1 1 M A C C P P A 0 L T S p a r e T S G CL PC N M p O S a D E r E e S p S a M r e Spare Figure 5. Serial Input Word Format (Alternate Programming, ALT = 1) POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 23 TRF3040 MODULATOR/SYNTHESIZER SLWS057 – AUGUST 1999 PRINCIPLES OF OPERATION Table 5. Alternate Programming (ALT = 1) Function Table SYMBOL BITS FUNCTION NF 4 Main synthesizer fractional-N increment NM 18 Overall main divider integer division ratio CN 8 Binary current-setting factor for main charge pumps G 4 Speed-up mode duration (number of reference divider cycles) CK 4 Binary acceleration factor for integral charge pump current CL 2 Binary acceleration factor for proportional charge pump current MCP 1 Main charge pump polarity ACP 1 Auxiliary charge polarity NA 13 Auxiliary charge ratio FMOD 5 Fraction accumulator modulus NR 12 Reference divider ratio RSM 2 Reference select for main phase detector EM 1 Main divider enable flag (see Table 11) RSA 2 Reference select for auxiliary phase detector EA 1 Auxiliary divider enable flag (see Table 11) N 2 TXIF synthesizer divider ratio, ÷N, N = 6, 7, 8, 9 PC 7 Variable gain amplifier (VGA) power control function (see Table 14) SE 1 TXIF synthesizer on/off. SE=1, TXIF synthesizer on; SE=0, TXIF synthesizer off SM 1 Sleep mode bit: SM bit shuts down the synthesizers and the modulator section (see Table 3) MODE 1 Mode control: mode=1, digital (DAMPS); mode=0, analog (AMPS) ALT 1 Alternate programming bit: ALT=0, standard (STD) mode; ALT=1, enhanced (ALT) mode T 19 Test mode connection of internal signals to LOCK pin (see test modes section) Valid Data Change Data D0 tsu D1 D22 D23 D0 Last Clock th First Clock Clock tsu tsu Clock Disabled Store Data Strobe Clock Enabled – Shift In Data Figure 6. Serial Input Timing Sequence 24 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 TRF3040 MODULATOR/SYNTHESIZER SLWS057 – AUGUST 1999 PRINCIPLES OF OPERATION reference variable divider The internal reference signal INR, which is generated by the external crystal oscillator, is amplified to logic level by a single-ended input buffer. The OR function of the serial input bits EM an EA enables this input buffer. Subsequently, the output of the input buffer feeds the reference divider which consists of a 12-bit programmable divide-by-NR (NR = 4 to 4095) and a four-section postscaler. The main and auxiliary synthesizer sections can individually select a reference postscaler division of 1, 2, 4, or 8 by selecting RSM and RSA, respectively, as shown in Figure 7. Main Select RSM = 00 RSM = 01 RSM = 10 Main Phase Detector RSM = 11 Divide By NR Reference Input 1 2 4 8 Auxiliary Select RSA = 11 RSA = 10 RSA = 01 Auxiliary Phase Detector RSA = 00 Figure 7. Reference Variable Divider auxiliary variable divider The input signal on INA is amplified to logic level by a single-ended input buffer, which has sufficient sensitivity for direct connection to a typical VCO (200 mVpp at 200 MHz). The input stage is enabled when the serial control bit EA = 1. The auxiliary divider consists of a 13-bit programmable divider with a 8/9 dual-modulus prescaler. The 13-bit field divider is composed of two separate counters: a 3-bit NA2 counter and a 10-bit NA1 counter. The total divider ratio value can be expressed as: NA = 8 (NA1 – NA2) + 9 NA2, where 7 NA1 1023, and 0 NA2 7. This results in a continuous integral divide range of 56 to 8191. The detail of the 13-bit field of the auxiliary divider is shown in Figure 8. v v v C Word 1 0 0 1 NA NA1 0 0 0 0 0 0 v A L T NA2 Figure 8. 13-Bit Field Divider POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 25 TRF3040 MODULATOR/SYNTHESIZER SLWS057 – AUGUST 1999 PRINCIPLES OF OPERATION main variable divider – general The input signal on RXLO is amplified to a logic level by a differential-input comparator giving a common mode rejection. The input stage is enabled by serial control bit EM = 1. Disabling means that all currents in the comparator are switched off. The main variable divider is programmed using two different schemes: standard and alternate. The standard programming scheme (ALT=0) is referenced to a main divider section that implements a dual/triple-modulus prescaler [(64/65)/(64/65/72)] design. The dual/triple modulus prescaler is actually synthesized using a 32/33 dual-modulus prescaler with conversions that occur within the TRF3040 and are transparent to the user. Depending on the value of the prescaler select PR, the bit capacity for NM1, NM2, and NM3 is defined, as listed in Table 6 (see also Figure 4). Table 6. Main Variable Divider Bit Capacity BIT CAPACITY PR NM1 NM2 NM3 00 12 8 0 01 12 8 0 10 12 4 4 11 12 4 4 The total N-division ratio, as a function of the 64/65 dual-modulus and the 64/65/72 triple-modulus prescaler can be expressed as: D D Ntotal = 64(NM1 + 2) + 65(NM2), where PR = 0X, Ntotal = 64(NM1 + 2) + 65(NM2) + 72(NM3 + 1), where PR = 1X. For contiguous channels, the values of NM1, NM2, and NM3 are defined: D D v v v NM2 v 63, which yields minimum and maximum divide ratios 14 v NMI v 4095 and 0 v NM2 v 15 and 0 v NM3 v 15, which yields minimum and For PR = 0X: 61 NMI 4095 and 0 of 4032 and 266303, respectively. For PR = 1X: maximum divide ratios of 1096 and 264335, respectively. The alternate programming scheme (ALT=1) is provided for ease of use. The 32/33 dual modulus prescaler is the reference of the alternate programming scheme. Referring to the A-word of Figure 4 shown previously, the main divider consists of 18-bit NM-field counters. The NM-field counter section is composed of two separate counters: a 5-bit A-counter and a 13-bit B-counter, as shown in Figure 9. The prescaler divides by 33 until the A-counter reaches terminal count and then divides by 32 until the B-counter reaches terminal count where upon both counters reset and the cycle repeats. The total NM division is defined as: NMTotal = 32(B – A) + 33(A), where 0 v A v 31 and 31 v B v 8191. This results in a continuous integral divide range of 992 to 262143. If B < 31, the synthesizer no longer provides contiguous channels. It is important to note that the value assigned to A is never greater than the value assigned to B. 26 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 TRF3040 MODULATOR/SYNTHESIZER SLWS057 – AUGUST 1999 PRINCIPLES OF OPERATION main variable divider – general (continued) 32/33 Prescaler RFIN Structure of N-Word 5-Bit A-Counter N A 13 5 13 Bits LSB 18-Bit Register MSB 18 18 N FMOD to Phase Detector B 5 Bits NF 13-Bit B-Counter 4 5 5-Bit Fraction Accumulator 18-Bit Adder Figure 9. Main Divider Organization main variable divider – synchronization The A-word is loaded into working registers only when a main divider synchronization signal is active in order to avoid phase jumps when reprogramming the main divider. The synchronization signal is generated by the main divider and is active when the main divider reaches its terminal count; also at this time, a main divider output pulse is sent to the main phase detector. The new A-word is correctly loaded provided that the STROBE signal is at an active high. main variable divider – fractional accumulator The TRF3040 main synthesizer loop can operate as a traditional integer-N feedback phase-locked loop or as a fractional-N feedback phase-locked loop. The integer-N feedback loop divides the VCO frequency by integer values of N that result in phase detector reference comparisons at the desired channel spacing. A fractional-N feedback loop divides the VCO frequency by an integer term plus a fractional term that results in phase detector reference comparisons at integer multiples of the desired system channel spacing. Integer-N division: VCO frequency N = Phase detector reference frequency = channel spacing Fractional-N division: VCO frequency (N + NF/FMOD)= Phase detector reference frequency where 0 ≤ NF < FMOD and 1 ≤ FMOD ≤ 16. = FMOD × channel spacing Because the programmable main counter and prescaler can not divide by a fraction of an integer, fractional-N division is accomplished by averaging main divider cycles of division by N and N+1. A fractional accumulator that is programmed with values of NF and FMOD is responsible for causing the main counter and prescaler sections to divide by N or N+1. The fractional accumulator operates modulo-FMOD and is incremented by NF at the completion of each main divider cycle. When the fractional accumulator overflows, division by N+1 occurs. Otherwise, the main counters and prescaler divide by N; division by N+1 is transparent to the user. Table 7 shows the contents of the fractional accumulator and the resulting N or N+1 division for two fractional division ratios. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 27 TRF3040 MODULATOR/SYNTHESIZER SLWS057 – AUGUST 1999 PRINCIPLES OF OPERATION Table 7. Fractional Accumulator Operation NF = 3, FMOD = 8 ACCUMULATOR NUMERATOR STATE NF = 6, FMOD = 8 ACCUMULATOR NUMERATOR STATE 3 ÷N 6 ÷N 6 ÷N 4 ÷ N + 1, overflow 1 ÷ N + 1, overflow 2 ÷ N + 1, overflow 4 ÷N 0 ÷ N + 1, overflow 7 ÷N 6 ÷N 2 ÷ N + 1, overflow 4 ÷ N + 1, overflow 5 ÷N 2 ÷ N + 1, overflow 0 ÷ N + 1, overflow 0 ÷ N + 1, overflow For example, suppose that the main synthesizer input frequency is 1958.97 MHz, the main phase detector reference frequency is 240 kHz, and a channel spacing of 30 kHz is realized. The value of FMOD = 8 would be selected because 240 kHz/30 kHz = 8. Dividing the main synthesizer input frequency by the reference frequency results in 1958.97 ÷ 0.24 = 8162.375 = 8162 + 3/8. As a result, the fractional accumulator overflow cycle of this particular frequency is described with NF=3 and FMOD=8 (see Table 7). Figure 10 illustrates the division by N and N+1 for this 3/8 fractional channel example. Number of Main Divider Pulses N (8162) N (8162) N+1 (8163) N (8162) N (8162) N+1 (8163) N (8162) N+1 (8163) RF Input Main Divider Out Figure 10. 3/8 Fractional Channel Main Divider Operation The mean division over the complete fractional accumulator cycle as shown in Figure 9 is: + 8162 ) 8162 ) 8163 ) 8162 )8 8162 ) 8163 ) 8162 ) 8163 + 8162.375 + 8162 ) 3ń8. 1 Therefore, fractional channels are available every 30 kHz or 240 kHz + 2408kHz. FMOD N MEAN main divider – integer channels In the case where NF = 0, only division by N occurs and the fractional accumulator essentially is steady state with a numerator of 0 and never increments or overflows. A channel that requires NF = 0 is a pure integer channel because the fractional term of NF is zero. FMOD 28 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 TRF3040 MODULATOR/SYNTHESIZER SLWS057 – AUGUST 1999 PRINCIPLES OF OPERATION main divider – fractional-N sidebands and compensation Programming a fractional-N channel means the main divider and prescaler divide by N or N + 1 as dictated by the operation of the fractional accumulator. Because the main divider operation is integer in nature and the desired VCO frequency is not, the output of the main phase detector is modulated with a resultant fractional-N phase ripple that, if left uncompensated, produces sideband energy. This phase ripple is proportional and synchronized to the contents of the fractional accumulator that is used to control fractional-N sideband compensation. Only channels that require a nonzero value of NF have the fractional-N sideband energy. The fractional-N sidebands appear at offset frequencies from the VCO fundamental tone, which are multiples of NF/FMOD. Figure 11 shows the fractional-N phase detector ripple for a 3/8 fractional channel. 240 kHz Main Phase Detector Reference Main Phase Detector VCO Feedback Main Phase Detector Fractional-N Ripple Fractional Accumulator State 0 3 6 1 4 7 2 5 0 Figure 11. Fractional-N Phase Detector Ripple for 3/8 Fractional Channel The TRF3040 has internal circuitry that provides a means to compensate for the phase detector fractional-N phase ripple thereby significantly reducing the magnitude of the fractional-N sidebands. Because the current waveform output of the main phase-locked loop (PLL) proportional charge pumps is modulated with the phase detector fractional-N phase ripple, a fractional-N compensation charge pump output is summed with the main PLL proportional charge pump. Figure 12 shows the fractional-N ripple magnitude on the main PHP charge pump output. The magnitude is essentially constant and the pulse width is modulated with the contents of the fractional accumulator. The area under the Main PHP charge pump curve represents the amount of charge delivered to the system loop filter network. In order to minimize fractional-N sidebands in the VCO spectrum, the compensation current waveform is generated to have equal and opposite sign magnitude areas as the main PHP charge pump. Fractional Accumulator State Main PHP Charge Pump Fractional-N Ripple Magnitude 0 3 6 1 4 7 2 5 0 Pulse Width Modulation mA µA Compensation Charge Pump Fractional-N Ripple Magnitude Pulse Amplitude Modulation Figure 12. Main PHP and Compensation Charge Pump Fractional-N Waveforms for 3/8 Fractional Channel POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 29 TRF3040 MODULATOR/SYNTHESIZER SLWS057 – AUGUST 1999 PRINCIPLES OF OPERATION main divider – fractional-N sidebands and compensation (continued) The compensation waveform is pulse-amplitude modulated with the contents of the fractional accumulator. The main PHP pulse magnitude is much larger than the compensation pulse magnitude, but the compensation pulse has a much longer duration than that of the main PHP pulse. The compensation pulse is optimally centered about the main PHP charge pump pulse in order to avoid additional sideband energy due to phase-offset between the main and compensation pulses. The following step illustrates a method for determining correct values for RN, RF, and CN for minimal fractional-N sidebands based on VCO frequency and reference frequency. Assumptions: The main VCO is locked on channel. The 1970 ± 15-MHz main VCO operation, 1958.19 – 1983.15 MHz. 19.44-MHz reference frequency 240-kHz phase detector reference frequency 288-µA peak main PHP current 1. Determine the fundamental fractional-N pulse-width portion of the main PHP charge-pump output waveform for the lower, upper, and mean frequencies. Frac PW–LWR + f1 – + f1 – PD N f VCO + 2401kHz – 8159 1958.19 MHz + 63.83 ps, 8263 + 2401kHz – 1983.15 + 63.031 ps, MHz PD VCO Frac ) FracPW–UPR + 63.83 ps ) 63.031 ps + 63.43 ps. PW*LWR Frac + PW–MEAN Frac PW–UPR N f 2 2 Therefore, the mean unit pulse-width of the fractional-N portion of the main PHP charge-pump output waveform over the VCO frequencies of interest is 63.43 ps. This fundamental pulse width is modulated by the contents of the fractional accumulator. For the 3/8 fractional-N channel example, the pulse width varies as shown in Table 8. Table 8 also shows the area of the fractional-N portion of the main PHP charge-pump waveform. Table 8. Main PHP Fractional-N Pulse Widths and Areas for 3/8 Channel NF = 3, FMOD = 8 ACCUMULATOR STATE 30 MAIN PHP FRACTIONAL PULSE WIDTH (E–12 SECONDS) MAIN PHP FRACTIONAL AREA (E–12 SECOND X AMPS) 3 3 × PW–Mean = 190.29 190.29 ps × 288 µA = 0.54804 6 6 × PW–Mean = 380.58 380.58 ps × 288 µA = 0.109607 1 1 × PW–Mean = 63.43 63.43 ps × 288 µA = 0.018268 4 4 × PW–Mean = 253.72 253.72 ps × 288 µA = 0.073071 7 7 × PW–Mean = 444.01 444.01 ps × 288 µA = 0.127875 2 2 × PW–Mean = 126.86 126.86 ps × 288 µA = 0.036536 5 5 × PW–Mean = 317.15 317.15 ps × 288 µA = 0.091339 0 0 × PW–Mean = 0 0 ps × 288 µA = 0 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 TRF3040 MODULATOR/SYNTHESIZER SLWS057 – AUGUST 1999 PRINCIPLES OF OPERATION main divider – fractional-N sidebands and compensation (continued) 1. Determine the pulse width of the compensation charge-pump output waveform. Comp + f 1 + 19.441 MHz + 51.440 ns PW Ref 2. Determine the fundamental compensation charge pump current magnitude using the fundamental main PHP fractional area. Comp Mag Frac Area + 0.018268 psA + 0.3551 mA + Comp 51.440 ns PW Table 9 shows the magnitude of the compensation pulse as a function of the fractional accumulator. Table 9. Compensation Pulse Magnitudes for 3/8 Channel NF = 3, FMOD = 8 Accumulator Numerator Compensation Pulse Magnitude (µA) 3 3 × 0.3551 = 1.0653 6 6 × 0.3551 = 2.136 1 1 × 0.3551 = 0.3551 4 4 × 0.3551 = 1.4204 7 7 × 0.3551 = 2.4857 2 2 × 0.3551 = 0.7102 5 5 × 0.3551 = 2.4857 0 0 × 0.3551 = 0 3. Using the result of Step 2, determine the value of RF to give the fundamental compensation pulse magnitude. W RF (k ) VBG + 40 x Comp m ( A) Mag + 40 x1.25 + 88 kW. 0.3551 4. Determine values of CN and RN to give a main PHP charge-pump peak current of 500 µA. Assume a mid-range value of CN equal 128. W RN(k ) + ǒ 18.75 CN 256 1 I(mA) Ǔ – 0.75 + ǒ 18.75 128 256 Ǔ 1 – 0.75 0.288 mA + 32.55 kW. 5. The value of the fundamental compensation pulse magnitude calculated in step 3 is fixed, and the compensation pulse width calculated in step 2 is also fixed. However, because the VCO can tune over a significant range of frequencies, the pulse width of the fractional-N portion of the main PHP charge-pump waveform varies, thus the area of the same waveform varies. In order to maintain equal areas under the fractional-N portion of the main PHP charge-pump and compensation waveforms, CN is varied with the VCO frequency. As the VCO frequency increases, the fractional-N portion of the main PHP charge-pump waveform pulse width decreases proportionally, thereby decreasing the area under the same waveform. Therefore, CN must be adjusted to equalize the main PHP and compensation waveform areas. The lower and upper fractional–N pulse widths are calculated using the equations in step 1, as follows: FracPW-LWR = 64.168 ps for fVCO = 1958.19 MHz FracPW-UPR = 63.064 ps for fVCO = 1983.15 MHz POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 31 TRF3040 MODULATOR/SYNTHESIZER SLWS057 – AUGUST 1999 PRINCIPLES OF OPERATION1234 main divider – fractional-N sidebands and compensation (continued) The fundamental area mean value of the fractional-N portion of the main PHP charge-pump waveform was calculated to be 0.018268 pSA. If the fundamental area of the fractional-N portion of the main PHP charge-pump waveform uses the actual pulse widths calculated in step 1 in place of the average pulse width, the fractional-N main PHP areas are as follows: FracArea-LWR = 63.83 ps x 0.288 mA = 0.018383 (E-12 second × Amps), FracArea-UPR = 63.031 ps x 0.288 mA = 0.018383 (E-12 second × Amps). The actual areas under the fractional-N portion of the main PHP waveform require slight modification in the charge-pump current. The variation of CN required for area equalization can be determined using a simple ratio form: CN CN Frac Area–AVG + Frac CN Frac Area–AVG + UPR Frac CN LWR Area–LWR Area–UPR AVG + 0.018268 0.018383 128 + 127, AVG + 0.018268 0.018153 128 + 129. Therefore, CN values would vary from 127–129 over the VCO frequency range of 1958.19–1983.15 MHz for optimum fractional-N sideband suppression. Due to component and circuit tolerances, additional deviations in CN may be appropriate. phase detectors The main and auxiliary synthesizer sections (see Figure 13) incorporate dual D-type flip-flop phase-frequency detectors (PFD). The PFD has gain with phase error over a range of +/–2π and exhibits infinite pull-in range. Dead-band compensation about zero phase error is provided by forcing the sourcing and sinking charge pumps to have a minimum on-time rate of 1/fRef when the loop is operating in a locked condition. The phase detectors can be programmed for polarity sense. Normally, external system VCOs have a positive slope control voltage-frequency characteristic. Some VCOs have a negative slope characteristic. The TRF3040 main and auxiliary phase detectors can be programmed for use with positive or negative slope VCOs using the MCP and ACP fields, respectively, in the B word (EPM mode). For positive slope VCOs: MCP = ACP = 0; for negative slope VCOs: MCP = ACP = 1. 32 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 TRF3040 MODULATOR/SYNTHESIZER SLWS057 – AUGUST 1999 PRINCIPLES OF OPERATION phase detectors (continued) VDDA SET 1 Q D Reference Divider /NR REFIN CLR Q Charge Pump Output SET 1 Main or Auxiliary Reference Divider /N or /NR REFIN or AUXIN Q D CLR Q VSSA Figure 13. Main and Auxiliary Phase Detector Circuit charge-pump current plans The TRF3040 uses internal band-gap references and external resistors to develop biasing reference currents for the various charge pump sections. Three terminals are designated for the external resistors: RN, RF, and RA. Internal, programmable coefficients CN, CL, and CK are also used. Table 10 shows how the external resistors are used to achieve desired charge-pump peak currents. Table 10. Charge Pump Current Plans PARAMETER V CN BG + 17(RN ) 300) 2 CL)1 CN V BG Main PHP + SPEED UP 17(RN ) 300) V CN 2 CL)1 BG Main PHI + PSPEED UP 17 (RN ) 300) Main PHP NORMAL + 40VBGRF PHP + TBD SPEED UP PHI + TBD SPEED UP CK †Fractional PHP NORMAL Fractional Fractional Peak auxiliary current PHA PK + ǒ MODE CONDITION UNIT Normal RN in kΩ mA Speed-up RN in kΩ mA Speed-up RN in kΩ mA Normal RF in kΩ µA RA in kΩ mA Speed-up Ǔ Speed-up 1.25 x 20 RA Normal † The compensation charge-pump current is a pulse-amplitude modulated with the contents of the fractional accumulator. See the section on Main Divider – Fractional-N Sidebands and Compensation. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 33 TRF3040 MODULATOR/SYNTHESIZER SLWS057 – AUGUST 1999 PRINCIPLES OF OPERATION charge-pump current plans (continued) The average charge-pump current for the PHP, PHI, and PHA terminals is defined by: I AVG + qerror 2p x I . PK loop enable/disable The main and auxiliary loops can be enabled and disabled by the contents of enable bits EM and EA, respectively, as described in Table 11. When disabled, all currents in the RF input stages are switched off; the bias currents for the respective charge-pump circuits are switched off as well. When both loops are disabled (EM = EA = 0), the reference input stage currents are switched off. The reference chain can be turned off because the serial interface operates independent of the reference input for the loading of serial words. Table 11. Loop Enable/Disable EM EA 0 0 ENABLED DISABLED 0 1 Auxiliary, reference Main 1 0 Main, reference Auxiliary 1 1 Main, auxiliary, reference Main, auxiliary, reference speed-up mode When the main synthesizer frequency is changed, it may be desirable to increase the loop bandwidth for a short time in order to achieve a faster lock time. The proportional charge-pump current is increased and the integral charge-pump current is switched on for the duration of speed-up mode. The charge-pump current plans section, illustrates how the charge-pump currents are a function of the external resistor RN and the programmable coefficients CN, CL, and CK. The duration of speed-up mode is controlled by two different means that are dependent on the operational programming scheme of the TRF3040 device: either the alternate (ALT) or standard (STD) programming scheme. In the alternate programming scheme, the speed-up mode duration is controlled as a function of the G-field in the B-word and the reference frequency divider period. Duration ALT +G NR f , ALT speed-up mode duration REFIN The content of the G-field is the value of the most significant 4 bits of a total 8-bit programming operation. The least significant 4 bits are static 1 bits. Therefore the minimum of DurationALT is: Duration ALTmin + 15 NR f , REFIN and the maximum of DurationALT is: Duration + 255 NR , REFIN When the TRF3040 is operated in standard programming scheme, the speed-up mode duration is a function of the STROBE signal associated with the A-word. When the STROBE signal following an A-word write operation goes active, speed-up mode currents begin and persist until the STROBE signal is returned to an inactive state. 34 ALTmax f POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 TRF3040 MODULATOR/SYNTHESIZER SLWS057 – AUGUST 1999 PRINCIPLES OF OPERATION lock detect The LOCK terminal can be polled to determine the synthesizer lock condition of either or all three loops. The lock detect function is described by the Boolean expression: LOCK + ǒ LD Main ) EM Ǔ ǒ LD Aux Ǔ ) EA ǒTXIF_LD ) SEǓ test modes The LOCK terminal may be used for test operation. When test modes are enabled, the LOCK terminal is connected to internal nodes of the TRF3040. Test modes are enabled by writing to the E-word. Test modes are disabled by writing zeros to the E-word. These bits are also reset to zero when the D-word is written. Table 12 lists all available test modes and associated programming bits. Table 12. Test Modes TEST MODE T19 – T16 T15 – T12 T11 – T8 T7 – T4 T3 – T0 Lock detect 0000 0000 0000 0000 0000 Fractional overflow 0000 0000 0000 0000 0100 Auxiliary_VCO divider 0000 0000 0000 0000 0101 Main_VCO divider 0000 0000 0000 0000 0110 Main reference divider 0000 0000 0000 0000 0111 Force lock pin HIGH 1100 0000 0000 0000 0000 Force lock pin LOW 0100 0000 0000 0000 0000 Auxiliary and main pumps UP 0000 0000 0000 1010 1000 Auxiliary and main pumps DOWN 0000 0000 0000 0101 1000 Fractional pump test 0000 0000 0010 0000 0000 Main prescaler bypass 0000 0000 0001 0000 0110 Auxiliary prescaler bypass 0000 1000 0000 0000 0101 Enable reference chain test 0001 0000 0000 0000 0111 transmit modulator The transmit modulator section of the TRF3040 is composed of a transmit intermediate frequency synthesizer reset circuit that controls the operation of the transmit modulator, a transmit intermediate frequency phase-locked loop that generates the intermediate transmit frequency (TXIF), a single-sideband suppressed carrier (SSBSC) converter, an I/Q modulator, and an output VGA. transmit intermediate frequency synthesizer reset circuit Figure 14 and Figure 15 reveal that the falling edge of the STROBE toggles the Q output of flip flop (1) to a 1 state, which enables the TXIF phase detector, the TXIF_VCO, the divide-by-N, the TXIF buffer, and the SSB converter. Once the synthesizer is locked, the TXEN signal (enable = 1) turns on the modulator and the VGA. The rising edge of TXEN has no affect on SYNEN as shown in Figure 15. However, the falling edge of TXEN toggles the Q output of flip flop (2) to a 0 state which resets flip flop (1) and causes SYNEN to go to a 0 state, thus disabling the transmit intermediate synthesizer, the I/Q modulator, and the VGA. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 35 TRF3040 MODULATOR/SYNTHESIZER SLWS057 – AUGUST 1999 PRINCIPLES OF OPERATION TXEN VCC Clock Temporary Register MSB (G Word) 1 Data 0 1 1 D CLK R Q Q (2) SE Working Register D (3) D Strobe Q CLK Q R Q CLK Q SYNEN (1) Figure 14. Transmit Intermediate Frequency Synthesizer Reset Circuit TXEN Data LSB MSB Clock Strobe SYNEN Locked Time Transmit Pulse Width Figure 15. Transmit Intermediate Frequency Synthesizer Reset Circuit Timing Diagram 36 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 TRF3040 MODULATOR/SYNTHESIZER SLWS057 – AUGUST 1999 PRINCIPLES OF OPERATION transmit intermediate frequency (TXIF) synthesizer The transmit intermediate frequency (TXIF) PLL portion of the TRF3040 design consists of the following functional blocks: a reference oscillator, a TXIF phase detector, a divide-by-N (÷N), a TXIF_VCO, and an external passive loop filter. reference oscillator The reference crystal oscillator (XTAL OSC) generates the internal reference signal INR. This signal is directly fed to the phase detector of the PLL in the transmit modulator section and to three other different buffers. The first buffer feeds the reference divider of the main phase detector and the auxiliary phase detector. The second buffer, MCLK, is used to provide a clock for external digital circuitry, which is always on. The third buffer, RCLK, is used as a clock for the external circuitry that is used in standby and transmit modes. TXIF phase detector and charge pump The phase comparator compares the output of the divider with the reference oscillator. It provides an output proportional to the phase difference between the divided down TXIF_VCO and the reference. This output is then filtered and used as the control voltage input to the TXIF_VCO. The phase detector is a Gilbert multiplier cell type, with a linear output from 0 to π ( π /2 ± π /2), followed by a charge pump. The charge-pump peak output current could be programmable to 6.4 mA using an external resistor. TXIF lock detect A lock detect signal is provided and ANDed together with lock detect signals from both the main channel synthesizer and auxiliary synthesizer. While in standby mode, the lock detect signal is forced to a valid lock state so that the lock detect signal will indicate when the main and auxiliary phase detectors achieve phase lock. divide-by-N The ÷N is a 2-bit programmable divider that can be configured for any integer division from 6 to 9. The field bits setting for this ÷N is described in Note 6. The divider converts the VCO output down to the reference frequency before feeding it into the phase comparator. TXIF_VCO The voltage controlled oscillator, TXIF_VCO, generates the transmit IF frequency, TXIF, between 90 MHz and 200 MHz. This TXIF_VCO is configured using an external parallel inductor and a dual common-cathode tuning-varactor diode. DC blocking capacitors are used to isolate the varactor control voltage from the VCO tank dc bias voltages. SSBSC converter and TXIF buffer The TXIF buffer provides isolation between the SSBSC converter and the TXIF_VCO output. The converter is an active Gilbert cell multiplier (matched pair) combined with two quadrature phase shift networks and a band-pass filter. The SSBSC converter rejects the unwanted upper sideband that would normally occur during the conversion process. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 37 TRF3040 MODULATOR/SYNTHESIZER SLWS057 – AUGUST 1999 PRINCIPLES OF OPERATION I/Q modulator The quadrature modulator is an active Gilbert cell multiplier (matched pair) with cross-coupled outputs. These outputs are provided to the variable gain amplifier, DUALTX VGA. variable gain amplifier (VGA) and power amplifier (PA) driver The DUALTX VGA power control circuit has a control range of 50 dB (–41 dBm to 9 dBm) with a monotonically decreasing slope, 0.5 dB per step (typical), as shown in Figure 16. A 4:1 balun is used on the applications circuit to transform the 200- differential output impedance of the PA driver to a 50- single-ended impedance for testing purposes. W W 10 DUALTX Output Power – dBm 0 –10 –20 –30 Figure 16. Power Control 38 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 112 116 108 104 96 100 88 92 80 VGA Power Control (PC) Code 84 72 76 68 64 60 56 48 52 40 44 36 32 24 28 16 20 8 12 0 –50 4 –40 TRF3040 MODULATOR/SYNTHESIZER SLWS057 – AUGUST 1999 MECHANICAL DATA PT (S-PQFP-G48) PLASTIC QUAD FLATPACK 0,27 0,17 0,50 36 0,08 M 25 37 24 48 13 0,13 NOM 1 12 5,50 TYP 7,20 SQ 6,80 9,20 SQ 8,80 Gage Plane 0,25 0,05 MIN 1,45 1,35 Seating Plane 1,60 MAX 0°– 7° 0,75 0,45 0,10 4040052 / C 11/96 NOTES: A. B. C. D. All linear dimensions are in millimeters. This drawing is subject to change without notice. Falls within JEDEC MS-026 This may also be a thermally enhanced plastic package with leads connected to the die pads. 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