LM3463 Dynamic Headroom Controller with Thermal Control Interface and Individual Channel Dimming Control General Description Features The LM3463 is a six channel linear LED driver with Dynamic Headroom Control (DHC) interface that is specialized for high power LED lighting applications. The variation of the output current of every output channel in the temperature range of -40°C to 125°C is well controlled to less than ±1%. The output current of every channel is accurately matched to each other with less than ± 1% difference as well. By interfacing the LM3463 to the output voltage feedback node of a switching power supply via the DHC interface, the system efficiency is optimized automatically. The dynamic headroom control circuit in the LM3463 minimizes power dissipation on the external MOSFETs by adjusting the output voltage of the primary switching power supply according to the changing forward voltage of the LEDs. Comprising the advantages of linear and switching converters, the LM3463 delivers accurately regulated current to LEDs while maximizing the system efficiency. The dimming control interface of the LM3463 accepts both analog and PWM dimming control signals. The analog dimming control input controls the current of all LEDs while the PWM control inputs control the dimming duty of output channels individually. The LM3463 provides a sophisticated protection mechanism that secures high reliability and stability of the lighting system. The protection features include VIN Under-Voltage–Lock-Out (UVLO), thermal shut-down, LED short / open circuit protection and MOSFET drain voltage limiting. The LED short circuit protection protects both the LED and MOSFETS by limiting the power dissipation on the MOSFETS. ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ Dynamic Headroom Control output to maximize efficiency 6 channels current regulated LED driver High precision analog dimming control interface 4 individual PWM dimming control input Dimming control via digital data bus Built-in maximum MOSFET power limiting mechanism Allows cascade operation to extend the output channels Fault indicator output Thermal shutdown UVLO with hysteresis 48L LLP package Key Specifications ■ Wide supply voltage range (12V-95V) ■ Thermal fold-back dimming control ■ DHC regulates the lowest MOSFET drain voltage to 1V Applications ■ Streetlights ■ Solid State Lighting Solutions Typical Application 30175790 © 2012 Texas Instruments Incorporated 301757 SNVS807 www.ti.com LM3463 Dynamic headroom Controller with Thermal Control Interface and Individual Channel Dimming Control May 11, 2012 LM3463 Connection Diagram 30175704 Ordering Information Order Number Package Type NSC Package Drawing LLP-48 SQA48A LM3463SQ LM3463SQX Supplied As 1000 Units on Tape and Reel 2500 Units on Tape and Reel Pin Descriptions Pin Name 1 REFRTN 0V reference for small signal return paths This pin should connect to the end points of current sensing resistors with individual connections to ensure channel to channel current accuracy. 2 IOUTADJ Output current level adjust pin The current of all output channels (defined by RISNSn) reduces according to the voltage at this pin. This pin should connect to the VREF pin when output current reduction is not required. 3 VREF Precision reference voltage output This pin is the output of a precision reference voltage regulator. This pin must be bypassed through a ceramic capacitor to REFRTN. www.ti.com Description Application information 2 Name 4 EN Description LM3463 Pin Application information Device enable pin with internal pull-up Enable input Enable: VEN = Floating Disable: VEN = GND 5 FS 6 Faultb 7 8 9 10 11 12 DIM01 DIM23 Internal oscillator control or external clock input pin Fault indicator output. This pin is an open-drain output and is pulled low when an open circuit of LED string is identified. Multi-function input pin. The function of this pin differs depending on the selected operation mode that sets by the MODE pin. Channel 0/1 PWM dimming control Direct PWM mode: Apply a bi-level PWM signal (TTL logic high and low) to this pin to enable/disable ch0 and ch1. Apply logic high to this pin to enable channel 0 and 1. Serial data input In serial interface mode, this pin is configured as the serial data input. DC voltage dimming control In DC interface mode, the voltage on this pin is converted into PWM dimming duty for channel 0 and 1. Multi-function input pin. The function of this pin differs depending on the selected operation mode that sets by the MODE pin. Channel 2/3 PWM dimming control Direct PWM mode: apply bi-level PWM signal (TTL logic high and low) to this pin to enable/disable ch2 and ch3. Apply a logic high to this pin to enable both channel 2 and 3. Serial clock input In serial interface mode, this pin is configured as the serial clock signal input. DC voltage dimming control In DC interface mode, the voltage on this pin is converted into PWM dimming duty for channel 2 and 3. Multi-function input pin. The function of this pin differs depending on the selected operation mode that sets by the MODE pin. Channel 4 dimming control Direct PWM mode: apply bi-level PWM signal to this pin to enable/ disable channel 4. Apply logic high to this pin to enable channel 4. Load data control pin In serial interface mode, this pin is configured as load pulse input, pulling this pin low will latch the shifted-in data into internal register of the LM3463. This pin is pulled low if the requested load operation is not completed. User should check the status of this pin before writing data into the LM3463 through this pin. DC voltage dimming control In DC interface mode, the voltage on this pin is converted into PWM dimming duty for channel 4. Multi-function input pin. The function of this pin differs depending on the selected operation mode that sets by the MODE pin. Channel 5 dimming control Direct PWM mode: Apply a bi-level PWM signal (TTL logic high and low) to this pin to enable/disable channel 5. Apply a logic high to this pin to enable channel 5. Serial operation mode This pin should connect to GND when serial operation mode is selected. DC voltage dimming control In DC interface mode, the voltage on this pin is converted into PWM dimming duty for channel 5. Serial data output for cascade operation Serial control signal output pin for cascade operation. This signal synchronizes with the rising edge of the CLKOUT signal and carries information to the slave devices to turn on LEDs. Sync. pulse input in direct PWM mode This is a synchronization signal input pin for the slave device to perform LED pretest upon system startup. DIM5 CLKOUT The internal clock frequency can be defined by forcing an external clock signal to this pin. Fault indicator output DIM4 SYNC Frequency setting pin. Connect a resistor across this pin to GND to set the internal oscillator frequency. Dimming clock output for cascade Dimming clock output for cascade operation. The frequency at this operation / Sync pulse output for pin equal to 1/2 of the internal clock or externally applied clock Direct PWM mode frequency. 3 www.ti.com LM3463 Pin Name 13 ISR Description Start up current control pin Application information Connect a resistor from this pin to GND to set the additional bias current to the CDHC upon system startup. The voltage on this pin defines the threshold of the drain voltage of the external MOSFETs (VDRn) to begin output current reduction. MOSFET power limit setting input As the VDRn exceeds VDRVLIM, the LED driving current reduces according to the increasing of VDRn at certain fixed rate. This function prevents the MOSFET from over-heating. The maximum power dissipation is limited to VDRVLIM * ILED(per ch.). 14 DRVLIM 15 CDHC Dynamic headroom control time constant capacitor Connect a capacitor (CDHC) from this pin to ground to program the DHC loop response. 16 FCAP Fault de-bounce capacitor Connect a capacitor, CFLT from this pin to ground to program the fault de-bounce time. 17 GND System ground This pin should connect to the system ground Operation mode selection input pin. Bias this pin externally to set the LM3463 in different operation mode. 18 MODE Mode select input pin Direct PWM mode: VMODE = GND Serial interface mode: VMODE = No Connection DC interface mode: VMODE = VCC 19 20 VCC VLedFB Internal regulator output Rail voltage detection input pin Output terminal of the internal voltage regulator. This pin should be bypassed to GND through a 1uf ceramic capacitor. This pin detects the output voltage of the primary power supply (VRAIL). LEDs will be turned on when the voltage at this pin reaches 2.5V. Connect this pin to VCC to set a device as a slave. 21 OutP 22 NC 23 VIN 24 NC 25 DR5 26 NC 27 DR4 28 NC 29 DR3 30 NC 31 DR2 32 NC 33 DR1 34 NC www.ti.com DHC output Driver This pin is an open drain output (current sink) which should connect to the output voltage feedback node of the primary power supply through a resistor and a diode to realize rail voltage adjustment. No connection System supply Supply voltage input pin. This pin should be bypassed to GND using a 1uF ceramic capacitor. No connection Connect to the junction of the drain terminal of the external MOSFET Channel 5 drain voltage feedback and the cathode of the LED string. This pin is connected to the internal input to facilitate DHC comparator to facilitate DHC. No connection Connect to the junction of the drain terminal of the external MOSFET Channel 4 drain voltage feedback and the cathode of the LED string. This pin is connected to the internal input to facilitate DHC comparator to facilitate DHC. No connection Connect to the junction of the drain terminal of the external MOSFET Channel 3 drain voltage feedback and the cathode of the LED string. This pin is connected to the internal input to facilitate DHC comparator to facilitate DHC. No connection Connect to the junction of the drain terminal of the external MOSFET Channel 2 drain voltage feedback and the cathode of the LED string. This pin is connected to the internal input to facilitate DHC comparator to facilitate DHC. No connection Connect to the junction of the drain terminal of the external MOSFET Channel 1 drain voltage feedback and the cathode of the LED string. This pin is connected to the internal input to facilitate DHC comparator to facilitate DHC. No connection 4 Name 35 DR0 36 NC 37 SE5 Connect to the junction of the source terminal of the external Channel 5 LED driver sense input MOSFET and the sense resistor to facilitate current regulation for pin channel 5. 38 GD5 channel 5 gate drive output pin 39 SE4 Connect to the junction of the source terminal of the external Channel 4 LED driver sense input MOSFET and the sense resistor to facilitate current regulation for pin channel 4. 40 GD4 channel 4 gate drive output pin 41 SE3 Connect to the junction of the source terminal of the external Channel 3 LED driver sense input MOSFET and the sense resistor to facilitate current regulation for pin channel 3. 42 GD3 channel 3 gate drive output pin 43 SE2 Connect to the junction of the source terminal of the external Channel 2 LED driver sense input MOSFET and the sense resistor to facilitate current regulation for pin channel 2. 44 GD2 channel 2 gate drive output pin 45 SE1 Connect to the junction of the source terminal of the external Channel 1 LED driver sense input MOSFET and the sense resistor to facilitate current regulation for pin channel 1. 46 GD1 channel 1 gate drive output pin 47 SE0 Connect to the junction of the source terminal of the external Channel 0 LED driver sense input MOSFET and the sense resistor to facilitate current regulation for pin channel 0. 48 GD0 channel 0 gate drive output pin Gate driver output. Connect to the gate terminal of the external MOSFET. Thermal Pad Connect to the GND pin. The EP has no internal connection to ground and must connect to the GND pin externally. Place 9 vias from EP to copper ground plane. EP Description Application information Connect to the junction of the drain terminal of the external MOSFET Channel 0 drain voltage feedback and the cathode of the LED string. Voltage on this pin is being fed to input to facilitate DHC the internal comparator to facilitate DHC. No connection Gate driver output. Connect to the gate terminal of the external MOSFET. Gate driver output. Connect to the gate terminal of the external MOSFET. Gate driver output. Connect to the gate terminal of the external MOSFET. Gate driver output. Connect to the gate terminal of the external MOSFET. Gate driver output. Connect to the gate terminal of the external MOSFET. 5 www.ti.com LM3463 Pin LM3463 Human Body Model(Note 2) Storage Temperature Junction Temperature (TJ) Absolute Maximum Ratings (Note 1) If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/ Distributors for availability and specifications. VIN to GND DR0, DR1, DR2, DR3, DR4, DR5 to GND EN DRVLIM Faultb All other pins ESD Rating ±2 kV −65°C to +150°C −40°C to +125°C Operating Ratings -0.3V to 100V -0.3V to 100V -0.3V to 5.5V -0.3V to 6V -0.3V to 20V -0.3V to 7V Supply Voltage Range (VIN) Junction Temperature Range (TJ) 12V to 95V −40°C to + 125°C Thermal Resistance (θJA) 24°C/W Thermal Resistance (θJC) 2.5°C/W Electrical Characteristics Specification with standard type are for TA = TJ = +25°C only; limits in boldface type apply over the full Operating Junction Temperature (TJ) range. Minimum and Maximum are guaranteed through test, design or statistical correlation. Typical values represent the most likely parametric norm at TJ = +25°C, and are provided for reference purposes only. Unless otherwise stated, the following conditions apply: VIN = 48V. Symbol Parameter Conditions IIN VIN Quiescent Current ISD VIN Shut-Down Current Min Typ Max Units VEN pin floating 9.75 15 mA VEN = 0V 550 800 µA 7.4 10 V Supply VIN UVLO VIN-UVLO VIN Turn-on Threshold VIN Turn-off Threshold 4.5 VIN UVLO Hysteresis 7.1 V 300 mV VCC Regulator VCC VCC Regulated Voltage IVCC-LIM VCC Current Limit VCC-UVLO VCC Turn-on Threshold CVCC = 1 µF, IVCC=1mA 6.240 6.475 6.760 ICC = 10 mA 6.230 6.462 6.741 V 28 45 mA 4.5 4.7 V VCC = 0V VCC Turn-off Threshold VCC UVLO hysteresis 3.75 VCC Decreasing V 4.20 V 300 mV Internal Reference Voltage Regulator VVREF IVREF-SC Reference Voltage Regulator Output CVREF = 0.47 µF, No Load Voltage IVREF = 2mA VREF Pin Short-Circuit Current VVREF = VREFRTN 2.453 2.499 2.564 V 2.443 2.496 2.545 V 7.0 8.2 10.5 mA Dimming Control Interfaces Analog Mode VDIMn-MAX DIMn Voltage at 100% Output Duty Cycle MODE = VCC 5.65 V VDIMn-MIN DIMn Voltage at 0% Output Duty Cycle MODE = VCC 807 mV VDIMn-001H DIMn Voltage at data code = 001h MODE = VCC 826 mV VDIM-LED-ON DIMn Voltage Threshold at LED ON MODE = GND VDIM-LED-OFF DIMn Voltage Threshold at LED OFF VDIM-LED-HYS DIMn Voltage Hysteresis at LED ON to OFF PWM Mode 1.50 1.1 1.75 V 1.4 V 100 mV System Clock Generator VFS FS Pin Voltage FS Pin = Open IFS-SC FS Pin Short-Circuit Current VFS = 0V fOSC System Clock Frequency www.ti.com RFS = 14 kΩ 6 1.173 1.235 110 140 µA 0.90 1.00 1.15 MHz 1.297 V Parameter Conditions VSCLK-HIGH (DIM23) SCLK (Serial CLK) Logic High Threshold MODE = Hi-Z VSCLK-LOW (DIM23) SCLK (Serial CLK) Logic Low Threshold MODE = Hi-Z VSCLK-HYS (DIM23) SCLK (Serial CLK) Hysteresis VSDA-HIGH (DIM01) Min Typ Max Units 1.50 1.75 V Bus Interface Mode 1.4 V MODE = Hi-Z 100 mV SDA (Serial Data) Logic High Threshold MODE = Hi-Z 1.50 VSDA-LOW (DIM01) SDA (Serial Data) Logic Low Threshold MODE = Hi-Z VSDA-HYS (DIM01) SDA (Serial Data) Hysteresis MODE = Hi-Z 1.1 1.1 1.75 V 1.4 V 100 mV 0.95 V Dynamic headroom Control VDRn-DHC-STDEAY The lowest VDRn when DHC is under Measure at DRn pin steady state VVLedFB-TH VLedFB Voltage Threshold for Turning LEDs ON VVLedFB Increasing VVLedFB-HYS VLedFB Voltage Hysteresis VVLedFB decreasing VVLedFBEN-SLAVE VLedFB Pin Voltage Threshold for Slave Mode Measure at VLedFB pin 5.15 5.39 5.60 V VOutP-MAX OutP Max. Output Voltage IOutP = 1mA Current Sink VCDHC = 0.5V 2.90 3.10 3.25 V VOutP-MIN OutP Min. Output Voltage IOutP =1mA Current Sink VCDHC = 3.5V 0.050 0.120 0.235 V VISR ISR Pin Voltage IISR = 1µA Current Sink to GND 1.226 1.307 1.382 V IISR = 10µA Current Sink to GND 1.195 1.240 1.285 V IISR = 100µA Current Sink to GND 1.075 1.125 1.175 V 2.325 2.500 2.625 1.21 V V ICDHC-SOURCE CDHC Pin Max. Sourcing Current Any VDRn < 0.9V 15 26 35 µA ICDHC-SINK CDHC Pin Max. Sinking Current Any VDRn > 0.9V 20 33 45 µA RCDHC-SOURCE CDHC Pin Output Impedance Sourcing current from CDHC pin 1.20 1.70 2.25 MΩ RCDHC-SINK CDHC Pin Output Impedance Sinking current from CDHC pin 0.7 1.1 1.4 gmCDHC-OTA CDHC Pin OTA Transconductance VDRn ≥ 0.9V 75 µmho VDRn < 0.9V 17 µmho MΩ LED Current Regulator VGDn-MAX GDn Gate Driver Maximum Output Voltage VSEn = 0V 5.75 6.20 V IGDn-MAX GDn Gate Driver Short Circuit Current VGDn = 0V IDRn-MAX DRn pin Maximum Input Current VDRn = 80V 35 10 16 mA 50 65 µA VSEn Output Current Sensing Reference Voltage w.r.t VREFRTN VIOUTADJ = VVREF VIOUTADJ = VVREF / 2 190 200 210 mV 85 100 115 mV VIOUTADJ = VREFRTN 2.0 4.6 6.5 mV 5.30 Fault Detection and Handling VSEn-LED-OPEN-FLT LED Open Fault Detection Voltage Threshold at SEn Pin Measure at SEn pin ISEn-LED-OPEN-FLT LED Open Fault Detection Current Threshold at SEn Pin Measure at SEn pin 7 43 15 22 mV 30 µA www.ti.com LM3463 Symbol LM3463 Symbol Parameter Conditions Min Typ Max VDRn-LED-NORMAL LED Open Fault Detection Voltage Threshold at DRn Pin Measure at DRn pin IFCAP-CHG Fault Cap. Charging Current Fault = True 20 28 40 µA VFCAP-FLT-TH FCAP Pin Fault Confirm Voltage Threshold Measure at FCAP pin 3.3 3.6 3.9 V VFCAP-RST-TH FCAP Pin Fault Reset Voltage Threshold Measure at FCAP pin 85 157 230 mV 2.6 3.3 V 330 Units mV Device Enable VEN-ENABLE EN Pin Voltage Threshold for Device Enable VEN-DISABLE EN Pin Voltage Threshold for Device Disable VEN-HYS Device Enable Hysteresis 1.9 2.5 V 100 mV Thermal Protection TSD Thermal shutdown temperature TJ Rising 165 °C TSD-HYS Thermal shutdown temperature hysteresis TJ Falling 20 °C Note 1: Absolute Maximum Ratings are limits beyond which damage to the device may occur. Operating Ratings are conditions under which operation of the device is intended to be functional. For guaranteed specifications and test conditions, see the Electrical Characteristics. Note 2: Human Body Model, applicable std. JESD22-A114-C. Note 3: θJC measurements are performed in general accordance with Mil-Std 883B, Method 1012.1 and utilize the copper heat sink technique. Copper Heat Sink @ 60°C. Note 4: VCC provides self bias for the internal gate drive and control circuits. Device thermal limitations limit external loading. www.ti.com 8 All curves taken at VIN = 48V with configuration in typical application for driving twelve power LEDs with six output channels active and 350 mA output current per channel. TA = 25°C, unless otherwise specified. VSEn vs Temperature, VIOUTADJ=VREF VSEn vs Temperature, VIOUTADJ=0.5 VREF 0.203 103.0 102.5 0.202 102.0 V SEn (mV) 101.5 V SEn (V) 0.201 101.0 0.200 0.199 VIOUTADJ = VREF 0.198 -40 -20 0 100.5 CH0 CH1 CH2 CH3 CH4 CH5 100.0 99.5 VIOUTADJ=0.5*VREF CH0 CH2 CH3 CH4 CH5 99.0 20 40 60 80 100 120 140 TA (°C) -40 -20 0 20 40 60 80 100 120 140 T A (°C) 30175770 30175799 Variation of VSEn vs Temperature, VIOUTADJ=VREF Variation of VSEn vs Temperature, VIOUTADJ=0.5 VREF 1.5 0.8 0.6 0.2 ΔVSEn (%) ΔVSEn (%) 0.4 1.0 VIOUTADJ=VREF 0.0 -0.2 -0.4 -0.6 -0.8 -40 -20 0 CH0 CH1 CH2 CH3 CH4 CH5 VIOUTADJ=0.5*VREF 0.5 0.0 -0.5 -1.0 -1.5 20 40 60 80 100 120 140 TA (°C) -40 -20 0 CH0 CH1 CH2 CH3 CH4 CH5 20 40 60 80 100 120 140 T A (°C) 30175771 30175774 CH-CH Variation of VSEn vs Temperature, VIOUTADJ=VREF CH-CH Variation of VSEn vs Temperature, VIOUTADJ=0.5 VREF 0.29 0.56 V SEn CH-CH Variation (%) V SEn CH-CH Variation (%) 0.26 0.24 0.22 0.20 0.18 0.16 0.15 0.12 VIOUTADJ=VREF 0.10 -40 -20 0 0.50 0.45 0.40 0.35 0.30 0.25 VIOUTADJ=0.5*VREF 0.20 20 40 60 80 100 120 140 T A (°C) -40 -20 0 30175772 20 40 60 80 100 120 140 T A (°C) 30175775 9 www.ti.com LM3463 Typical Performance Characteristics All curves taken at VIN = 48V with configuration in typical application for driving twelve power LEDs with six output channels active and 350 mA output current per channel. TA = 25°C, unless otherwise specified. VSEn vs VIOUTADJ, TA=125°C VSEn vs VIOUTADJ (VIOUTADJ < 60 mV), TA=125°C 12 0.200 0.175 TA=125°C 10 TA=125°C 0.150 V SEn (V) V SEn (mV) 0.125 0.100 0.075 8 6 CH0 CH1 CH2 CH3 CH4 CH5 4 0.050 2 0.025 0.000 0 0.0 0.5 1.0 1.5 V IOUTADJ (V) 2.0 2.5 0 10 20 30 40 V IOUTADJ (mV) 50 30175784 VSEn vs VIOUTADJ, TA=25°C VSEn vs VIOUTADJ (VIOUTADJ < 60 mV), TA=25°C 12 0.200 0.175 TA=25°C 10 TA=25°C 0.150 V SEn (V) V SEn (mV) 0.125 0.100 0.075 8 6 CH0 CH1 CH2 CH3 CH4 CH5 4 0.050 2 0.025 0.000 0 0.0 0.5 1.0 1.5 V IOUTADJ (V) 2.0 2.5 0 10 20 30 40 V IOUTADJ (mV) 50 30175783 VSEn vs VIOUTADJ (VIOUTADJ < 60 mV), TA=–40°C 12 0.200 0.175 0.150 TA=-40°C 10 TA=-40°C V SEn (mV) 0.125 0.100 0.075 8 6 CH0 CH1 CH2 CH3 CH4 CH5 4 0.050 2 0.025 0.000 0.0 60 30175782 VSEn vs VIOUTADJ, TA=–40°C 0 0.5 1.0 1.5 V IOUTADJ (V) 2.0 2.5 0 30175780 www.ti.com 60 30175785 V SEn (V) LM3463 Typical Performance Characteristics 10 20 30 40 V IOUTADJ (mV) 50 60 30175781 10 All curves taken at VIN = 48V with configuration in typical application for driving twelve power LEDs with six output channels active and 350 mA output current per channel. TA = 25°C, unless otherwise specified. VREF vs Temperature 3.50 2.55 3.45 2.54 3.40 2.53 3.35 2.52 3.30 2.51 V REF (V) V OutP-MAX (V) VOutP-MAX vs Temperature 3.25 3.20 2.50 2.50 3.15 2.48 3.10 2.48 3.05 2.46 3.00 2.46 -40 -20 0 20 40 60 80 100 120 140 T A (°C) -40 -20 0 20 40 60 80 100 120 140 T A (°C) 30175776 30175777 VCC vs Temperature Operating IIN vs Temperature 6.56 9.00 6.54 8.95 OPERATING I IN (mA) V CC (V) 6.52 6.50 6.48 6.46 6.44 6.42 8.85 8.80 8.75 8.70 8.65 8.60 8.56 6.40 -40 -20 0 8.90 8.50 -40 -20 0 20 40 60 80 100 120 140 T A (°C) 30175778 20 40 60 80 100 120 140 T A (°C) 30175779 11 www.ti.com LM3463 Typical Performance Characteristics LM3463 Block Diagram 30175711 www.ti.com 12 LED Current Regulators and Analog Dimming Control The LM3463 is a six channel linear current regulator which designed for LED lighting applications. The use of the Dynamic Headroom Control (DHC) method secures high system power efficiency and prolongs system operation lifetime by minimizing the power stress on critical components. The output currents of the LM3463 driver stage are regulated by six individual low-side current regulators. The current regulators are accompanied by a high precision current sensing circuit. In order to ensure excellent current matching among output channels, the current sensing inputs are corresponding to a dedicated reference point, the REFRTN pin to insulate the ground potential differences due to trace resistances. With this current sensing circuit, the channel to channel output current difference is well controlled below ±10% when the output current is reduced (DC LED current reduction) to 5%. The LM3463 provides six individual linear current regulators to perform LED current regulation. Each current regulator includes an internal MOSFET driver and error amplifier and an external MOSFET and current sensing resistor. The output current of every output channel is defined by the value of an external current sensing resistor individually. The reference voltage of the regulators can be adjusted by changing the bias voltage at the IOUTADJ pin. When analog dimming control applies, the output current of all channels reduces proportional to the voltage being applied to the IOUTADJ pin. Figure 1 shows the simplified block diagram of a current regulator. 30175768 FIGURE 1. Block diagram of a linear current regulator Since the driving current of a LED string is determined by the resistance of the current sensing resistor RISNSn individually, every channel can have different output current by using different value of RISNSn. The LED current, IOUTn is calculated using the following expression: out of the guaranteed specification. Figure 2 shows the relationship of VIOUTADJ and VSEn. 0.25 0.20 V SEn (V) AND since: 0.15 0.10 0.05 Thus, 0.00 0 The above equations apply when VIOUTADJ is equal to or below VREF (2.5V). Generally the VIOUTADJ should not be set higher than VREF. Applying a voltage high than VREF to the IOUTADJ pin could result in inaccurate LED driving currents which fall 1 2 3 4 5 V IOUTADJ (V) 6 7 30175720 FIGURE 2. VSEn versus VIOUTADJ 13 www.ti.com LM3463 Overview LM3463 Since the analog dimming control interface is designed for slow brightness control only, the rate of change of the voltage at the IOUTADJ pin must not be higher than 1.25V/sec to allow good tracking of the output current and changing of the VIOUTADJ. The voltage at the IOUTADJ pin can be provided by an external voltage source as shown in Figure 3. VCC Regulator The VCC regulator accepts an input voltage in the range of 12V to 95V from the VIN pin and delivers a 6.5V typical constant voltage at the VCC pin to provide power and bias voltages to the internal circuits. The VCC pin should be bypassed to ground by a low ESR capacitor across the VCC and GND pins. A 1uF 10V X7R capacitor is suggested. The output current of the VCC regulator is limited to 20 mA which includes the biasing currents to the internal circuit. When using the VCC regulator to bias external circuits, it is suggested to sink no more than 10 mA from the VCC regulator to prevent over-heating of the device. VREF Regulator The VREF regulator is used to provide precision reference voltage to internal circuits and the IOUTADJ pin. Other than providing bias voltage to the IOUTADJ pin, the VREF pin should not be used to provide power to external circuit. The VREF pin must be bypassed to ground by a low ESR capacitor across the VREF and RETRTN pins. A 0.47uF 10V X7R capacitor is suggested. 30175760 FIGURE 3. Adjust VSEn by external voltage To secure high accuracy and linearity of dimming control, the voltage of the IOUTADJ pin can be provided by a voltage divider connecting across the VREF and REFRTN pins as shown in Figure 4. 30175761 FIGURE 4. Biasing IOUTADJ from VREF www.ti.com 14 LM3463 30175762 FIGURE 5. Individual connections to REFRTN REFRTN and GND System Clock Generator The REFRTN pin is the reference point for the high precision and low noise internal circuits. The pins which referenced to the REFRTN are VREF, IOUTADJ, SE0, SE1, SE2, SE3, SE4 and SE5. To secure accurate current regulations, the current sensing resistors, RISNSn should connect to the REFRTN pin directly using dedicated connections. And the REFRTN and GND pins should be connected together using dedicated connection as shown in figure 5. The LM3463 includes an internal clock generator which is used to provide clock signal to the internal digital circuits. The clock frequency at the CLKOUT pin is equal to 1/2 of the frequency of the internal system clock generator. The system clock generator governs the rate of operation of the following functions: • PWM dimming frequency in Serial Interface Mode • PWM dimming frequency in DC Interface Mode • Clock frequency in cascade operation (CLKOUT pin) The system clock frequency is defined by the value of an external resistor, RFS following the equation: Device Enable The LM3463 can be disabled by pulling the EN pin to ground. The EN pin is pulled up by an internal weak-pull-up circuit, thus the LM3463 is enabled by default. Pulling the EN pin to ground will reset all fault status. A system restart will be undertaken when the EN pin is released from pulling low. Open Circuit of LED String(s) Operation Mode CLKOUT Freq. Dimming Freq. RFS Serial Interface Mode 125 kHz 488. 3Hz 125 kΩ DC Interface Mode 625 kHz 488.3Hz 62.2 kΩ Direct PWM Mode 625 kHz Virtually no limit 62.2 kΩ When a LED string is disconnected, the LM3463 pulls the Faultb low to indicate a fault condition. The Faultb is an opendrain output pin. An open circuit of a LED string is detected when a VSEn is below 43 mV and the VDRn of the corresponding channel is below 300mV simultaneously. When the fault conditions are fulfilled, the LM3463 waits for a delay time to recognize whether there is a disconnected LED or not. If the conditions of open circuit of LED is sustained longer than the delay time, a real fault is recognized. The delay time for fault recognition is defined by the value of an external capacitor, CFLT, and governed by the following equation: Dynamic Headroom Control (DHC) The fault indication can be reset by either applying a falling edge to the EN pin or performing a system re-powering. The Dynamic Headroom Control (DHC) is a control method which aimed at minimizing the voltage drops on the linear regulators to optimize system efficiency. The DHC circuit inside the LM3463 controls the output voltage of the primary power supply (VRAIL) until the voltage at any drain voltage sensing pin (VDRn) equals 1V. The LM3463 interacts with the 15 www.ti.com LM3463 primary power supply through the OutP pin in a slow manner which determined by the capacitor, CDHC. Generally, the value of the CDHC defines the frequency response of the LM3463. The higher the capacitance of the CDHC, the lower the frequency response of the DHC loop, and vice versa. Since the VRAIL is controlled by the LM3463 via the DHC loop, the response of the LM3463 driver stage must be set one decade lower than the generic response of the primary power supply to secure stable operation. The cut-off frequency of the DHC loop is governed by the following equation: Holding VRAIL In Analog Dimming Control Due to the V-I characteristic of the LED, the forward voltage of the LED strings decreases when the forward current is decreased. In order to compensate the rising of the voltage drop on the linear regulators when performing analog dimming control (due to the reduction of LED forward voltages), the DHC circuit in the LM3463 reduces the rail voltage (V RAIL) to maintain minimum voltage headroom (i.e. minimum VDRn). In order to ensure good response of analog dimming control, the VRAIL is maintained at a constant level to provide sufficient voltage headroom when the output currents are adjusted to a very low level. When the voltage at the IOUTADJ pin is decreased from certain level to below 0.63V, the DHC circuit stops to react to the changing of VDRn and maintains the VRAIL at the level while VIOUTADJ equals 0.63V. DHC resumes when the VIOUTADJ is increased to above 0.63V. Figure 6 shows the relationship of the VRAIL, VSEn and VIOUTADJ. Practically, the frequency response of the primary power supply might not be easily identified (e.g. off-the-shelf AC/DC power supply). For the situations that the primary power supply has an unknown frequency response, it is suggested to use a 2.2uF 10V X7R capacitor for CDHC as an initial value and decrease the value of the CDHC to increase the response of the whole system as needed. 30175792 FIGURE 6. Holding VRAIL when VIOUTADJ is below 0.63V www.ti.com 16 When the LM3463 is powered, the internal Operational Transconductance Amplifier (OTA) charges the capacitor CDHC through the CDHC pin. As the voltage at the CDHC pin increases, the voltage at the OutP pin starts to reduce from VCC. When the voltage of the OutP pin falls below VFB + 0.7V, the OutP pin sinks current from the VFB node and eventually pulls up the output voltage of the primary power supply (VRAIL). As the VRAIL reaches VDHC_READY, the LM3463 performs a test to identify the status of the LED strings (short / open circuit of LED strings). The VDHC_REDAY is defined by an external voltage divider which consists of RFB1 and RFB2. The VDHC_READY is calculated following the equation: After the test is completed, the LM3463 turns on the LED strings with regulated output currents. At the moment that the LM3463 turns the LEDs on, the OutP pin stops sinking current from the VFB node and in turn VRAIL slews down. Along with the decreasing of VRAIL, the voltage at the VDRn pins falls to approach 1V. When a VDRn is decreased to 1V, the DHC loop enters a steady state to maintain the lowest VDRn to 1V average at a slow manner defined by CDHC. Figure 7 presents the changes of VRAIL from system power up to DHC loop enters steady state. 30175767 FIGURE 8. Setting different startup time using different RISR Generally, the system startup time tST is the longest when the ISR pin is left open (tST-1). The amount of the decreasing of the startup time is inversely proportional to the current being drawn from the ISR pin, thus determined by the value of the resistor, RISR. The rate of decreasing of the startup time is governed by the following equation. The practical startup time varies according to the settings of the VDHC_READY, VFB, CDHC and RISR with respect to the following equations. 30175769 where FIGURE 7. Changes of VRAIL during system startup Shortening System Startup Time The system startup time can be shortened by sinking current from the ISR pin to ground through a resistor, RISR. The lower resistance the RISR carries, the shorter time the system startup takes. Sinking current from the ISR pin increases the charging current to the capacitor, CDHCand eventually in- Sinking higher than 100 µA from the ISR pin could damage the device. The value of the RISR should be no lower than 13 kΩ to prevent potential damages. 17 www.ti.com LM3463 creases the rate of the increasing of VRAIL during startup (VRAIL ramps up from VRAIL(nom) to VDHC_READY). Figure 8 shows how the system startup time is shortened by using different value of RISR. System Startup LM3463 30175763 FIGURE 9. Procedure of defining startup parameters HOT. For most applications, the VRAIL(nom) can be set 5 V lower than the VLED-MIN-HOT. Figure 10 shows an example connection diagram of interfacing the LM3463 to a power supply of 2.5V feedback reference voltage. Setting the RDHC and VRAIL Prior to defining the parameters for the operations in steady state, the value of the RDHC and different levels of the supply rail voltage (VRAIL) during system startup must be determined. Figure 9 illustrates the procedures of determining the value of the RDHC and voltage levels of the VRAIL(nom), VRAIL(peak) and VDHC_READY. In Figure 9, the VLED-MAX-COLD and VLED-MIN-HOT are the maximum and minimum forward voltages of the LED strings under the required lowest and highest operation temperatures respectively. In order to ensure all the LED string are supplied with adequate forward current when turning on the LEDs, the VDHC_READY must be set higher than the VLED-MAX-COLD. For most applications, the VDHC_READY can be set 5 V higher than the VLED-MAX-COLD. In order to reserve voltage headroom to perform DHC under high operation temperature, the nominal output voltage of the primary power supply must be set lower than the VLED-MIN- www.ti.com 30175765 FIGURE 10. Connecting the LM3463 to a power supply 18 LM3463 30175766 FIGURE 11. Procedures of selecting the primary power supply If the voltage at any DRn pin is detected lower than 350 mV in the LED test period, that particular output channel will be disabled and excluded from the DHC loop. All disabled output channels will remain in OFF state until a system restarting is undertaken. The LED test performs only once after the voltage at VLedFB pin hits 2.5V. The disabled channel can be reenabled by pulling the EN pin to GND for 10 ms (issuing a system restart) or re-powering the entire system. Choosing the proper Primary Power Supply If the primary power supply is an off-the-shelf power converter, it is essential to make certain that the power converter is able to withstand the VRAIL(peak). In order to allow DHC, the nominal output voltage of the primary power supply needs to be adjusted to below VLED-MIN-HOT as well. The suggested procedures for selecting the proper power supply are as shown in Figure 11. MOSFET Power Dissipation Limit In order to protect the MOSFETs from thermal break down when a short circuit of the LED sting(s) is encountered, the LM3463 reduces the output current according to the increment of the drain voltage of the MOSFET (VDRn) when the drain voltage exceeds a certain preset threshold voltage to limit the power dissipation on the MOSFETs. This threshold voltage is defined by the voltage being applied to the DRVLIM pin, VDRVLIM and is roughly four times the voltage of the VDRVLIM. For example, if the desired drain threshold voltage to perform output current reduction is 16V, the DRVLIM pin voltage should be biased to 4V. Figure 12 shows the relation between VSEn, VDRn and VDRVLIM. Selection of External MOSFET The selection of external MOSFET is dependent on the highest current and the highest voltage that could be applied to the drain terminal of the MOSFET. Generally, the Drain-toSource breakdown voltage (VDSS) and the continuous drain current (ID) of the external MOSFET must be higher than the defined peak supply rail voltage (VRAIL(peak)) and the maximum output LED current (IOUTn) respectively. Testing LEDs at System Startup As VRAIL increases to VDHC_READY, the voltage at the VLedFB pin equals 2.5V. When the voltage at the VLedFB pin rises to 2.5V, the LM3463 sinks 100 µA through every LED strings from the supply rail into the DRn pins for certain period of time to determine the status of the LED strings. The time for checking LED strings is defined by the value of the external capacitor, CFLT and is governed by the following equation: 19 www.ti.com LM3463 Group A CH0 and CH1, controlled by DIM01 pin Group B CH2 and CH3, controlled by DIM23 pin Group C CH4, controlled by DIM4 pin Group D CH5, controlled by DIM5 pin In order to secure accurate current regulation, the pull-up time of every dimming control input must not be shorter than 8 µs. If a 256 level (8-bit resolution) brightness control is needed, the PWM dimming frequency should be no higher than 488Hz. Serial Interface Mode Leaving MODE pin floating enables serial interface mode. In serial interface mode, the DIM01, DIM23 and DIM4 pins are used together as a serial data interface to accept external dimming control data frames serially. The following table presents the functions of the DIM01, DIM23 and DIM4 pins in serial interface mode: 30175764 FIGURE 12. VSEn reduces as VDRn exceeds VDRVLIM x4 Dimming Mode Control The LM3463 provides three modes of PWM dimming control. The three modes are: Direct PWM dimming mode, Serial interface mode and DC interface mode. Selection of the mode of dimming mode is made by leaving the MODE pin open or connecting the MODE pin to GND or VCC. Regardless of the selection of the mode of PWM dimming control, the output channels 0 and 1 are controlled commonly by the signal at the DIM01 pin and the output channels 2 and 3 are controlled commonly by the PWM signal at the DIM23 pin. The dimming duty of the channel 4 and 5 are controlled by the signals on DIM4 and DIM5 pins respectively. The DIM01, DIM23, DIM4 and DIM5 pins are pulled down by an internal 2 MΩ weak pull-downs to prevent the pins from floating. Thus the dimming control input pins are default to 'LED OFF' state and need external pulled up resistors when the pins are connected to open collector/drain signal sources. Figure 13 shows a suggested circuit for connecting the LM3463 to an open collector/drain dimming signal sources. DIM01 Serial data packet input (8-bit packet size) DIM23 Clock signal input for data bit latching DIM4 End Of Frame (EOF) signal input for data packet loading The DIM5 pin is not used in this mode and should connect to GND. Every data frame contains four 8–bit wide data byte for PWM dimming control. Every data byte controls the PWM dimming duty of its corresponding output channel(s): A hexadecimal 000h gives 0% dimming duty; a hexadecimal 0FFh gives 100% dimming duty. Respectively, the first byte being loaded into the LM3463 controls the dimming duty of CH0 and CH1, the second byte controls the dimming duty of CH2 and CH3, the third byte controls the dimming duty of CH4 and the forth byte controls the dimming duty of CH5. In serial interface mode, the six output channels are separated into four individual groups as listed in the following table: Group A CH0 and CH1, controlled by the first byte Group B CH2 and CH3, controlled by the second byte Group C CH4, controlled by the third byte Group D controlled by the forth byte A data bit is latched into the LM3463 by applying a rising edge to the DIM02 pin. After clocking 32 bits (4 data bytes) into the LM3463, a falling edge should be applied to the DIM4 pin to indicate an EOF and load data bytes from data buffer to output channels accordingly. Figure 14 shows the serial input waveforms to the LM3463 to facilitate in serial interface mode. Figure 15 shows the timing parameters of the serial data interface. The PWM dimming duty in the serial interface mode is governed by the following equation: 30175791 FIGURE 13. Adding an external pull-up resistor to the DIMn pin The PWM dimming duty at decimal data codes 01 (001h) and 02 (002h) are rounded up to 2/256. Thus the minimum dimming duty in the serial interface mode is 2/256 or 0.781%. Figure 16 shows the relationship of the PWM dimming duty and the code value of a data byte in the serial interface mode. The PWM dimming frequency in serial interface mode is defined by the system clock of the LM3463. The dimming frequency in the serial interface mode is equal to the system clock frequency divided by 256 which follows the equation below: Direct PWM Dimming Mode Connecting the MODE pin to ground enables direct PWM dimming mode. Every dimming control pin (DIM01 to DIM5) in direct PWM control mode accepts active high TTL logic level signal. In direct PWM dimming mode, the six output channels are separated into four individual groups to accept external PWM dimming signals. The configuration of output channels are as listed in the following table: www.ti.com 20 should be no shorter than 8us, thus a dimming frequency of 488Hz is suggested to use. In order to achieve a 256 level (8–bit resolution) brightness control, the minimum on time of every channel (1/(fSERIAL- 30175746 FIGURE 14. Input waveform to the LM3463 in serial interface mode 30175747 FIGURE 15. Timing parameters of the serial data interface 21 www.ti.com LM3463 DIM*256)) LM3463 30175788 FIGURE 16. PWM dimming duty vs code value of a data byte www.ti.com 22 Group A CH0 and CH1, controlled by the voltage at DIM01 pin Group B CH2 and CH3, controlled by the voltage at DIM23 pin Group C CH4, controlled by the voltage at DIM4 pin Group D CH5, controlled by the voltage at DIM5 pin 100 DIMMING DUTY (%) In DC interface mode, the DIM01, DIM23, DIM4 and DIM5 pins accept DC voltages in the range of 0.8V to 5.7V to facilitate PWM dimming control. The voltage at the DIMn pins (VDIMn) and the PWM dimming duty in the DC interface mode (DDC-DIM) are governed by the following equation. Figure 17 shows the correlation of VDIMn and DDC-DIM. The conversion characteristic is shown in Figure 18. where 0.8V < VDIMn < 5.7V The PWM dimming frequency in the DC interface mode is defined by the system clock of the LM3463. The dimming frequency in the DC interface mode is equal to the system clock frequency divided by 1280 which follows the equation below: 80 60 40 20 0 0 1 2 3 4 V DIMn (V) 5 6 7 30175730 FIGURE 17. Dimming Duty vs VDIMn in DC interface mode 30175789 FIGURE 18. Conversion characteristic of the analog voltage to PWM dimming control circuit 23 www.ti.com LM3463 In order to achieve a 256 level (8–bit resolution) brightness control, the minimum on time of every channel (1/(fSERIALDIM*256)) should be no shorter than 8 us, thus a dimming frequency of 488Hz is suggested to use. The LM3463 samples the analog voltage at the DIMn pins and updates the dimming duty of each output channel at a rate of 1280 system clock cycle (1280/fCLKOUT). In order to ensure correct conversion of analog voltage to PWM dimming duty, the slew rate of the analog voltage for dimming control is limited the following equation: DC Interface Mode Connecting the MODE pin to VCC enables DC interface mode. In this mode the LM3463 converts the voltage on the dimming signal input pins into PWM dimming duty to the corresponding output channels. The six output channels are separated into four individual groups to accept external PWM dimming signals as listed in the following table: LM3463 consists of the DIM01, DIM23 and DIM4 pins and passes the frames to the following slave LM3463 through its serial data output interface (SYNC and CLKOUT pins). Every slave unit shifts data in and out bit by bit to its following slave unit. DC interface mode in cascade operation In the DC interface mode, the master unit accepts four individual analog dimming control signals from external signal sources (via the DIM01, DIM23, DIM4 and DIM5 pins) and encodes the analog signals into 8-bit serial dimming control signals. The master LM3463 passes the encoded dimming control signals serially to the following slave unit through its serial data output interface (SYNC and CLKOUT pins). Every slave unit shifts data in and out bit by bit to its following slave unit. Direct PWM dimming mode in cascade operation In the Direct PWM Dimming mode, the master and slave units share the PWM dimming control signals at the DIM01, DIM23, DIM4 and DIM5 pin to facilitate dimming control. In this mode, the SYNC and CLKOUT of all slave units should be connected to the SYNC and CLKOUT pin of the master unit accordingly to perform startup synchronization. Since the dimming control signal inputs of all the LM3464 are connected in parallel to share the control signals, it is essential to ensure the signal source is strong enough to drive all the LM3463 in parallel. Using Less than Six Output Channels If less than 6 output channels are needed, the unused output channel(s) of the LM3463 can be disabled by not installing the external MOSFET and current sensing resistor. The drain voltage sensing pin (DRn), gate driver output pin (GDn) and current sensing input pin (SEn) of a disabled channel must be left floating to secure proper operation. The output channel(s) which has no external MOSFET and current sensing resistor installed is disabled and excluded from DHC loop at system startup while the VRAIL reaches VDHC_READY. A total of five output channels of the LM3463 can be disabled. The channel 0 must be in use regardless of the number of disabled channel. This feature also applies in cascade operation. Cascading of LM3463 For the applications that require more than six output channels, two or more pieces of LM3463 can be cascaded to expand the number of output channel. Dimming control is allowed in cascade operation. The connection diagrams for cascade operation in different modes of dimming control are as shown in Figure 19. Serial interface mode in cascade operation In the serial interface mode, the master LM3463 accepts external data frames through the serial data interface which www.ti.com 24 LM3463 Serial Data Interface 30175712 DC Voltage Dimming Control Interface 30175713 Direct PWM Diming Control Interface 30175714 FIGURE 19. Connect diagram for cascade operations in different modes of dimming control 25 www.ti.com LM3463 Application Examples LM3463 typical application circuit for stand alone operation 30175701 www.ti.com 26 LM3463 LM3463 typical application circuit for true analog dimming control 30175703 27 www.ti.com LM3463 White LEDs Only 30175715 White + Amber LEDs for Color Temperature Adjustment 30175716 www.ti.com 28 LM3463 White + Red + Green LEDs for CRI Adjustment 30175717 Red + Green + Blue LEDs for Color Mixing 30175718 29 www.ti.com LM3463 Physical Dimensions inches (millimeters) unless otherwise noted 48-Lead Plastic Package NS Package Number SQA48A www.ti.com 30 LM3463 Notes 31 www.ti.com LM3463 Dynamic headroom Controller with Thermal Control Interface and Individual Channel Dimming Control Notes www.ti.com IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. 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