W987Z6CBN/BG 2M × 4 BANKS × 16 BIT SDRAM GENERAL DESCRIPTION W987Z6CB is a high-speed synchronous dynamic random access memory (SDRAM), organized as 2M words × 4 banks × 16 bits. Using pipelined architecture and 0.175 µm process technology, W987Z6CB delivers a data bandwidth of up to 125M words per second (-8). For different application, W987Z6CB is sorted into two speed grades: -75 and –8. The –75 is compliant to the 133MHz/CL3 specification; the -8 is compliant to the 125Mhz/CL3 specification. For handheld device application, these parts are specially designed with several power saving mechanisms to achieve extremely low Self Refresh Current. Accesses to the SDRAM are burst oriented. Consecutive memory location in one page can be accessed at a burst length of 1, 2, 4, 8 or full page when a bank and row is selected by an ACTIVE command. Column addresses are automatically generated by the SDRAM internal counter in burst operation. Random column read is also possible by providing its address at each clock cycle. The multiple bank nature enables interleaving among internal banks to hide the precharging time. By having a programmable Mode Register, the system can change burst length, latency cycle, interleave or sequential burst to maximize its performance. W987Z6CB is ideal for main memory in high performance applications. FEATURES • • • • Power supply VDD = 2.7V −3.6V VDDQ = 2.7V −3.6V Standard Self Refresh Mode Power Down Mode • • • • • • CAS Latency: 2 and 3 Burst Length: 1, 2, 4, 8, and full page 4K Refresh cycles / 64 mS Interface: LVTTL Package: 54 balls FBGA, Operating Temperature Range • Commercial temperature(0°C − 70°C) • Industrial temperature(-40°C − 85°C) AVAILABLE PART NUMBER Part Number Speed Self Refresh Current (max.) Temperature Range Lead-free Package W987Z6CBN75 133MHz/CL3 400µA 0°C − 70 °C No W987Z6CBG75 133MHz/CL3 400µA 0°C − 70 °C Yes W987Z6CBN80 125MHz/CL3 400µA 0°C − 70 °C No W987Z6CBG80 125MHz/CL3 400µA 0°C − 70 °C Yes -1- Publication Release Date: March 2002 Revision P11 W987Z6CBN/BG BALL ASSIGNMENT (TOP VIEW) 1 2 3 Vss DQ15 VSSQ DQ14 DQ13 DQ12 4 5 6 7 8 9 VDDQ DQ0 VDD A VDDQ VSSQ DQ2 DQ1 B DQ11 VSSQ VDDQ DQ4 DQ3 C DQ10 DQ9 VDDQ VSSQ DQ6 DQ5 D DQ8 NC VSS VDD LDQM DQ7 E UDQM CLK CKE CAS RAS WE F NC A11 A9 BA0 BA1 CS G A8 A7 A6 A0 A1 A10/ AP H Vss A5 A4 A3 A2 VDD J Package dimension 8mm x 9 mm -2- W987Z6CBN/BG BALL DESCRIPTION PIN NUMBER BALL NAME FUNCTION H7, H8, J8, J7, J3, J2, H3, H2, DESCRIPTION Multiplexed pins for row and column address. A0 − A11 Address BS0, BS1 Bank Select Row address: A0 − A11. Column address: A0 − A8. H1, G3, H9, G2 G7, G8 A8, B9, B8, C9, C8, D9, D8, E9, DQ0 − DQ15 E1, D2 D1, C2, C1, B2, B1, A2 G9 Select bank to activate during row address latch time, or bank to read/write during address latch time. Multiplexed pins for data output and input. Data Input/ Output Disable or enable the command decoder. When command decoder is disabled, new command is ignored and previous operation continues. CS Chip Select F8 RAS Row Address Strobe F7 CAS F9 WE Write Enable Referred to RAS UDQM LDQM Input/Output Mask The output buffer is placed at Hi-Z (with latency of 2) when DQM is sampled high in read cycle. In write cycle, sampling DQM high will block the write operation with zero latency. F2 CLK Clock Inputs System clock used to sample inputs on the rising edge of clock. F3 CKE Clock Enable CKE controls the clock activation and deactivation. When CKE is low, Power Down mode, Suspend mode or Self Refresh mode is entered. A9, E7, J9 VDD Power Power for input buffers and logic circuit inside DRAM. A1, E3, J1 VSS Ground Ground for input buffers and logic circuit inside DRAM. A7, B3, C7, D3 VDDQ Power for I/O Buffer A3, B7, C3, D7 VSSQ Ground for I/O Separated ground from VSS, used for output buffers Buffer to improve noise. E2, G1 NC F1, E8 Command input. When sampled at the rising edge of the clock, RAS , CAS and WE define the operation to be executed. Column Referred to RAS Address Strobe Separated power from VCC, used for output buffers to improve noise. No Connection No connection -3- Publication Release Date: March 2002 Revision P11 W987Z6CBN/BG BLOCK DIAGRAM CLK CLOCK BUFFER CKE CS RAS CAS CONTROL SIGNAL GENERATOR COMMAND DECODER COLUMN DECODER WE A10 MODE R E G ISTER A0 D E C O D E R COLUMN DECODER R O W R O W CELL ARRAY BANK #0 D E C O D E R CELL ARRAY BANK #1 SENSE AMPLIFIER SENSE AMPLIFIER ADDRESS BUFFER A9 A11 BS0 BS1 DMn DQ0 DATA CONTROL DQ BUFFER CIRCUIT REFRESH COUNTER COLUMN COUNTER DQ15 UDQM LDQM COLUMN DECODER COLUMN DECODER R O W R O W D E C O D E R CELL ARRAY BANK #2 SENSE AMPLIFIER Note: The cell array configuration is 4096 * 512 * 16. -4- D E C O D E R CELL ARRAY BANK #3 SENSE AMPLIFIER W987Z6CBN/BG ABSOLUTE MAXIMUM RATINGS PARAMETER SYMBOL RATING UNIT NOTE Input/Output Voltage VIN, VOUT -0.3 − Vdd +0.3 V 1 Power Supply Voltage VDD, VDDQ -0.3 − 3.6 V 1 Operating Temperature (Commercial parts) TOPR 0 − 70 °C 1 Operating Temperature (Industrial parts) TOPR -40 − 85 °C 1 Storage Temperature TSTG -55 − 150 °C 1 TSOLDER 260 °C 1 PD 1 W 1 IOUT 50 mA 1 Soldering Temperature (10s) Power Dissipation Short Circuit Output Current DC ELECTRICAL CHARACTERISTICS AND OPERATING CONDITIONS (TA = 0°C to 70°C for commercial parts,TA = -40°C to 85°C for Industrial parts) PARAMETER SYMBOL MIN. TYP. MAX. UNIT VDD 2.7 3.0 3.6 V VDDQ 2.7 3.0 3.6 V Input High level Voltage VIH 0.8*VDDQ - VDDQ + 0.3 V Input Low level Voltage VIL -0.3 - 0.2*VDDQ V LVTTL Output H Level Voltage (IOUT = -0.1 mA ) VOH VDDQ – 0.2 - - V LVTTL Output ″L″ Level Voltage (IOUT = +0.1 mA ) VOL - - 0.2 V II(L) -5 - 5 µA IO(L) -5 - 5 µA Supply Voltage Supply Voltage (for I/O Buffer) ″ ″ Input Leakage Current (0V ≤ VIN ≤ VDD, all other pins not under test = 0V) Output Leakage Current (Output disable , 0V ≤ VOUT ≤ VCCQ) Note: VIH(max) = VDD/ VDDQ+1.2V for pulse width < 5 nS VIL(min) = VSS/ VSSQ-1.2V for pulse width < 5 nS CAPACITANCE (VDD =2.7V – 3.6V , f = 1 MHz, TA = 25°C) PARAMETER SYMBOL MIN. MAX. UNIT CI - 3.8 pf Input Capacitance (CLK) CCLK - 3.5 pf Input/Output capacitance CIO - 6.5 pf Input Capacitance (A0 to A11, BS0, BS1, CS , RAS , CAS , WE , DQM, CKE) Note: These parameters are periodically sampled and not 100% tested. -5- Publication Release Date: March 2002 Revision P11 W987Z6CBN/BG OPERATING CURRENT (VDD = 2.7V – 3.6V, TA = 0°C to 70°C for commercial parts ,TA = -40°C to 85°C for Industrial parts) PARAMETER SYM. -75/75I -8/-8I MAX. MAX. UNIT NOTES Operating Current tCK = min., tRC = min. Active precharge command cycling without burst operation 1 bank operation ICC1 65 60 3 Standby Current CKE = VIH ICC2 20 20 3 VIH / L = VIH (min.)/ VIL (max.) Bank: Inactive state CKE = VIL (Power Down mode) ICC2P 0.5 0.5 3 Standby Current CKE = VIH ICC2S 10 10 VIH / L = VIH (min.)/ VIL (max.) BANK: Inactive state CKE = VIL (Power down mode) ICC2PS 0.35 0.35 No Operating Current CKE = VIH ICC3 30 30 ICC3P 2 2 Burst Operating Current tCK = min. Read/ Write command cycling ICC4 90 85 3, 4 Auto Refresh Current tCK = min. Auto refresh command cycling ICC5 150 140 3 Self Refresh Current Self Refresh Mode CKE = 0.2V ICC6 400 400 tCK = min, CS = VIH CLK = VIL, CS = VIH mA tCK = min., CS = VIH (min.) BANK: Active state (4 banks) CKE = VIL (Power down mode) -6- µA W987Z6CBN/BG AC CHARACTERISTICS AND OPERATING CONDITION (Vcc =2.7V – 3.6V , TA = 0° to 70°C for commercial parts ,TA = -40°C to 85°C for Industrial parts; Notes: 5, 6, 7, 8) PARAMETER SYM. -75/75I MIN. -8/-8I MAX. MIN. Ref/Active to Ref/Active Command Period tRC 65 Active to precharge Command Period tRAS 45 Active to Read/Write Command Delay Time tRCD 20 20 Read/Write(a) to Read/Write(b)Command Period tCCD 1 1 Precharge to Active Command Period tRP 20 20 Active(a) to Active(b) Command Period tRRD 15 16 Write Recovery Time CL* = 2 CL* = 3 CLK Cycle Time CL* = 2 CL* = 3 tWR tCK 68 100000 48 10 10 7.5 8 10 10 7.5 8 CLK High Level width tCH 2.5 3 CLK Low Level width tCL 2.5 3 Access Time from CLK CL* = 2 CL* = 3 tAC UNIT MAX. 100000 Cycle 6 6 5.4 6 Output Data Hold Time tOH 3 Output Data High Impedance Time tHZ 3 Output Data Low Impedance Time tLZ 0 Power Down Mode Entry Time tSB 0 7.5 0 8 Transition Time of CLK (Rise and Fall) tT 0.3 10 0.3 10 Data-in Set-up Time tDS 1.5 Data-in Hold Time tDH 1 1 Address Set-up Time tAS 1.5 2 Address Hold Time tAH 1 1 CKE Set-up Time tCKS 1.5 2 CKE Hold Time tCKH 1 1 Command Set-up Time tCMS 1.5 2 Command Hold Time tCMH 1 1 Refresh Time tREF Mode register Set Cycle Time tRSC nS 3 7.5 3 8 0 2 64 15 nS 64 16 mS nS *CL = CAS Latency -7- Publication Release Date: March 2002 Revision P11 W987Z6CBN/BG Notes: 1. Operation exceeds "ABSOLUTE MAXIMUM RATING" may adversely affect the life and reliability of the devices. 2. All voltages are referenced to VSS 3. These parameters depend on the cycle rate and listed values are measured at a cycle rate with the minimum values of tCK and tRC. 4. These parameters depend on the output loading conditions. specified values are obtained with output open. 5. Power up sequence is further described in the "Functional Description" section. 6. AC Testing Conditions Output Reference Level 0.5 * VDDQ Output Load See diagram below Input Signal Levels 0.8* VDDQ / 0.2* VDDQ Transition Time (Rise and Fall) of Input Signal Input Reference Level 1 nS 0.5 * VDDQ 0.5 x VDDQ 50 ohms output Z = 50 ohms 30pF AC TEST LOAD 7. Transition times are measured between VIH and VIL. 8. tHZ defines the time at which the outputs achieve the open circuit condition and is not referenced to output level. 9. The value that shown on table are based on silicon simulation result. It will be changed according to real product characteristic. -8- W987Z6CBN/BG Operation Mode Fully synchronous operations are performed to latch the commands at the positive edges of CLK. Table 1 shows the truth table for the operation commands. Table 1 Truth Table (Note (1), (2)) COMMAND DEVICE STATE CKEn-1 CKEn DQM BS0, 1 A10 A0−A9 A11 CS Bank Active Idle H x x v v v L L H H Bank Precharge Any H x x v L x L L H L Precharge All RAS CAS WE Any H x x x H x L L H L Write Active (3) H x x v L v L H L L Write with Autoprecharge Active (3) H x x v H v L H L L Read Active (3) H x x v L v L H L H Read with Autoprecharge Active (3) H x x v H v L H L H Mode Register Set Idle H x x v v v L L L L No – Operation Any H x x x x x L H H H Burst Stop Active (4) H x x x x x L H H L Device Deselect Any H x x x x x H x x x Auto – Refresh Idle H H x x x x L L L H Self - Refresh Entry Idle H L x x x x L L L H Self Refresh Exit idle (S.R.) L L H H x x x x x x x x H L x H x H x x Clock suspend Entry Active H L x x x x x x x x Power Down Entry Idle Active (5) H H L L x x x x x x x x H L x H x H x x Clock Suspend Exit Active L H x x x x x x x x Any (power down) L L H H x x x x x x x x H L x H x H x x Power Down Exit Deep Power Down Entry Idle H L x x x x L H H L Deep Power Down Exit DPDM L H x x x x x x x x Data write/Output Enable Active H x L x x x x x x x Data write/Output Disable Active H x H x x x x x x x L = Low Level H = High Level Notes: 1. V = Valid 2. CKEn signal is input level when commands are provided. CKEn-1 signal is the input level one clock cycle before the command is issued. X = Don't care 3. These are state of bank designated by BS0, BS1 signals. 4. Device state is full page burst operation. 5. Power Down Mode can not be entered in the burst cycle. When this command asserts in the burst cycle, device state is clock suspend mode. -9- Publication Release Date: March 2002 Revision P11 W987Z6CBN/BG FUNCTIONAL DESCRIPTION 1. Power Up Sequence The default power up state of the mode register is unspecified. The following power up and initialization sequence need to be followed to guarantee the device being preconditioned to each user specific needs. During power up, all VDD and VDDQ pins must be ramp up simultaneously to the specified voltage when the input signals are held in the "NOP" state. The power up voltage must not exceed VDD +0.3V on any of the input pins or VDD supplies. After power up, an initial pause of 200 µS is required followed by a precharge of all banks using the precharge command. To prevent data contention on the DQ bus during power up, it is required that the DQM and CKE pins be held high during the initial pause period. Once all banks have been precharged, the Mode Register Set Command must be issued to initialize the Mode Register. An additional eight Auto Refresh cycles (CBR) are also required before or after programming the Mode Register to ensure proper subsequent operation. 2. Command Function 2-1 Bank Activate command ( RAS =”L”, CAS =”H”, WE =”H”, BS0, BS1=Bank, A0 to A11=Row Address) The Bank Activate command activates the bank designated by the BS (Bank select) signal. Row addresses are latched on A0 to A11 when this command is issued and the cell data is read out of the sense amplifiers. The maximum time that each bank can be held in the active state is specified as tRAS (max). After this command is issued, Read or Write operation can be executed. 2-2 Bank Precharge command ( RAS =”L”, CAS =”H”, WE =”L”, BS0, BS1=Bank, A10=”L”, A0 to A9, A11=Don’t care) The Bank Precharge command percharges the bank designated by BS. The precharged bank is switched from the active state to the idle state. 2-3 Precharge All command ( RAS =”L”, CAS =”H”, WE =”L”, BS0, BS1=Don’t care, A10=”H”, A0 to A9, A11= Don’t care) The Precharge All command precharges all banks simultaneously. Then all banks are switched to the idle state. 2-4 Write command ( RAS =”H”, CAS =”L”, WE =”L”, BS0, BS1=Bank, A10=”L”, A0 to A8=Column Address) The write command performs a Write operation to the bank designated by BS. The write data are latched at rising edge of CLK. The length of the write data (Burst Length) and column access sequence (Addressing Mode) must be programmed in the Mode Register at power-up prior to the Write operation. 2-5 Write with Auto Precharge command ( RAS =”H”, CAS =”L”, WE =”L”, BS0, BS1=Bank, A10=”H”, A0 to A8=Column Address) The Write with Auto Precharge command performs the Precharge operation automatically after the Write operation. This command must not be interrupted by any other commands. 2-6 Read command - 10 - W987Z6CBN/BG ( RAS =”H”, CAS =”L”, WE =”H”, BS0, BS1=Bank, A10=”L”, A0 to A8=Column Address) The Read command performs a Read operation to the bank designated by BS. The length of read data (Burst Length), Addressing Mode and CAS Latency (access time from CAS command in a clock cycle) must be programmed in the Mode Register at power-up prior to the Read operation. 2-7 Read with Auto Precharge command ( RAS =”H”, CAS =”L”, WE =”H”, BS0, BS1=Bank, A10=”H”, A0 to A8=Column Address) The Read with Auto precharge command automatically performs the Precharge operation after the Read operation. This command must not be interrupted by any other command. 2-8 Mode Register Set command ( RAS =”L”, CAS =”L”, WE =”L”, BS0=”L”, BS1=”L”, A0 to A11=Register Data) The Mode Register Set command programs the values of Burst Length, Addressing Mode, CAS latency and Write Mode in the Mode Register. The default values in the Mode Register after power-up are undefined, therefore this command must be issued during the power-up sequence. Also, this command can be issued while all banks are in the idle state. Refer to the table for specific codes. 2-9 Extended Mode Register Set command ( RAS =”L”, CAS =”L”, WE =”L”, BS0=”L”, BS1=”H”, A0 to A11=Register data) The Extended Mode Register Set command programs the values of Driver Strength, Temperature Compensated Self Refresh and Partial Array Self Refresh. The default value of the extended mode register is Full Driver Strength, 70 degrees C and All banks Refreshed 2-10 No-Operation command ( RAS =”H”, CAS =”H”, WE =”H”) The No-Operation command simply performs no operation (same command as Device Deselect). 2-11 Burst Read stop command ( RAS =”H”, CAS =”H”, WE =”L”) The Burst stop command is used to stop the burst operation. This command is only valid during a Burst Read operation. 2-12 Device Deselect command ( CS =”H”) The Device Deselect command disables the command decoder so that the RAS , CAS , WE and Address inputs are ignored. This command is similar to the No-Operation command. 2-13 Auto Refresh command ( RAS =”L”, CAS =”L”, WE =”H”, CKE=”H”, BS0, BS1, A0 to A11=Don’t care) The Auto Refresh command is used to refresh the row address provided by the internal refresh counter. The Refresh operation must be performed 4096 times within 64ms. The next command can be issued after tRC from the end of the Auto Refresh command. When the Auto Refresh command is used, all banks must be in the idle state. - 11 - Publication Release Date: March 2002 Revision P11 W987Z6CBN/BG 2-14 Self Refresh Entry command ( RAS =”L”, CAS =”L”, WE =”H”, CKE=”L”, BS0, BS1, A0 to A11=don’t care) The Self Refresh Entry command is used to enter Self Refresh mode. While the device is in Self Refresh mode, all input and output buffer (except the CKE buffer) are disabled and the Refresh operation is automatically performed. Self Refresh mode is exited by taking CKE “high” (the Self Refresh Exit command). 2-15 Self Refresh Exit command (CKE= ”H” during SDRAM in Self Refresh Mode) This command is used to exit from Self Refresh mode. Any subsequent commands can be issued after tRC from the end of this command. 2-16 Deep Power Down Mode Entry command ( RAS =”H”, CAS =”H”, WE =”L”, CKE=”L”, BS0, BS1, A0 to A11=don’t care) The Deep Power Down Mode Entry command is used to enter Deep Power Down mode. While the device is in Deep Power Down mode, all internal circuits (except the CKE buffer) are disabled in order to 10uA current consumption. 2-17 Deep Power Down Mode Exit command (CKE= ”H” during SDRAM in Deep Power Down Mode) This command is used to exit from Deep Power Down mode. Full initialization is required when the device exits from Deep Power Down Mode. 2-18 Data Write Enable /Disable command (LDQM, UDQM=”L/H”) During a Write cycle, the LDQM or UDQM signal functions as Data Mask and can control every word of the input data. The LDQM signal controls DQ0 to DQ7 and UDQM signal controls DQ8 to DQ15. 3. Read Operation Issuing the Bank Activate command to the idle bank puts it into the active state. When the Read command is issued after tRCD from the Bank Activate command, the data is read out sequentially. The address inputs determine the starting column address for the burst. The initial read data becomes available after CAS latency from the issuing of the Read command. The CAS latency must be set in the Mode Register at power-up. When the Precharge Operation is performed on a bank during a Burst Read and operation, the Burst operation is terminated. When the Read with Auto Precharge command is issued, the Precharge operation is performed automatically after the Read cycle, then the bank is switched to the idle state. This command cannot be interrupted by any other commands. Refer to the diagrams for Read operation. - 12 - W987Z6CBN/BG 4. Write Operation Issuing the Write command after tRCD from the bank activate command. The address inputs determine the starting column address. Data for the first burst write cycle must be applied on the DQ pins on the same clock cycle that the Write Command is issued. The remaining data inputs must be supplied on each subsequent rising clock edge until the burst length is completed. Data supplied to the DQ pins after burst finishes will be ignored. The burst length of the Write data (Burst Length) and Addressing Mode must be set in the Mode Register at power-up. When the Precharge operation is performed in a bank during a Burst Write operation, the Burst operation is terminated. When the Write with Auto Precharge command is issued, the Precharge operation is performed automatically after the Write cycle, then the bank is switched to the idle state, The Write with Auto Precharge command cannot be interrupted by any other command for the entire burst data duration. 5. Precharge The Precharge Command is used to precharge or close a bank that has been activated. The Precharge Command is entered when CS, RAS and WE are low and CAS is high at the rising edge of the clock. The Precharge Command can be used to precharge each bank separately or all banks simultaneously. Three address bits, A10, BS0, and BS1, are used to define which bank(s) is to be precharged when the command is issued. After the Precharge Command is issued, the precharged bank must be reactivated before a new read or write access can be executed. The delay between the Precharge Command and the Activate Command must be greater than or equal to the Precharge time (tRP). 6. Burst Termination When the Precharge command is used for a bank in a Burst cycle, the Burst operation is terminated. When Burst Read cycle is interrupted by the Precharge command, read operation is disabled after clock cycle of ( CAS latency) from the Precharge command. When the Burst Write cycle is interrupted by the Precharge command . the input circuit is reset at the same clock cycle at which the precharge command is issued. In this case, the DQM signal must be asserted “high” during tWR to prevent writing the invalided data to the cell array. When the Burst Read Stop command is issued for the bank in a Burst Read cycle, the Burst Read operation is terminated. The Burst read Stop command is not supported during a write burst operation. - 13 - Publication Release Date: March 2002 Revision P11 W987Z6CBN/BG 7. Interruption Read Interrupted by a Read A Burst Read may be interrupted by another Read Command. When the previous burst is interrupted, the remaining addresses are overridden by the new read address with the full burst length. The data from the first Read Command continues to appear on the outputs until the CAS latency from the interrupting Read Command the is satisfied. Read Interrupted by a Write To interrupt a burst read with a Write Command, DQM may be needed to place the DQs (output drivers) in a high impedance state to avoid data contention on the DQ bus. If a Read Command will issue data on the first and second clocks cycles of the write operation, DQM is needed to insure the DQs are tri-stated. After that point the Write Command will have control of the DQ bus and DQM masking is no longer needed. Write Interrupted by a Write A burst write may be interrupted before completion of the burst by another Write Command. When the previous burst is interrupted, the remaining addresses are overridden by the new address and data will be written into the device until the programmed burst length is satisfied. Write Interrupted by a Read A Read Command will interrupt a burst write operation on the same clock cycle that the Read Command is activated. The DQs must be in the high impedance state at least one cycle before the new read data appears on the outputs to avoid data contention. When the Read Command is activated, any residual data from the burst write cycle will be ignored. 8. Refresh Operation Two types of Refresh operation can be performed on the device: Auto Refresh and Self Refresh. By repeating the Auto Refresh cycle, each bank in turn refreshed automatically. The Refresh operation must be performed 4096 times (rows) within 64ms. The period between the Auto Refresh command and the next command is specified by tRC. The Self Refresh Mode is entered by issuing the Self Refresh Entry Command at the rising edge of the clock. All banks must be idle prior to issuing the Self Refresh Entry Command. Once the command is registered, CKE must be held low to keep the device in Self Refresh mode. When the SDRAM has entered Self Refresh mode all of the external control signals, except CKE, are disabled. The clock is internally disabled during Self Refresh Operation to save power. The device will exit Self Refresh operation after CKE is returned high. A minimum delay time is required when the device exits Self Refresh Operation and before the next command can be issued. This delay is equal to the tRC cycle time plus the Self Refresh exit time. If, during normal operation, AUTO REFRESH cycles are issued in bursts (as opposed to being evenly distributed), a burst of 4,096 AUTO REFRESH cycles should be completed just prior to entering and just after exiting the self refresh mode. - 14 - W987Z6CBN/BG 9. Power Down Mode The Power Down mode is initiated by holding CKE low. All of the receiver circuits except CKE are gated off to reduce the power. The Power Down mode does not perform any refresh operations, therefore the device can not remain in Power Down mode longer than the Refresh period (tREF) of the device. 10. Deep Power Down Mode The Deep Power Down Mode is an operating mode to achieve maximum power reduction by cutting the power of the whole memory array of the devices. Data will not be retained once the device enters Deep Power Down Mode. When the Deep Power Down Mode is exited by asserting CKE high. The following initialization sequence need to be followed to guarantee the device being preconditioned to each user specific needs. 1. Maintain NOP input conditions for a minimum of 200 µS. 2. Issue precharge commands for all banks of the device 3. Issue 8 or more auto refresh commands. 4. Issue a mode register set command to initialize the mode register. 5. Issue an extended mode register set command to initialize the extended mode register. - 15 - Publication Release Date: March 2002 Revision P11 W987Z6CBN/BG 11. Mode Register Set Operation The mode register is programmed by the Mode Register Set command (MRS/EMRS) when all banks are in the idle state. The data to be set in the Mode Register is transferred using the Address pins of A0 to A11 inputs. The combination of BS0, BS1 detains this cycle is MRS or EMRS. 11.1 Mode Register Description The Mode Register designates the operation mode for the read or write cycle. The register is divided into four fields; (1) Burst Length field sets the length of burst data (2) Addressing Mode selection bit to designate the column access sequence in a Burst cycle (3) CAS Latency field sets the access time in clock cycle (4) Single Write Mode selection bit to designate write operation in burst or single write. A0 A1 Burst Length A2 A3 Addressing Mode A4 A5 CAS Latency A2 0 0 0 0 1 1 1 1 A6 A0 A7 "0" (Test Mode) A8 "0" Reserved A0Mode Write A0 A9 A10 "0" A11 A0 "0" BS0 "0" BS1 "0" Reserved Defines it is a MRS cycls A0 A1 A0 A0 0 A0 0 A0 1 A0 1 A0 0 A0 0 A0 1 A0 1 A0 0 1 0 1 0 1 0 1 A0 A3 A0 0 A0 1 A6 0 0 0 0 1 A5 A0 A0 0 A0 0 A0 1 A0 1 A0 0 A0 A9 A0 0 A0 1 BurstA0 Length Sequential A0 Interleave A0 1 A0 1 A0 2 A0 2 A0 4 A0 4 A0 8 A0 8 A0 Reserved A0 Mode Addressing Sequential A0 Interleave A0 A4 0 1 0 1 0 CAS Latency A0 Reserved A0 Reserved A0 2 A0 3 Reserved Single Write Mode Burst read and A0 Burst write Burst read and A0 single write Mode Register Definition - 16 - A0 Reserved FullA0 Page W987Z6CBN/BG • Address sequence of Sequential mode A column access is performed by incrementing the column address input to the device. The address is varied by the Burst Length as the following. Addressing Sequence of Sequential Mode • DATA ACCESS ADDRESS BURST LENGTH Data 0 n 2 words (address bits is A0) Data 1 n+1 No carried from A0 to A1 Data 2 n+2 4 words (address bit A0, A1) Data 3 n+3 Not carried from A1 to A2 Data 4 n+4 Data 5 n+5 8 words(address bits A2, A1 and A0) Data 6 n+6 Not carried from A2 to A3 Data 7 n+7 Addressing sequence of Interleave mode A Column access is started from the inputted column address and is performed by interleaving the address bits in the sequence shown as the following. Address Sequence for Interleave Mode DATA ACCESS ADDRESS Data 0 A8 A7 A6 A5 A4 A3 A2 A1 A0 Data 1 A8 A7 A6 A5 A4 A3 A2 A1 A0 Data 2 A8 A7 A6 A5 A4 A3 A2 A1 A0 Data 3 A8 A7 A6 A5 A4 A3 A2 A1 A0 Data 4 A8 A7 A6 A5 A4 A3 A2 A1 A0 Data 5 A8 A7 A6 A5 A4 A3 A2 A1 A0 Data 6 A8 A7 A6 A5 A4 A3 A2 A1 A0 Data 7 A8 A7 A6 A5 A4 A3 A2 A1 A0 - 17 - BURST LENGTH 2 words 4 words 8 words Publication Release Date: March 2002 Revision P11 W987Z6CBN/BG TIMING WAVEFORMS Command Input Timing tCL tCK tCH VIH CLK VIL tT tCMS tCMH tCMS tCMH tCMS tCMH tCMS tCMH tAS tAH tCMH CS RAS CAS WE A0-A11 BS0, 1 tCKS tCKH tCKS t CKH tCKS CKE - 18 - tCKH tT tCMS W987Z6CBN/BG Timing Waveforms, continued Read Timing Read CAS Latency CLK CS RAS CAS WE A0-A11 BS0, 1 tAC tAC tLZ tHZ tOH tOH Valid Data-Out Valid Data-Out DQ Read Command Burst Length - 19 - Publication Release Date: March 2002 Revision P11 W987Z6CBN/BG Timing Waveforms, continued Control Timing of Input / Output Data Control Timing of Input Data (Word Mask) CLK tCMS tCMH tCMH tCMS DQM tDS tDH tDS Valid Data-in DQ0 -15 tDH tDS Valid Data-in tDH tDS Valid Data-in tDH Valid Data-in (Clock Mask) CLK tCKH tCKS tDH tDS tCKH tCKS CKE tDS DQ0 -15 Valid Data-in tDH tDS Valid Data-in tDH tDS Valid Data-in tDH Valid Data-in Control Timing of Output Data (Output Enable) CLK tCMS tCMH tCMH tCMS DQM tAC tLZ tOH Valid Data-Out DQ0 -15 tAC tHZ tAC tOH tOH Valid Data-Out tAC tOH Valid Data-Out OPEN (Clock Mask) CLK tCKH tCKS tCKH tCKS CKE tAC tOH DQ0 -15 tAC tAC tOH tOH Valid Data-Out Valid Data-Out - 20 - tAC tOH Valid Data-Out W987Z6CBN/BG Timing Waveforms, continued Mode Register Set Cycle tRSC CLK tCMS t CMH tCMS t CMH CS RAS tCMS t CMH tCMS t CMH CAS WE t AS A0-A11 BS0,1 t AH Register set data A0 A1 Burst Length A2 A3 Addressing Mode A4 A5 CAS Latency A2 0 0 0 0 1 1 1 1 A6 A0 A7 "0" A8 "0" A10 "0" A11 A0 "0" BS0 "0" BS1 "0" A0 A3 A0 0 A0 1 (Test Mode) Reserved WriteA0 Mode A9 A0 A0 Reserved A0 A1 A0 A0 A0 0 0 A0 0 1 A0 1 0 A0 1 1 A0 0 0 A0 0 1 A0 1 0 A0 1 1 A6 0 0 0 0 1 A5 A0 A4 A0 0 0 A0 0 1 A0 1 0 A0 1 1 A0 0 0 A0 A9 A0 0 A0 1 - 21 - next command Burst A0 Length Sequential A0 Interleave A0 1 A0 1 A0 A0 2 2 A0 4 A0 4 A0 8 A0 8 A0 Reserved A0 Reserved FullA0 Page A0 Mode Addressing Sequential A0 Interleave A0 CAS Latency A0 Reserved A0 Reserved A0 2 A0 3 Reserved Single Write Mode Burst read and A0 Burst write Burst read and A0single write Publication Release Date: March 2002 Revision P11 W987Z6CBN/BG OPERATING TIMING EXAMPLE Interleaved Bank Read (Burst Length = 4, CAS Latency = 3) (CLK = 100 MHz) 1 0 2 3 4 6 5 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 CLK CS tRC tRC tRC tRC RAS tRAS tRP tRAS tRAS tRP tRP tRAS CAS WE BS0 BS1 tRCD A10 RAa A0-A9, A11 RAa tRCD tRCD RBb CBx RBb CAw tRCD RAc RBd RAc CAy RAe RBd CBz RAe DQM CKE DQ aw0 tRRD Bank #0 Active Bank #1 tAC tAC tAC aw1 aw2 aw3 bx0 Precharge Active bx2 bx3 Active Bank #2 Idle Bank #3 - 22 - cy1 cy2 cy3 tRRD Precharge Read Precharge Read tAC cy0 tRRD tRRD Read bx1 Active Read Active W987Z6CBN/BG Operating Timing Example, contined Interleaved Bank Read (Burst Length = 4, CAS Latency = 3, Autoprecharge) (CLK = 100 MHz) 0 1 2 3 4 6 5 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 CLK CS tRC tRC tRC tRC RAS tRAS tRP tRAS tRAS tRP tRP tRAS CAS WE BS0 BS1 tRCD A10 RAa A0-A9, A11 RAa tRCD tRCD RBb CAw tRCD CBx RBb RAe RBd RAc CAy RAc CBz RBd RAe DQM CKE tAC DQ tRRD Active Bank #0 Bank #1 aw1 aw2 aw3 bx0 Active AP* Active bx1 bx2 bx3 tAC cy0 cy1 tRRD tRRD Read tAC tAC aw0 Read cy2 cy3 dz0 tRRD Read AP* AP* Active Active Read Bank #2 Idle Bank #3 * AP is the internal precharge start timing - 23 - Publication Release Date: March 2002 Revision P11 W987Z6CBN/BG Operating Timing Example, contined Interleaved Bank Read (Burst Length = 8, CAS Latency = 3) (CLK = 100 MHz) 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 CLK CS tRC tRC tRC RAS tRAS tRP tRAS tRP tRAS tRP CAS WE BS0 BS1 tRCD A10 RAa A0-A9, A11 RAa tRCD tRCD RAc RBb CAx RBb CBy RAc CAz DQM CKE tAC DQ tAC ax0 ax1 tRRD Bank #0 Active ax3 ax4 ax5 ax6 by0 by1 by4 by5 by6 by7 tRRD Read Precharge Bank #1 ax2 tAC Precharge Active Read Bank #2 Idle Bank #3 - 24 - Active Read Precharge CZ0 22 23 W987Z6CBN/BG Operating Timing Example, contined Interleaved Bank Read (Burst Length = 8, CAS Latency = 3, Autoprecharge) (CLK = 100 MHz) 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 CLK tRC CS tRC RAS tRAS tRP tRAS tRAS tRP CAS WE BS0 BS1 tRCD tRCD tRCD A10 A0-A9, A11 RBb RAa RAa CAx RAc RBb RAc CBy CAz DQM CKE tCAC tCAC DQ ax0 ax1 ax2 tRRD Bank #0 Active ax3 ax4 ax5 ax7 by0 by1 by4 by5 by6 CZ0 tRRD AP* Read Active Bank #1 ax6 tCAC Active Read Read AP* Bank #2 Idle Bank #3 * AP is the internal precharge start timing - 25 - Publication Release Date: March 2002 Revision P11 W987Z6CBN/BG Operating Timing Example, contined Interleaved Bank Write (Burst Length = 8) (CLK = 100 MHz) 1 0 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 CLK CS tRC RAS tRAS tRAS tRP tRP tRAS CAS tRCD tRCD tRCD WE BS0 BS1 A10 RAa A0-A9, A11 RAa RBb CAx RAc RBb CBy RAc CAz DQM CKE DQ ax0 ax1 ax4 ax5 ax6 ax7 by0 tRRD Bank #0 Active by3 Precharge Write Write Bank #2 Bank #3 by2 by4 by5 by6 by7 CZ0 CZ1 CZ2 tRRD Active Bank #1 by1 Idle - 26 - Active Write Precharge W987Z6CBN/BG Operating Timing Example, contined Interleaved Bank Write (Burst Length = 8, Autoprecharge) (CLK = 100 MHz) 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 CLK CS tRC RAS tRP tRAS tRAS tRAS tRP CAS WE BS0 BS1 tRCD tRCD A10 RAa A0-A9, A11 RAa tRCD RBb CAx RAb CBy RBb CAz RAc DQM CKE ax0 DQ ax1 ax4 ax5 ax6 ax7 by0 by1 tRRD Bank #0 Active by3 by4 by5 by6 by7 CZ0 CZ1 CZ2 tRRD AP* Write Active Bank #1 by2 Write Active Write AP* Bank #2 Idle Bank #3 * AP is the internal precharge start timing - 27 - Publication Release Date: March 2002 Revision P11 W987Z6CBN/BG Operating Timing Example, contined Page Mode Read (Burst Length = 4, CAS Latency = 3) (CLK = 100 MHz) 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 CLK tCCD tCCD tCCD CS tRAS tRP tRAS tRP RAS CAS WE BS0 BS1 tRCD A10 RAa A0-A9, A11 RAa tRCD RBb RBb CAI CBx CAy CAm CBz DQM CKE tAC DQ tAC tAC a0 a1 a2 a3 bx0 bx1 Ay0 tAC Ay1 Ay2 tAC am0 am1 am2 bz0 bz1 tRRD Bank #0 Active Read Active Bank #1 Read Read Read Precharge Read Bank #2 Idle Bank #3 * AP is the internal precharge start timing - 28 - AP* bz2 bz3 23 W987Z6CBN/BG Operating Timing Example, contined Page Mode Read / Write (Burst Length = 8, CAS Latency = 3) (CLK = 100 MHz) 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 CLK CS tRAS tRP RAS CAS WE BS0 BS1 tRCD A10 RAa A0-A9, A11 RAa CAx CAy DQM CKE tAC DQ tWR ax0 Q Q Bank #0 Active ax1 ax3 ax2 Q Q ax5 ax4 Q Q Read ay1 ay0 D D Write ay2 D ay4 ay3 D D Precharge Bank #1 Bank #2 Bank #3 Idle - 29 - Publication Release Date: March 2002 Revision P11 W987Z6CBN/BG Operating Timing Example, contined Auto Precharge Read (Burst Length = 4, CAS Latency = 3) (CLK = 100 MHz) 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 CLK CS tRC tRC RAS tRAS tRP tRAS tRP CAS WE BS0 BS1 tRCD A10 RAa A0-A9, A11 RAa tRCD RAb CAw RAb CAx DQM CKE tAC DQ Bank #0 tAC aw0 Active Read aw1 AP* aw2 aw3 bx0 Active Read Bank #1 Bank #2 Idle Bank #3 * AP is the internal precharge start timing - 30 - bx1 AP* bx2 bx3 23 W987Z6CBN/BG Operating Timing Example, contined Auto Precharge Write (Burst Length = 4) (CLK = 100 MHz) CLK 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 CS tRC tRC RAS tRAS tRP tRAS tRP CAS WE BS0 BS1 tRCD tRCD A10 RAa A0-A9, A11 RAa RAc RAb CAw RAb CAx RAc DQM CKE DQ Bank #0 aw0 Active aw1 Write aw2 bx0 aw3 AP* Active Write bx1 bx2 bx3 AP* Active Bank #1 Bank #2 Idle Bank #3 * AP is the internal precharge start timing - 31 - Publication Release Date: March 2002 Revision P11 W987Z6CBN/BG Operating Timing Example, contined Auto Refresh Cycle (CLK = 100 MHz) 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 CLK tRP tRC tRC CS RAS CAS WE BS0,1 A10 A0-A9, A11 DQM CKE DQ All Banks Prechage Auto Refresh Auto Refresh (Arbitrary Cycle) - 32 - 21 22 23 W987Z6CBN/BG Operating Timing Example, contined Self Refresh Cycle (CLK = 100 MHz) 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 CLK CS tRP RAS CAS WE BS0,1 A10 A0-A9, A11 DQM tCKS tCKS tSB CKE tCKS DQ tRC Self Refresh Cycle All Banks Precharge No Operation Cycle Self Refresh Entry Arbitrary Cycle - 33 - Publication Release Date: March 2002 Revision P11 W987Z6CBN/BG Operating Timing Example, contined Burst Read and Single Write (Burst Length = 4, CAS Latency = 3) (CLK = 100 MHz) 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 CLK CS RAS CAS tRCD WE BS0 BS1 A10 RBa A0-A9, A11 RBa CBv CBw CBx CBy CBz DQM CKE tAC DQ tAC av0 Q Bank #0 Active Bank #1 Bank #2 Bank #3 av1 Q av2 av3 aw0 ax0 ay0 az0 az1 az2 az3 Q Q D D D Q Q Q Q Read Single Write Read Idle - 34 - 22 23 W987Z6CBN/BG Operating Timing Example, contined PowerDown Mode (CLK = 100 MHz) 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 CLK CS RAS CAS WE BS A10 RAa A0-A9 A11 RAa RAa CAa RAa CAx DQM tSB tSB CKE tCKS tCKS tCKS DQ ax0 Active ax1 ax2 NOP Read tCKS ax3 Precharge NOPActive Precharge Standby Power Down mode Active Standby Power Down mode Note: The PowerDown Mode is entered by asserting CKE "low". All Input/Output buffers (except CKE buffers) are turned off in the PowerDown mode. When CKE goes high, command input must be No operation at next CLK rising edge. - 35 - Publication Release Date: March 2002 Revision P11 W987Z6CBN/BG Operating Timing Example, contined Autoprecharge Timing (Read Cycle) 0 1 Read AP 2 3 4 5 6 7 8 9 10 11 (1) CAS Latency=2 ( a ) burst length = 1 Command DQ Act tRP Q0 ( b ) burst length = 2 Command Read AP Act tRP DQ Q0 Q1 ( c ) burst length = 4 Command Read AP Act tRP DQ Q0 Q1 Q2 Q3 Q0 Q1 Q2 Q3 ( d ) burst length = 8 Command Read AP DQ Q4 Q5 Q6 Act tRP Q7 (2) CAS Latency=3 ( a ) burst length = 1 Command Read AP Act tRP Q0 DQ ( b ) burst length = 2 Command Read AP Act tRP Q0 DQ ( c ) burst length = 4 Command Read Q1 AP Act tRP Q0 DQ Q1 Q2 Q3 ( d ) burst length = 8 Command Read AP Act tRP Q0 DQ Q1 Q2 Q3 Q4 Q5 Q6 Q7 Note ) Read represents the Read with Auto precharge command. AP represents the start of internal precharging. Act represents the Bank Activate command. When the Auto precharge command is asserted, the period from Bank Activate command to the start of internal precgarging must be at least tRAS(min). - 36 - W987Z6CBN/BG Operating Timing Example, contined Autoprecharge Timing (Write Cycle) 0 1 2 3 4 5 6 7 8 9 10 11 (1) CAS Latency=2 ( a ) burst length = 1 Command Write AP Act tWR DQ tRP D0 ( b ) burst length = 2 Command Write AP Act tWR DQ D0 tRP D1 ( c ) burst length = 4 Command Write AP Act tWR DQ D0 D1 D2 tRP D3 ( d ) burst length = 8 Command Write AP tWR DQ D0 D1 D2 D3 D4 D5 D6 Act tRP D7 (2) CAS Latency=3 ( a ) burst length = 1 Command Write AP Act tWR DQ ( b ) burst length = 2 Command tRP D0 Write AP Act tWR DQ D0 tRP D1 ( c ) burst length = 4 Command Write AP Act tWR DQ D0 D1 D2 tRP D3 ( d ) burst length = 8 Command Write AP tWR DQ D0 D1 D2 D3 D4 D5 D6 Act tRP D7 Note ) Write represents the Write with Auto precharge command. AP represents the start of internal precharging. Act represents the Bank Activate command. When the Auto precharge command is asserted, the period from Bank Activate command to the start of internal precgarging must be at least tRAS (min). - 37 - Publication Release Date: March 2002 Revision P11 W987Z6CBN/BG Operating Timing Example, contined Timing Chart of Read to Write Cycle In the case of Burst Length = 4 (1) CAS Latency=2 0 1 2 3 4 5 D1 D2 D3 D0 D1 D2 D1 D2 D3 D1 D2 6 7 8 9 10 11 9 10 11 Read Write ( a ) Command DQM DQ D0 Read ( b ) Command Write DQM DQ D3 (2) CAS Latency=3 Read Write ( a ) Command DQM D0 DQ Read ( b ) Command Write DQM D0 DQ D3 Note: The Output data must be masked by DQM to avoid I/O conflict Timing Chart of Write to Read Cycle In the case of Burst Length=4 0 1 2 3 4 5 6 7 8 Q0 Q1 Q2 Q3 Q0 Q1 Q2 Q3 Q0 Q1 Q2 Q3 Q0 Q1 Q2 (1) CAS Latency=2 ( a ) Command Write Read DQM DQ ( b ) Command D0 Read Write DQM DQ D0 D1 (2) CAS Latency=3 ( a ) Command Write Read DQM DQ ( b ) Command D0 Write Read DQM DQ D0 D1 Operating Timing Example, contined - 38 - Q3 W987Z6CBN/BG Timing Chart of Burst Stop Cycle (Burst Stop Command) 0 1 2 3 4 5 6 7 8 9 10 11 10 11 (1) Read cycle ( a ) CAS latency =2 Read Command BST Q0 DQ Q1 Q2 Q3 Q4 ( b )CAS latency = 3 Read Command BST Q0 DQ Q1 Q2 Q3 Q4 (2) Write cycle Write Command Q0 DQ BST Q1 Q2 Note: Q3 Q4 BST represents the Burst stop command Timing Chart of Burst Stop Cycle (Precharge Command) In the case of Burst Lenght = 8 0 1 2 3 4 5 6 7 8 9 (1) Read cycle ( a )CAS latency =2 Command Read PRCG Q0 DQ ( b )CAS latency = 3 Command Q1 Q2 Q3 Read Q4 PRCG Q0 DQ DQ Q1 Q2 Q3 Q4 (2) Write cycle ( a ) CAS latency =2 PRCG Write tWR Command DQM DQ ( b )CAS latency = 3 D0 D1 D2 D3 D4 Write PRCG tWR Command DQM DQ D0 D1 D2 D3 D4 - 39 - Publication Release Date: March 2002 Revision P11 W987Z6CBN/BG Operating Timing Example, contined CKE/DQM Input Timing (Write Cycle) CLK cycle No. 1 2 3 D1 D2 D3 4 5 6 7 External CLK Internal CKE DQM DQ D5 DQM MASK D6 CKE MASK (1) CLK cycle No. 1 2 3 D1 D2 D3 4 5 6 7 External CLK Internal CKE DQM DQ D5 DQM MASK D6 CKE MASK (2) CLK cycle No. 1 2 3 D1 D2 D3 4 5 6 7 External CLK Internal CKE DQM DQ D4 CKE MASK (3) - 40 - D5 D6 W987Z6CBN/BG Operating Timing Example, contined CKE/DQM Input Timing (Read Cycle) CLK cycle No. 1 2 3 4 Q1 Q2 Q3 Q4 5 6 7 External CLK Internal CKE DQM DQ Q6 Open Open (1) CLK cycle No. 1 2 3 Q1 Q2 Q3 4 5 6 7 External CLK Internal CKE DQM DQ Q4 Q6 Open (2) CLK cycle No. 1 2 Q1 Q2 3 4 5 6 7 Q4 Q5 Q6 External CLK Internal CKE DQM DQ Q3 (3) - 41 - Publication Release Date: March 2002 Revision P11 W987Z6CBN/BG Operating Timing Example, contined Self Refresh/Power Down Mode Exit Timing Asynchronous Control Input Buffer turn on time ( Power down mode exit time ) is specified by tCKS(min) + tCK(min) A ) tCK < tCKS(min)+tCK(min) tCK CLK CKE tCKS(min)+tCK(min) NOP Command Command Input Buffer Enable B) tCK >= tCKS(min) + tCK (min) tCK CLK tCKS(min)+tCK(min) CKE Command Command Input Buffer Enable Note ) All Input Buffer(Include CLK Buffer) are turned off in the Power Down mode and Self Refresh mode NOP Command Represents the No-Operation command Represents one command - 42 - W987Z6CBN/BG DEEP POWER DOWN ENTRY TIMING CLK CKE CS RAS CAS WE tR P Precharge if needed D eep Pow er D ow n entry - 43 - Publication Release Date: March 2002 Revision P11 W987Z6CBN/BG DEEP POWER DOWN EXIT TIMING CLK CKE CS RAS CAS WE 200µs D eep Pow er D ow n exit tR P A llbanks precharge tR C A uto refresh A uto refresh - 44 - M ode R egister Set Extended M ode R egister Set N ew C om m and A ccepted H ere W987Z6CBN/BG PACKAGE DIMENSION FBGA 54 Balls (8X9X1.2 mm^3, Ø=0.40mm) - 45 - Publication Release Date: March 2002 Revision P11 W987Z6CBN/BG REVISION HISTORY VERSION Preliminary datasheet Version P10 Preliminary datasheet Version P11 DATE 03/15/2002 03/262002 PAGE DESCRIPTION 1 Modify Self Refresh Current to 400uA 6 Modify DC Current Value Icc1~Icc7 6 Modify DC Current value Icc2 and Icc3 1,5,6 Modify VDD Range 2.7v ~ 3.6v - 46 - W987Z6CBN/BG Headquarters Winbond Electronics (H.K.) Ltd. Unit 9-15, 22F, Millennium City, No. 4, Creation Rd. III, No. 378 Kwun Tong Rd; Science-Based Industrial Park, Kowloon, Hong Kong Hsinchu, Taiwan TEL: 852 -27513100 TEL: 886-3-5770066 FAX: 852 -27552064 FAX: 886 -3-5792766 http://www.winbond.com.tw/ Voice & Fax-on-demand: 886 -2-27197006 Winbond Electronics North America Corp. Winbond Memory Lab. Winbond Microelectronics Corp. Winbond Systems Lab. 2727 N. First Street, San Jose, CA 95134, U.S.A. TEL: 408-9436666 FAX: 408-5441798 Taipei Office 11F, No. 115, Sec. 3, Min-Sheng East Rd., Taipei, Taiwan TEL: 886-2-27190505 FAX: 886 -2-27197502 Note: All data and specifications are subject to change without notice. - 47 - Publication Release Date: March 2002 Revision P11