SN74HC595-EP www.ti.com SCLS719 – FEBRUARY 2010 8-BIT SHIFT REGISTERS WITH 3-STATE OUTPUT REGISTERS Check for Samples: SN74HC595-EP FEATURES 1 • • • • • • • • 8-Bit Serial-In, Parallel-Out Shift Wide Operating Voltage Range of 2 V to 6 V High-Current 3-State Outputs Can Drive Up To 15 LSTTL Loads Low Power Consumption: 80-mA (Max) ICC tpd = 13 ns (Typ) ±6-mA Output Drive at 5 V Low Input Current: 1 mA (Max) Shift Register Has Direct Clear PW PACKAGE (TOP VIEW) QB QC QD QE QF QG QH GND 1 16 2 15 3 14 4 13 5 12 6 11 7 10 8 9 VCC QA SER OE RCLK SRCLK SRCLR QH′ SUPPORTS DEFENSE, AEROSPACE, AND MEDICAL APPLICATIONS • • • • • • • (1) Controlled Baseline One Assembly/Test Site One Fabrication Site Available in Military (–55°C/125°C) Temperature Range (1) Extended Product Life Cycle Extended Product-Change Notification Product Traceability Additional temperature ranges available - contact factory DESCRIPTION The SN74HC595 contains an 8-bit serial-in, parallel-out shift register that feeds an 8-bit D-type storage register. The storage register has parallel 3-state outputs. Separate clocks are provided for both the shift and storage register. The shift register has a direct overriding clear (SRCLR) input, serial (SER) input, and serial outputs for cascading. When the output-enable (OE) input is high, the outputs are in the high-impedance state. Both the shift register clock (SRCLK) and storage register clock (RCLK) are positive-edge triggered. If both clocks are connected together, the shift register always is one clock pulse ahead of the storage register. 1 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2010, Texas Instruments Incorporated SN74HC595-EP SCLS719 – FEBRUARY 2010 www.ti.com ORDERING INFORMATION (1) PACKAGE (2) TA –55°C to 125°C (1) (2) TSSOP – PW Reel of 2000 ORDERABLE PART NUMBER TOP-SIDE MARKING SN74HC595MPWREP HC595EP For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI web site at www.ti.com. Package drawings, thermal data, and symbolization are available at www.ti.com/packaging. Table 1. FUNCTION TABLE INPUTS 2 FUNCTION SER SRCLK SRCLR RCLK OE X X X X H Outputs QA−QH are disabled. X X X X L Outputs QA−QH are enabled. X X L X X Shift register is cleared. L ↑ H X X First stage of the shift register goes low. Other stages store the data of previous stage, respectively. H ↑ H X X First stage of the shift register goes high. Other stages store the data of previous stage, respectively. X X X ↑ X Shift-register data is stored in the storage register. Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s): SN74HC595-EP SN74HC595-EP www.ti.com SCLS719 – FEBRUARY 2010 LOGIC DIAGRAM (POSITIVE LOGIC) OE RCLK SRCLR SRCLK SER 13 12 10 11 14 1D C1 R 3R C3 3S 15 2S 2R C2 R 3R C3 3S 1 2S 2R C2 R 3R C3 3S 2 2S 2R C2 R 3R C3 3S 3 2S 2R C2 R 3R C3 3S 4 2S 2R C2 R 3R C3 3S 5 2S 2R C2 R 3R C3 3S 6 2S 2R C2 R 3R C3 3S 7 QA QB QC 9 QD QE QF QG QH QH′ Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s): SN74HC595-EP 3 SN74HC595-EP SCLS719 – FEBRUARY 2010 www.ti.com TIMING DIAGRAM SRCLK SER RCLK SRCLR OE QA QB QC QD QE QF QG QH QH’ NOTE: implies that the output is in 3-State mode. ABSOLUTE MAXIMUM RATINGS (1) over operating free-air temperature range (unless otherwise noted) VCC Supply voltage range IIK Input clamp current (2) −0.5 V to 7 V (2) IOK Output clamp current IO Continuous output current VI < 0 or VI > VCC ±20 mA VO < 0 or VO > VCC ±20 mA VO = 0 to VCC ±35 mA Continuous current through VCC or GND ±70 mA qJA Package thermal impedance (3) 108°C/W Tstg Storage temperature range (1) (2) (3) 4 −65°C to 150°C Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. The input and output voltage ratings may be exceeded if the input and output current ratings are observed. The package thermal impedance is calculated in accordance with JESD 51-7. Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s): SN74HC595-EP SN74HC595-EP www.ti.com SCLS719 – FEBRUARY 2010 RECOMMENDED OPERATING CONDITIONS (1) MIN VCC Supply voltage VCC = 2 V VIH NOM 2 High-level input voltage MAX 5 VCC = 4.5 V 3.15 V 4.2 VCC = 2 V Low-level input voltage 0.5 VCC = 4.5 V 1.35 VCC = 6 V VI Input voltage VO Output voltage 0 0 Input transition rise/fall time (2) TA (1) (2) V 1.8 VCC = 2 V Δt/Δv V 1.5 VCC = 6 V VIL UNIT 6 VCC V VCC V 1000 VCC = 4.5 V 500 VCC = 6 V 400 Operating free-air temperature –55 125 ns °C All unused inputs of the device must be held at VCC or GND to ensure proper device operation. See the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004. If this device is used in the threshold region (from VILmax = 0.5 V to VIHmin = 1.5 V), there is a potential to go into the wrong state from induced grounding, causing double clocking. Operating with the inputs at tt = 1000 ns and VCC = 2 V does not damage the device; however, functionally, the CLK inputs are not ensured while in the shift, count, or toggle operating modes. ELECTRICAL CHARACTERISTICS over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS IOH = −20 mA VOH VI = VIH or VIL QH′, IOH = −4 mA QA−QH, IOH = −6 mA QH′, IOH = −5.2 mA QA−QH, IOH = −7.8 mA IOL = 20 mA VOL VI = VIH or VIL QH′, IOL = 4 mA QA−QH, IOL = 6 mA QH′, IOL = 5.2 mA QA−QH, IOL = 7.8 mA II VCC TA = 25°C TA = –55°C to 125°C MIN TYP 2V 1.9 1.998 1.9 4.5 V 4.4 4.499 4.4 6V 5.9 5.999 5.9 3.98 4.3 3.7 3.98 4.3 3.7 5.48 5.8 5.2 5.48 5.8 4.5 V 6V MAX MIN MAX V 5.2 2V 0.002 0.1 0.1 4.5 V 0.001 0.1 0.1 6V 0.001 0.1 0.1 0.17 0.26 0.4 0.17 0.26 0.4 0.15 0.26 0.4 0.15 0.26 0.4 4.5 V 6V UNIT V VI = VCC or 0 6V ±0.1 ±100 ±1000 nA IOZ VO = VCC or 0, QA−QH 6V ±0.01 ±0.5 ±10 µA ICC VI = VCC or 0, IO = 0 6V 8 160 µA 10 10 pF Ci 2V to 6 V 3 Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s): SN74HC595-EP 5 SN74HC595-EP SCLS719 – FEBRUARY 2010 www.ti.com TIMING REQUIREMENTS over operating free-air temperature range (unless otherwise noted) VCC fclock Clock frequency TA = 25°C MIN tw Pulse duration SRCLR low SER before SRCLK↑ SRCLK↑ before RCLK↑ (1) tsu Setup time SRCLR low before RCLK↑ SRCLR high (inactive) before SRCLK↑ th (1) 6 Hold time, SER after SRCLK↑ MIN MAX 2V 6 4.2 4.5 V 31 21 6V SRCLK or RCLK high or low TA = –55°C to 125°C MAX 36 UNIT MHz 25 2V 80 120 4.5 V 16 24 6V 14 20 2V 80 120 4.5 V 16 24 6V 14 20 2V 100 150 4.5 V 20 30 6V 17 25 2V 75 113 4.5 V 15 23 6V 13 19 2V 50 75 4.5 V 10 15 6V 9 13 2V 50 75 4.5 V 10 15 6V 9 13 2V 0 0 4.5 V 0 0 6V 0 0 ns ns ns This setup time allows the storage register to receive stable data from the shift register. The clocks can be tied together, in which case the shift register is one clock pulse ahead of the storage register. Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s): SN74HC595-EP SN74HC595-EP www.ti.com SCLS719 – FEBRUARY 2010 SWITCHING CHARACTERISTICS over recommended operating free-air temperature range, CL = 50 pF (unless otherwise noted) PARAMETER FROM (INPUT) TO (OUTPUT) fmax SRCLK QH′ tpd QA−QH RCLK tPHL ten tdis SRCLR QH′ QA−QH OE QA−QH OE QA−QH tt QH′ VCC TA = 25°C MIN TYP TA = –55°C to 125°C MAX MIN 2V 6 26 4.2 4.5 V 31 38 21 6V 36 42 MAX UNIT MHz 25 2V 50 160 240 4.5 V 17 32 48 6V 14 27 41 2V 50 150 225 4.5 V 17 30 45 6V 14 26 38 2V 51 175 261 4.5 V 18 35 52 6V 15 30 44 2V 40 150 255 4.5 V 15 30 45 6V 13 26 38 2V 42 200 300 4.5 V 23 40 60 6V 20 34 51 2V 28 60 90 4.5 V 8 12 18 6V 6 10 15 2V 28 75 110 4.5 V 8 15 22 6V 6 13 19 ns ns ns ns ns SWITCHING CHARACTERISTICS over recommended operating free-air temperature range, CL = 150 pF (unless otherwise noted) PARAMETER FROM (INPUT) TO (OUTPUT) VCC tpd RCLK QA−QH ten QA−QH OE QA−QH tt TA = 25°C MIN TA = –55°C to 125°C TYP MAX MIN MAX 2V 60 200 300 4.5 V 22 40 60 6V 19 34 51 2V 70 200 298 4.5 V 23 40 60 6V 19 34 51 2V 45 210 315 4.5 V 17 42 63 6V 13 36 53 UNIT ns ns ns OPERATING CHARACTERISTICS TA = 25°C PARAMETER Cpd Power dissipation capacitance TEST CONDITIONS No load TYP UNIT 400 pF Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s): SN74HC595-EP 7 SN74HC595-EP SCLS719 – FEBRUARY 2010 www.ti.com PARAMETER MEASUREMENT INFORMATION VCC S1 Test Point From Output Under Test PARAMETER RL CL (see Note A) tPZH ten 1 kΩ tPZL tPHZ tdis S2 RL tPLZ 1 kΩ Reference Input VCC Data Input VCC 50% 10% 50% VCC 0V In-Phase Output 50% 10% tPHL 90% 90% tr tPHL Out-ofPhase Output 90% 50% 10% tf Closed Closed Open Open Open VCC th 90% 90% VCC 50% 10% 0 V tf Output Control (Low-Level Enabling) VCC 50% 50% 0V tPZL VOH 50% 10% V OL tf tPLZ Output Waveform 1 (See Note B) 90% tr VOH VOL VOLTAGE WAVEFORMS PROPAGATION DELAY AND OUTPUT TRANSITION TIMES ≈VCC ≈VCC 50% 10% tPZH tPLH 50% 10% Open VOLTAGE WAVEFORMS SETUP AND HOLD AND INPUT RISE AND FALL TIMES 50% tPLH Open tr VOLTAGE WAVEFORMS PULSE DURATIONS 50% Closed 0V 0V Input Closed tsu 0V 50% Open 50% 50% tw Low-Level Pulse S2 50 pF or 150 pF LOAD CIRCUIT 50% S1 50 pF tpd or tt High-Level Pulse CL 50 pF or 150 pF VOL tPHZ Output Waveform 2 (See Note B) 50% 90% VOH ≈0 V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES FOR 3-STATE OUTPUTS NOTES: A. CL includes probe and test-fixture capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control. C. Phase relationships between waveforms were chosen arbitrarily. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tr = 6 ns, tf = 6 ns. D. For clock inputs, fmax is measured when the input duty cycle is 50%. E. The outputs are measured one at a time, with one input transition per measurement. F. t PLZ and tPHZ are the same as tdis. G. tPZL and tPZH are the same as ten. H. tPLH and tPHL are the same as tpd. Figure 1. Load Circuit and Voltage Waveforms 8 Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s): SN74HC595-EP PACKAGE OPTION ADDENDUM www.ti.com 22-Mar-2010 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing SN74HC595MPWREP PREVIEW TSSOP PW Pins Package Eco Plan (2) Qty 16 2000 TBD Lead/Ball Finish Call TI MSL Peak Temp (3) Call TI (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. OTHER QUALIFIED VERSIONS OF SN74HC595-EP : SN74HC595 • Catalog: • Military: SN54HC595 NOTE: Qualified Version Definitions: - TI's standard catalog product • Catalog • Military - QML certified for Military and Defense Applications Addendum-Page 1 MECHANICAL DATA MTSS001C – JANUARY 1995 – REVISED FEBRUARY 1999 PW (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE 14 PINS SHOWN 0,30 0,19 0,65 14 0,10 M 8 0,15 NOM 4,50 4,30 6,60 6,20 Gage Plane 0,25 1 7 0°– 8° A 0,75 0,50 Seating Plane 0,15 0,05 1,20 MAX PINS ** 0,10 8 14 16 20 24 28 A MAX 3,10 5,10 5,10 6,60 7,90 9,80 A MIN 2,90 4,90 4,90 6,40 7,70 9,60 DIM 4040064/F 01/97 NOTES: A. B. C. D. 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