XILINX XA3S1400A

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XA Spartan-3A Automotive
FPGA Family Data Sheet
DS681 (v1.1) February 3, 2009
Product Specification
Summary
The Xilinx Automotive (XA) Spartan®-3A family of FPGAs
solves the design challenges in most high-volume,
cost-sensitive, I/O-intensive automotive electronics
applications. The four-member family offers densities
ranging from 200,000 to 1.4 million system gates, as shown
in Table 1.
♦
♦
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♦
•
XA devices are available in both extended-temperature
Q-Grade (–40°C to +125°C TJ) and I-Grade (–40°C to
+100°C TJ) and are qualified to the industry recognized
AEC-Q100 standard.
The XA Spartan-3A family builds on the success of the
earlier XA Spartan-3E and XA Spartan-3 FPGA families by
increasing the amount of I/O per logic, significantly reducing
the cost per I/O. New features improve system performance
and reduce the cost of configuration. These XA Spartan-3A
family enhancements, combined with proven 90 nm process
technology, deliver more functionality and bandwidth per
dollar than ever before, setting the new standard in the
programmable logic industry.
Because of their exceptionally low cost, XA Spartan-3A
FPGAs are ideally suited to a wide range of automotive
electronics applications, including infotainment, driver
information, and driver assistance modules.
♦
♦
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•
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•
Features
•
Very low cost, high-performance logic solution for
high-volume, cost-conscious applications
•
Dual-range VCCAUX supply simplifies 3.3V-only design
•
Suspend, Hibernate modes reduce system power
•
Multi-voltage, multi-standard SelectIO™ interface pins
Up to 375 I/O pins or 165 differential signal pairs
LVCMOS, LVTTL, HSTL, and SSTL single-ended I/O
3.3V, 2.5V, 1.8V, 1.5V, and 1.2V signaling
Selectable output drive, up to 24 mA per pin
QUIETIO standard reduces I/O switching noise
Full 3.3V ± 10% compatibility and hot swap compliance
640+ Mb/s data transfer rate per differential I/O
Densities up to 25,344 logic cells, including optional shift
register or distributed RAM support
Efficient wide multiplexers, wide logic
Fast look-ahead carry logic
Enhanced 18 x 18 multipliers with optional pipeline
IEEE 1149.1/1532 JTAG programming/debug port
Hierarchical SelectRAM™ memory architecture
Up to 576 Kbits of fast block RAM with byte write enables
for processor applications
Up to 176 Kbits of efficient distributed RAM
Up to eight Digital Clock Managers (DCMs)
♦
♦
♦
♦
Clock skew elimination (delay locked loop)
Frequency synthesis, multiplication, division
High-resolution phase shifting
Wide frequency range (5 MHz to over 320 MHz)
•
Eight low-skew global clock networks, eight additional
clocks per half device, plus abundant low-skew routing
•
Configuration interface to industry-standard PROMs
♦
♦
♦
The XA Spartan-3A family is a superior alternative to mask
programmed ASICs. FPGAs avoid the high initial mask set
costs and lengthy development cycles, while also permitting
design upgrades in the field with no hardware replacement
necessary because of its inherent programmability, an
impossibility with conventional ASICs and ASSPs with their
inflexible architecture.
♦
♦
♦
♦
♦
♦
♦
Abundant, flexible logic resources
♦
Introduction
LVDS, RSDS, mini-LVDS, HSTL/SSTL differential I/O
with integrated differential termination resistors
Enhanced Double Data Rate (DDR) support
DDR/DDR2 SDRAM support up to 266 Mb/s
Fully compliant 32-/64-bit, 33 MHz PCI™ technology
support
Low-cost, space-saving SPI serial Flash PROM
x8 or x8/x16 parallel NOR Flash PROM
Unique Device DNA identifier for design authentication
•
Complete Xilinx ISE® and WebPACK™ software
support plus Spartan-3A Starter Kit
•
MicroBlaze™ and PicoBlaze™ embedded processor
cores
•
BGA packaging, Pb-free ONLY
♦
Common footprints support easy density migration
Refer to the Spartan-3A FPGA Family Data Sheet (DS529)
for a full product description, AC and DC specifications, and
package pinout descriptions. Any values shown specifically
in this XA Spartan-3A Automotive FPGA Family data sheet
override those shown in DS529.
For information regarding reliability qualification, refer to
RPT103 (Xilinx Spartan-3A Family Automotive Qualification
Report) and RPT070 (Spartan-3A Commercial Qualification
Report).
© 2008–2009 Xilinx, Inc. XILINX, the Xilinx logo, Virtex, Spartan, ISE, and other designated brands included herein are trademarks of Xilinx in the United States and other
countries. PCI, PCIe, and PCI Express are trademarks of PCI-SIG and used under license. All other trademarks are the property of their respective owners.
DS681 (v1.1) February 3, 2009
Product Specification
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Key Feature Differences from Commercial XC Devices
•
AEC-Q100 device qualification and full production part
approval process (PPAP) documentation support
available in both extended temperature I- and
Q-Grades
•
Guaranteed to meet full electrical specification over the
TJ = –40°C to +125°C temperature range (Q-Grade)
•
XA Spartan-3A devices are available in the -4 speed
grade only
•
PCI-66 is not supported in the XA Spartan-3A FPGA
product line
•
Platform Flash is not supported within the XA family
•
XA Spartan-3A devices are available in Pb-Free
packaging only.
•
MultiBoot is not supported in XA versions of this
product.
•
The XA Spartan-3A device must be power cycled prior
to reconfiguration.
Table 1: Summary of XA Spartan-3A FPGA Attributes
CLB Array
(One CLB = Four Slices)
Device
XA3S200A
XA3S400A
XA3S700A
XA3S1400A
System Equivalent
Gates Logic Cells Rows Columns
Total
CLBs
200K
400K
700K
1400K
448 1,792
896 3,584
1,472 5,888
2,816 11,264
4,032
8,064
13,248
25,344
32
40
48
72
16
24
32
40
Total
Slices
Distributed
RAM bits(1)
Block
RAM
bits(1)
28K
56K
92K
176K
288K
360K
360K
576K
Maximum
Dedicated
Maximum Differential
Multipliers DCMs User I/O
I/O Pairs
16
20
20
32
4
4
8
8
195
311
372
375
90
142
165
165
Notes:
1. By convention, one Kb is equivalent to 1,024 bits.
Architectural Overview
•
The XA Spartan-3A family architecture consists of five
fundamental programmable functional elements:
•
Configurable Logic Blocks (CLBs) contain flexible
Look-Up Tables (LUTs) that implement logic plus
storage elements used as flip-flops or latches. CLBs
perform a wide variety of logical functions as well as
store data.
•
Input/Output Blocks (IOBs) control the flow of data
between the I/O pins and the internal logic of the
device. IOBs support bidirectional data flow plus
3-state operation. Supports a variety of signal
standards, including several high-performance
differential standards. Double Data-Rate (DDR)
registers are included.
•
Block RAM provides data storage in the form of
18-Kbit dual-port blocks.
•
Multiplier Blocks accept two 18-bit binary numbers as
inputs and calculate the product.
2
Digital Clock Manager (DCM) Blocks provide
self-calibrating, fully digital solutions for distributing,
delaying, multiplying, dividing, and phase-shifting clock
signals.These elements are organized as shown in
Figure 1. A dual ring of staggered IOBs surrounds a
regular array of CLBs. Each device has two columns of
block RAM. Each RAM column consists of several
18-Kbit RAM blocks. Each block RAM is associated
with a dedicated multiplier. The DCMs are positioned in
the center with two at the top and two at the bottom of
the device. The XA3S700A and XA3S1400A add two
DCMs in the middle of the two columns of block RAM
and multipliers. The XA Spartan-3A family features a
rich network of routing that interconnect all five
functional elements, transmitting signals among them.
Each functional element has an associated switch
matrix that permits multiple connections to the routing.
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DS681 (v1.1) February 3, 2009
Product Specification
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IOBs
DCM
Multiplier
Block RAM
CLB
IOBs
OBs
IOBs
IOBs
CLBs
DCM
Block RAM / Multiplier
DCM
IOBs
DS312-1_01_032606
Notes:
1.
The XA3S700A and XA3S1400A have two additional DCMs on both the left and right sides as indicated by the
dashed lines.
Figure 1: XA Spartan-3A Family Architecture
Configuration
XA Spartan-3A FPGAs are programmed by loading
configuration data into robust, reprogrammable, static
CMOS configuration latches (CCLs) that collectively control
all functional elements and routing resources. The FPGA’s
configuration data is stored externally in a SPI serial Flash
or some other non-volatile medium, either on or off the
board. After applying power, the configuration data is written
to the FPGA using any of five different modes:
•
Serial Peripheral Interface (SPI) from an
industry-standard SPI serial Flash
DS681 (v1.1) February 3, 2009
Product Specification
•
Byte Peripheral Interface (BPI) Up from an
industry-standard x8 or x8/x16 parallel NOR Flash
•
Slave Serial, typically downloaded from a processor
•
Slave Parallel, typically downloaded from a processor
•
Boundary Scan (JTAG), typically downloaded from a
processor or system tester
Additionally, each XA Spartan-3A FPGA contains a unique,
factory-programmed Device DNA identifier useful for
tracking purposes, anti-cloning designs, or IP protection.
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I/O Capabilities
•
The XA Spartan-3A FPGA SelectIO interface supports
many popular single-ended and differential standards.
Table 2 shows the number of user I/Os as well as the
number of differential I/O pairs available for each
device/package combination. Some of the user I/Os are
unidirectional input-only pins as indicated in Table 2.
SSTL I and II at 1.8V, 2.5V, and 3.3V, commonly used
for memory applications
XA Spartan-3A FPGAs support the following differential
standards:
•
XA Spartan-3A FPGAs support the following single-ended
standards:
LVDS, mini-LVDS, RSDS, and PPDS I/O at 2.5V or
3.3V
•
Bus LVDS I/O at 2.5V
•
3.3V low-voltage TTL (LVTTL)
•
TMDS I/O at 3.3V
•
Low-voltage CMOS (LVCMOS) at 3.3V, 2.5V, 1.8V,
1.5V, or 1.2V
•
Differential HSTL and SSTL I/O
•
LVPECL inputs at 2.5V or 3.3V
•
3.3V PCI at 33 MHz
•
HSTL I, II, and III at 1.5V and 1.8V, commonly used in
memory applications
Table 2: Available User I/Os and Differential (Diff) I/O Pairs
Device
FTG256
FGG400
FGG484
User
Diff
User
Diff
User
Diff
XA3S200A
195
(35)
90
(50)
-
-
-
-
XA3S400A
195
(35)
90
(50)
311
(63)
142
(78)
-
-
XA3S700A
-
-
311
(63)
142
(78)
372
(84)
165
(93)
XA3S1400A
-
-
-
-
375
(87)
165
(93)
Notes:
1.
4
The number shown in bold indicates the maximum number of I/O and input-only
pins. The number shown in (italics) indicates the number of input-only pins. The
differential (Diff) input-only pin count includes both differential pairs on input-only
pins and differential pairs on I/O pins within I/O banks that are restricted to
differential inputs.
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DS681 (v1.1) February 3, 2009
Product Specification
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Production Status
Table 3 indicates the production status of each XA
Spartan-3A FPGA by temperature range and speed grade.
The table also lists the earliest speed file version required
for creating a production configuration bitstream. Later
versions are also supported.
Part Number
Table 3: XA Spartan-3A FPGA Family Production Status (Production Speed File)
Temperature Range
I-Grade
Q-Grade
Speed Grade
Standard (–4)
Standard (–4)
XA3S200A
Production
(v1.41)
Production
(v1.41)
XA3S400A
Production
(v1.41)
Production
(v1.41)
XA3S700A
Production
(v1.41)
Production
(v1.41)
XA3S1400A
Production
(v1.41)
Production
(v1.41)
Package Marking
Figure 2 shows the top marking for Spartan-3A FPGAs in BGA packages. The markings for the BGA packages are nearly
identical to those for the quad-flat packages, except that the marking is rotated with respect to the ball A1 indicator.
Mask Revision Code
BGA Ball A1
R
SPARTAN
Device Type
Package
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XA3S200ATM
FTG256AGQ0625
D1234567A
4I
Fabrication Code
Process Code
Date Code
Lot Code
Speed Grade
Temperature Range
DS529-1_02_021206
Figure 2: XA Spartan-3A FPGA BGA Package Marking Example
Ordering Information
XA Spartan-3A FPGAs are available in Pb-free packaging only for all device/package combinations.
Pb-Free Packaging
Example:
XA3S200A -4 FT G 256 I
Device Type
Temperature Range:
Q - Grade (TJ = –40°C to 125°C)
I - Grade (TJ = –40°C to 100°C)
Number of Pins
Pb-free
Speed Grade
-4: Standard Performance
Package Type
DS529-1_04_012009
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Product Specification
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Device
XA3S200A
Speed Grade
–4 Standard
Performance
Package Type / Number of Pins
Temperature Range ( TJ )
FTG256
256-ball Fine-Pitch Thin Ball Grid Array (FTBGA) I I-Grade (–40°C to 100°C)
XA3S400A
FGG400
400-ball Fine-Pitch Ball Grid Array (FBGA)
XA3S700A
FGG484
484-ball Fine-Pitch Ball Grid Array (FBGA)
Q Q-Grade (–40°C to 125°C)
XA3S1400A
Notes:
1.
The XA Spartan-3A FPGA product line is available in -4 Speed Grade only.
DC Electrical Characteristics
Absolute Maximum Ratings
All parameter limits are representative of worst-case supply
voltage and junction temperature conditions. Unless
otherwise noted, the published parameter values apply
to all XA Spartan-3A devices, and AC and DC
characteristics are specified using the same numbers
for both I-Grade and Q-Grade.
Stresses beyond those listed under Table 4: Absolute
Maximum Ratings may cause permanent damage to the
device. These are stress ratings only; functional operation
of the device at these or any other conditions beyond those
listed under the Recommended Operating Conditions is not
implied. Exposure to absolute maximum conditions for
extended periods of time adversely affects device reliability.
Table 4: Absolute Maximum Ratings
Symbol
Description
Conditions
Min
Max
Units
VCCINT
Internal supply voltage
–0.5
1.32
V
VCCAUX
Auxiliary supply voltage
–0.5
3.75
V
VCCO
Output driver supply voltage
–0.5
3.75
V
VREF
Input reference voltage
–0.5
VCCO + 0.5
V
–0.95
4.6
V
–0.5
4.6
V
Human body model
–
–
Machine model
–
±2000
±500
±200
V
Charged device model
VIN
Voltage applied to all User I/O pins and
Dual-Purpose pins
Driver in a high-impedance state
Voltage applied to all Dedicated pins
Electrostatic Discharge Voltage
VESD
V
V
TJ
Junction temperature
–
125
°C
TSTG
Storage temperature
–65
150
°C
Notes:
1.
6
For soldering guidelines, see UG112: Device Packaging and Thermal Characteristics and XAPP427: Implementation and Solder Reflow
Guidelines for Pb-Free Packages.
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DS681 (v1.1) February 3, 2009
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Power Supply Specifications
Table 5: Supply Voltage Thresholds for Power-On Reset
Symbol
Description
Min
Max
Units
VCCINTT
Threshold for the VCCINT supply
0.4
1.0
V
VCCAUXT
Threshold for the VCCAUX supply
0.8
2.0
V
VCCO2T
Threshold for the VCCO Bank 2 supply
0.8
2.0
V
Notes:
1.
2.
VCCINT, VCCAUX, and VCCO supplies to the FPGA can be applied in any order. However, the FPGA’s configuration source (SPI Flash, parallel
NOR Flash, microcontroller) might have specific requirements. Check the data sheet for the attached configuration source. Apply VCCINT last
for lowest overall power consumption (see UG331 chapter "Powering Spartan-3 Generation FPGAs" for more information).
To ensure successful power-on, VCCINT, VCCO Bank 2, and VCCAUX supplies must rise through their respective threshold-voltage ranges with
no dips at any point.
Table 6: Supply Voltage Ramp Rate
Symbol
Description
Min
Max
Units
VCCINTR
Ramp rate from GND to valid VCCINT supply level
0.2
100
ms
VCCAUXR
Ramp rate from GND to valid VCCAUX supply level
0.2
100
ms
VCCO2R
Ramp rate from GND to valid VCCO Bank 2 supply level
0.2
100
ms
Notes:
1.
2.
VCCINT, VCCAUX, and VCCO supplies to the FPGA can be applied in any order. However, the FPGA’s configuration source (SPI Flash, parallel
NOR Flash, microcontroller) might have specific requirements. Check the data sheet for the attached configuration source. Apply VCCINT last
for lowest overall power consumption (see UG331 chapter "Powering Spartan-3 Generation FPGAs" for more information).
To ensure successful power-on, VCCINT, VCCO Bank 2, and VCCAUX supplies must rise through their respective threshold-voltage ranges with
no dips at any point.
Table 7: Supply Voltage Levels Necessary for Preserving CMOS Configuration Latch (CCL) Contents and RAM
Data
Symbol
Description
Min
Units
VDRINT
VCCINT level required to retain CMOS Configuration Latch (CCL) and RAM data
1.0
V
VDRAUX
VCCAUX level required to retain CMOS Configuration Latch (CCL) and RAM data
2.0
V
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General Recommended Operating Conditions
Table 8: General Recommended Operating Conditions
Symbol
TJ
Description
Junction temperature
Min
Nominal
Max
Units
I-Grade
-40
–
100
°C
Q-Grade
-40
–
125
°C
VCCINT
Internal supply voltage
1.140
1.200
1.260
V
VCCO (1)
Output driver supply voltage
1.100
–
3.600
V
VCCAUX
Auxiliary supply voltage
VCCAUX = 2.5
2.250
2.500
2.750
V
VCCAUX = 3.3
3.000
3.300
3.600
V
I/O, Input-only and
Dual-purpose pins
-0.5
–
VCCO+0.5
V
Dedicated pins
-0.5
–
VCCAUX+0.5
V
–
–
500
ns
VIN
TIN
Input voltage(2)
Input signal transition
time(3)
Notes:
1.
2.
3.
8
This VCCO range spans the lowest and highest operating voltages for all supported I/O standards. Table 11 lists the recommended VCCO
range specific to each of the single-ended I/O standards, and Table 13 lists that specific to the differential standards.
See XAPP459, "Eliminating I/O Coupling Effects when Interfacing Large-Swing Single-Ended Signals to User I/O Pins."
Measured between 10% and 90% VCCO.
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General DC Characteristics for I/O Pins
Table 9: General DC Characteristics of User I/O, Dual-Purpose, and Dedicated Pins
Symbol
Description
Test Conditions
Min
Typ
Max
Units
IL
Leakage current at User I/O,
Input-only, Dual-Purpose, and
Dedicated pins, FPGA powered
Driver is in a high-impedance state,
VIN = 0V or VCCO max, sample-tested
–10
–
+10
μA
IHS
Leakage current on pins during
hot socketing, FPGA unpowered
All pins except INIT_B, PROG_B, DONE, and JTAG
pins when PUDC_B = 1.
–10
–
+10
μA
INIT_B, PROG_B, DONE, and JTAG pins or other
pins when PUDC_B = 0.
IRPU(2)
RPU
(2)
IRPD
(2)
RPD(2)
Current through pull-up resistor
at User I/O, Dual-Purpose,
Input-only, and Dedicated pins.
Dedicated pins are powered by
VCCAUX.
Equivalent pull-up resistor value
at User I/O, Dual-Purpose,
Input-only, and Dedicated pins
(based on IRPU per Note 2)
Current through pull-down
resistor at User I/O,
Dual-Purpose, Input-only, and
Dedicated pins
Equivalent pull-down resistor
value at User I/O, Dual-Purpose,
Input-only, and Dedicated pins
(based on IRPD per Note 2)
VCCO or VCCAUX =
3.0V to 3.6V
–151
–315
–710
μA
VCCO or VCCAUX =
2.3V to 2.7V
–82
–182
–437
μA
VCCO = 1.7V to 1.9V
–36
–88
–226
μA
VCCO = 1.4V to 1.6V
–22
–56
–148
μA
VCCO = 1.14V to 1.26V
–11
–31
–83
μA
VCCO = 3.0V to 3.6V
5.1
11.4
23.9
kΩ
VCCO = 2.3V to 2.7V
6.2
14.8
33.1
kΩ
VCCO = 1.7V to 1.9V
8.4
21.6
52.6
kΩ
VCCO = 1.4V to 1.6V
10.8
28.4
74.0
kΩ
VCCO = 1.14V to 1.26V
15.3
41.1
119.4
kΩ
VCCAUX = 3.0V to 3.6V
167
346
659
μA
VCCAUX = 2.25V to 2.75V
100
225
457
μA
VIN = 3.0V to 3.6V
5.5
10.4
20.8
kΩ
VIN = 2.3V to 2.7V
4.1
7.8
15.7
kΩ
VIN = 1.7V to 1.9V
3.0
5.7
11.1
kΩ
VIN = 1.4V to 1.6V
2.7
5.1
9.6
kΩ
VIN = GND
VIN = GND
VIN = VCCO
VCCAUX = 3.0V to 3.6V
VIN = 1.14V to 1.26V
2.4
4.5
8.1
kΩ
VIN = 3.0V to 3.6V
7.9
16.0
35.0
kΩ
VIN = 2.3V to 2.7V
5.9
12.0
26.3
kΩ
VIN = 1.7V to 1.9V
4.2
8.5
18.6
kΩ
VIN = 1.4V to 1.6V
3.6
7.2
15.7
kΩ
VIN = 1.14V to 1.26V
3.0
6.0
12.5
kΩ
All VCCO levels
–10
–
+10
μA
–
3
–
10
pF
VCCAUX = 2.25V to 2.75V
IREF
VREF current per pin
CIN
Input capacitance
RDT
Resistance of optional differential
termination circuit within a
differential I/O pair. Not available
on Input-only pairs.
μA
Add IHS + IRPU
VCCO = 3.3V ± 10%
LVDS_33,
MINI_LVDS_33,
RSDS_33
90
100
115
Ω
VCCO = 2.5V ± 10%
LVDS_25,
MINI_LVDS_25,
RSDS_25
90
110
–
Ω
Notes:
1.
2.
The numbers in this table are based on the conditions set forth in Table 8.
This parameter is based on characterization. The pull-up resistance RPU = VCCO / IRPU. The pull-down resistance RPD = VIN / IRPD.
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Quiescent Current Requirements
Table 10: Quiescent Supply Current Characteristics
Symbol
ICCINTQ
ICCOQ
ICCAUXQ
Description
Quiescent VCCINT supply current
Quiescent VCCO supply current
Quiescent VCCAUX supply current
Typical(2)
I-Grade
Maximum(2)
Q-Grade
Maximum(2)
Units
XA3S200A
7
70
110
mA
XA3S400A
10
125
230
mA
XA3S700A
13
185
330
mA
XA3S1400A
24
310
580
mA
XA3S200A
0.2
3
4
mA
XA3S400A
0.3
4
5
mA
XA3S700A
0.3
4
5
mA
XA3S1400A
0.3
4
5
mA
XA3S200A
5
15
20
mA
XA3S400A
5
24
40
mA
XA3S700A
6
34
60
mA
XA3S1400A
10
58
95
mA
Device
Notes:
1.
2.
3.
4.
5.
10
The numbers in this table are based on the conditions set forth in Table 8.
Quiescent supply current is measured with all I/O drivers in a high-impedance state and with all pull-up/pull-down resistors at the I/O pads
disabled. Typical values are characterized using typical devices at ambient room temperature (TA of 25°C at VCCINT = 1.2V, VCCO = 3.3V, and
VCCAUX = 2.5V). The maximum limits are tested for each device at the respective maximum specified junction temperature and at maximum
voltage limits with VCCINT = 1.26V, VCCO = 3.6V, and VCCAUX = 3.6V. The FPGA is programmed with a “blank” configuration data file (that is,
a design with no functional elements instantiated). For conditions other than those described above (for example, a design including
functional elements), measured quiescent current levels will be different than the values in the table.
There are two recommended ways to estimate the total power consumption (quiescent plus dynamic) for a specific design: a) The
Spartan-3A FPGA XPower Estimator provides quick, approximate, typical estimates, and does not require a netlist of the design. b) XPower
Analyzer uses a netlist as input to provide maximum estimates as well as more accurate typical estimates.
The maximum numbers in this table indicate the minimum current each power rail requires in order for the FPGA to power-on successfully.
For information on the power-saving Suspend mode, see XAPP480: Using Suspend Mode in Spartan-3 Generation FPGAs. Suspend mode
typically saves 40% total power consumption compared to quiescent current.
www.xilinx.com
DS681 (v1.1) February 3, 2009
Product Specification
R
Single-Ended I/O Standards
Table 11: Recommended Operating Conditions for User I/Os Using Single-Ended Standards
IOSTANDARD
Attribute
VCCO for Drivers(2)
VREF
Min (V)
Nom (V)
Max (V)
VIL
VIH
Max (V)
Min (V)
Min (V)
Nom (V)
Max (V)
LVTTL
3.0
3.3
3.6
0.8
2.0
LVCMOS33(4)
3.0
3.3
3.6
0.8
2.0
LVCMOS25(4,5)
2.3
2.5
2.7
0.7
1.7
0.4
0.8
VREF is not used for
these I/O standards
LVCMOS18(4)
1.65
1.8
1.95
LVCMOS15(4)
1.4
1.5
1.6
0.4
0.8
LVCMOS12(4)
1.1
1.2
1.3
0.4
0.7
PCI33_3(6)
3.0
3.3
3.6
0.3 • VCCO
0.5 • VCCO
HSTL_I
1.4
1.5
1.6
0.68
0.75
0.9
VREF - 0.1
VREF + 0.1
HSTL_III
1.4
1.5
1.6
–
0.9
-
VREF - 0.1
VREF + 0.1
HSTL_I_18
1.7
1.8
1.9
0.8
0.9
1.1
VREF - 0.1
VREF + 0.1
HSTL_II_18
1.7
1.8
1.9
–
0.9
–
VREF - 0.1
VREF + 0.1
HSTL_III_18
1.7
1.8
1.9
–
1.1
–
VREF - 0.1
VREF + 0.1
SSTL18_I
1.7
1.8
1.9
0.833
0.900
0.969
VREF - 0.125
VREF + 0.125
SSTL18_II
1.7
1.8
1.9
0.833
0.900
0.969
VREF - 0.125
VREF + 0.125
SSTL2_I
2.3
2.5
2.7
1.15
1.25
1.38
VREF - 0.150
VREF + 0.150
SSTL2_II
2.3
2.5
2.7
1.15
1.25
1.38
VREF - 0.150
VREF + 0.150
SSTL3_I
3.0
3.3
3.6
1.3
1.5
1.7
VREF - 0.2
VREF + 0.2
SSTL3_II
3.0
3.3
3.6
1.3
1.5
1.7
VREF - 0.2
VREF + 0.2
Notes:
1.
2.
3.
4.
5.
6.
Descriptions of the symbols used in this table are as follows:
VCCO – the supply voltage for output drivers
VREF – the reference voltage for setting the input switching threshold
VIL – the input voltage that indicates a Low logic level
VIH – the input voltage that indicates a High logic level
In general, the VCCO rails supply only output drivers, not input circuits. The exceptions are for LVCMOS25 inputs when VCCAUX = 3.3V range
and for PCI I/O standards.
For device operation, the maximum signal voltage (VIH max) can be as high as VIN max. See Table 8.
There is approximately 100 mV of hysteresis on inputs using LVCMOS33 and LVCMOS25 I/O standards.
All Dedicated pins (PROG_B, DONE, SUSPEND, TCK, TDI, TDO, and TMS) draw power from the VCCAUX rail and use the LVCMOS25 or
LVCMOS33 standard depending on VCCAUX. The Dual-Purpose configuration pins use the LVCMOS25 standard before the User mode.
When using these pins as part of a standard 2.5V configuration interface, apply 2.5V to the VCCO lines of Banks 0, 1, and 2 at power-on as
well as throughout configuration.
For information on PCI IP solutions, see http://www.xilinx.com/products/design_resources/conn_central/protocols/pci_pcix.htm. The PCI
IOSTANDARD is not supported on input-only pins. The PCIX IOSTANDARD is available and has equivalent characteristics, but no PCI-X IP
is supported.
DS681 (v1.1) February 3, 2009
Product Specification
www.xilinx.com
11
R
Table 12: DC Characteristics of User I/Os Using
Single-Ended Standards (Continued)
Table 12: DC Characteristics of User I/Os Using
Single-Ended Standards
Test
Conditions
IOSTANDARD
Attribute
LVTTL(3)
2
4
LVCMOS25(3)
LVCMOS18(3)
LVCMOS15(3)
LVCMOS12(3)
12
IOH
(mA)
VOL
Max (V)
VOH
Min (V)
PCI33_3(5)
1.5
–0.5
10% VCCO
90% VCCO
–4
HSTL_I(4)
8
–8
0.4
VCCO - 0.4
24(6)
–8
0.4
VCCO - 0.4
IOH
(mA)
VOL
Max (V)
VOH
Min (V)
2
–2
0.4
2.4
IOSTANDARD
Attribute
6
6
–6
HSTL_III(4)
8
8
–8
HSTL_I_18
8
–8
0.4
VCCO - 0.4
12
12
–12
HSTL_II_18(4)
16
–16(6)
0.4
VCCO - 0.4
16
16
–16
HSTL_III_18
24(6)
–8
0.4
VCCO - 0.4
24
LVCMOS33(3)
Logic Level
Characteristics
IOL
(mA)
IOL
(mA)
4
Test
Conditions
Logic Level
Characteristics
24(7)
VTT – 0.475 VTT + 0.475
–24
SSTL18_I
6.7
–6.7
SSTL18_II(4)
13.4
–13.4 VTT – 0.475 VTT + 0.475
2
2
–2
0.4
VCCO – 0.4
4
4
–4
SSTL2_I
8.1
–8.1
VTT – 0.61
VTT + 0.61
16.2
–16.2
VTT – 0.80
VTT + 0.80
6
6
–6
SSTL2_II(4)
8
8
–8
SSTL3_I
8
–8
VTT – 0.6
VTT + 0.6
12
12
–12
SSTL3_II
16
–16
VTT – 0.8
VTT + 0.8
16
16
–16(7)
Notes:
1.
24(4)
24
–24(7)
2
2
–2
4
4
–4
6
6
–6
8
8
–8
12
12
–12
16(4)
16
–16(7)
24(4)
24(7)
–24(7)
2
2
–2
4
4
–4
6
6
–6(7)
8
8
–8
12(4)
12
–12(7)
16(4)
16
–16
2
2
–2
4
4
–4
6
6
–6
8(4)
8
–8
12(4)
12
–12
2
2
–2
4(4)
4
–4
6(4)
6
–6
0.4
VCCO – 0.4
0.4
VCCO – 0.4
2.
IOL – the output current condition under which VOL is tested
IOH – the output current condition under which VOH is tested
VOL – the output voltage that indicates a Low logic level
VOH – the output voltage that indicates a High logic level
VIL – the input voltage that indicates a Low logic level
VIH – the input voltage that indicates a High logic level
VCCO – the supply voltage for output drivers
VREF – the reference voltage for setting the input switching threshold
VTT – the voltage applied to a resistor termination
3.
4.
5.
0.4
VCCO – 0.4
0.4
VCCO – 0.4
The numbers in this table are based on the conditions set forth in
Table 8 and Table 11.
Descriptions of the symbols used in this table are as follows:
6.
7.
For the LVCMOS and LVTTL standards: the same VOL and VOH
limits apply for both the Fast and Slow slew attributes.
These higher-drive output standards are supported only on
FPGA banks 1 and 3. Inputs are unrestricted. See the chapter
"Using I/O Resources" in UG331.
Tested according to the relevant PCI specifications. For
information on PCI IP solutions, see
http://www.xilinx.com/products/design_resources/conn_central/
protocols/pci_pcix.htm. The PCI IOSTANDARD is not supported
on input-only pins. The PCIX IOSTANDARD is available and has
equivalent characteristics, but no PCI-X IP is supported.
DE-RATE by 5% for TJ above 100oC
DE-RATE by 20% for TJ above 100oC
www.xilinx.com
DS681 (v1.1) February 3, 2009
Product Specification
R
Differential I/O Standards
Differential Input Pairs
VINP
Internal
Logic
VINN
VINN
VID
50%
VINP
Differential
I/O Pair Pins
P
N
VICM
GND level
VICM = Input common mode voltage =
VINP + VINN
2
VID = Differential input voltage = VINP - VINN
DS529-3_10_012907
Figure 3: Differential Input Voltages
Table 13: Recommended Operating Conditions for User I/Os Using Differential Signal Standards
IOSTANDARD Attribute
VCCO for Drivers(1)
Min (V)
Nom (V)
Max (V)
VID
Min (mV) Nom (mV) Max (mV)
Min (V)
VICM(2)
Nom (V)
Max (V)
2.35
LVDS_25(3)
2.25
2.5
2.75
100
350
600
0.3
1.25
LVDS_33(3)
3.0
3.3
3.6
100
350
600
0.3
1.25
2.35
BLVDS_25(4)
2.25
2.5
2.75
100
300
–
0.3
1.3
2.35
MINI_LVDS_25(3)
2.25
2.5
2.75
200
–
600
0.3
1.2
1.95
MINI_LVDS_33(3)
3.0
3.3
3.6
1.95
200
–
600
0.3
1.2
LVPECL_25(5)
Inputs Only
100
800
1000
0.3
1.2
1.95
LVPECL_33(5)
Inputs Only
100
800
1000
0.3
1.2
2.8(6)
100
200
–
0.3
1.2
1.5
RSDS_25(3)
2.25
2.5
2.75
RSDS_33(3)
3.0
3.3
3.6
100
200
–
0.3
1.2
1.5
TMDS_33(3, 4, 7)
3.14
3.3
3.47
150
–
1200
2.7
–
3.23
PPDS_25(3)
2.25
2.5
2.75
100
–
400
0.2
–
2.3
PPDS_33(3)
3.0
3.3
3.6
100
–
400
0.2
–
2.3
DIFF_HSTL_I_18
1.7
1.8
1.9
100
–
–
0.8
–
1.1
DIFF_HSTL_II_18(8)
1.7
1.8
1.9
100
–
–
0.8
–
1.1
DIFF_HSTL_III_18
1.7
1.8
1.9
100
–
–
0.8
–
DIFF_HSTL_I
1.4
1.5
1.6
100
–
–
0.68
1.1
0.9
DIFF_HSTL_III
1.4
1.5
1.6
100
–
–
–
0.9
–
DIFF_SSTL18_I
1.7
1.8
1.9
100
–
–
0.7
–
1.1
DIFF_SSTL18_II(8)
1.7
1.8
1.9
100
–
–
0.7
–
1.1
DIFF_SSTL2_I
2.3
2.5
2.7
100
–
–
1.0
–
1.5
DIFF_SSTL2_II(8)
2.3
2.5
2.7
100
–
–
1.0
–
1.5
DIFF_SSTL3_I
3.0
3.3
3.6
100
–
–
1.1
–
1.9
DIFF_SSTL3_II
3.0
3.3
3.6
100
–
–
1.1
–
1.9
Notes:
1.
2.
3.
4.
5.
6.
7.
8.
9.
The VCCO rails supply only differential output drivers, not input circuits.
VICM must be less than VCCAUX.
These true differential output standards are supported only on FPGA banks 0 and 2. Inputs are unrestricted. See the chapter "Using I/O Resources" in UG331.
See "External Termination Requirements for Differential I/O," page 15.
LVPECL is supported on inputs only, not outputs. Requires VCCAUX = 3.3V ± 10%.
LVPECL_33 maximum VICM = VCCAUX – (VID / 2)
Requires VCCAUX = 3.3V ± 10% for inputs. (VCCAUX – 300 mV) ≤ VICM ≤ (VCCAUX – 37 mV)
These higher-drive output standards are supported only on FPGA banks 1 and 3. Inputs are unrestricted. See the chapter "Using I/O Resources" in UG331.
VREF inputs are used for the DIFF_SSTL and DIFF_HSTL standards. The VREF settings are the same as for the single-ended versions in Table 11. Other differential
standards do not use VREF.
DS681 (v1.1) February 3, 2009
Product Specification
www.xilinx.com
13
R
Differential Output Pairs
VOUTP
Internal
Logic
P
N
VOUTN
Differential
I/O Pair Pins
VOH
VOUTN
VOD
50%
VOUTP
VOL
VOCM
GND level
VOCM = Output common mode voltage =
VOUTP + VOUTN
2
VOD = Output differential voltage = VOUTP - VOUTN
VOH = Output voltage indicating a High logic level
VOL = Output voltage indicating a Low logic levelDS529-3_11_012907
Figure 4: Differential Output Voltages
Table 14: DC Characteristics of User I/Os Using Differential Signal Standards
VOD
IOSTANDARD Attribute
LVDS_25
LVDS_33
BLVDS_25
MINI_LVDS_25
MINI_LVDS_33
RSDS_25
RSDS_33
TMDS_33
PPDS_25
PPDS_33
DIFF_HSTL_I_18
DIFF_HSTL_II_18
DIFF_HSTL_III_18
DIFF_HSTL_I
DIFF_HSTL_III
DIFF_SSTL18_I
DIFF_SSTL18_II
DIFF_SSTL2_I
DIFF_SSTL2_II
DIFF_SSTL3_I
DIFF_SSTL3_II
Min (mV)
247
247
240
300
300
100
100
400
100
100
–
–
–
Typ
(mV)
350
350
350
–
–
–
–
–
–
–
–
–
–
–
–
VOCM
Max (mV)
Min (V)
454
1.125
454
1.125
460
–
600
1.0
600
1.0
400
1.0
400
1.0
800
VCCO – 0.405
400
0.5
400
0.5
–
–
–
–
–
–
–
–
Typ (V)
–
–
1.30
–
–
–
–
–
0.8
0.8
–
–
–
Max (V)
1.375
1.375
–
1.4
1.4
1.4
1.4
VCCO – 0.190
1.4
1.4
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
VOH
VOL
Min (V)
–
–
–
–
–
–
–
–
–
–
VCCO – 0.4
VCCO – 0.4
VCCO – 0.4
VCCO – 0.4
VCCO – 0.4
VTT + 0.475
VTT + 0.475
VTT + 0.61
VTT + 0.81
VTT + 0.6
VTT + 0.8
Max (V)
–
–
–
–
–
–
–
–
–
–
0.4
0.4
0.4
0.4
0.4
VTT – 0.475
VTT – 0.475
VTT – 0.61
VTT – 0.81
VTT – 0.6
VTT – 0.8
Notes:
1. The numbers in this table are based on the conditions set forth in Table 8 and Table 13.
2. See "External Termination Requirements for Differential I/O," page 15.
3. Output voltage measurements for all differential standards are made with a termination resistor (RT) of 100Ω across the N and P pins
of the differential signal pair.
4. At any given time, no more than two of the following differential output standards can be assigned to an I/O bank: LVDS_25,
RSDS_25, MINI_LVDS_25, PPDS_25 when VCCO=2.5V, or LVDS_33, RSDS_33, MINI_LVDS_33, TMDS_33, PPDS_33 when
VCCO = 3.3V
14
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DS681 (v1.1) February 3, 2009
Product Specification
R
External Termination Requirements for Differential I/O
LVDS, RSDS, MINI_LVDS, and PPDS I/O Standards
Bank 0 and 2
Any Bank
Bank 0
Bank 2
VCCO = 3.3V
VCCO = 2.5V
LVDS_33,
MINI_LVDS_33,
RSDS_33,
PPDS_33
LVDS_25,
MINI_LVDS_25,
RSDS_25,
PPDS_25
Bank 1
1/4 th of Bourns
Part Number
Z0 = 50Ω CAT16-PT4F4
Bank 3
Bank 0
No VCCO Restrictions
LVDS_33, LVDS_25,
MINI_LVDS_33,
MINI_LVDS_25,
RSDS_33, RSDS_25,
PPDS_33, PPDS_25
Bank 2
100Ω
Z0 = 50Ω
DIFF_TERM=No
a) Input-only differential pairs or pairs not using DIFF_TERM=Yes constraint
Z0 = 50Ω
VCCO = 3.3V
VCCO = 2.5V
LVDS_33,
MINI_LVDS_33,
RSDS_33,
PPDS_33
LVDS_25,
MINI_LVDS_25,
RSDS_25,
PPDS_25
RDT
Z0 = 50Ω
VCCO = 3.3V
VCCO = 2.5V
LVDS_33,
MINI_LVDS_33,
RSDS_33,
PPDS_33
LVDS_25,
MINI_LVDS_25,
RSDS_25,
PPDS_25
DIFF_TERM=Yes
b) Differential pairs using DIFF_TERM=Yes constraint
DS529-3_09_020107
Figure 5: External Input Termination for LVDS, RSDS, MINI_LVDS, and PPDS I/O Standards
BLVDS_25 I/O Standard
Any Bank
Any Bank
Bank 0
Bank 3
1/4 th of Bourns
Part Number
CAT16-PT4F4
Z0 = 50Ω
165Ω
140Ω
BLVDS_25
Z0 = 50Ω
Bank 1
Bank 1
Bank 2
VCCO = 2.5V
1/4 th of Bourns
Part Number
CAT16-LV4F12
Bank 3
Bank 0
Bank 2
No VCCO Requirement
100Ω
BLVDS_25
165Ω
DS529-3_07_020107
Figure 6: External Termination Resistors for BLVDS_25 I/O Standard
TMDS_33 I/O Standard
Any Bank
Bank 0 and 2
Bank 0
3.3V
Bank 2
50Ω
Bank 1
Bank 3
Bank 0
50Ω
Bank 2
VCCAUX = 3.3V
VCCO = 3.3V
TMDS_33
TMDS_33
DVI/HDMI cable
DS529-3_08_020107
Figure 7: External Input Resistors Required for TMDS_33 I/O Standard
DS681 (v1.1) February 3, 2009
Product Specification
www.xilinx.com
15
R
Device DNA Data Retention, Read Endurance
Table 15: Device DNA Identifier Memory Characteristics
Symbol
Description
Minimum
Units
DNA_CYCLES
Number of READ operations or JTAG ISC_DNA read operations. Unaffected by
HOLD or SHIFT operations.
30,000,000
Read
cycles
Switching Characteristics
All XA Spartan-3A FPGAs ship in the -4 speed grade.
Switching characteristics in this document are designated
as Production as shown in Table 16.
To create a Xilinx MySupport user account and sign up for
automatic E-mail notification whenever this data sheet is
updated:
Production: These specifications are approved once
enough production silicon of a particular device family
member has been characterized to provide full correlation
between speed files and devices over numerous production
lots. There is no under-reporting of delays, and customers
receive formal notification of any subsequent changes.
•
Software Version Requirements
Production-quality systems must use FPGA designs
compiled using a speed file designated as PRODUCTION
status. FPGA designs using a less mature speed file
designation should only be used during system prototyping
or pre-production qualification. FPGA designs with speed
files designated as Preview, Advance, or Preliminary should
not be used in a production-quality system.
Whenever a speed file designation changes, as a device
matures toward Production status, rerun the latest Xilinx
ISE software on the FPGA design to ensure that the FPGA
design incorporates the latest timing information and
software updates.
All parameter limits are representative of worst-case supply
voltage and junction temperature conditions. Unless
otherwise noted, the published parameter values apply
to all XA Spartan-3A devices, and AC and DC
characteristics are specified using the same numbers
for both I-Grade and Q-Grade.
16
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Timing parameters and their representative values are
selected for inclusion below either because they are
important as general design requirements or they indicate
fundamental device performance characteristics. The XA
Spartan-3A FPGA speed files (v1.41), part of the Xilinx
Development Software, are the original source for many but
not all of the values. The speed grade designations for
these files are shown in Table 16. For more complete, more
precise, and worst-case data, use the values reported by
the Xilinx static timing analyzer (TRACE in the Xilinx
development software) and back-annotated to the
simulation netlist.
Table 16: XA Spartan-3A FPGA v1.41 Speed Grade
Designations
Device
Production
XA3S200A
–4
XA3S400A
–4
XA3S700A
–4
XA3S1400A
–4
Table 17 provides the recent history of the XA Spartan-3A
FPGA speed files.
Table 17: XA Spartan-3A FPGA Speed File Version
History
Version
ISE
Release
1.39
10.1.01i
Initial release.
1.40
10.1.02i
Updated input timing adjustments.
1.41
10.1.03i
Updated output timing adjustments.
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Description
DS681 (v1.1) February 3, 2009
Product Specification
R
I/O Timing
Pin-to-Pin Clock-to-Output Times
Table 18: Pin-to-Pin Clock-to-Output Times for the IOB Output Path
Speed Grade
-4
Symbol
Description
Conditions
Device
Max
Units
XA3S200A
3.27
ns
XA3S400A
3.33
ns
XA3S700A
3.50
ns
XA3S1400A
3.99
ns
XA3S200A
5.24
ns
XA3S400A
5.12
ns
XA3S700A
5.34
ns
XA3S1400A
5.69
ns
Clock-to-Output Times
TICKOFDCM
TICKOF
When reading from the Output Flip-Flop
(OFF), the time from the active transition on
the Global Clock pin to data appearing at the
Output pin. The DCM is in use.
LVCMOS25(2), 12mA
output drive, Fast slew
rate, with DCM(3)
When reading from OFF, the time from the
LVCMOS25(2), 12mA
active transition on the Global Clock pin to
output drive, Fast slew
data appearing at the Output pin. The DCM is rate, without DCM
not in use.
Notes:
1.
2.
3.
The numbers in this table are tested using the methodology presented in Table 26 and are based on the operating conditions set forth in
Table 8 and Table 11.
This clock-to-output time requires adjustment whenever a signal standard other than LVCMOS25 is assigned to the Global Clock Input or a
standard other than LVCMOS25 with 12 mA drive and Fast slew rate is assigned to the data Output. If the former is true, add the appropriate
Input adjustment from Table 22. If the latter is true, add the appropriate Output adjustment from Table 25.
DCM output jitter is included in all measurements.
DS681 (v1.1) February 3, 2009
Product Specification
www.xilinx.com
17
R
Pin-to-Pin Setup and Hold Times
Table 19: Pin-to-Pin Setup and Hold Times for the IOB Input Path (System Synchronous)
Speed Grade
-4
Symbol
Description
Conditions
Device
Min
Units
XA3S200A
2.84
ns
XA3S400A
2.68
ns
XA3S700A
2.57
ns
XA3S1400A
2.17
ns
Setup Times
TPSDCM
TPSFD
When writing to the Input Flip-Flop (IFF),
the time from the setup of data at the Input
pin to the active transition at a Global Clock
pin. The DCM is in use. No Input Delay is
programmed.
LVCMOS25(2),
IFD_DELAY_VALUE = 0,
with DCM(4)
When writing to IFF, the time from the setup
of data at the Input pin to an active transition
at the Global Clock pin. The DCM is not in
use. The Input Delay is programmed.
LVCMOS25(2),
XA3S200A
2.76
ns
IFD_DELAY_VALUE = 5,
without DCM
XA3S400A
2.60
ns
XA3S700A
2.63
ns
XA3S1400A
2.41
ns
XA3S200A
-0.52
ns
XA3S400A
-0.29
ns
XA3S700A
-0.12
ns
XA3S1400A
0.00
ns
XA3S200A
-0.56
ns
XA3S400A
-0.42
ns
XA3S700A
-0.75
ns
XA3S1400A
-0.69
ns
Hold Times
TPHDCM
TPHFD
When writing to IFF, the time from the active
transition at the Global Clock pin to the
point when data must be held at the Input
pin. The DCM is in use. No Input Delay is
programmed.
LVCMOS25(3),
IFD_DELAY_VALUE = 0,
with DCM(4)
When writing to IFF, the time from the active
transition at the Global Clock pin to the
point when data must be held at the Input
pin. The DCM is not in use. The Input Delay
is programmed.
LVCMOS25(3),
IFD_DELAY_VALUE = 5,
without DCM
Notes:
1.
2.
3.
4.
18
The numbers in this table are tested using the methodology presented in Table 26 and are based on the operating conditions set forth in
Table 8 and Table 11.
This setup time requires adjustment whenever a signal standard other than LVCMOS25 is assigned to the Global Clock Input or the data
Input. If this is true of the Global Clock Input, subtract the appropriate adjustment from Table 22. If this is true of the data Input, add the
appropriate Input adjustment from the same table.
This hold time requires adjustment whenever a signal standard other than LVCMOS25 is assigned to the Global Clock Input or the data Input.
If this is true of the Global Clock Input, add the appropriate Input adjustment from Table 22. If this is true of the data Input, subtract the
appropriate Input adjustment from the same table. When the hold time is negative, it is possible to change the data before the clock’s active
edge.
DCM output jitter is included in all measurements.
www.xilinx.com
DS681 (v1.1) February 3, 2009
Product Specification
R
Input Setup and Hold Times
Table 20: Setup and Hold Times for the IOB Input Path
Speed Grade
Symbol
Description
Conditions
IFD_
DELAY_
VALUE
Device
Min
Units
0
XA3S200A
1.81
ns
XA3S400A
1.51
ns
XA3S700A
1.51
ns
XA3S1400A
1.74
ns
XA3S200A
2.20
ns
2
2.93
ns
3
3.78
ns
4
4.37
ns
5
4.20
ns
6
5.23
ns
7
6.11
ns
8
6.71
ns
2.02
ns
2
2.67
ns
3
3.43
ns
4
3.96
ns
5
3.95
ns
6
4.81
ns
7
5.66
ns
8
6.19
ns
1.95
ns
2
2.83
ns
3
3.72
ns
4
4.31
ns
5
4.14
ns
6
5.19
ns
7
6.10
ns
8
6.73
ns
2.17
ns
2
2.92
ns
3
3.76
ns
4
4.32
ns
5
4.19
ns
6
5.09
ns
7
5.98
ns
8
6.57
ns
-4
Setup Times
TIOPICK
TIOPICKD
Time from the setup of data at the Input pin LVCMOS25(2)
to the active transition at the ICLK input of
the Input Flip-Flop (IFF). No Input Delay is
programmed.
Time from the setup of data at the Input pin LVCMOS25(2)
to the active transition at the ICLK input of
the Input Flip-Flop (IFF). The Input Delay is
programmed.
1
1
1
1
DS681 (v1.1) February 3, 2009
Product Specification
www.xilinx.com
XA3S400A
XA3S700A
XA3S1400A
19
R
Table 20: Setup and Hold Times for the IOB Input Path (Continued)
Speed Grade
Symbol
Description
Conditions
IFD_
DELAY_
VALUE
Device
Min
Units
0
XA3S200A
–0.65
ns
XA3S400A
–0.42
ns
XA3S700A
–0.67
ns
XA3S1400A
–0.71
ns
XA3S200A
–1.51
ns
2
–2.09
ns
3
–2.40
ns
4
–2.68
ns
5
–2.56
ns
6
–2.99
ns
7
–3.29
ns
8
–3.61
ns
–1.12
ns
2
–1.70
ns
3
–2.08
ns
4
–2.38
ns
5
–2.23
ns
6
–2.69
ns
7
–3.08
ns
8
–3.35
ns
–1.67
ns
2
–2.27
ns
3
–2.59
ns
4
–2.92
ns
5
–2.89
ns
6
–3.22
ns
7
–3.52
ns
8
–3.81
ns
–1.60
ns
2
–2.06
ns
3
–2.46
ns
4
–2.86
ns
5
–2.88
ns
6
–3.24
ns
7
–3.55
ns
8
–3.89
ns
-4
Hold Times
TIOICKP
TIOICKPD
Time from the active transition at the ICLK
input of the Input Flip-Flop (IFF) to the
point where data must be held at the Input
pin. No Input Delay is programmed.
LVCMOS25(2)
Time from the active transition at the ICLK
input of the Input Flip-Flop (IFF) to the
point where data must be held at the Input
pin. The Input Delay is programmed.
LVCMOS25(2)
1
1
1
1
20
www.xilinx.com
XA3S400A
XA3S700A
XA3S1400A
DS681 (v1.1) February 3, 2009
Product Specification
R
Table 20: Setup and Hold Times for the IOB Input Path (Continued)
Speed Grade
Description
Symbol
IFD_
DELAY_
VALUE
Conditions
-4
Device
Min
Units
All
1.61
ns
Set/Reset Pulse Width
TRPW_IOB
Minimum pulse width to SR control input
on IOB
Notes:
1.
2.
3.
The numbers in this table are tested using the methodology presented in Table 26 and are based on the operating conditions set forth in
Table 8 and Table 11.
This setup time requires adjustment whenever a signal standard other than LVCMOS25 is assigned to the data Input. If this is true, add the
appropriate Input adjustment from Table 22.
These hold times require adjustment whenever a signal standard other than LVCMOS25 is assigned to the data Input. If this is true, subtract
the appropriate Input adjustment from Table 22. When the hold time is negative, it is possible to change the data before the clock’s active
edge.
Input Propagation Times
Table 21: Propagation Times for the IOB Input Path
Speed Grade
Symbol
Description
Conditions
IFD_
DELAY_
VALUE
Device
Max
Units
0
XA3S200A
2.04
ns
XA3S400A
1.74
ns
XA3S700A
1.74
ns
XA3S1400A
1.97
ns
-4
Propagation Times
TIOPLI
The time it takes for data to travel
from the Input pin through the IFF
latch to the I output with no input
delay programmed
DS681 (v1.1) February 3, 2009
Product Specification
LVCMOS25(2)
www.xilinx.com
21
R
Table 21: Propagation Times for the IOB Input Path (Continued)
Speed Grade
Symbol
TIOPLID
Description
The time it takes for data to travel
from the Input pin through the IFF
latch to the I output with the input
delay programmed
Conditions
LVCMOS25(2)
IFD_
DELAY_
VALUE
Device
Max
Units
1
XA3S200A
2.43
ns
2
3.16
ns
3
4.01
ns
4
4.60
ns
5
4.43
ns
6
5.46
ns
7
6.33
ns
8
6.94
ns
2.25
ns
2
2.90
ns
3
3.66
ns
4
4.19
ns
5
4.18
ns
6
5.03
ns
7
5.88
ns
8
6.42
ns
2.18
ns
2
3.06
ns
3
3.95
ns
4
4.54
ns
5
4.37
ns
6
5.42
ns
7
6.33
ns
8
6.96
ns
2.40
ns
2
3.15
ns
3
3.99
ns
4
4.55
ns
5
4.42
ns
6
5.32
ns
7
6.21
ns
8
6.80
ns
1
1
1
-4
XA3S400A
XA3S700A
XA3S1400A
Notes:
1.
2.
22
The numbers in this table are tested using the methodology presented in Table 26 and are based on the operating conditions set forth in
Table 8 and Table 11.
This propagation time requires adjustment whenever a signal standard other than LVCMOS25 is assigned to the data Input. When this is
true, add the appropriate Input adjustment from Table 22.
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DS681 (v1.1) February 3, 2009
Product Specification
R
Input Timing Adjustments
Table 22: Input Timing Adjustments by IOSTANDARD
Convert Input Time from
LVCMOS25 to the Following
Signal Standard
(IOSTANDARD)
Add the
Adjustment
Below
Speed Grade
-4
Units
Table 22: Input Timing Adjustments by
Convert Input Time from
LVCMOS25 to the Following
Signal Standard
(IOSTANDARD)
Add the
Adjustment
Below
Speed Grade
-4
Units
Differential Standards
Single-Ended Standards
LVTTL
0.62
ns
LVDS_25
0.79
ns
LVCMOS33
0.54
ns
LVDS_33
0.79
ns
0.79
ns
LVCMOS25
0
ns
BLVDS_25
LVCMOS18
0.83
ns
MINI_LVDS_25
0.84
ns
LVCMOS15
0.60
ns
MINI_LVDS_33
0.84
ns
0.80
ns
0.80
ns
LVCMOS12
0.31
ns
LVPECL_25
PCI33_3
0.45
ns
LVPECL_33
HSTL_I
0.72
ns
RSDS_25
0.83
ns
0.83
ns
HSTL_III
0.85
ns
RSDS_33
HSTL_I_18
0.69
ns
TMDS_33
0.80
ns
HSTL_II_18
0.83
ns
PPDS_25
0.81
ns
0.81
ns
HSTL_III_18
0.79
ns
PPDS_33
SSTL18_I
0.71
ns
DIFF_HSTL_I_18
0.80
ns
0.98
ns
SSTL18_II
0.71
ns
DIFF_HSTL_II_18
SSTL2_I
0.71
ns
DIFF_HSTL_III_18
1.05
ns
SSTL2_II
0.71
ns
DIFF_HSTL_I
0.77
ns
1.05
ns
SSTL3_I
0.78
ns
DIFF_HSTL_III
SSTL3_II
0.78
ns
DIFF_SSTL18_I
0.76
ns
DIFF_SSTL18_II
0.76
ns
DIFF_SSTL2_I
0.77
ns
DIFF_SSTL2_II
0.77
ns
DIFF_SSTL3_I
1.06
ns
DIFF_SSTL3_II
1.06
ns
Notes:
1.
2.
DS681 (v1.1) February 3, 2009
Product Specification
The numbers in this table are tested using the methodology
presented in Table 26 and are based on the operating
conditions set forth in Table 8, Table 11, and Table 13.
These adjustments are used to convert input path times
originally specified for the LVCMOS25 standard to times that
correspond to other signal standards.
www.xilinx.com
23
R
Output Propagation Times
Table 23: Timing for the IOB Output Path
Speed Grade
-4
Symbol
Description
Conditions
Device
Max
Units
All
3.13
ns
LVCMOS25(2), 12 mA output
drive, Fast slew rate
All
2.91
ns
LVCMOS25(2), 12 mA output
drive, Fast slew rate
All
3.89
ns
9.65
ns
Clock-to-Output Times
TIOCKP
When reading from the Output Flip-Flop
LVCMOS25(2), 12 mA output
(OFF), the time from the active transition at drive, Fast slew rate
the OCLK input to data appearing at the
Output pin
Propagation Times
TIOOP
The time it takes for data to travel from the
IOB’s O input to the Output pin
Set/Reset Times
TIOSRP
Time from asserting the OFF’s SR input to
setting/resetting data at the Output pin
TIOGSRQ
Time from asserting the Global Set Reset
(GSR) input on the
STARTUP_SPARTAN3A primitive to
setting/resetting data at the Output pin
Notes:
1.
2.
24
The numbers in this table are tested using the methodology presented in Table 26 and are based on the operating conditions set forth in
Table 8 and Table 11.
This time requires adjustment whenever a signal standard other than LVCMOS25 with 12 mA drive and Fast slew rate is assigned to the data
Output. When this is true, add the appropriate Output adjustment from Table 25.
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DS681 (v1.1) February 3, 2009
Product Specification
R
Three-State Output Propagation Times
Table 24: Timing for the IOB Three-State Path
Speed Grade
-4
Symbol
Description
Conditions
Device
Max
Units
All
0.76
ns
All
3.06
ns
LVCMOS25, 12 mA
output drive, Fast slew
rate
All
10.36
ns
LVCMOS25, 12 mA
output drive, Fast slew
rate
All
1.86
ns
All
3.82
ns
Synchronous Output Enable/Disable Times
TIOCKHZ
Time from the active transition at the OTCLK input
of the Three-state Flip-Flop (TFF) to when the
Output pin enters the high-impedance state
TIOCKON(2)
Time from the active transition at TFF’s OTCLK
input to when the Output pin drives valid data
LVCMOS25, 12 mA
output drive, Fast slew
rate
Asynchronous Output Enable/Disable Times
TGTS
Time from asserting the Global Three State (GTS)
input on the STARTUP_SPARTAN3A primitive to
when the Output pin enters the high-impedance
state
Set/Reset Times
TIOSRHZ
Time from asserting TFF’s SR input to when the
Output pin enters a high-impedance state
TIOSRON(2)
Time from asserting TFF’s SR input at TFF to
when the Output pin drives valid data
Notes:
1.
2.
The numbers in this table are tested using the methodology presented in Table 26 and are based on the operating conditions set forth in
Table 8 and Table 11.
This time requires adjustment whenever a signal standard other than LVCMOS25 with 12 mA drive and Fast slew rate is assigned to the
data Output. When this is true, add the appropriate Output adjustment from Table 25.
DS681 (v1.1) February 3, 2009
Product Specification
www.xilinx.com
25
R
Output Timing Adjustments
Table 25: Output Timing Adjustments for IOB (Continued)
Table 25: Output Timing Adjustments for IOB
Convert Output Time from
LVCMOS25 with 12mA Drive and
Fast Slew Rate to the Following
Signal Standard (IOSTANDARD)
Add the
Adjustment
Below
Speed Grade
-4
Units
LVCMOS33
Single-Ended Standards
LVTTL
Slow
Fast
QuietIO
26
Convert Output Time from
LVCMOS25 with 12mA Drive and
Fast Slew Rate to the Following
Signal Standard (IOSTANDARD)
Slow
Add the
Adjustment
Below
Speed Grade
-4
Units
2 mA
5.58
ns
3.30
ns
2 mA
5.58
ns
4 mA
4 mA
3.45
ns
6 mA
3.30
ns
2.26
ns
6 mA
3.45
ns
8 mA
8 mA
2.26
ns
12 mA
1.29
ns
12 mA
1.66
ns
16 mA
1.22
ns
24 mA
2.79
ns
2 mA
3.72
ns
16 mA
1.29
ns
24 mA
2.97
ns
2 mA
3.37
ns
4 mA
2.05
ns
2.08
ns
Fast
4 mA
2.27
ns
6 mA
6 mA
2.27
ns
8 mA
0.53
ns
8 mA
0.63
ns
12 mA
0.59
ns
16 mA
0.59
ns
12 mA
0.61
ns
16 mA
0.59
ns
QuietIO
24 mA
0.51
ns
2 mA
27.67
ns
24 mA
0.60
ns
2 mA
27.67
ns
4 mA
27.67
ns
4 mA
27.67
ns
6 mA
27.67
ns
16.71
ns
6 mA
27.67
ns
8 mA
8 mA
16.71
ns
12 mA
16.29
ns
16.18
ns
12.11
ns
12 mA
16.67
ns
16 mA
16 mA
16.22
ns
24 mA
24 mA
12.11
ns
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DS681 (v1.1) February 3, 2009
Product Specification
R
Table 25: Output Timing Adjustments for IOB (Continued)
Convert Output Time from
LVCMOS25 with 12mA Drive and
Fast Slew Rate to the Following
Signal Standard (IOSTANDARD)
LVCMOS25
Slow
Fast
QuietIO
LVCMOS18
Slow
Fast
QuietIO
Add the
Adjustment
Below
Speed Grade
-4
Units
2 mA
5.33
ns
4 mA
2.91
6 mA
8 mA
Table 25: Output Timing Adjustments for IOB (Continued)
Convert Output Time from
LVCMOS25 with 12mA Drive and
Fast Slew Rate to the Following
Signal Standard (IOSTANDARD)
Add the
Adjustment
Below
Speed Grade
-4
Units
2 mA
6.42
ns
ns
4 mA
3.97
ns
2.92
ns
6 mA
3.21
ns
1.23
ns
8 mA
2.53
ns
12 mA
1.23
ns
12 mA
2.06
ns
16 mA
0.91
ns
2 mA
5.83
ns
24 mA
2.31
ns
4 mA
3.05
ns
LVCMOS15
Slow
Fast
2 mA
4.71
ns
6 mA
1.95
ns
4 mA
2.20
ns
8 mA
1.60
ns
6 mA
1.49
ns
12 mA
1.30
ns
8 mA
0.39
ns
2 mA
34.11
ns
12 mA
0
ns
QuietIO
4 mA
25.66
ns
16 mA
0.01
ns
6 mA
24.64
ns
24 mA
0.01
ns
8 mA
22.06
ns
2 mA
25.92
ns
12 mA
20.64
ns
4 mA
25.92
ns
2 mA
7.14
ns
6 mA
25.92
ns
4 mA
4.87
ns
8 mA
15.57
ns
6 mA
5.67
ns
12 mA
15.59
ns
2 mA
6.77
ns
16 mA
14.27
ns
4 mA
5.02
ns
24 mA
11.37
ns
2 mA
5.00
ns
4 mA
3.69
ns
6 mA
2.91
ns
8 mA
2.03
ns
PCI33_3
12 mA
1.57
ns
HSTL_I
16 mA
1.19
ns
HSTL_III
1.16
ns
2 mA
4.12
ns
HSTL_I_18
0.35
ns
4 mA
2.63
ns
HSTL_II_18
0.30
ns
6 mA
1.91
ns
HSTL_III_18
0.47
ns
8 mA
1.06
ns
SSTL18_I
0.40
ns
12 mA
0.83
ns
SSTL18_II
0.30
ns
16 mA
0.63
ns
SSTL2_I
0
ns
2 mA
24.97
ns
SSTL2_II
–0.05
ns
4 mA
24.97
ns
SSTL3_I
0
ns
6 mA
24.08
ns
SSTL3_II
0.17
ns
8 mA
16.43
ns
12 mA
14.52
ns
16 mA
13.41
ns
DS681 (v1.1) February 3, 2009
Product Specification
LVCMOS12
Slow
Fast
QuietIO
www.xilinx.com
6 mA
4.09
ns
2 mA
50.76
ns
4 mA
43.17
ns
6 mA
37.31
ns
0.34
ns
0.86
ns
27
R
Table 25: Output Timing Adjustments for IOB (Continued)
Convert Output Time from
LVCMOS25 with 12mA Drive and
Fast Slew Rate to the Following
Signal Standard (IOSTANDARD)
Add the
Adjustment
Below
Speed Grade
-4
Units
Differential Standards
Table 25: Output Timing Adjustments for IOB (Continued)
Convert Output Time from
LVCMOS25 with 12mA Drive and
Fast Slew Rate to the Following
Signal Standard (IOSTANDARD)
Add the
Adjustment
Below
Speed Grade
-4
Units
DIFF_HSTL_III_18
0.36
ns
ns
LVDS_25
1.50
ns
DIFF_HSTL_I
1.01
LVDS_33
0.47
ns
DIFF_HSTL_III
1.16
ns
BLVDS_25
0.11
ns
DIFF_SSTL18_I
0.49
ns
MINI_LVDS_25
1.11
ns
DIFF_SSTL18_II
0.41
ns
MINI_LVDS_33
0.41
ns
DIFF_SSTL2_I
0.91
ns
DIFF_SSTL2_II
0.11
ns
LVPECL_25
Input Only
DIFF_SSTL3_I
1.18
ns
RSDS_25
1.73
ns
DIFF_SSTL3_II
0.28
ns
RSDS_33
0.64
ns
Notes:
TMDS_33
0.07
ns
1.
PPDS_25
1.28
ns
PPDS_33
0.88
ns
DIFF_HSTL_I_18
0.43
ns
DIFF_HSTL_II_18
0.41
ns
LVPECL_33
2.
The numbers in this table are tested using the methodology
presented in Table 26 and are based on the operating
conditions set forth in Table 8, Table 11, and Table 13.
These adjustments are used to convert output- and
three-state-path times originally specified for the LVCMOS25
standard with 12 mA drive and Fast slew rate to times that
correspond to other signal standards. Do not adjust times that
measure when outputs go into a high-impedance state.
Timing Measurement Methodology
When measuring timing parameters at the programmable
I/Os, different signal standards call for different test
conditions. Table 26 lists the conditions to use for each
standard.
LVCMOS, LVTTL), then RT is set to 1 MΩ to indicate an
open connection, and VT is set to zero. The same
measurement point (VM) that was used at the Input is also
used at the Output.
The method for measuring Input timing is as follows: A
signal that swings between a Low logic level of VL and a
High logic level of VH is applied to the Input under test.
Some standards also require the application of a bias
voltage to the VREF pins of a given bank to properly set the
input-switching threshold. The measurement point of the
Input signal (VM) is commonly located halfway between VL
and VH.
The Output test setup is shown in Figure 8. A termination
voltage VT is applied to the termination resistor RT, the other
end of which is connected to the Output. For each standard,
RT and VT generally take on the standard values
recommended for minimizing signal reflections. If the
standard does not ordinarily use terminations (for example,
28
www.xilinx.com
VT (VREF)
FPGA Output
RT (RREF)
VM (VMEAS)
CL (CREF)
DS312-3_04_102406
Notes:
1.
The names shown in parentheses are
used in the IBIS file.
Figure 8: Output Test Setup
DS681 (v1.1) February 3, 2009
Product Specification
R
Table 26: Test Methods for Timing Measurement at I/Os
Signal Standard
(IOSTANDARD)
Inputs
Inputs and
Outputs
Outputs
VREF (V)
VL (V)
VH (V)
RT (Ω)
VT (V)
VM (V)
LVTTL
-
0
3.3
1M
0
1.4
LVCMOS33
-
0
3.3
1M
0
1.65
LVCMOS25
-
0
2.5
1M
0
1.25
LVCMOS18
-
0
1.8
1M
0
0.9
LVCMOS15
-
0
1.5
1M
0
0.75
LVCMOS12
-
0
1.2
1M
0
0.6
-
Note 3
Note 3
25
0
0.94
25
3.3
2.03
Single-Ended
PCI33_3
Rising
Falling
HSTL_I
0.75
VREF – 0.5
VREF + 0.5
50
0.75
VREF
HSTL_III
0.9
VREF – 0.5
VREF + 0.5
50
1.5
VREF
HSTL_I_18
0.9
VREF – 0.5
VREF + 0.5
50
0.9
VREF
HSTL_II_18
0.9
VREF – 0.5
VREF + 0.5
25
0.9
VREF
HSTL_III_18
1.1
VREF – 0.5
VREF + 0.5
50
1.8
VREF
SSTL18_I
0.9
VREF – 0.5
VREF + 0.5
50
0.9
VREF
SSTL18_II
0.9
VREF – 0.5
VREF + 0.5
25
0.9
VREF
SSTL2_I
1.25
VREF – 0.75
VREF + 0.75
50
1.25
VREF
SSTL2_II
1.25
VREF – 0.75
VREF + 0.75
25
1.25
VREF
SSTL3_I
1.5
VREF – 0.75
VREF + 0.75
50
1.5
VREF
SSTL3_II
1.5
VREF – 0.75
VREF + 0.75
25
1.5
VREF
LVDS_25
-
VICM – 0.125
VICM + 0.125
50
1.2
VICM
LVDS_33
-
VICM – 0.125
VICM + 0.125
50
1.2
VICM
BLVDS_25
-
VICM – 0.125
VICM + 0.125
1M
0
VICM
MINI_LVDS_25
-
VICM – 0.125
VICM + 0.125
50
1.2
VICM
MINI_LVDS_33
-
VICM – 0.125
VICM + 0.125
50
1.2
VICM
LVPECL_25
-
VICM – 0.3
VICM + 0.3
N/A
N/A
VICM
LVPECL_33
-
VICM – 0.3
VICM + 0.3
N/A
N/A
VICM
RSDS_25
-
VICM – 0.1
VICM + 0.1
50
1.2
VICM
RSDS_33
-
VICM – 0.1
VICM + 0.1
50
1.2
VICM
TMDS_33
-
VICM – 0.1
VICM + 0.1
50
3.3
VICM
PPDS_25
-
VICM – 0.1
VICM + 0.1
50
0.8
VICM
PPDS_33
-
VICM – 0.1
VICM + 0.1
50
0.8
VICM
DIFF_HSTL_I
0.75
VREF – 0.5
VREF + 0.5
50
0.75
VREF
DIFF_HSTL_III
0.9
VREF – 0.5
VREF + 0.5
50
1.5
VREF
DIFF_HSTL_I_18
0.9
VREF – 0.5
VREF + 0.5
50
0.9
VREF
DIFF_HSTL_II_18
0.9
VREF – 0.5
VREF + 0.5
50
0.9
VREF
DIFF_HSTL_III_18
1.1
VREF – 0.5
VREF + 0.5
50
1.8
VREF
Differential
DS681 (v1.1) February 3, 2009
Product Specification
www.xilinx.com
29
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Table 26: Test Methods for Timing Measurement at I/Os (Continued)
Signal Standard
(IOSTANDARD)
Inputs
Inputs and
Outputs
Outputs
VREF (V)
VL (V)
VH (V)
RT (Ω)
VT (V)
VM (V)
DIFF_SSTL18_I
0.9
VREF – 0.5
VREF + 0.5
50
0.9
VREF
DIFF_SSTL18_II
0.9
VREF – 0.5
VREF + 0.5
50
0.9
VREF
DIFF_SSTL2_I
1.25
VREF – 0.5
VREF + 0.5
50
1.25
VREF
DIFF_SSTL2_II
1.25
VREF – 0.5
VREF + 0.5
50
1.25
VREF
DIFF_SSTL3_I
1.5
VREF – 0.5
VREF + 0.5
50
1.5
VREF
DIFF_SSTL3_II
1.5
VREF – 0.5
VREF + 0.5
50
1.5
VREF
Notes:
1.
2.
3.
Descriptions of the relevant symbols are as follows:
VREF – The reference voltage for setting the input switching threshold
VICM – The common mode input voltage
VM – Voltage of measurement point on signal transition
VL – Low-level test voltage at Input pin
VH – High-level test voltage at Input pin
RT – Effective termination resistance, which takes on a value of 1 MΩ when no parallel termination is required
VT – Termination voltage
The load capacitance (CL) at the Output pin is 0 pF for all signal standards.
According to the PCI specification.
The capacitive load (CL) is connected between the output
and GND. The Output timing for all standards, as published
in the speed files and the data sheet, is always based on a
CL value of zero. High-impedance probes (less than 1 pF)
are used for all measurements. Any delay that the test
fixture might contribute to test measurements is subtracted
from those measurements to produce the final timing
numbers as published in the speed files and data sheet.
Using IBIS Models to Simulate Load
Conditions in Application
IBIS models permit the most accurate prediction of timing
delays for a given application. The parameters found in the
IBIS model (VREF, RREF, and VMEAS) correspond directly
with the parameters used in Table 26 (VT, RT, and VM). Do
not confuse VREF (the termination voltage) from the IBIS
model with VREF (the input-switching threshold) from the
table. A fourth parameter, CREF, is always zero. The four
parameters describe all relevant output test conditions. IBIS
models are found in the Xilinx development software as well
as at the following link:
Delays for a given application are simulated according to its
specific load conditions as follows:
1. Simulate the desired signal standard with the output
driver connected to the test setup shown in Figure 8.
Use parameter values VT, RT, and VM from Table 26.
CREF is zero.
2. Record the time to VM.
3. Simulate the same signal standard with the output
driver connected to the PCB trace with load. Use the
appropriate IBIS model (including VREF, RREF, CREF,
and VMEAS values) or capacitive value to represent the
load.
4. Record the time to VMEAS.
5. Compare the results of steps 2 and 4. Add (or subtract)
the increase (or decrease) in delay to (or from) the
appropriate Output standard adjustment (Table 25) to
yield the worst-case delay of the PCB trace.
http://www.xilinx.com/xlnx/xil_sw_updates_home.jsp
30
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DS681 (v1.1) February 3, 2009
Product Specification
R
Simultaneously Switching Output Guidelines
Table 27 and Table 28 provide the essential SSO
guidelines. For each device/package combination, Table 27
provides the number of equivalent VCCO/GND pairs. For
each output signal standard and drive strength, Table 28
recommends the maximum number of SSOs, switching in
the same direction, allowed per VCCO/GND pair within an
I/O bank. The guidelines in Table 28 are categorized by
package style, slew rate, and output drive current.
Furthermore, the number of SSOs is specified by I/O bank.
Generally, the left and right I/O banks (Banks 1 and 3)
support higher output drive current.
This section provides guidelines for the recommended
maximum allowable number of Simultaneous Switching
Outputs (SSOs). These guidelines describe the maximum
number of user I/O pins of a given output signal standard
that should simultaneously switch in the same direction,
while maintaining a safe level of switching noise. Meeting
these guidelines for the stated test conditions ensures that
the FPGA operates free from the adverse effects of ground
and power bounce.
Ground or power bounce occurs when a large number of
outputs simultaneously switch in the same direction. The
output drive transistors all conduct current to a common
voltage rail. Low-to-High transitions conduct to the VCCO
rail; High-to-Low transitions conduct to the GND rail. The
resulting cumulative current transient induces a voltage
difference across the inductance that exists between the die
pad and the power supply or ground return. The inductance
is associated with bonding wires, the package lead frame,
and any other signal routing inside the package. Other
variables contribute to SSO noise levels, including stray
inductance on the PCB as well as capacitive loading at
receivers. Any SSO-induced voltage consequently affects
internal switching noise margins and ultimately signal
quality.
Multiply the appropriate numbers from Table 27 and
Table 28 to calculate the maximum number of SSOs
allowed within an I/O bank. Exceeding these SSO
guidelines might result in increased power or ground
bounce, degraded signal integrity, or increased system jitter.
SSOMAX/IO Bank = Table 27 x Table 28
The recommended maximum SSO values assumes that the
FPGA is soldered on the printed circuit board and that the
board uses sound design practices. The SSO values do not
apply for FPGAs mounted in sockets, due to the lead
inductance introduced by the socket.
Ball grid array packages are recommended for applications
with a large number of simultaneously switching outputs.
Table 27: Equivalent VCCO/GND Pairs per Bank
Package Style (Pb-free)
Device
FTG256
FGG400
FGG484
XA3S200A
4
–
–
XA3S400A
4
5
–
XA3S700A
–
5
5
XA3S1400A
–
–
6
DS681 (v1.1) February 3, 2009
Product Specification
www.xilinx.com
31
R
Table 28: Recommended Number of Simultaneously
Switching Outputs per VCCO-GND Pair
(VCCAUX=3.3V)
Signal Standard
(IOSTANDARD)
Package Type
Package Type
FTG256, FGG400, FGG484
FTG256, FGG400, FGG484
Top, Bottom
Left, Right
(Banks 0,2)
(Banks 1,3)
Slow
Fast
QuietIO
32
Signal Standard
(IOSTANDARD)
LVCMOS33
Single-Ended Standards
LVTTL
Table 28: Recommended Number of Simultaneously
Switching Outputs per VCCO-GND Pair
(VCCAUX=3.3V)(Continued)
Slow
Top, Bottom
Left, Right
(Banks 0,2)
(Banks 1,3)
2
76
76
46
46
2
60
60
4
4
41
41
6
27
27
20
20
6
29
29
8
8
22
22
12
13
13
10
10
12
13
13
16
16
11
11
24
–
9
24
9
9
2
10
10
8
8
Fast
2
10
10
4
4
6
6
6
5
5
4
4
6
5
5
8
8
3
3
12
4
4
16
2
2
12
3
3
16
3
3
QuietIO
24
–
2
2
76
76
24
2
2
2
80
80
4
46
46
4
48
48
6
32
32
26
26
6
36
36
8
8
27
27
12
18
18
14
14
–
10
12
16
16
16
16
13
13
24
24
12
12
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DS681 (v1.1) February 3, 2009
Product Specification
R
Table 28: Recommended Number of Simultaneously
Switching Outputs per VCCO-GND Pair
(VCCAUX=3.3V)(Continued)
Signal Standard
(IOSTANDARD)
LVCMOS25
Slow
Fast
QuietIO
LVCMOS18
Slow
Fast
QuietIO
Table 28: Recommended Number of Simultaneously
Switching Outputs per VCCO-GND Pair
(VCCAUX=3.3V)(Continued)
Package Type
Package Type
FTG256, FGG400, FGG484
FTG256, FGG400, FGG484
Top, Bottom
Left, Right
(Banks 0,2)
(Banks 1,3)
Signal Standard
(IOSTANDARD)
LVCMOS15
Slow
Top, Bottom
Left, Right
(Banks 0,2)
(Banks 1,3)
2
76
76
2
55
55
4
46
46
4
31
31
6
33
33
6
18
18
8
24
24
8
–
15
12
18
18
16
–
11
24
–
2
4
12
–
10
2
25
25
7
4
10
10
18
18
6
6
6
14
14
8
–
4
6
6
6
8
6
6
Fast
QuietIO
12
–
3
2
70
70
12
3
3
4
40
40
16
–
3
6
31
31
24
–
2
8
–
31
2
76
76
12
–
20
4
60
60
2
40
40
6
48
48
4
–
25
8
36
36
6
–
18
12
36
36
2
31
31
16
–
36
4
–
13
24
–
8
2
64
64
4
34
6
22
LVCMOS12
Slow
Fast
6
–
9
2
55
55
34
4
–
36
22
6
–
36
QuietIO
8
18
18
PCI33_3
16
16
12
–
13
HSTL_I
–
20
16
–
10
HSTL_III
–
8
2
18
18
HSTL_I_18
17
17
4
9
9
HSTL_II_18
–
5
6
7
7
HSTL_III_18
10
8
8
4
4
SSTL18_I
7
15
12
–
4
SSTL18_II
–
9
16
–
3
SSTL2_I
18
18
2
64
64
SSTL2_II
–
9
4
64
64
SSTL3_I
8
10
6
48
48
SSTL3_II
6
7
8
36
36
12
–
36
16
–
24
DS681 (v1.1) February 3, 2009
Product Specification
www.xilinx.com
33
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Table 28: Recommended Number of Simultaneously
Switching Outputs per VCCO-GND Pair
(VCCAUX=3.3V)(Continued)
Signal Standard
(IOSTANDARD)
Table 28: Recommended Number of Simultaneously
Switching Outputs per VCCO-GND Pair
(VCCAUX=3.3V)(Continued)
Package Type
Package Type
FTG256, FGG400, FGG484
FTG256, FGG400, FGG484
Top, Bottom
Left, Right
(Banks 0,2)
(Banks 1,3)
Signal Standard
(IOSTANDARD)
Top, Bottom
Left, Right
(Banks 0,2)
(Banks 1,3)
Differential Standards (Number of I/O Pairs or Channels)
DIFF_HSTL_I
–
10
LVDS_25
22
–
DIFF_HSTL_III
–
4
LVDS_33
27
–
DIFF_HSTL_I_18
8
8
BLVDS_25
4
4
DIFF_HSTL_II_18
–
2
MINI_LVDS_25
22
–
DIFF_HSTL_III_18
5
4
MINI_LVDS_33
27
–
DIFF_SSTL18_I
3
7
DIFF_SSTL18_II
–
4
LVPECL_25
LVPECL_33
DIFF_SSTL2_I
9
9
22
–
DIFF_SSTL2_II
–
4
RSDS_33
27
–
DIFF_SSTL3_I
4
5
TMDS_33
27
–
DIFF_SSTL3_II
3
3
PPDS_25
22
–
Notes:
PPDS_33
27
–
1.
RSDS_25
2.
3.
34
Not all I/O standards are supported on all I/O banks. The left and
right banks (I/O banks 1 and 3) support higher output drive
current than the top and bottom banks (I/O banks 0 and 2).
Similarly, true differential output standards, such as LVDS, RSDS,
PPDS, miniLVDS, and TMDS, are only supported in top or bottom
banks (I/O banks 0 and 2). Refer to UG331: Spartan-3
Generation FPGA User Guide for additional information.
The numbers in this table are recommendations that assume
sound board lay out practice. Test limits are the VIL/VIH voltage
limits for the respective I/O standard.
If more than one signal standard is assigned to the I/Os of a given
bank, refer to XAPP689: Managing Ground Bounce in Large
FPGAs for information on how to perform weighted average SSO
calculations.
www.xilinx.com
DS681 (v1.1) February 3, 2009
Product Specification
R
Configurable Logic Block (CLB) Timing
Table 29: CLB (SLICEM) Timing
Speed Grade
-4
Symbol
Description
Min
Max
Units
–
0.68
ns
Clock-to-Output Times
TCKO
When reading from the FFX (FFY) Flip-Flop, the time from the active
transition at the CLK input to data appearing at the XQ (YQ) output
Setup Times
TAS
Time from the setup of data at the F or G input to the active transition at
the CLK input of the CLB
0.36
–
ns
TDICK
Time from the setup of data at the BX or BY input to the active transition
at the CLK input of the CLB
1.88
–
ns
TAH
Time from the active transition at the CLK input to the point where data
is last held at the F or G input
0
–
ns
TCKDI
Time from the active transition at the CLK input to the point where data
is last held at the BX or BY input
0
–
ns
Hold Times
Clock Timing
TCH
The High pulse width of the CLB’s CLK signal
0.75
–
ns
TCL
The Low pulse width of the CLK signal
0.75
–
ns
FTOG
Toggle frequency (for export control)
0
667
MHz
The time it takes for data to travel from the CLB’s F (G) input to the X (Y)
output
–
0.71
ns
1.61
–
ns
Propagation Times
TILO
Set/Reset Pulse Width
TRPW_CLB
The minimum allowable pulse width, High or Low, to the CLB’s SR input
Notes:
1.
The numbers in this table are based on the operating conditions set forth in Table 8.
DS681 (v1.1) February 3, 2009
Product Specification
www.xilinx.com
35
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Table 30: CLB Distributed RAM Switching Characteristics
Speed Grade
-4
Symbol
Description
Min
Max
Units
–
2.01
ns
Clock-to-Output Times
TSHCKO
Time from the active edge at the CLK input to data appearing on the
distributed RAM output
Setup Times
TDS
Setup time of data at the BX or BY input before the active transition at the CLK
input of the distributed RAM
–0.02
–
ns
TAS
Setup time of the F/G address inputs before the active transition at the CLK
input of the distributed RAM
0.36
–
ns
TWS
Setup time of the write enable input before the active transition at the CLK
input of the distributed RAM
0.59
–
ns
TDH
Hold time of the BX and BY data inputs after the active transition at the CLK
input of the distributed RAM
0.13
–
ns
TAH, TWH
Hold time of the F/G address inputs or the write enable input after the active
transition at the CLK input of the distributed RAM
0.01
–
ns
Minimum High or Low pulse width at CLK input
1.01
–
ns
Hold Times
Clock Pulse Width
TWPH, TWPL
Table 31: CLB Shift Register Switching Characteristics
Speed Grade
-4
Symbol
Description
Min
Max
Units
–
4.82
ns
Setup time of data at the BX or BY input before the active transition at the CLK
input of the shift register
0.18
–
ns
Hold time of the BX or BY data input after the active transition at the CLK input
of the shift register
0.16
–
ns
Minimum High or Low pulse width at CLK input
1.01
–
ns
Clock-to-Output Times
TREG
Time from the active edge at the CLK input to data appearing on the shift
register output
Setup Times
TSRLDS
Hold Times
TSRLDH
Clock Pulse Width
TWPH, TWPL
36
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DS681 (v1.1) February 3, 2009
Product Specification
R
Clock Buffer/Multiplexer Switching Characteristics
Table 32: Clock Distribution Switching Characteristics
Maximum
Speed Grade
Description
Symbol
Minimum
-4
Units
Global clock buffer (BUFG, BUFGMUX, BUFGCE) I input to O-output delay
TGIO
–
0.23
ns
Global clock multiplexer (BUFGMUX) select S-input setup to I0 and I1
inputs. Same as BUFGCE enable CE-input
TGSI
–
0.63
ns
FBUFG
0
333
MHz
Frequency of signals distributed on global buffers (all sides)
Notes:
The numbers in this table are based on the operating conditions set forth in Table 8.
18 x 18 Embedded Multiplier Timing
Table 33: 18 x 18 Embedded Multiplier Timing
Speed Grade
-4
Symbol
Description
Min
Max
Units
–
4.88
ns
Combinatorial Delay
TMULT
Combinational multiplier propagation delay from the A and B inputs to the P outputs,
assuming 18-bit inputs and a 36-bit product (AREG, BREG, and PREG registers
unused)
Clock-to-Output Times
TMSCKP_P
Clock-to-output delay from the active transition of the CLK input to valid data appearing
on the P outputs when using the PREG register(2,3)
–
1.30
ns
TMSCKP_A
TMSCKP_B
Clock-to-output delay from the active transition of the CLK input to valid data appearing
on the P outputs when using either the AREG or BREG register(2,4)
–
4.97
ns
TMSDCK_P
Data setup time at the A or B input before the active transition at the CLK when using
only the PREG output register (AREG, BREG registers unused)(3)
3.98
–
ns
TMSDCK_A
Data setup time at the A input before the active transition at the CLK when using the
AREG input register(4)
0.00
–
ns
TMSDCK_B
Data setup time at the B input before the active transition at the CLK when using the
BREG input register(4)
0.00
–
ns
TMSCKD_P
Data hold time at the A or B input after the active transition at the CLK when using only
the PREG output register (AREG, BREG registers unused)(3)
0.00
–
ns
TMSCKD_A
Data hold time at the A input after the active transition at the CLK when using the AREG
input register(4)
0.45
–
ns
TMSCKD_B
Data hold time at the B input after the active transition at the CLK when using the BREG
input register(4)
0.45
–
ns
Setup Times
Hold Times
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37
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Table 33: 18 x 18 Embedded Multiplier Timing (Continued)
Speed Grade
-4
Symbol
Description
Min
Max
Units
Internal operating frequency for a two-stage 18x18 multiplier using the AREG and BREG
input registers and the PREG output register(1)
0
250
MHz
Clock Frequency
FMULT
Notes:
1.
2.
3.
4.
5.
Combinational delay is less and pipelined performance is higher when multiplying input data with less than 18 bits.
The PREG register is typically used in both single-stage and two-stage pipelined multiplier implementations.
The PREG register is typically used when inferring a single-stage multiplier.
Input registers AREG or BREG are typically used when inferring a two-stage multiplier.
The numbers in this table are based on the operating conditions set forth in Table 8.
Block RAM Timing
Table 34: Block RAM Timing
Speed Grade
-4
Symbol
Description
Min
Max
Units
When reading from block RAM, the delay from the active transition at the CLK input
to data appearing at the DOUT output
–
2.49
ns
TRCCK_ADDR Setup time for the ADDR inputs before the active transition at the CLK input of the
block RAM
0.36
–
ns
TRDCK_DIB
Setup time for data at the DIN inputs before the active transition at the CLK input of
the block RAM
0.31
–
ns
TRCCK_ENB
Setup time for the EN input before the active transition at the CLK input of the block
RAM
0.77
–
ns
TRCCK_WEB
Setup time for the WE input before the active transition at the CLK input of the block
RAM
1.26
–
ns
TRCKC_ADDR Hold time on the ADDR inputs after the active transition at the CLK input
0
–
ns
TRCKD_DIB
Hold time on the DIN inputs after the active transition at the CLK input
0
–
ns
TRCKC_ENB
Hold time on the EN input after the active transition at the CLK input
0
–
ns
TRCKC_WEB
Hold time on the WE input after the active transition at the CLK input
0
–
ns
Clock-to-Output Times
TRCKO
Setup Times
Hold Times
Clock Timing
TBPWH
High pulse width of the CLK signal
1.79
–
ns
TBPWL
Low pulse width of the CLK signal
1.79
–
ns
0
280
MHz
Clock Frequency
FBRAM
Block RAM clock frequency
Notes:
1.
38
The numbers in this table are based on the operating conditions set forth in Table 8.
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DS681 (v1.1) February 3, 2009
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Digital Clock Manager Timing
For specification purposes, the DCM consists of three key
components: the Delay-Locked Loop (DLL), the Digital
Frequency Synthesizer (DFS), and the Phase Shifter (PS).
Aspects of DLL operation play a role in all DCM
applications. All such applications inevitably use the CLKIN
and the CLKFB inputs connected to either the CLK0 or the
CLK2X feedback, respectively. Thus, specifications in the
DLL tables (Table 35 and Table 36) apply to any application
that only employs the DLL component. When the DFS
and/or the PS components are used together with the DLL,
then the specifications listed in the DFS and PS tables
(Table 37 through Table 40) supersede any corresponding
ones in the DLL tables. DLL specifications that do not
change with the addition of DFS or PS functions are
presented in Table 35 and Table 36.
Period jitter and cycle-cycle jitter are two of many different
ways of specifying clock jitter. Both specifications describe
statistical variation from a mean value.
Period jitter is the worst-case deviation from the ideal clock
period over a collection of millions of samples. In a
histogram of period jitter, the mean value is the clock period.
Cycle-cycle jitter is the worst-case difference in clock period
between adjacent clock cycles in the collection of clock
periods sampled. In a histogram of cycle-cycle jitter, the
mean value is zero.
Delay-Locked Loop
Table 35: Recommended Operating Conditions for the DLL
Speed Grade
-4
Symbol
Description
Min
Max
Units
5(2)
250(3)
MHz
Input Frequency Ranges
FCLKIN
CLKIN_FREQ_DLL
Frequency of the CLKIN clock input
Input Pulse Requirements
CLKIN_PULSE
CLKIN pulse width as a percentage
of the CLKIN period
Input Clock Jitter Tolerance and Delay Path
CLKIN_CYC_JITT_DLL_LF
CLKIN_CYC_JITT_DLL_HF
FCLKIN < 150 MHz
40%
60%
–
FCLKIN > 150 MHz
45%
55%
–
FCLKIN < 150 MHz
–
±300
ps
FCLKIN > 150 MHz
–
±150
ps
Variation(4)
Cycle-to-cycle jitter at the CLKIN
input
CLKIN_PER_JITT_DLL
Period jitter at the CLKIN input
–
±1
ns
CLKFB_DELAY_VAR_EXT
Allowable variation of off-chip feedback delay from the DCM
output to the CLKFB input
–
±1
ns
Notes:
1.
2.
3.
4.
5.
DLL specifications apply when any of the DLL outputs (CLK0, CLK90, CLK180, CLK270, CLK2X, CLK2X180, or CLKDV) are in use.
The DFS, when operating independently of the DLL, supports lower FCLKIN frequencies. See Table 37.
To support double the maximum effective FCLKIN limit, set the CLKIN_DIVIDE_BY_2 attribute to TRUE. This attribute divides the
incoming clock period by two as it enters the DCM. The CLK2X output reproduces the clock frequency provided on the CLKIN input.
CLKIN input jitter beyond these limits might cause the DCM to lose lock.
The DCM specifications are guaranteed when both adjacent DCMs are locked.
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Table 36: Switching Characteristics for the DLL
Speed Grade
-4
Symbol
Description
Device
Min
Max
Units
All
5
250
MHz
Output Frequency Ranges
CLKOUT_FREQ_CLK0
Frequency for the CLK0 and CLK180 outputs
CLKOUT_FREQ_CLK90
Frequency for the CLK90 and CLK270 outputs
5
200
MHz
CLKOUT_FREQ_2X
Frequency for the CLK2X and CLK2X180 outputs
10
334
MHz
CLKOUT_FREQ_DV
Frequency for the CLKDV output
0.3125
166
MHz
Output Clock Jitter(2,3,4)
CLKOUT_PER_JITT_0
Period jitter at the CLK0 output
–
±100
ps
CLKOUT_PER_JITT_90
Period jitter at the CLK90 output
–
±150
ps
CLKOUT_PER_JITT_180
Period jitter at the CLK180 output
–
±150
ps
CLKOUT_PER_JITT_270
Period jitter at the CLK270 output
–
±150
ps
CLKOUT_PER_JITT_2X
Period jitter at the CLK2X and CLK2X180 outputs
±[0.5%
of CLKIN
period
+ 100]
ps
–
–
±150
ps
±[0.5%
of CLKIN
period
+ 100]
ps
–
±[1% of
CLKIN
period
+ 350]
ps
–
–
±150
ps
±[1% of
CLKIN
period
+ 100]
ps
–
±[1% of
CLKIN
period
+ 150]
ps
–
–
5
ms
600
μs
35
ps
All
CLKOUT_PER_JITT_DV1
Period jitter at the CLKDV output when performing integer division
CLKOUT_PER_JITT_DV2
Period jitter at the CLKDV output when performing non-integer division
Duty Cycle(4)
CLKOUT_DUTY_CYCLE_DLL Duty cycle variation for the CLK0, CLK90, CLK180, CLK270, CLK2X,
CLK2X180, and CLKDV outputs, including the BUFGMUX and clock tree
duty-cycle distortion
All
Phase Alignment(4)
CLKIN_CLKFB_PHASE
Phase offset between the CLKIN and CLKFB inputs
CLKOUT_PHASE_DLL
Phase offset between DLL outputs
All
CLK0 to CLK2X
(not CLK2X180)
All others
Lock Time
LOCK_DLL(3)
When using the DLL alone: The time
from deassertion at the DCM’s Reset
input to the rising transition at its
LOCKED output. When the DCM is
locked, the CLKIN and CLKFB signals
are in phase
5 MHz < FCLKIN < 15 MHz
All
FCLKIN > 15 MHz
–
Delay Lines
DCM_DELAY_STEP(5)
Finest delay resolution, averaged over all steps
All
15
Notes:
1.
2.
3.
4.
5.
40
The numbers in this table are based on the operating conditions set forth in Table 8 and Table 35.
Indicates the maximum amount of output jitter that the DCM adds to the jitter on the CLKIN input.
For optimal jitter tolerance and faster lock time, use the CLKIN_PERIOD attribute.
Some jitter and duty-cycle specifications include 1% of input clock period or 0.01 UI. For example, the data sheet specifies a maximum
jitter of “±[1% of CLKIN period + 150]”. Assume the CLKIN frequency is 100 MHz. The equivalent CLKIN period is 10 ns and 1% of 10 ns
is 0.1 ns or 100 ps. According to the data sheet, the maximum jitter is ±[100 ps + 150 ps] = ±250ps.
The typical delay step size is 23 ps.
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Digital Frequency Synthesizer
Table 37: Recommended Operating Conditions for the DFS
Speed Grade
-4
Symbol
Description
Min
Max
Units
0.200
333
MHz
FCLKFX < 150 MHz
–
±300
ps
FCLKFX > 150 MHz
–
±150
ps
–
±1
ns
Input Frequency Ranges(2)
FCLKIN
CLKIN_FREQ_FX
Frequency for the CLKIN input
Input Clock Jitter Tolerance(3)
CLKIN_CYC_JITT_FX_LF
CLKIN_CYC_JITT_FX_HF
Cycle-to-cycle jitter at the CLKIN
input, based on CLKFX output
frequency
CLKIN_PER_JITT_FX
Period jitter at the CLKIN input
Notes:
1.
2.
3.
DFS specifications apply when either of the DFS outputs (CLKFX or CLKFX180) are used.
If both DFS and DLL outputs are used on the same DCM, follow the more restrictive CLKIN_FREQ_DLL specifications
in Table 35.
CLKIN input jitter beyond these limits may cause the DCM to lose lock.
Table 38: Switching Characteristics for the DFS
Speed Grade
-4
Symbol
Description
Device
Min
Max
Units
Frequency for the CLKFX and CLKFX180 outputs
All
5
320
MHz
Period jitter at the CLKFX and CLKFX180
outputs.
All
Typ
Max
Output Frequency Ranges
CLKOUT_FREQ_FX(2)
Output Clock Jitter(3,4)
CLKOUT_PER_JITT_FX
CLKIN
≤ 20 MHz
CLKIN
> 20 MHz
Use the
Spartan-3A Jitter
Calculator:
www.xilinx.com/s
upport/document
ation/data_sheets
/s3a_jitter_calc.zi
p
ps
±[1% of ±[1% of
CLKFX CLKFX
period
period
+ 100]
+ 200]
ps
±[1% of
CLKFX
period
+ 350]
ps
–
–
±200
ps
ps
–
±[1% of
CLKFX
period
+ 200]
Duty Cycle(5,6)
CLKOUT_DUTY_CYCLE_FX
Duty cycle precision for the CLKFX and CLKFX180 outputs,
including the BUFGMUX and clock tree duty-cycle distortion
All
CLKOUT_PHASE_FX
Phase offset between the DFS CLKFX output and the DLL CLK0
output when both the DFS and DLL are used
All
CLKOUT_PHASE_FX180
Phase offset between the DFS CLKFX180 output and the DLL
CLK0 output when both the DFS and DLL are used
All
Phase Alignment(6)
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Table 38: Switching Characteristics for the DFS (Continued)
Speed Grade
-4
Symbol
Description
Device
Min
Max
Units
The time from deassertion at the DCM’s
5 MHz < FCLKIN
Reset input to the rising transition at its
< 15 MHz
LOCKED output. The DFS asserts LOCKED
F
when the CLKFX and CLKFX180 signals are CLKIN > 15 MHz
valid. If using both the DLL and the DFS, use
the longer locking time.
All
–
5
ms
450
μs
Lock Time
LOCK_FX(2, 3)
–
Notes:
1.
2.
3.
4.
5.
6.
The numbers in this table are based on the operating conditions set forth in Table 8 and Table 37.
DFS performance requires the additional logic automatically added by ISE 9.1i and later software revisions.
For optimal jitter tolerance and faster lock time, use the CLKIN_PERIOD attribute.
Maximum output jitter is characterized within a reasonable noise environment (40 SSOs and 25% CLB switching) on an
XC3S1400A FPGA. Output jitter strongly depends on the environment, including the number of SSOs, the output drive
strength, CLB utilization, CLB switching activities, switching frequency, power supply and PCB design. The actual
maximum output jitter depends on the system application.
The CLKFX and CLKFX180 outputs always have an approximate 50% duty cycle.
Some duty-cycle and alignment specifications include a percentage of the CLKFX output period. For example, the data
sheet specifies a maximum CLKFX jitter of “±[1% of CLKFX period + 200]”. Assume the CLKFX output frequency is 100
MHz. The equivalent CLKFX period is 10 ns and 1% of 10 ns is 0.1 ns or 100 ps. According to the data sheet, the
maximum jitter is ±[100 ps + 200 ps] = ±300 ps.
Phase Shifter
Table 39: Recommended Operating Conditions for the PS in Variable Phase Mode
Speed Grade
-4
Symbol
Description
Min
Max
Units
1
167
MHz
40%
60%
–
Operating Frequency Ranges
PSCLK_FREQ
(FPSCLK)
Frequency for the PSCLK input
Input Pulse Requirements
PSCLK_PULSE
PSCLK pulse width as a percentage of the PSCLK period
Table 40: Switching Characteristics for the PS in Variable Phase Mode
Symbol
Description
Phase Shift Amount
Units
Maximum allowed number of
CLKIN < 60 MHz
DCM_DELAY_STEP steps for a given
CLKIN clock period, where T = CLKIN CLKIN ≥ 60 MHz
clock period in ns. If using
CLKIN_DIVIDE_BY_2 = TRUE,
double the clock effective clock
period.
±[INTEGER(10 • (TCLKIN – 3 ns))]
steps
Phase Shifting Range
MAX_STEPS(2)
±[INTEGER(15 • (TCLKIN – 3 ns))]
FINE_SHIFT_RANGE_MIN
Minimum guaranteed delay for variable phase shifting
±[MAX_STEPS •
DCM_DELAY_STEP_MIN]
ns
FINE_SHIFT_RANGE_MAX
Maximum guaranteed delay for variable phase shifting
±[MAX_STEPS •
DCM_DELAY_STEP_MAX]
ns
Notes:
1. The numbers in this table are based on the operating conditions set forth in Table 8 and Table 39.
2. The maximum variable phase shift range, MAX_STEPS, is only valid when the DCM is has no initial fixed phase shifting, that is, the
PHASE_SHIFT attribute is set to 0.
3. The DCM_DELAY_STEP values are provided at the bottom of Table 36.
42
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Miscellaneous DCM Timing
Table 41: Miscellaneous DCM Timing
Symbol
Description
Min
Max
Units
DCM_RST_PW_MIN
Minimum duration of a RST pulse width
3
–
CLKIN
cycles
DCM_RST_PW_MAX(2)
Maximum duration of a RST pulse width
N/A
N/A
seconds
N/A
N/A
seconds
N/A
N/A
minutes
N/A
N/A
minutes
DCM_CONFIG_LAG_TIME(3)
Maximum duration from VCCINT applied to FPGA
configuration successfully completed (DONE pin goes High)
and clocks applied to DCM DLL
Notes:
1.
2.
3.
This limit only applies to applications that use the DCM DLL outputs (CLK0, CLK90, CLK180, CLK270, CLK2X, CLK2X180, and CLKDV).
The DCM DFS outputs (CLKFX, CLKFX180) are unaffected.
This specification is equivalent to the Virtex®-4 DCM_RESET specification. This specification does not apply for Spartan-3A FPGAs.
This specification is equivalent to the Virtex-4 TCONFIG specification. This specification does not apply for Spartan-3A FPGAs.
DNA Port Timing
Table 42: DNA_PORT Interface Timing
Symbol
Description
Min
Max
Units
TDNASSU
Setup time on SHIFT before the rising edge of CLK
1.0
–
ns
TDNASH
Hold time on SHIFT after the rising edge of CLK
0.5
–
ns
TDNADSU
Setup time on DIN before the rising edge of CLK
1.0
–
ns
TDNADH
Hold time on DIN after the rising edge of CLK
0.5
–
ns
TDNARSU
Setup time on READ before the rising edge of CLK
5.0
10,000
ns
TDNARH
Hold time on READ after the rising edge of CLK
0
–
ns
0.5
1.5
ns
TDNADCKO
Clock-to-output delay on DOUT after rising edge of CLK
TDNACLKF
CLK frequency
0
100
MHz
TDNACLKL
CLK High time
1.0
∞
ns
TDNACLKH
CLK Low time
1.0
∞
ns
Notes:
1.
The minimum READ pulse width is 5 ns, the maximum READ pulse width is 10 μs.
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Suspend Mode Timing
Entering Suspend Mode
Exiting Suspend Mode
sw_gwe_cycle
sw_gts_cycle
SUSPEND Input
tSUSPENDHIGH_AWAKE
tSUSPENDLOW_AWAKE
AWAKE Output
tAWAKE_GWE
tSUSPEND_GWE
Flip-Flops, Block RAM,
Distributed RAM
Write Protected
tAWAKE_GTS
tSUSPEND_GTS
FPGA Outputs
Defined by SUSPEND constraint
tSUSPEND_DISABLE
FPGA Inputs,
Interconnect
tSUSPEND_ENABLE
Blocked
DS610-3_08_061207
Figure 9: Suspend Mode Timing
Table 43: Suspend Mode Timing Parameters
Symbol
Description
Min
Typ
Max
Units
–
7
–
ns
+160
+300
+600
ns
Entering Suspend Mode
TSUSPENDHIGH_AWAKE Rising edge of SUSPEND pin to falling edge of AWAKE pin without glitch filter
(suspend_filter:No)
TSUSPENDFILTER
Adjustment to SUSPEND pin rising edge parameters when glitch filter
enabled (suspend_filter:Yes)
TSUSPEND_GWE
Rising edge of SUSPEND pin until FPGA output pins drive their defined
SUSPEND constraint behavior
–
10
–
ns
TSUSPEND_GTS
Rising edge of SUSPEND pin to write-protect lock on all writable clocked
elements
–
<5
–
ns
TSUSPEND_DISABLE
Rising edge of the SUSPEND pin to FPGA input pins and interconnect
disabled
–
340
–
ns
Exiting Suspend Mode
TSUSPENDLOW_AWAKE
Falling edge of the SUSPEND pin to rising edge of the AWAKE pin. Does not
include DCM lock time.
–
4 to 108
–
μs
TSUSPEND_ENABLE
Falling edge of the SUSPEND pin to FPGA input pins and interconnect
re-enabled
–
3.7 to
109
–
μs
TAWAKE_GWE1
Rising edge of the AWAKE pin until write-protect lock released on all writable
clocked elements, using sw_clk:InternalClock and sw_gwe_cycle:1.
–
67
–
ns
TAWAKE_GWE512
Rising edge of the AWAKE pin until write-protect lock released on all writable
clocked elements, using sw_clk:InternalClock and sw_gwe_cycle:512.
–
14
–
μs
TAWAKE_GTS1
Rising edge of the AWAKE pin until outputs return to the behavior described
in the FPGA application, using sw_clk:InternalClock and sw_gts_cycle:1.
–
57
–
ns
TAWAKE_GTS512
Rising edge of the AWAKE pin until outputs return to the behavior described
in the FPGA application, using sw_clk:InternalClock and
sw_gts_cycle:512.
–
14
–
μs
Notes:
1.
2.
44
These parameters based on characterization.
For information on using the Spartan-3A Suspend feature, see XAPP480: Using Suspend Mode in Spartan-3 Generation FPGAs.
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Configuration and JTAG Timing
General Configuration Power-On/Reconfigure Timing
1.2V
VCCINT
(Supply)
1.0V
VCCAUX
(Supply)
2.0V
VCCO Bank 2
(Supply)
1.0V
2.5V
or
3.3V
TPOR
PROG_B
(Input)
TPROG
INIT_B
(Open-Drain)
TPL
TICCK
CCLK
(Output)
DS529-3_01_112906
Notes:
1.
2.
3.
The VCCINT, VCCAUX, and VCCO supplies can be applied in any order.
The Low-going pulse on PROG_B is optional after power-on.
The rising edge of INIT_B samples the voltage levels applied to the mode pins (M0 - M2).
Figure 10: Waveforms for Power-On and the Beginning of Configuration
Table 44: Power-On Timing and the Beginning of Configuration
-4 Speed Grade
Symbol
Description
Device
TPOR(2)
The time from the application of VCCINT, VCCAUX, and VCCO
Bank 2 supply voltage ramps (whichever occurs last) to the
rising transition of the INIT_B pin
TPROG
The width of the low-going pulse on the PROG_B pin
TPL(2)
The time from the rising edge of the PROG_B pin to the
rising transition on the INIT_B pin
Min
Max
Units
All
–
18
ms
All
0.5
-
μs
XA3S200A
–
0.5
ms
XA3S400A
–
1
ms
XA3S700A
–
2
ms
–
2
ms
TINIT
Minimum Low pulse width on INIT_B output
All
250
–
ns
TICCK(3)
The time from the rising edge of the INIT_B pin to the
generation of the configuration clock signal at the CCLK
output pin
All
0.5
4
μs
XA3S1400A
Notes:
1.
2.
3.
The numbers in this table are based on the operating conditions set forth in Table 8. This means power must be applied to all VCCINT, VCCO,
and VCCAUX lines.
Power-on reset and the clearing of configuration memory occurs during this period.
This specification applies only to the Master Serial, SPI, and BPI modes.
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45
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Configuration Clock (CCLK) Characteristics
Table 45: Master Mode CCLK Output Period by ConfigRate Option Setting
ConfigRate
Setting
Temperature
Range
Minimum
Maximum
Units
1
(power-on value)
I-Grade &
Q-Grade
1,053
2,500
ns
TCCLK3
3
I-Grade &
Q-Grade
351
833
ns
TCCLK6
6
I-Grade &
Q-Grade
174
417
ns
TCCLK7
7
I-Grade &
Q-Grade
148
357
ns
TCCLK8
8
I-Grade &
Q-Grade
132
313
ns
TCCLK10
10
I-Grade &
Q-Grade
104
250
ns
TCCLK12
12
I-Grade &
Q-Grade
87
208
ns
TCCLK13
13
I-Grade &
Q-Grade
80
192
ns
TCCLK17
17
I-Grade &
Q-Grade
61
147
ns
TCCLK22
22
I-Grade &
Q-Grade
47
114
ns
TCCLK25
25
I-Grade &
Q-Grade
42
100
ns
TCCLK27
27
I-Grade &
Q-Grade
35
93
ns
TCCLK33
33
I-Grade &
Q-Grade
31
76
ns
TCCLK44
44
I-Grade &
Q-Grade
24
57
ns
TCCLK50
50
I-Grade &
Q-Grade
19
50
ns
TCCLK100
100
I-Grade &
Q-Grade
9.4
25
ns
Symbol
TCCLK1
Description
CCLK clock period by
ConfigRate setting
Notes:
1.
46
Set the ConfigRate option value when generating a configuration bitstream.
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Table 46: Master Mode CCLK Output Frequency by ConfigRate Option Setting
Description
ConfigRate
Setting
Temperature
Range
Minimum
Maximum
Units
Equivalent CCLK clock frequency
by ConfigRate setting
1
(power-on value)
I-Grade &
Q-Grade
0.40
0.95
MHz
FCCLK3
3
I-Grade &
Q-Grade
1.20
2.85
MHz
FCCLK6
6
I-Grade &
Q-Grade
2.40
5.74
MHz
FCCLK7
7
I-Grade &
Q-Grade
2.80
6.74
MHz
FCCLK8
8
I-Grade &
Q-Grade
3.20
7.58
MHz
FCCLK10
10
I-Grade &
Q-Grade
4.00
9.65
MHz
FCCLK12
12
I-Grade &
Q-Grade
4.80
11.48
MHz
FCCLK13
13
I-Grade &
Q-Grade
5.20
12.49
MHz
FCCLK17
17
I-Grade &
Q-Grade
6.80
16.33
MHz
FCCLK22
22
I-Grade &
Q-Grade
8.80
21.23
MHz
FCCLK25
25
I-Grade &
Q-Grade
10.00
23.59
MHz
FCCLK27
27
I-Grade &
Q-Grade
10.80
28.31
MHz
FCCLK33
33
I-Grade &
Q-Grade
13.20
32.67
MHz
FCCLK44
44
I-Grade &
Q-Grade
17.60
42.47
MHz
FCCLK50
50
I-Grade &
Q-Grade
20.00
53.08
MHz
FCCLK100
100
I-Grade &
Q-Grade
40.00
106.16
MHz
Symbol
FCCLK1
Table 47: Master Mode CCLK Output Minimum Low and High Time
ConfigRate Setting
Symbol
TMCCL,
TMCCH
Description
Master Mode
CCLK
Minimum Low
and High Time
I-Grade &
Q-Grade
1
3
474
158
6
7
8
10
12
13
17
22
25
27
33
44
78.4 66.8 59.3 46.6 39.2 36.0 27.6 21.2 19.1 15.9 13.8 10.6
50
100
Units
8.5
4.2
ns
Table 48: Slave Mode CCLK Input Low and High Time
Symbol
TSCCL,
TSCCH
Description
CCLK Low and High time
DS681 (v1.1) February 3, 2009
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Min
Max
Units
5
∞
ns
47
R
Master Serial and Slave Serial Mode Timing
PROG_B
(Input)
INIT_B
(Open-Drain)
TMCCH
TSCCH
TMCCL
TSCCL
CCLK
(Input/Output)
TDCC
DIN
(Input)
1/FCCSER
TCCD
Bit 0
Bit 1
Bit n
Bit n+1
TCCO
DOUT
(Output)
Bit n-64
Bit n-63
DS312-3_05_103105
Figure 11: Waveforms for Master Serial and Slave Serial Configuration
Table 49: Timing for the Master Serial and Slave Serial Configuration Modes
Description
Slave/
Master
The time from the falling transition on the CCLK pin to data appearing at the
DOUT pin
Symbol
-4 Speed Grade
Min
Max
Units
Both
1.5
10
ns
The time from the setup of data at the DIN pin to the rising transition at the
CCLK pin
Both
7
–
ns
The time from the rising transition at the CCLK pin to the point when data is
last held at the DIN pin
Master
0
Slave
1.0
Clock-to-Output Times
TCCO
Setup Times
TDCC
Hold Times
TCCD
–
ns
Clock Timing
TCCH
TCCL
FCCSER
High pulse width at the CCLK input pin
Low pulse width at the CCLK input pin
Frequency of the clock signal at the
CCLK input pin
No bitstream compression
With bitstream compression
Master
See Table 47
Slave
See Table 48
Master
See Table 47
Slave
See Table 48
Slave
0
100
MHz
0
100
MHz
Notes:
1.
2.
48
The numbers in this table are based on the operating conditions set forth in Table 8.
For serial configuration with a daisy-chain of multiple FPGAs, the maximum limit is 25 MHz.
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Slave Parallel Mode Timing
PROG_B
(Input)
INIT_B
(Open-Drain)
TSMCSCC
TSMCCCS
CSI_B
(Input)
TSMCCW
TSMWCC
RDWR_B
(Input)
TMCCH
TSCCH
TMCCL
TSCCL
CCLK
(Input)
TSMDCC
D0 - D7
(Inputs)
TSMCCD
Byte 0
1/FCCPAR
Byte 1
Byte n
Byte n+1
DS529-3_02_051607
Notes:
1.
It is possible to abort configuration by pulling CSI_B Low in a given CCLK cycle, then switching RDWR_B Low or High in any subsequent
cycle for which CSI_B remains Low. The RDWR_B pin asynchronously controls the driver impedance of the D0 - D7 bus. When RDWR_B
switches High, be careful to avoid contention on the D0 - D7 bus.
Figure 12: Waveforms for Slave Parallel Configuration
Table 50: Timing for the Slave Parallel Configuration Mode
-4 Speed Grade
Symbol
Description
Min
Max
Units
TSMDCC(2)
The time from the setup of data at the D0-D7 pins to the rising transition at the CCLK pin
7
–
ns
TSMCSCC
Setup time on the CSI_B pin before the rising transition at the CCLK pin
7
–
ns
TSMCCW
Setup time on the RDWR_B pin before the rising transition at the CCLK pin
15
–
ns
TSMCCD
The time from the rising transition at the CCLK pin to the point when data is last held at
the D0-D7 pins
1.0
–
ns
TSMCCCS
The time from the rising transition at the CCLK pin to the point when a logic level is last
held at the CSO_B pin
0
–
ns
TSMWCC
The time from the rising transition at the CCLK pin to the point when a logic level is last
held at the RDWR_B pin
0
–
ns
TCCH
The High pulse width at the CCLK input pin
5
–
ns
TCCL
The Low pulse width at the CCLK input pin
5
–
ns
FCCPAR
Frequency of the clock signal No bitstream compression
at the CCLK input pin
With bitstream compression
0
80
MHz
0
80
MHz
Setup Times
Hold Times
Clock Timing
Notes:
1.
2.
The numbers in this table are based on the operating conditions set forth in Table 8.
Some Xilinx documents refer to Parallel modes as “SelectMAP” modes.
DS681 (v1.1) February 3, 2009
Product Specification
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49
R
Serial Peripheral Interface Configuration Timing
PROG_B
(Input)
PUDC_B
PUDC_B must be stable before INIT_B goes High and constant throughout the configuration process.
(Input)
VS[2:0]
<1:1:1>
(Input)
M[2:0]
Mode input pins M[2:0] and variant select input pins VS[2:0] are sampled when INIT_B
goes High. After this point, input values do not matter until DONE goes High, at which
point these pins become user-I/O pins.
<0:0:1>
(Input)
TMINIT
TINITM
INIT_B
New ConfigRate active
(Open-Drain)
TCCLKn
TMCCHn
TMCCLn
TCCLK1
TMCCL1 TMCCH1
T CCLK1
CCLK
TV
DIN
Data
(Input)
TCSS
Data
Data
TDCC
Data
TCCD
CSO_B
TCCO
Command
(msb)
MOSI
Command
(msb-1)
TDSU
T DH
Pin initially pulled High by internal pull-up resistor if PUDC_B input is Low.
Pin initially high-impedance (Hi-Z) if PUDC_B input is High. External pull-up resistor required on CSO_B.
Shaded values indicate specifications on attached SPI Flash PROM.
DS529-3_06_102506
Figure 13: Waveforms for SPI Configuration
Table 51: Timing for SPI Configuration Mode
Symbol
Description
Minimum
Maximum
Units
TCCLK1
Initial CCLK clock period
See Table 45
TCCLKn
CCLK clock period after FPGA loads ConfigRate bitstream option setting
See Table 45
TMINIT
Setup time on VS[2:0] variant-select pins and M[2:0] mode pins before the
rising edge of INIT_B
50
–
ns
TINITM
Hold time on VS[2:0] variant-select pins and M[2:0] mode pins after the
rising edge of INIT_B
0
–
ns
TCCO
MOSI output valid delay after CCLK falling clock edge
See Table 49
TDCC
Setup time on the DIN data input before CCLK rising clock edge
See Table 49
TCCD
Hold time on the DIN data input after CCLK rising clock edge
See Table 49
50
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DS681 (v1.1) February 3, 2009
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Table 52: Configuration Timing Requirements for Attached SPI Serial Flash
Symbol
Description
Requirement
Units
TCCS
SPI serial Flash PROM chip-select time
T CCS ≤ T MCCL1 – T CCO
ns
TDSU
SPI serial Flash PROM data input setup time
T DSU ≤ T MCCL1 – T CCO
ns
TDH
SPI serial Flash PROM data input hold time
TV
SPI serial Flash PROM data clock-to-output time
fC or fR
Maximum SPI serial Flash PROM clock frequency (also depends on
specific read command used)
T DH ≤ T MCCH1
ns
T V ≤ T MCCLn – T DCC
ns
1
f C ≥ --------------------------------T CCLKn ( min )
MHz
Notes:
1.
2.
These requirements are for successful FPGA configuration in SPI mode, where the FPGA generates the CCLK signal. The
post-configuration timing can be different to support the specific needs of the application loaded into the FPGA.
Subtract additional printed circuit board routing delay as required by the application.
DS681 (v1.1) February 3, 2009
Product Specification
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51
R
Byte Peripheral Interface Configuration Timing
PROG_B
(Input)
PUDC_B
(Input)
PUDC_B must be stable before INIT_B goes High and constant throughout the configuration process.
M[2:0]
(Input)
Mode input pins M[2:0] are sampled when INIT_B goes High. After this point,
input values do not matter until DONE goes High, at which point the mode pins
become user-I/O pins.
<0:1:0>
TMINIT
INIT_B
(Open-Drain)
TINITM
Pin initially pulled High by internal pull-up resistor if PUDC_B input is Low.
Pin initially high-impedance (Hi-Z) if PUDC_B input is High.
LDC[2:0]
HDC
CSO_B
New ConfigRate active
TCCLK1
TCCLK1
T INITADDR
TCCLKn
CCLK
TCCO
000_0000
A[25:0]
Address
000_0001
Byte 0
Byte 1
Address
TDCC
TAVQV
D[7:0]
(Input)
Address
Data
TCCD
Data
Data
Shaded values indicate specifications on attached parallel NOR Flash PROM.
Data
DS529-3_05_121107
Figure 14: Waveforms for BPI Configuration
Table 53: Timing for BPI Configuration Mode
Symbol
Description
Minimum
Maximum
Units
TCCLK1
Initial CCLK clock period
See Table 45
TCCLKn
CCLK clock period after FPGA loads ConfigRate setting
See Table 45
TMINIT
Setup time on M[2:0] mode pins before the rising edge of INIT_B
TINITM
TINITADDR
TCCO
Address A[25:0] outputs valid after CCLK falling edge
TDCC
Setup time on D[7:0] data inputs before CCLK rising edge
See TSMDCC in Table 50
TCCD
Hold time on D[7:0] data inputs after CCLK rising edge
0
52
50
–
Hold time on M[2:0] mode pins after the rising edge of INIT_B
0
–
ns
Minimum period of initial A[25:0] address cycle; LDC[2:0] and HDC are asserted
and valid
5
5
TCCLK1
cycles
www.xilinx.com
ns
See Table 49
–
ns
DS681 (v1.1) February 3, 2009
Product Specification
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Table 54: Configuration Timing Requirements for Attached Parallel NOR Flash
Symbol
Description
Requirement
Units
TCE
(tELQV)
Parallel NOR Flash PROM chip-select time
T CE ≤ T INITADDR
ns
TOE
(tGLQV)
Parallel NOR Flash PROM output-enable time
T OE ≤ T INITADDR
ns
TACC
(tAVQV)
Parallel NOR Flash PROM read access time
T ACC ≤ 50%T CCLKn ( min ) – T CCO – T DCC – PCB
ns
T BYTE ≤ T INITADDR
ns
TBYTE
For x8/x16 PROMs only: BYTE# to output valid time(3)
(tFLQV, tFHQV)
Notes:
1.
2.
3.
These requirements are for successful FPGA configuration in BPI mode, where the FPGA generates the CCLK signal. The
post-configuration timing can be different to support the specific needs of the application loaded into the FPGA.
Subtract additional printed circuit board routing delay as required by the application.
The initial BYTE# timing can be extended using an external, appropriately sized pull-down resistor on the FPGA’s LDC2 pin. The resistor
value also depends on whether the FPGA’s PUDC_B pin is High or Low.
DS681 (v1.1) February 3, 2009
Product Specification
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IEEE 1149.1/1553 JTAG Test Access Port Timing
TCCH
TCCL
TCK
(Input)
1/FTCK
TTCKTMS
TTMSTCK
TMS
(Input)
TTDITCK
TTCKTDI
TDI
(Input)
TTCKTDO
TDO
(Output)
DS099_06_040703
Figure 15: JTAG Waveforms
Table 55: Timing for the JTAG Test Access Port
-4 Speed Grade
Symbol
Description
Min
Max
Units
1.0
11.0
ns
All devices and functions except those shown below
7.0
–
ns
Boundary scan commands (INTEST, EXTEST,
SAMPLE) on XA3S700A and XA3S1400A FPGAs
11.0
7.0
–
ns
0
–
ns
0
–
ns
5
–
ns
5
–
ns
10
10,000
ns
10
10,000
ns
0
33
MHz
Clock-to-Output Times
TTCKTDO The time from the falling transition on the TCK pin to data appearing at the TDO pin
Setup Times
TTDITCK
The time from the setup of data at the
TDI pin to the rising transition at the
TCK pin
TTMSTCK The time from the setup of a logic level at the TMS pin to the rising transition at the TCK pin
Hold Times
TTCKTDI
The time from the rising transition at
the TCK pin to the point when data is
last held at the TDI pin
All functions except those shown below
Configuration commands (CFG_IN, ISC_PROGRAM)
TTCKTMS The time from the rising transition at the TCK pin to the point when a logic level is last held at the
TMS pin
2.0
Clock Timing
TCCH
The High pulse width at the TCK pin
TCCL
The Low pulse width at the TCK pin
TCCHDNA The High pulse width at the TCK pin
All functions except ISC_DNA command
During ISC_DNA command
TCCLDNA The Low pulse width at the TCK pin
FTCK
Frequency of the TCK signal
All operations on XA3S200A and XA3S400A FPGAs
and for BYPASS or HIGHZ instructions on all FPGAs
All operations on XA3S700A and XA3S1400A FPGAs,
except for BYPASS or HIGHZ instructions
20
Notes:
1.
54
The numbers in this table are based on the operating conditions set forth in Table 8.
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DS681 (v1.1) February 3, 2009
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Revision History
The following table shows the revision history for this document.
Date
Version
04/30/08
1.0
05/07/08
1.0.1
02/03/09
1.1
Revision
Initial release.
Updated Figure 14, minor edits under Features and Package Marking, Table 20 and 21.
•
•
•
•
•
•
•
•
•
•
•
•
Updated "Key Feature Differences from Commercial XC Devices," page 2.
Removed MultiBoot description from "Configuration," page 3.
Updated to v1.41 in Table 3 and Table 16.
Removed -5 high performance (commercial only) speed grade from "Ordering Information," page 5.
Replaced VICM with VCCAUX in Note 7 of Table 13.
Added versions 1.40 and 1.41 to Table 17.
Updated Note 2 in Figure 10.
Removed TIOOLP from Table 23.
Updated TIOCKHZ and TIOCKON in Table 24.
Updated Table 22 and Table 25.
Updated SSO number for left and right I/O banks of DIFF_SSTL18_II standard in Table 28.
Updated TACC requirement in Table 54.
Notice of Disclaimer
THE XILINX HARDWARE FPGA AND CPLD DEVICES REFERRED TO HEREIN (“PRODUCTS”) ARE SUBJECT TO THE TERMS AND
CONDITIONS OF THE XILINX LIMITED WARRANTY WHICH CAN BE VIEWED AT http://www.xilinx.com/warranty.htm. THIS LIMITED
WARRANTY DOES NOT EXTEND TO ANY USE OF PRODUCTS IN AN APPLICATION OR ENVIRONMENT THAT IS NOT WITHIN THE
SPECIFICATIONS STATED IN THE XILINX DATA SHEET. ALL SPECIFICATIONS ARE SUBJECT TO CHANGE WITHOUT NOTICE.
PRODUCTS ARE NOT DESIGNED OR INTENDED TO BE FAIL-SAFE OR FOR USE IN ANY APPLICATION REQUIRING FAIL-SAFE
PERFORMANCE, SUCH AS LIFE-SUPPORT OR SAFETY DEVICES OR SYSTEMS, OR ANY OTHER APPLICATION THAT INVOKES
THE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR PROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL
APPLICATIONS”). USE OF PRODUCTS IN CRITICAL APPLICATIONS IS AT THE SOLE RISK OF CUSTOMER, SUBJECT TO
APPLICABLE LAWS AND REGULATIONS.
Automotive Applications Disclaimer
XILINX PRODUCTS ARE NOT DESIGNED OR INTENDED TO BE FAIL-SAFE, OR FOR USE IN ANY APPLICATION REQUIRING
FAIL-SAFE PERFORMANCE, SUCH AS APPLICATIONS RELATED TO: (I) THE DEPLOYMENT OF AIRBAGS, (II) CONTROL OF A
VEHICLE, UNLESS THERE IS A FAIL-SAFE OR REDUNDANCY FEATURE (WHICH DOES NOT INCLUDE USE OF SOFTWARE IN
THE XILINX DEVICE TO IMPLEMENT THE REDUNDANCY) AND A WARNING SIGNAL UPON FAILURE TO THE OPERATOR, OR (III)
USES THAT COULD LEAD TO DEATH OR PERSONAL INJURY. CUSTOMER ASSUMES THE SOLE RISK AND LIABILITY OF ANY
USE OF XILINX PRODUCTS IN SUCH APPLICATIONS.
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Product Specification
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56
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Product Specification