TI TPS74701-Q1

TPS74701-Q1
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SBVS141A – APRIL 2010 – REVISED SEPTEMBER 2010
500-mA LOW-DROPOUT LINEAR REGULATOR WITH PROGRAMMABLE SOFT-START
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FEATURES
1
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Qualified for Automotive Applications
VOUT Range: 0.8 V to 3.6 V
Ultralow VIN Range: 0.8 V to 5.5 V
VBIAS Range 2.7 V to 5.5 V
Low Dropout: 50 mV typ at 500 mA, VBIAS = 5 V
Power Good (PG) Output Allows Supply
Monitoring or Provides a Sequencing Signal
for Other Supplies
2% Accuracy Over Line/Load/Temperature
Programmable Soft-Start Provides Linear
Voltage Startup
VBIAS Permits Low VIN Operation with Good
Transient Response
Stable with Any Output Capacitor ≥ 2.2 mF
Available in a Small 3mm × 3mm × 1mm
SON-10 Package
APPLICATIONS
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DESCRIPTION
The TPS74701 low-dropout (LDO) linear regulator
provides an easy-to-use, robust power management
solution for a wide variety of applications.
User-programmable soft-start minimizes stress on the
input power source by reducing capacitive inrush
current on start-up. The soft-start is monotonic and
well-suited for powering many different types of
processors and ASICs. The enable input and power
good output allow easy sequencing with external
regulators. This complete flexibility permits the user to
configure a solution that meets the sequencing
requirements of FPGAs, DSPs, and other
applications with special start-up requirements.
A precision reference and error amplifier deliver 2%
accuracy over load, line, temperature, and process.
The device is stable with any type of capacitor
greater than or equal to 2.2mF, and is fully specified
from –40°C to +125°C. The TPS74701 is offered in a
small 3mm × 3mm SON-10 package for compatibility
with the TPS74801.
FPGA Applications
DSP Core and I/O Voltages
Post-Regulation Applications
Applications with Special Start-Up Time or
Sequencing Requirements
Hot-Swap and Inrush Controls
CSS = 0nF
CSS = 560pF
VIN
IN
CIN
EN
TPS74701
R1
GND
CSS
VOUT
OUT
SS
CBIAS
VOUT
R3
BIAS
VBIAS
CSS = 5600pF
0.5V/div
PG
FB
3.8V
COUT
R2
1V/div
VEN
1.8V
Time (2ms/div)
Figure 1. Typical Application Circuit (Adjustable)
Figure 2. Turn-On Response
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2010, Texas Instruments Incorporated
TPS74701-Q1
SBVS141A – APRIL 2010 – REVISED SEPTEMBER 2010
www.ti.com
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
ORDERING INFORMATION (1)
PACKAGE (2)
TJ
–40°C to 125°C
(1)
(2)
SON – DRC
Reel of 3000
ORDERABLE PART NUMBER
TPS74701QDRCRQ1
TOP-SIDE MARKING
PAE
For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
web site at www.ti.com.
Package drawings, thermal data, and symbolization are available at www.ti.com/packaging.
ABSOLUTE MAXIMUM RATINGS (1)
At TJ = –40°C to +125°C, unless otherwise noted. All voltages are with respect to GND.
TPS74701
UNIT
VIN, VBIAS
Input voltage range
–0.3 to +6
V
VEN
Enable voltage range
–0.3 to +6
V
VPG
Power good voltage range
–0.3 to +6
V
IPG
PG sink current
0 to +1.5
mA
VSS
Soft-start voltage range
–0.3 to +6
V
VFB
Feedback voltage range
–0.3 to +6
V
VOUT
Output voltage range
–0.3 to VIN + 0.3
V
IOUT
Maximum output current
Internally limited
Output short-circuit duration
Indefinite
PDISS
Continuous total power dissipation
TJ
Operating junction temperature range
–40 to +125
°C
TSTG
Storage junction temperature range
–55 to +150
°C
(1)
See Thermal Information table
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only and functional operation of the device at these conditions is not implied. Exposure to absolute-maximum-rated conditions for
extended periods may affect device reliability.
THERMAL INFORMATION
THERMAL METRIC (1) (2)
TPS74701-Q1
DRC (10 PINS)
qJA
Junction-to-ambient thermal resistance
50.4
qJCtop
Junction-to-case (top) thermal resistance
70.0
qJB
Junction-to-board thermal resistance
17.7
yJT
Junction-to-top characterization parameter
0.7
yJB
Junction-to-board characterization parameter
16.9
qJCbot
Junction-to-case (bottom) thermal resistance
5.9
(1)
(2)
2
UNITS
°C/W
For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
For thermal estimates of this device based on PCB copper area, see the TI PCB Thermal Calculator.
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ELECTRICAL CHARACTERISTICS
At VEN = 1.1V, VIN = VOUT + 0.3V, CBIAS = 0.1mF, CIN = COUT = 10mF, CNR = 1nF, IOUT = 50mA, VBIAS = 5.0V, and TJ = –40°C to
+125°C, unless otherwise noted. Typical values are at TJ = +25°C.
TPS74701
PARAMETER
TEST CONDITIONS
VIN
Input voltage range
VBIAS
Bias pin voltage range
VREF
Internal reference (Adj.)
Accuracy (1)
VOUT/VIN
Line regulation
VOUT/IOUT
Load regulation
VBIAS dropout voltage
2.7
TJ = +25°C
0.796
VIN = 5V, IOUT = 500mA
VREF
2.97V ≤ VBIAS ≤ 5.5V,
50mA ≤ IOUT ≤ 500mA
–2
VOUT
VIN dropout voltage (2)
VDO
TYP
VOUT + VDO
Output voltage range
VOUT
MIN
(2)
ICL
Current limit
IBIAS
Bias pin current
ISHDN
Shutdown supply current
(IGND)
IFB
Feedback pin current
Power-supply rejection
(VIN to VOUT)
PSRR
Power-supply rejection
(VBIAS to VOUT)
+ 0.3 ≤ VIN ≤ 5.5V
0.8
±0.5
MAX
UNIT
5.5
V
5.5
V
0.804
V
3.6
V
2
%
0.03
%/V
50mA ≤ IOUT ≤ 500mA
0.09
%/A
IOUT = 500mA,
VBIAS – VOUT (NOM) ≥ 1.62V (3)
50
(NOM)
IOUT = 500mA, VIN = VBIAS
VOUT = 80% × VOUT (NOM)
1.31
–1
mV
1.39
V
1350
mA
1
2
mA
1
50
mA
0.150
1
mA
800
VEN ≤ 0.4V
120
1kHz, IOUT = 500mA,
VIN = 1.8V, VOUT = 1.5V
60
300kHz, IOUT = 500mA,
VIN = 1.8V, VOUT = 1.5V
30
1kHz, IOUT = 500mA,
VIN = 1.8V, VOUT = 1.5V
50
300kHz, IOUT = 500mA,
VIN = 1.8V, VOUT = 1.5V
30
dB
dB
Noise
Output noise voltage
100Hz to 100kHz,
IOUT = 500mA, CSS = 0.001mF
25 × VOUT
tSTR
Minimum startup time
RLOAD for IOUT = 1.0A, CSS = open
200
ms
ISS
Soft-start charging current
VSS = 0.4V
440
nA
VEN, HI
Enable input high level
1.1
VEN, LO
Enable input low level
0
VEN, HYS
Enable pin hysteresis
VEN, DG
Enable pin deglitch time
IEN
Enable pin current
VIT
PG trip threshold
VHYS
PG trip hysteresis
VPG,
PG output low voltage
IPG,
LO
LKG
PG leakage current
TJ
Operating junction
temperature
TSD
Thermal shutdown
temperature
(1)
(2)
(3)
mVRMS
5.5
V
0.4
V
50
mV
20
VEN = 5V
VOUT decreasing
85
ms
0.1
1
mA
90
94
%VOUT
3
IPG = 1mA (sinking), VOUT < VIT
VPG = 5.25V, VOUT > VIT
0.1
–40
Shutdown, temperature increasing
+165
Reset, temperature decreasing
+140
%VOUT
0.3
V
1
mA
+125
°C
°C
Adjustable devices tested at 0.8V; resistor tolerance is not taken into account.
Dropout is defined as the voltage from VIN to VOUT when VOUT is 3% below nominal.
1.62V is a test condition of this device and can be adjusted by referring to Figure 8.
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FUNCTIONAL BLOCK DIAGRAM
IN
Current
Limit
BIAS
UVLO
OUT
Thermal
Limit
0.44mA
VOUT
R1
SS
CSS
Soft-Start
Discharge
0.8V
Reference
FB
PG
EN
Hysteresis
and Deglitch
R2
0.9 ´ VREF
GND
Table 1. Standard 1% Resistor Values for Programming the Output Voltage (1)
(1)
R1 (kΩ)
R2 (kΩ)
VOUT (V)
Short
Open
0.8
0.619
4.99
0.9
1.13
4.53
1.0
1.37
4.42
1.05
1.87
4.99
1.1
2.49
4.99
1.2
4.12
4.75
1.5
3.57
2.87
1.8
3.57
1.69
2.5
3.57
1.15
3.3
VOUT = 0.8 × (1 + R1/R2).
Table 2. Standard Capacitor Values for Programming the Soft-Start Time (1)
(1)
4
CSS
SOFT-START TIME
Open
0.1ms
270pF
0.5ms
560pF
1ms
2.7nF
5ms
5.6nF
10ms
0.01mF
18ms
–7
tSS(s) = 0.8 × CSS(F)/4.4 × 10 .
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DEVICE INFORMATION
DRC PACKAGE
3mm × 3mm SON
(TOP VIEW)
IN 1
IN 2
PG 3
BIAS 4
EN 5
Thermal
Pad
10 OUT
9 OUT
8 FB
7 SS
6 GND
PIN DESCRIPTIONS
TPS74701
NAME
PIN #
IN
1, 2
DESCRIPTION
EN
5
SS
7
Soft-Start pin. A capacitor connected on this pin to ground sets the start-up time. If this pin is left
unconnected, the regulator output soft-start ramp time is typically 200ms.
BIAS
4
Bias input voltage for error amplifier, reference, and internal control circuits.
PG
3
Power Good pin. An open-drain, active-high output that indicates the status of VOUT. When VOUT
exceeds the PG trip threshold, the PG pin goes into a high-impedance state. When VOUT is
below this threshold the pin is driven to a low-impedance state. A pull-up resistor from 10kΩ to
1MΩ should be connected from this pin to a supply of up to 5.5V. The supply can be higher than
the input voltage. Alternatively, the PG pin can be left unconnected if output monitoring is not
necessary.
FB
8
Feedback pin. The feedback connection to the center tap of an external resistor divider network
that sets the output voltage. This pin must not be left floating.
OUT
9, 10
Regulated output voltage. A small capacitor (total typical capacitance ≥ 2.2mF, ceramic) is
needed from this pin to ground to assure stability.
NC
N/A
No connection. This pin can be left floating or connected to GND to allow better thermal contact
to the top-side plane.
Input to the device.
Enable pin. Driving this pin high enables the regulator. Driving this pin low puts the regulator into
shutdown mode. This pin must not be left unconnected.
GND
6
Ground
Thermal Pad
—
Should be soldered to the ground plane for increased thermal performance.
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TYPICAL CHARACTERISTICS
At TJ = +25°C, VIN = VOUT(TYP) + 0.3V, VBIAS = 5V, IOUT = 50mA, VEN = VIN, CIN = 1mF, CBIAS = 4.7mF, and COUT = 10mF,
unless otherwise noted.
VBIAS LINE REGULATION
0.5
0.15
0.4
0.3
0.10
Change in VOUT (%)
Change in VOUT (%)
VIN LINE REGULATION
0.20
-40°C
0.05
0
+25°C
+125°C
-0.05
0.2
-40°C
0.1
0
-0.1
+125°C
+25°C
-0.2
-0.01
-0.3
-0.15
-0.4
-0.20
-0.5
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
0.5
5.0
1.0
1.5
2.0
2.5
3.0
VIN - VOUT (V)
VBIAS - VOUT (V)
Figure 3.
Figure 4.
LOAD REGULATION
3.5
4.0
LOAD REGULATION
1.2
0.5
0.4
0.3
Change in VOUT (%)
Change in VOUT (%)
1.0
0.8
0.6
0.4
0.2
+125°C
0.1
0
-0.1
-40°C
+25°C
-0.2
-0.3
0.2
-0.4
0
-0.5
10
20
30
40
0
50
400
500
IOUT (mA)
Figure 6.
DROPOUT VOLTAGE vs
IOUT AND TEMPERATURE (TJ)
DROPOUT VOLTAGE vs
(VBIAS – VOUT) AND TEMPERATURE (TJ)
200
90
180
80
160
70
60
50
40
+125°C
30
+25°C
120
100
20
-40°C
300
400
+125°C
60
40
200
+25°C
80
10
100
IOUT = 0.5A
140
20
0
-40°C
0
500
0
0.5
IOUT (mA)
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
VBIAS - VOUT (V)
Figure 7.
6
300
200
IOUT (mA)
100
0
100
Figure 5.
VDO (VIN - VOUT) (mV)
VDO (VIN - VOUT) (mV)
0
Figure 8.
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TYPICAL CHARACTERISTICS (continued)
At TJ = +25°C, VIN = VOUT(TYP) + 0.3V, VBIAS = 5V, IOUT = 50mA, VEN = VIN, CIN = 1mF, CBIAS = 4.7mF, and COUT = 10mF,
unless otherwise noted.
VBIAS DROPOUT VOLTAGE vs
IOUT AND TEMPERATURE (TJ)
VBIAS PSRR vs FREQUENCY
2200
Power-Supply Rejection Ratio (dB)
90
VDO (VBIAS - VOUT) (mV)
2000
1800
1600
1400
+125°C
1200
1000
+25°C
-40°C
800
600
80
IOUT = 0.1A
70
60
50
40
IOUT = 0.5A
30
VIN = 1.8V
VOUT = 1.2V
VBIAS = 5V
CSS = 1nF
20
10
0
0
100
300
200
400
500
10
100
1k
IOUT (mA)
10k
Figure 9.
VIN PSRR vs FREQUENCY
VIN PSRR vs (VIN – VOUT)
80
70
60
IOUT = 100mA
50
40
30
VIN = 1.8V
VOUT = 1.2V
COUT = 10mF
CSS = 1nF
20
10
10
100
IOUT = 500mA
Power-Supply Rejection Ratio (dB)
Power-Supply Rejection Ratio (dB)
10M
90
0
80
1kHz
70
60
10kHz
50
40
100kHz
30
500kHz
20
VOUT = 1.2V
IOUT = 500mA
CSS = 1nF
10
0
1k
10k
100k
1M
0
10M
0.25
0.50
0.75
1.00
1.25
1.50
1.75
2.00 2.25
VIN - VOUT (V)
Frequency (Hz)
Figure 11.
Figure 12.
NOISE SPECTRAL DENSITY
BIAS PIN CURRENT vs
IOUT AND TEMPERATURE (TJ)
2.0
IOUT = 100mA
VOUT = 1.2V
1.8
+125°C
1.6
1.4
IBIAS (mA)
Output Spectral Noise Density (mV/ÖHz)
1M
Figure 10.
90
1
100k
Frequency (Hz)
CSS = 0nF
0.1
CSS = 10nF
1.2
1.0
0.8
+25°C
0.6
CSS = 1nF
-40°C
0.4
0.2
0
0.01
100
1k
10k
100k
0
100
200
300
400
500
IOUT (mA)
Frequency (Hz)
Figure 13.
Figure 14.
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TYPICAL CHARACTERISTICS (continued)
At TJ = +25°C, VIN = VOUT(TYP) + 0.3V, VBIAS = 5V, IOUT = 50mA, VEN = VIN, CIN = 1mF, CBIAS = 4.7mF, and COUT = 10mF,
unless otherwise noted.
BIAS PIN CURRENT vs
VBIAS AND TEMPERATURE (TJ)
SOFT-START CHARGING CURRENT (ISS) vs
TEMPERATURE (TJ)
2.0
500
1.8
475
+125°C
1.6
450
1.2
ISS (nA)
IBIAS (mA)
1.4
+25°C
1.0
0.8
425
400
375
0.6
-40°C
350
0.4
325
0.2
300
0
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
-50
0
-25
VBIAS (V)
Figure 15.
75
100
125
CURRENT LIMIT vs (VBIAS – VOUT)
1.0
1.5
0.9
1.4
0.8
1.3
0.7
1.2
Current Limit (A)
VOL Low-Level PG Voltage (V)
50
Figure 16.
LOW-LEVEL PG VOLTAGE vs CURRENT
0.6
0.5
0.4
0.3
VOUT = 0.8V
+125°C
1.1
1.0
-40°C
0.9
+25°C
0.8
0.2
0.7
0.1
0.6
0
0.5
0
2
4
6
8
10
12
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
VBIAS - VOUT (V)
PG Current (mA)
Figure 17.
8
25
Junction Temperature (°C)
Figure 18.
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TYPICAL CHARACTERISTICS
At TJ = +25°C, VIN = VOUT(TYP) + 0.3V, VBIAS = 5V, IOUT = 1A, VEN = VIN = 1.8V, VOUT = 1.5V, CIN = 1mF, CBIAS = 4.7mF, and
COUT = 10mF, unless otherwise noted.
VBIAS LINE TRANSIENT
VIN LINE TRANSIENT
CSS = 1nF
COUT = 2.2mF (Ceramic)
COUT = 2.2mF (Ceramic)
50mV/div
50mV/div
CSS = 1nF
3.8V
5.0V
1V/div
1V/div
1V/ms
3.3V
1V/ms
1.8V
Time (50ms/div)
Time (50ms/div)
Figure 19.
Figure 20.
OUTPUT LOAD TRANSIENT RESPONSE
TURN-ON RESPONSE
CSS = 0nF
COUT = 470mF (OSCON)
100mV/div
CSS = 560pF
CSS = 1nF
CSS = 5600pF
0.5V/div
VOUT
100mV/div
COUT = 10mF (Ceramic)
100mV/div
3.8V
COUT = 2.2mF (Ceramic)
1V/div
500mA/div
VEN
1.8V
1A/ms
50mA
Time (50ms/div)
Time (2ms/div)
Figure 21.
Figure 22.
POWER-UP/POWER-DOWN
1V/div
VIN = VBIAS = VEN
VOUT
VPG
Time (20ms/div)
Figure 23.
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APPLICATION INFORMATION
The TPS74701 belongs to a family of low-dropout regulators that feature soft-start capability. These regulators
use a low current bias input to power all internal control circuitry, allowing the NMOS pass transistor to regulate
very low input and output voltages.
The use of an NMOS-pass FET offers several critical advantages for many applications. Unlike a PMOS topology
device, the output capacitor has little effect on loop stability. This architecture allows the TPS74701 to be stable
with any capacitor type of value 2.2mF or greater. Transient response is also superior to PMOS topologies,
particularly for low VIN applications.
The TPS74701 features a programmable voltage-controlled soft-start circuit that provides a smooth, monotonic
start-up and limits startup inrush currents that may be caused by large capacitive loads. A power good (PG)
output is available to allow supply monitoring and sequencing of other supplies. An enable (EN) pin with
hysteresis and deglitch allows slow-ramping signals to be used for sequencing the device. The low VIN and VOUT
capability allows for inexpensive, easy-to-design, and efficient linear regulation between the multiple supply
voltages often present in processor-intensive systems.
Figure 24 illustrates the typical application circuit for the TPS74701 adjustable output device.
VIN
IN
CIN
1mF
PG
R3
BIAS
EN
VBIAS
TPS74701
R1
SS
CBIAS
1mF
VOUT
OUT
FB
GND
CSS
COUT
10mF
R2
(
VOUT = 0.8 ´ 1 +
R1
R2
)
Figure 24. Typical Application Circuit for the TPS74701 (Adjustable)
R1 and R2 can be calculated for any output voltage using the formula shown in Figure 24. Refer to Table 1 for
sample resistor values of common output voltages. In order to achieve the maximum accuracy specifications, R2
should be less than or equal to 4.99kΩ.
INPUT, OUTPUT, AND BIAS CAPACITOR REQUIREMENTS
The device is designed to be stable for all available types and values of output capacitors greater than or equal
to 2.2mF. The device is also stable with multiple capacitors in parallel, which can be of any type or value.
The capacitance required on the IN and BIAS pins strongly depends on the input supply source impedance. To
counteract any inductance in the input, the minimum recommended capacitor for VIN and VBIAS is 1mF. If VIN and
VBIAS are connected to the same supply, the recommended minimum capacitor for VBIAS is 4.7mF. Good quality,
low ESR capacitors should be used on the input; ceramic X5R and X7R capacitors are preferred. These
capacitors should be placed as close the pins as possible for optimum performance.
TRANSIENT RESPONSE
The TPS74701 was designed to have excellent transient response for most applications with a small amount of
output capacitance. In some cases, the transient response may be limited by the transient response of the input
supply. This limitation is especially true in applications where the difference between the input and output is less
than 300mV. In this case, adding additional input capacitance improves the transient response much more than
just adding additional output capacitance would do. With a solid input supply, adding additional output
capacitance reduces undershoot and overshoot during a transient event; refer to Figure 21 in the Typical
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Characteristics section. Because the TPS74701 is stable with output capacitors as low as 2.2mF, many
applications may then need very little capacitance at the LDO output. For these applications, local bypass
capacitance for the powered device may be sufficient to meet the transient requirements of the application. This
design reduces the total solution cost by avoiding the need to use expensive, high-value capacitors at the LDO
output.
DROPOUT VOLTAGE
The TPS74701 offers very low dropout performance, making it well-suited for high-current, low VIN/low VOUT
applications. The low dropout of the TPS74701 allows the device to be used in place of a dc/dc converter and
still achieve good efficiency. This feature provides designers with the power architecture for their applications to
achieve the smallest, simplest, and lowest cost solution.
There are two different specifications for dropout voltage with the TPS74701. The first specification (shown in
Figure 25) is referred to as VIN Dropout and is used when an external bias voltage is applied to achieve low
dropout. This specification assumes that VBIAS is at least 1.62V (1) above VOUT, which is the case for VBIAS when
powered by a 3.3V rail with 5% tolerance and with VOUT = 1.5V. If VBIAS is higher than VOUT +1.62V (1), VIN
dropout is less than specified.
BIAS
IN
Reference
VBIAS = 5V ±5%
VIN = 1.8V
VOUT = 1.5V
IOUT = 1.5A
Efficiency = 83%
OUT
VOUT
COUT
FB
Simplified Block Diagram
Figure 25. Typical Application of the TPS74701 Using an Auxiliary Bias Rail
The second specification (shown in Figure 26) is referred to as VBIAS Dropout and applies to applications where
IN and BIAS are tied together. This option allows the device to be used in applications where an auxiliary bias
voltage is not available or low dropout is not required. Dropout is limited by BIAS in these applications because
VBIAS provides the gate drive to the pass FET; therefore, VBIAS must be 1.39V above VOUT. Because of this
usage, IN and BIAS tied together easily consume huge power. Pay attention not to exceed the power rating of
the IC package.
VIN
BIAS
Reference
IN
VBIAS = 3.3V ±5%
VIN = 3.3V ± 5V
VOUT = 1.5V
IOUT = 1.5A
Efficiency = 45%
OUT
VOUT
COUT
FB
Simplified Block Diagram
Figure 26. Typical Application of the TPS74701 Without an Auxiliary Bias Rail
(1)
1.62V is a test condition of this device and can be adjusted by referring to Figure 8.
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PROGRAMMABLE SOFT-START
The TPS74701 features a programmable, monotonic, voltage-controlled soft-start that is set with an external
capacitor (CSS). This feature is important for many applications because it eliminates power-up initialization
problems when powering FPGAs, DSPs, or other processors. The controlled voltage ramp of the output also
reduces peak inrush current during start-up, minimizing start-up transient events to the input power bus.
To achieve a linear and monotonic soft-start, the TPS74701 error amplifier tracks the voltage ramp of the
external soft-start capacitor until the voltage exceeds the internal reference. The soft-start ramp time depends on
the soft-start charging current (ISS), soft-start capacitance (CSS), and the internal reference voltage (VREF), and
can be calculated using Equation 1:
(VREF ´ CSS)
tSS =
ISS
(1)
If large output capacitors are used, the device current limit (ICL) and the output capacitor may set the start-up
time. In this case, the start-up time is given by Equation 2:
(VOUT(NOM) ´ COUT)
tSSCL =
ICL(MIN)
(2)
where:
VOUT(NOM) is the nominal output voltage,
COUT is the output capacitance, and
ICL(MIN) is the minimum current limit for the device.
In applications where monotonic startup is required, the soft-start time given by Equation 1 should be set greater
than Equation 2.
The maximum recommended soft-start capacitor is 0.015mF. Larger soft-start capacitors can be used and do not
damage the device; however, the soft-start capacitor discharge circuit may not be able to fully discharge the
soft-start capacitor when enabled. Soft-start capacitors larger than 0.015mF could be a problem in applications
where it is necessary to rapidly pulse the enable pin and still require the device to soft-start from ground. CSS
must be low-leakage; X7R, X5R, or C0G dielectric materials are preferred. Refer to Table 2 for suggested
soft-start capacitor values.
SEQUENCING REQUIREMENTS
VIN, VBIAS, and VEN can be sequenced in any order without causing damage to the device. However, for the
soft-start function to work as intended, certain sequencing rules must be applied. Connecting EN to IN is
acceptable for most applications, as long as VIN is greater than 1.1V and the ramp rate of VIN and VBIAS is faster
than the set soft-start ramp rate. If the ramp rate of the input sources is slower than the set soft-start time, the
output tracks the slower supply minus the dropout voltage until it reaches the set output voltage. If EN is
connected to BIAS, the device soft-starts as programmed, provided that VIN is present before VBIAS. If VBIAS and
VEN are present before VIN is applied and the set soft-start time has expired, then VOUT tracks VIN. If the soft-start
time has not expired, the output tracks VIN until VOUT reaches the value set by the charging soft-start capacitor.
Figure 27 shows the use of an RC-delay circuit to hold off VEN until VBIAS has ramped. This technique can also
be used to drive EN from VIN. An external control signal can also be used to enable the device after VIN and
VBIAS are present.
NOTE:
current
charge
greater
12
When VBIAS and VEN are present and VIN is not supplied, this device outputs approximately 50mA of
from OUT. Although this condition does not cause any damage to the device, the output current may
up the OUT node if total resistance between OUT and GND (including external feedback resistors) is
than 10kΩ.
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VIN
VOUT
OUT
IN
R1
CIN
BIAS TPS74701
FB
R2
R
VBIAS
EN
CBIAS
C
COUT
GND
SS
CSS
Figure 27. Soft-Start Delay Using an RC Circuit to Enable the Device
OUTPUT NOISE
The TPS74701 provides low output noise when a soft-start capacitor is used. When the device reaches the end
of the soft-start cycle, the soft-start capacitor serves as a filter for the internal reference. By using a 0.001mF
soft-start capacitor, the output noise is reduced by half and is typically 30mVRMS for a 1.2V output (10Hz to
100kHz). Further increasing CSS has little effect on noise. Because most of the output noise is generated by the
internal reference, the noise is a function of the set output voltage. The RMS noise with a 0.001mF soft-start
capacitor is given in Equation 3:
(
VN(mVRMS) = 25
mVRMS
V
)x V
OUT(V)
(3)
The low output noise of the TPS74701 makes it a good choice for powering transceivers, PLLs, or other
noise-sensitive circuitry.
ENABLE/SHUTDOWN
The enable (EN) pin is active high and is compatible with standard digital signaling levels. VEN below 0.4V turns
the regulator off, while VEN above 1.1V turns the regulator on. Unlike many regulators, the enable circuitry has
hysteresis and deglitching for use with relatively slowly ramping analog signals. This configuration allows the
TPS74701 to be enabled by connecting the output of another supply to the EN pin. The enable circuitry typically
has 50mV of hysteresis and a deglitch circuit to help avoid on-off cycling as a result of small glitches in the VEN
signal.
The enable threshold is typically 0.8V and varies with temperature and process variations. Temperature variation
is approximately –1mV/°C; process variation accounts for most of the rest of the variation to the 0.4V and 1.1V
limits. If precise turn-on timing is required, a fast rise-time signal must be used to enable the TPS74701.
If not used, EN can be connected to either IN or BIAS. If EN is connected to IN, it should be connected as close
as possible to the largest capacitance on the input to prevent voltage droops on that line from triggering the
enable circuit.
POWER GOOD
The power good (PG) pin is an open-drain output and can be connected to any 5.5V or lower rail through an
external pull-up resistor. This pin requires at least 1.1V on VBIAS in order to have a valid output. The PG output is
high-impedance when VOUT is greater than VIT + VHYS. If VOUT drops below VIT or if VBIAS drops below 1.9V, the
open-drain output turns on and pulls the PG output low. The PG pin also asserts when the device is disabled.
The recommended operating condition of the PG pin sink current is up to 1mA, so the pull-up resistor for PG
should be in the range of 10kΩ to 1MΩ. If output voltage monitoring is not needed, the PG pin can be left
floating.
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INTERNAL CURRENT LIMIT
The TPS74701 features a factory-trimmed, accurate current limit that is flat over temperature and supply voltage.
The current limit allows the device to supply surges of up to 1A and maintain regulation. The current limit
responds in about 10ms to reduce the current during a short-circuit fault.
The internal current limit protection circuitry of the TPS74701 is designed to protect against overload conditions.
It is not intended to allow operation above the rated current of the device. Continuously running the TPS74701
above the rated current degrades device reliability.
THERMAL PROTECTION
Thermal protection disables the output when the junction temperature rises to approximately +160°C, allowing
the device to cool. When the junction temperature cools to approximately +140°C, the output circuitry is enabled.
Depending on power dissipation, thermal resistance, and ambient temperature the thermal protection circuit may
cycle on and off. This cycling limits the dissipation of the regulator, protecting it from damage as a result of
overheating.
Activation of the thermal protection circuit indicates excessive power dissipation or inadequate heatsinking. For
reliable operation, junction temperature should be limited to +125°C maximum. To estimate the margin of safety
in a complete design (including heatsink), increase the ambient temperature until thermal protection is triggered;
use worst-case loads and signal conditions. For good reliability, thermal protection should trigger at least +40°C
above the maximum expected ambient condition of the application. This condition produces a worst-case junction
temperature of +125°C at the highest expected ambient temperature and worst-case load.
The internal protection circuitry of the TPS74701 is designed to protect against overload conditions. It is not
intended to replace proper heatsinking. Continuously running the TPS74701 into thermal shutdown degrades
device reliability.
LAYOUT RECOMMENDATIONS AND POWER DISSIPATION
An optimal layout can greatly improve transient performance, PSRR, and noise. To minimize the voltage drop on
the input of the device during load transients, the capacitance on IN and BIAS should be connected as close as
possible to the device. This capacitance also minimizes the effects of parasitic inductance and resistance of the
input source and can therefore improve stability. To achieve optimal transient performance and accuracy, the top
side of R1 in Figure 24 should be connected as close as possible to the load. If BIAS is connected to IN, it is
recommended to connect BIAS as close to the sense point of the input supply as possible. This connection
minimizes the voltage drop on BIAS during transient conditions and can improve the turn-on response.
Knowing the device power dissipation and proper sizing of the thermal plane that is connected to the thermal pad
is critical to avoiding thermal shutdown and ensuring reliable operation. Power dissipation of the device depends
on input voltage and load conditions and can be calculated using Equation 4:
PD = (VIN - VOUT) ´ IOUT
(4)
Power dissipation can be minimized and greater efficiency can be achieved by using the lowest possible input
voltage necessary to achieve the required output voltage regulation.
On the SON (DRC) package, the primary conduction path for heat is through the exposed pad to the printed
circuit board (PCB). The pad can be connected to ground or be left floating; however, it should be attached to an
appropriate amount of copper PCB area to ensure the device will not overheat. The maximum junction to
ambient thermal resistance depends on the maximum ambient temperature, maximum device junction
temperature, and power dissipation of the device, and can be calculated using Equation 5:
(+125°C - TA)
RqJA =
PD
(5)
Knowing the maximum RqJA and system air flow, the minimum amount of PCB copper area needed for
appropriate heatsinking can be calculated using Figure 28 through Figure 30.
14
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PCB Top View
PCB Cross Section
TJ
RqJC
TC
RqCS
0.062"
TS
0.5 in2
RqSA
4-layer, 0.062” FR4.
Vias are 0.012” diameter, plated.
Top/Bottom layers are 2oz. copper.
Inner layers are 1oz. copper.
1.0 in2
TA
2.0 in2
RqJA = RqJC + RqCS + RqSA
90
85
0 LFM
80
qJA (°C/W)
75
150 LFM
70
65
250 LFM
60
55
50
45
40
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
2
Area (in )
Figure 28. DRC (3 x 3 SON) PCB Layout and Corresponding RqJA Data, No Vias Under Thermal Pad
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PCB Top View
PCB Cross Section
TJ
RqJC
TC
RqCS
0.062"
TS
0.5 in2
RqSA
4-layer, 0.062” FR4.
Vias are 0.012” diameter, plated.
Top/Bottom layers are 2oz. copper.
Inner layers are 1oz. copper.
1.0 in2
TA
2.0 in2
RqJA = RqJC + RqCS + RqSA
90
85
80
qJA (°C/W)
75
70
65
0 LFM
60
150 LFM
55
50
45
250 LFM
40
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
Area (in2)
Figure 29. DRC (3 x 3 SON) PCB Layout and Corresponding RqJA Data, Vias Under Thermal Pad
16
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PCB Top View
PCB Cross Section
TJ
RqJC
TC
RqCS
0.062"
TS
RqSA
4-layer, 0.062” FR4.
Vias are 0.012” diameter, plated.
Top/Bottom layers are 2oz. copper.
Inner layers are 1oz. copper.
0.5 in2
TA
1.0 in2
RqJA = RqJC + RqCS + RqSA
2.0 in2
90
85
80
qJA (°C/W)
75
0 LFM
70
65
60
150 LFM
55
250 LFM
50
45
40
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
Area (in2)
Figure 30. DRC (3 x 3 SON) PCB Layout and Corresponding RqJA Data, Top Layer Only
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PACKAGE OPTION ADDENDUM
www.ti.com
29-Jul-2010
PACKAGING INFORMATION
Orderable Device
TPS74701QDRCRQ1
Status
(1)
Package Type Package
Drawing
ACTIVE
SON
DRC
Pins
Package Qty
10
3000
Eco Plan
(2)
Green (RoHS
& no Sb/Br)
Lead/
Ball Finish
MSL Peak Temp
(3)
CU NIPDAU Level-3-260C-168 HR
Samples
(Requires Login)
Request Free Samples
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF TPS74701-Q1 :
• Catalog: TPS74701
NOTE: Qualified Version Definitions:
• Catalog - TI's standard catalog product
Addendum-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
14-Jul-2012
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
TPS74701QDRCRQ1
Package Package Pins
Type Drawing
SON
DRC
10
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
3000
330.0
12.4
Pack Materials-Page 1
3.3
B0
(mm)
K0
(mm)
P1
(mm)
3.3
1.1
8.0
W
Pin1
(mm) Quadrant
12.0
Q2
PACKAGE MATERIALS INFORMATION
www.ti.com
14-Jul-2012
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
TPS74701QDRCRQ1
SON
DRC
10
3000
367.0
367.0
35.0
Pack Materials-Page 2
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