AKM AK7740ET

[ASAHI KASEI]
[AK7740ET]
AK7740ET
24bit 2ch ADC + 24bit 4ch DAC with Audio DSP
1. General Description
The AK7740 is a highly integrated audio processing IC, including four 24-bit output D/A channels, a stereo 24-bit
input A/D, and an audio DSP. High quality analog output performance is provided by the quad DAC with 97dB
dynamic range, and the stereo ADC with 98dB dynamic range. The converters support sampling frequencies from
32kHz to 48kHz. This device includes 72kbits of SRAM audio delay that is suitable for simulated sound fields. The
DSP is optimized for audio signal processing. The design allows up to 512 execution lines per audio sample cycle,
with multiple functions per line. The AK7740 is ideal for sound field control applications, including echo, 3D,
parametric equalization, and speaker compensation. It is housed in a 48-lead LQFP package.
2. Features
DSP:
-
Word length:
24-bit (Data RAM)
Instruction cycle time: 40ns (512fs, fs=48kHz )
Multiplier: 24 x 16 → 40-bit
Divider:
24 / 24 → 16-bit or 24-bit
ALU:
34-bit arithmetic operation (overflow margin: 4-bits)
24-bit arithmetic and logic operation
Shift+Register: 1, 2, 3, 4, 6, 8 and 15 bits shifted left
1, 2, 3, 4, 8 , 14 and 15 bits shifted right
Other numbers in parentheses are restricted. Provided with indirect shift function
Program RAM:
512 x 32-bit
Coefficient RAM:
512 x 16-bit
Data RAM:
256 x 24-bit
Offset RAM:
48 x 13-bit
- (6144 x 12-bit / 3072 x 24-bit / 4096 x 12-bit + 1024 x 24-bit )
- Internal Memory:
72kbit SRAM
- Sampling frequency: 32kHz to 48kHz
- Serial interface port for micro-controller
- Master clock: 512fs
- Master/Slave operation
- Serial signal input port ( 2 to 4 ch ): 16/20/24-bit : Output port ( 2 ch ): 24-bit
ADC: 2 channels
- 24-bit 64x over-sampling delta sigma
- DR, S/N : 98dBA ( full-differential Input )
- S/(N+D) : 89dB
- Digital HPF (fc = 1Hz)
- Single-ended or full-differential Input
DAC: 4 channels
- 24-bit 128x over-sampling advanced multi-bit
- DR, S/N : 97dBA
- S/(N+D) : 89dB
- Single ended or differential output
Input Selector
- 1 full-differential and 4 single-ended Input
Other
- Power supply:
+3.3V±10%
- Operating temperature range: -10°C~70°C
- Package: 48pin LQFP (0.5mm pitch)
<Pre-E-01>
-1-
2006/10
[ASAHI KASEI]
[AK7740ET]
3. Block diagram
OUTAE
LRCLK
BITCLK
CLKOUT
XTI XTO
SMODE
LRCLK
BITCLK
CLKOUT
XTI XTO
SMODE
INIT_RESET
CONTROLLER
SDOUTA
S_RESET
INIT_RESET
S_RESET
AINL-
ADC
SW3
SDINA
SDIN
AINLAINL+
AINL1
AINL2
AINL3
AINL4
AINR-
AINL+
SW0
RQ
DSP
RQ
SI
SI
SO
SO
SDATA
SDIN
AINR-
AINR+
AINR1
AINR2
AINR3
AINR4
VREFH
VCOM
AINR+
SCLK
SCLK
RDY
RDY
DRDY
DRDY
JX
SDINA
ISEL[2:0]
SW2
SDOUTD1
VREF
SDATA
JX
DAC1
AOUTL
AOUTL1
AOUTR
AOUTR1
AOUTL
AOUTL2
AOUTR
AOUTR2
SW2
SDOUTD2
SDATA
SDOUT
DAC2
SW1
SDOUT
72kbit DLRAM
* SW1,SW2,SW3,ISEL[2:0],
OUTAE control register
Note)
A
B
C
Q
When C is “L”(0) then A connects with Q.
This block diagram is a simplified illustration of the AK7740; it is not a circuit diagram.
<Pre-E-01>
-2-
2006/10
[ASAHI KASEI]
[AK7740ET]
‹ AK7740 DSP Block diagram
CP0,CP1
DP0,DP1
DLP0,DLP1
CRAM
512 X 16
DRAM
256 X 24
DLRAM
6K X 12 or 3K X 24
4K X 12 & 1K X 24
OFRAM
48 X 13
CMP(Compress & Expand)
CBUS(16bit)
DBUS(24bit)
X
Micom I/F
Control
MPX24
DEC
MPX16
Y
Multiply
16 X 24 -> 40
24bit
40bit
MUL
34bit
PRAM
512 X 32
PC
Stack : 1level
DBUS
SHIFT
TMP 8 X 24bit
34bit
A
Serial I/F
PTMP 24bit X 6(LIFO)
B
ALU1
34bit
Overflow Margin: 4bit
DR0 ∼ 3
24bit
2 X 24 bit
ADC
2 X 24/20/16bit
SDIN
Divider
24 ÷ 24 → 24
Over Flow Data
Generator
<Pre-E-01>
-3-
2 X 24bit
DAC1
2 X 24bit
DAC2
2 X 24bit
SDOUT
2006/10
[ASAHI KASEI]
[AK7740ET]
4. Description of Input/Output Pins
AINR3
AINL4
AINR4
AINL+
AINL-
AINR+
AINR-
AVSS
VCOM
AVDD
AOUTL1
AOUTR1
48
47
46
45
44
43
42
41
40
39
38
37
(1) Pin layout
31
INIT_RESET
AVDD
7
(TOP VIEW)
30
S_RESET
AVSS
8
29
RQ
DVSS
9
28
SCLK
DVDD
10
27
SI
XTI
11
26
SO
XTO
12
25
RDY
LRCLK
24
48pin LQFP
DVDD
6
23
VREFH
DVSS
DVDD
22
32
DRDY
5
21
AINL1
SDOUT
DVSS
20
33
SDOUTA
4
19
AINR1
SDINA
BVSS
18
34
SDIN
3
17
AINL2
BITCLK
AOUTR2
16
35
15
2
SMODE
AINR2
14
AOUTL2
JX
36
13
1
CLKO
AINL3
Note) JX,SDIN and SDINA are Pull-down pins
<Pre-E-01>
-4-
2006/10
[ASAHI KASEI]
[AK7740ET]
(2) Pin function
Pin No.
1
2
3
4
5
6
Pin name
AINL3
AINR2
AINL2
AINR1
AINL1
VREFH
I/O
I
I
I
I
I
I
7
8
9
10
AVDD
AVSS
DVSS
DVDD
-
11
XTI
I
12
XTO
O
13
CLKO
O
14
JX
I
15
SMODE
I
16
LRCLK
I/O
17
BITCLK
I/O
18
SDIN
I
19
SDINA
<Pre-E-01>
Function
ADC single-ended analog Lch input pin 3
ADC single-ended analog Rch input pin 2
ADC single-ended analog Lch input pin 2
ADC single-ended analog Rch input pin 1
ADC single-ended analog Lch input pin 1
Analog reference voltage input
Connect to AVDD (pin 7), and bypass with 0.1uF and
10uF capacitors between this pin and AVSS.
Analog power supply 3.3V typical
Analog ground
Digital ground
Digital power supply 3.3V typical
Master clock input
Connect a crystal oscillator between this pin and the XTO pin,
or input an external CMOS clock signal to the XTI pin.
Crystal oscillator output
When a crystal oscillator is used, connect between XTI and XTO.
When an external clock is used, keep this pin open
Clock output
Outputs the XTI clock.
Allows the output to be set to "L" by control register setting.
External condition jump (pulldown)
Slave/master mode selector
Sets LRCLK and BITCLK to input or output mode.
SMODE="L": Slave mode (clock input mode)
SMODE="H": Master mode (clock output mode)
LR channel select clock
SMODE="L": Slave mode: Inputs the fs clock
SMODE="H": Master mode: Outputs the fs clock
Serial bit clock
SMODE="L": Slave mode: Inputs 64 fs or 48 fs clocks
SMODE="H": Master mode: Outputs 64 fs clocks
DSP serial data input ( Pulldown)
Compatible with MSB/LSB justified 24, 20 and 16 bits.
Classification
Analog section
Analog
Power Supply
Digital
Power Supply
System clock
System clock
Condition input
Control
System clock
Digital section
Serial input data
DSP serial data input (Pulldown)
I When using the ADC, leave open or connect to DVSS.
Compatible with MSB justified 24 bits.
-5-
2006/10
[ASAHI KASEI]
Pin No.
20
Pin name
SDOUTA
21
SDOUT
22
DRDY
23
24
25
26
DVSS
DVDD
RDY
SO
27
SI
28
SCLK
RQ
29
30
S_RESET
31
INIT_RESET
32
33
34
35
36
37
38
39
40
DVDD
DVSS
BVSS
AOUTR2
AOUTL2
AOUTR1
AOUTL1
AVDD
VCOM
41
42
43
44
45
46
47
48
AVSS
AINRAINR+
AINLAINL+
AINR4
AINL4
AINR3
<Pre-E-01>
[AK7740ET]
I/O
Function
O DSP serial data output
Outputs MSB justified 24-bit data selected from ADC or SDOUTD1
by control register setting
O DSP serial data output
Outputs MSB justified 24-bit data
O Output data ready pin for microcontroller interface
O
O
Digital ground
Digital power supply 3.3V typical
Data write ready output for microcontroller interface
Serial data output for microcontroller interfaces
Microcontroller interface serial data input and serial data
I output control
When SI does not use, leave SI=”L”
Microcontroller interface serial data clock
I When SCLK is not used, leave SCLK=”H”
Classification
Digital section
Serial output data
Microcontroller
interface
Power supply
Microcontroller
interface
Microcontroller interface writes request pin.
I
RQ =”L”: Microcontroller interface enable
I System Reset
Reset
I Reset (for initialization)
Input “L” to initialize the AK7740 at power-on
- Digital power supply 3.3V typical
- Digital ground
- Substrate ground
O DAC2 Rch analog output
O DAC2 Lch analog output
O DAC1 Rch analog output
O DAC1 Lch analog output
- Analog power supply 3.3V typical
O Common voltage
Connect to 0.1uF and 10uF capacitors between this pin and
AVSS. Do not connect to external circuitry
- An alog ground
I ADC Rch analog inverted input
I ADC Rch analog non-inverted input
I ADC Lch analog inverted input
I ADC Lch analog non-inverted input
I ADC single-ended analog Rch input 4
I ADC single-ended analog Lch input 4
I ADC single-ended analog Rch input 3
-6-
Power supply
Power supply
Analog section
Power supply
Analog section
Power supply
Analog section
2006/10
[ASAHI KASEI]
[AK7740ET]
5. Absolute Maximum Rating
(AVSS, BVSS, DVSS = 0 V: All voltages indicated are relative to the ground)
Item
Symbol
min
max
Power supply voltage
Analog (AVDD)
VA
-0.3
4.6
Digital (DVDD)
VD
-0.3
4.6
|AVSS (BVSS)-DVSS|
Note 1)
0.3
∆GND
Input current (except for power supply pin )
IIN
±10
Analog input voltage
AINL+,AINL-,AINR+,AINR-,AINL1,
VINA
-0.3
VA+0.3
AINR1,AINL2,AINR2,AINL3,AINR3,
AINL4,AINR4,VREFH
Digital input voltage
VIND
-0.3
VD+0.3
Operating ambient temperature
Ta
-10
70
Storage temperature
Tstg
-65
150
Unit
V
V
V
mA
V
V
°C
°C
Note 1) AVSS(BVSS) should be at the same level as DVSS
WARNING: Operation at or beyond these limits may result in permanent damage of the device.
Normal operation is not guaranteed when these limits are exceeded
6. Recommended Operating Conditions
(AVSS, BVSS, DVSS = 0 V: All voltages indicated are relative to the ground.)
Items
Symbol
min
typ
max
Unit
Power supply voltage
AVDD
VA
3.0
3.3
3.6
V
DVDD
VD
3.0
3.3
VA
V
Reference voltage (VREF)
VREFH Note 1)
Note 1)
VRH
VA
V
VREFH normally connects to AVDD.
Note: The analog input voltage and output voltage are proportional to VREFH voltage.
<Pre-E-01>
-7-
2006/10
[ASAHI KASEI]
[AK7740ET]
7. Electric Characteristics
(1) Analog characteristics
(Unless otherwise specified, Ta = 25°C; AVDD, DVDD = 3.3V; VREFH = AVDD;
BITCLK = 64 fs; Signal frequency 1kHz;
Measurement bandwidth = 20Hz to 20kHz @ 48kHz;
DSP section in reset state; ADC with all differential inputs)
Parameter
Min
Typ
Max
Unit
Resolution
24
Bits
ADC
Section
Dynamic characteristics
S/(N+D)
fs = 48kHz (-1dB)
(Note1)
80
89
dB
Dynamic range fs = 48kHz (A filter) (Note2)
90
98
dB
S/N
fs = 48kHz (A filter)
90
98
dB
Inter-channel isolation (f =1kHz)
(Note3)
90
110
dB
DC accuracy
Inter-channel gain mismatching
0.1
0.3
dB
Analog input
Input voltage (Differencial)
(Note4)
Vp-p
±1.85
±2.00
±2.15
Input Voltage (Single-ended)
(Note5)
1.85
2.00
2.15
Vp-p
Input impedance
(Note6)
15
33
kΩ
Resolution
24
Bits
DAC
Section
Dynamic characteristics
S/(N+D)
fs = 48kHz (0dB)
80
89
dB
Dynamic range fs = 48kHz (A filter) (Note2)
90
97
dB
S/N
fs = 48kHz (A filter)
90
97
dB
Inter-channel isolation (f =1kHz)
(Note7)
90
105
dB
DC accuracy
Inter-channel gain mismatching
(Note7)
0.2
0.5
dB
Analog output
Output voltage
(Note8)
1.85
2.00
2.15
Vp-p
Load resistance
10
kΩ
Note:
1. Specification only guaranteed for differential inputs
2. Indicates S/(N+D) when -60dB signal is applied
3. Specified for L and R of each input selector
4. Applies to AINL+, AINL-, AINR+ and AINRFullscale (∆AIN = (AIN+) - (AIN-)) can be represented by (±FS = ±(VREFH-AVSS)×(2.0/3.3))
5. Applies to AINL1,AINR1,AINL2,AINR2,AINL3,AINR3,AINL4 and AINR4
Fullscale single-ended input is (FS=(VREFH-AVSS) × (2.0/3.3))
6. Applies to AINL1, AINR1, AINL2, AINR2, AINL3, AINR3, AINL4, AINR4, AINL+, AINL-,
AINR+ and AINR7. Specified for L and R of each DAC.
8. Fullscale output voltage when VREFH=AVDD
<Pre-E-01>
-8-
2006/10
[ASAHI KASEI]
[AK7740ET]
(2) DC characteristics
(VDD=AVDD=DVDD=3.0~3.6V,Ta=25°C)
Parameter
High level input voltage
Low level input voltage
High level output voltage Iout=-100µA
Low level output voltage Iout=100µA
Input leak current
Note 1)
Input leak current (pull-down) Note 2)
Input leak current (XTI pin)
Symbol
VIH
VIL
VOH
VOL
Iin
Iid
Iix
Min
80%VDD
Typ
Max
20%VDD
VDD-0.5
0.5
±10
22
24
Unit
V
V
V
V
µA
µA
µA
Note:
1.
2.
3.
Pins with pull-down resistors and the XTI pin are not included
Pull-down pins are JX, SDIN and SDINA. The pull-down resistor value is 156kΩ
For input/output levels in this datasheet: the low level will be represented as "L" or 0, and the high
level as "H" or 1. In principle, "0" and "1" will be used to represent the bus (serial/parallel) such as
registers.
(3) Current consumption
(AVDD=DVDD=3.0V~3.6V, Ta=25°C; master clock (XTI)=24.576MHz=512fs[fs=48kHz];
When operating 4 DAC channels with a 1kHz sine wave full-scale input to each of ADC analog input pin)
Power supply
Parameter
Power supply current
1) During operation
a) AVDD
Min
Note 1)
2) INIT_RESET ="L"
Note 2)
2) INIT_RESET ="L"
Max
34
b) DVDD
c) Total (a+b)
Power consumption
1)During operation
a) AVDD
b) DVDD
c) Total (a+b)
Typ
31
65
5
112
102
214
17
Note 1)
Note 2)
Unit
mA
90
324
mA
mA
mA
mW
mW
mW
mW
Note:
1) Varies slightly depending on sampling frequency and the content of the DSP program.
2) This is a reference value when using a crystal oscillator. Most of the supply current during the initial reset state
is in the oscillator section; the value varies slightly depending on the type of crystal oscillator and external
circuit.
<Pre-E-01>
-9-
2006/10
[ASAHI KASEI]
[AK7740ET]
(4) Digital filter characteristics
Values described below are design values, cited for reference.
4-1) ADC Section:
(Ta=25°C; AVDD,DVDD =3.0V~3.6V; fs=48kHz; HPF=off)
Parameter
Symbol
Min
Pass band
(-0.02dB)
PB
0
(-6.0dB)
0
Stop band
(Note 1)
SB
26.5
Pass band ripple
(Note 2)
PR
Stop band attenuation (Note3,4)
SA
80
Group delay distortion
∆GD
Group delay
(Ts=1/fs)
GD
Typ
Max
21.768
24.00
±0.005
0
29.3
Unit
kHz
kHz
kHz
dB
dB
us
Ts
Note: : HPF response is not included
1. The stop band is from 26.5kHz to 3.0455MHz when fs = 48kHz.
2. The pass band is from DC to 21.5kHz from DC when fs = 48kHz.
3. When fs = 48kHz, the modulator samples the analog input at 3.072MHz. The input signal is not attenuated by
the digital filter in multiple bands (n x 3.072MHz ± 21.99kHz; n=0, 1, 2, 3...) of the sampling frequency.
4-2) DAC section
(Ta=25°C; AVDD,DVDD =3.0V~3.6V; fs=48kHz)
Parameter
Symbol
Min
Digital filter
PB
0
Pass band ±0.07dB (Note 1)
(-6.0dB)
Stop band
(Note 1)
SB
26.2
Pass band ripple
PR
Stop band attenuation
SA
47
Group delay
(Note 2)
GD
Digital filter+SCF
Amplitude characteristics
0~20.0kHz
Typ
Max
Unit
24.0
21.7
-
15
kHz
kHz
kHz
dB
dB
Ts
±0.5
dB
±0.07
Note:
1. Pass band and stop band frequencies are proportional to "fs" (system sampling rate), and are equal to PB =
0.4535fs (@-0.06dB) and SB = 0.546fs, respectively.
2. Calculated delay time in the digital filter from setting the 24-bit data of both channels on the input data
register to the output of analog signal.
<Pre-E-01>
- 10 -
2006/10
[ASAHI KASEI]
[AK7740ET]
(5) Switching characteristics
5-1) System clock
(AVDD=DVDD=3.0V~3.6V,Ta=-10~70°C,CL=20pF)
Parameter
Symbol
Min
Master clock (XTI)
a) With crystal oscillator
384fs: frequency
fMCLK
12.288
512fs: frequency
fMCLK
16.384
b) With external clock:
40
Duty factor (≤18.432MHz)
45
(>18.432MHz)
:Frequency
fMCLK
10.0
: High level width
tMCLKH
16
: Low level width
tMCLKL
16
Clock rise time
tCR
Clock fall time
tCF
LRCLK sampling frequency
Slave mode :clock rise time
Slave mode :clock fall time
fs
32
Typ
Max
Unit
18.432
24.576
19
25
MHz
MHz
50
50
24.576
60
55
25
%
6
6
48
1
tLR
tLF
fBCLK
BITCLK
Note 1)
Slave mode: High level width
tBCLKH
Slave mode: Low level width
tBCLKL
Slave mode :clock rise time
tBR
Slave mode :clock fall time
tBF
Note 1) 48fs mode can only be applied in slave mode.
48
150
150
50
MHz
ns
ns
ns
ns
6
6
kHz
fs
ns
ns
6
6
fs
ns
ns
ns
ns
64
5-2) Reset
(AVDD=DVDD=3.0V~3.6V,Ta=-10~70°C,CL=20pF)
Parameter
Symbol
tRST
INIT_RESET
Note 1)
S_RESET
tRST
min
150
typ
max
150
Unit
ns
ns
Note 1) “L” is acceptable when power is turned on, but ”H” requires a stable master clock input.
<Pre-E-01>
- 11 -
2006/10
[ASAHI KASEI]
[AK7740ET]
5-3) Audio interface
(AVDD=DVDD=3.0V~3.6V,Ta=-10~70°C,CL=20pF)
Parameter
Symbol
Slave mode
BITCLK frequency
fBCLK
BITCLK low level width
tBCLKL
BITCLK high level width
tBCLKH
Delay time from BITCLK"↑" to LRCLK tBLRD
Delay time from LRCLK to BITCLK "↑" tLRBD
Delay time from LRCLK to serial data
tLRD
output
Delay time from BITCLK to serial data
tBSOD
output
Serial data input latch hold time
tBSIDS
Serial data input latch setup time
tBSIDH
Master mode
BITCLK frequency
fBCLK
BITCLK duty factor
Delay time from BITCLK"↑" to LRCLK tBLRD
Delay time from LRCLK to BITCLK"↑" tLRBD
Delay time from LRCLK to serial data
tLRD
output
Delay time from BITCLK to serial data
tBSOD
output
Serial data input latch hold time
tBSIDS
Serial data input latch setup time
tBSIDH
<Pre-E-01>
- 12 -
Min
Typ
48
150
150
40
40
64
Max
Unit
80
fs
ns
ns
ns
ns
ns
80
ns
40
40
ns
ns
64
50
80
fs
%
ns
ns
ns
80
ns
40
40
40
40
ns
ns
2006/10
[ASAHI KASEI]
[AK7740ET]
5-4) Microcontroller interface
(AVDD=DVDD=3.0V~3.6V,Ta=-10~70°C,CL=20pF)
Parameter
Symbol
Microcontroller interface signal
tWRF
RQ Fall time
max
Unit
8
ns
tWRR
8
ns
SCLK fall time
SCLKrise time
SCLK low level width
SCLK high level width
Microcontroller to AK7740
tSF
tSR
tSCLKL
tSCLKH
8
8
30
30
ns
ns
ns
ns
Time from RESET "↓" to RQ "↓"
tREW
200
ns
Time from RQ "↑" to RESET "↑"
tWRE
200
ns
tWRQH
200
ns
Time from RQ "↓" to SCLK"↓"
tWSC
200
ns
Time from SCLK"↑" to RQ "↑"
tSCW
6×tMCLK
ns
SI latch setup time
SI latch hold time
AK7740 to microcontroller
Time from SCLK"↑" to DRDY"↓"
Time from SI"↑"to DRDY"↓"
SI high level width
Delay time from SCLK"↓" to SO output
AK7740 to microcontroller
(RAM DATA read-out)
SI latch setup time (SI="H")
SI latch setup time (SI="L")
SI latch hold time
Time from SCLK"↓" to SO
tSIS
tSIH
100
100
ns
ns
RQ Rise time
min
typ
Note 1)
RQ high level width
tSDR
tSIDR
tSIH
tSOS
3×tMCLK
3×tMCLK
100
ns
ns
ns
ns
100
ns
ns
ns
ns
3×tMCLK
tRSISH
tRSISL
tRSIH
tSOD
30
30
30
Note 1) Except for external jump code set at reset state.
<Pre-E-01>
- 13 -
2006/10
[ASAHI KASEI]
[AK7740ET]
(6) Timing waveform
6-1) System clock
1/fMCLK
1/fMCLK
tMCLK=1/fMCL
XTI
VIH
tMCLK
tMCLK
tCR
VIL
tCF
1/fs
1/fs
VIH
LRCLK
tLR
1/fBCLK
1/fBCLK
VIL
tLF
tBCLK=1/fBCLK
VIH
BITCLK
tBR
tBCLK
VIL
tBF
tBCLK
6-2) Reset signal
INIT_RESET
S_RESET
tRST
VIL
<Pre-E-01>
- 14 -
2006/10
[ASAHI KASEI]
[AK7740ET]
6-3) Audio interface
LRCLK
50%DVDD
tBLRD
tLRBD
BITCLK
50%DVDD
tLRD
tBSOD
SDOUT
SDOUTA
50%DVDD
tBSIDS
SDIN
SDINA
<Pre-E-01>
tBSIDH
50%DVDD
- 15 -
2006/10
[ASAHI KASEI]
[AK7740ET]
6-4) Microcontroller interface
* Microcontroller interface signals
RQ
tWR
tWR
tSF
VIH
VIL
tSR
VIH
VIL
SCLK
tSCLKL
tSCLKH
* Microcontroller to AK7740
tWRE
tREW
50%DVDD
S_RESET
50%DVDD
RQ
tWRQ
50%DVDD
SCLK
tWSC
tSCW
tWSC
tSCW
SI
tSIS
50%DVDD
tSIH
NOTE : Timing for RUN state is the same except that RESET is set to a "H"
RESET represents system reset in normal use.
<Pre-E-01>
- 16 -
2006/10
[ASAHI KASEI]
[AK7740ET]
z AK7740 to microcontroller (DBUS data)
1) DBUS data for 24-bit data output.
S_RESET
DVDD
50%DVDD
DVSS
RQ
DVDD
50%DVDD
DVSS
50%DVDD
DVSS
SI
50%DVDD
tSDR
DRDY
50%DVDD
tSOS
SCLK
50%DVDD
SO
2) DBUS data for less than 24-bits data output (when using SI)
DVDD
50%DVDD
DVSS
S_RESET
RQ
tSIH
DVDD
50%DVDD
DVSS
50%DVDD
SI
tSIDR
DRDY
50%DVDD
50%DVDD
SCLK
tSOS
50%DVDD
SO
<Pre-E-01>
- 17 -
2006/10
[ASAHI KASEI]
[AK7740ET]
z AK7740 to microcontroller (RAM DATA read-out)
S_RESET
50%DVDD
DVSS
RQ
50%DVDD
DVSS
tRSISL
SI
50%DVDD
tRSIS
tRSIH
SCLK
50%DVDD
SO
50%DVDD
tSOD
<Pre-E-01>
- 18 -
2006/10
[ASAHI KASEI]
[AK7740ET]
Functional Description
(1) Various setting
1-1) SMODE : slave and master mode selector pin
Sets LRCLK and BITCLK to either input or output.
a) Slave mode :SMODE="L"
LRCLK (1fs) and BITCLK (64fs or 48fs ) are inputs.
b) Master mode: SMODE="H"
LRCLK (1fs) and BITCLK (64fs) are outputs.
Note) SMODE is required to be fixed “L” or “H”. After releasing initial reset ( INIT_RESET =”L”→”H”), this
pin may only change during a system reset state ( S_RESET ="L") . In slave mode, phase matching between
internal and external clocks start when system reset is released (see (8.(4)), resetting). Do not change SMODE
during normal operation.
(2) Control registers
The control registers can be set via the microcontroller interface in addition to the control pins.These registers
consist of four parts, and each register contains 8-bits. For details about writing to the control registers, see the
description of the microcontroller interface.This section describes the control register maps.
Command
Code
Write Read
60h
64h
68h
6Ch
70h
74h
78h
7Ch
Name
D7
CONT0
CONT1
CONT2
CONT3
CKS1
DATARAM
SW2
ISEL[2]
TEST: for TEST (input 0,X: input data ignored, but a 0 should be written).
D6
D5
D4
D3
D2
D1
D0 Default
CKS0
RM
SW1
ISEL[1]
DIF
BANK[1]
SW0
ISEL[0]
DIF1
BANK[0]
PSDA2
SW3
DIF0
CMP_N
PSDA1
OUTAE
DISCK
SS[1]
TEST
PSAD
SELCKO
SS[0]
TEST
TEST
X
X
X
X
00h
00h
00h
00h
Data can be loaded into the control registers only when S_RESET = "L". Do not attempt to change any value in
the control register when S_RESET = "H”.
1. CONT0 can be set only when system reset ( S_RESET = "L").
2. CONT1~3 should be set when system reset ( S_RESET = "L"), otherwise noise will be output.
Prior to changing the input selector (CONT3: ISEL[2:0], clocks should be applied and the ADC should be in
normal operation mode. The ADC is powered up by setting CONT3:PSAD = 0. Spontaneous changes to the
input selector may result in output noise (generated in the ADC data), so an external mute circuit after the DAC
output may be required.
3. Default setting is the same value that is initialized by initial reset ( INIT_RESET =”L” ).
<Pre-E-01>
- 19 -
2006/10
[ASAHI KASEI]
[AK7740ET]
2-1) CONT0 : clock and interface selector
This register is enabled only during system reset state ( S_RESET =”L”).
Command
Code
Write Read
Name
D7
D6
D5
D4
D3
D2
D1
D0
Default
60h
CONT0
CKS1
CKS0
DIF
DIF1
DIF0
DISCK
SELCKO
X
00h
70h
c D7,D6:CKS1 CKS0 master clock select
Mode
1
2
3
4
CKS1(D7)
0
0
1
1
CKS0(D6)
0
1
0
1
512fs
384fs(Program steps of DSP are also limited 384 steps)
TEST
TEST
d D5:DIF audio interface selector
0: MSB-justified
2
2
1: I S compatible (all input / output pins are I S compatible)
e D4, D3:DIF1, DIF0 SDIN input mode selector
Mode
D4
D3
1
0
0
MSB justified (24bit)
2
0
1
LSB justified (24bit)
3
1
0
LSB justified (20bit)
4
1
1
LSB justified (16bit)
2
Note) When D5 = 1, the state is I S compatible independent of mode setting, but set this register to Mode 1.
f D2:DISCK LRCLK,BITCLK output control
0: Normal Operation
2
1: Sets BITCLK = ”L” and LRCLK = ”H” int master mode. (for I S compatible setting, it changes to
LRCLK=”L”.) This setting is only available for analog input and analog output. When this mode is selected,
SDIN and SDOUT are not available.
g D1:SELCKO CLKO output selector.
0: CLKO outputs the same frequency as XTI.
1: CLKO outputs “L” level. After setting CONT0 (when the last clock of SCLK rises), CLKO frequency will
change.
h D0: Always 0
Note) Underlined settings for c~g indicates default.
<Pre-E-01>
- 20 -
2006/10
[ASAHI KASEI]
[AK7740ET]
2-2) CONT1: RAM control
Command
Code
Write Read
Name
D7
D6
D5
D4
D3
D2
D1
64h
CONT1
DATARAM
RM
BANK[1]
BANK[0]
CMP_N
SS[1]
SS[0]
74h
D0 Default
X
00h
c D7: DATARAM addressing mode selector
0:Ring addressing mode
1:Linear addressing mode
DATARAM has 256-word x 24-bit with two address pointers (DP0, DP1).
Ring addressing mode: increments starting address by one every sample.
Linear addressing mode: starting address is always the same: DP0 = 00h and DP1 = 80h.
d D6:RM: decompress bit mode
0: SIGN bit
1: Random data
When the compress and decompress function is selected (D3:CMP_N = 0), this bit determines the content o
f the decompressed LSB bits.
e D5,D4:BANK[1:0] DLRAM setting
Mode
D5
D4
Memory
0
0
0
24bit 3kword (RAM A)
1
0
1
12bit 6kword (RAM A)
2
1
0
12bit 4kword (RAM A),24bit 1kword (RAM B)
3
1
1
24bit 1kword (RAM A),12bit 4kword (RAM B)
Note) In mode 0 or 1, both pointer 0 and 1 are available for both RAM A and B.
In mode 2 or 3, pointer 0 is available for RAM A and pointer 1 is available for RAM B.
f D3:CMP_N 12bitDLRAM compress & decompress selector
In mode 1,2 or 3, this register turns the compress / decompress function ON or OFF.
0: Compress & decompress function ON
When writing to DLRAM the DBUS data is compressed to 12-bits, and when reading from DLRAM, the
data is decompressed to 16-bits.
1: Compress & decompress function OFF
12-bits of DBUS data is always written to DLRAM, and 12-bit data is read from the DLRAM and 000h
is added for the LSB bits.
g D2,D1:SS[1:0] DLRAM setting of sampling timing (only for RAM A)
Mode
D2
D1
RAM A mode selected by BANK[1:0]
0
0
0
Update every sampling time
1
0
1
Update every 2 sampling time
2
1
0
Update every 4 sampling time
3
1
1
Update every 8 sampling time
Note) When the mode 1,2 or 3 is selected, it comes out aliasing.
h D0: Input always 0
Note) Underlined settings for c~g indicates default.
<Pre-E-01>
- 21 -
2006/10
[ASAHI KASEI]
[AK7740ET]
2-3) CONT2 : DAC ,DSP control
Command
Code
Write Read
Name
D7
D6
D5
D4
D3
D2
D1
D0
Defaul
t
68h
CONT2
SW2
SW1
SW0
PSDA2
PSDA1
TESTT
TEST
X
00h
78h
c D7,D6,D5: SW2, SW1, SW0 internal path setting
SW2(D7)
0
SW1(D6)
0
SW0(D5)
0
Normal operation
These settings are reserved for test; set these values to “0” (refer to the block-diagram).
d D4:PSDA2 DAC2 power down control
0:Normal operation
1:DAC2 power down
If not using DAC2, set this value to “1”, and DAC2 will RESET.
When changing to normal operation, set this value to “0” at system reset.
e D3:PSDA1 DAC1 power down control
0:Normal operation
1:DAC1 power down
In the case of not using DAC1, set this value to “1” and DAC1 will be in RESET.
When changing to normal operation, set this value to “0” at system reset.
f D2:TEST
0:Normal operation
1:Test mode (Do NOT use this mode)
g D1:TEST
0:Normal operation
1:Test mode (Do NOT use this mode)
h D0: Always input 0
Note): Underlined settings for c~h indicates default.
<Pre-E-01>
- 22 -
2006/10
[ASAHI KASEI]
[AK7740ET]
2-4) CONT3: ADC control
Command
Code
Write Read
Name
D7
D6
D5
D4
D3
D2
D1
D0
Defaul
t
6Ch
CONT3
ISEL[2]
ISEL[1]
ISEL[0]
SW3
OUTAE
PSAD
TEST
X
00h
7Ch
c D7,D6,D5:ISEL[2:0] analog input selector setting
ISEL[2](D7)
ISEL[1](D6)
ISEL[0](D5)
0
0
0
1
0
0
1
0
1
1
1
0
1
1
1
Analog input pin
AINL-,AINL+,AINR-,AINR+
AINL1,AINR1
AINL2,AINR2
AINL3,AINR3
AINL4,AINR4
d D4: SW3 internal path setting
0:Normal operation (ADC SDATA select)
1:DSP SDOUTD1 select
e D3:OUTAE SDOUT disable
0:SDOUTA=”L”
1:Output data selected by SW3
f D2:PSAD ADC power down
0:Normal operation
1:ADC power down
When not using the ADC, set this value to “1”, and the ADC will be in RESET.
The digital output data of the ADC will 00000h in power down mode.
When changing to normal operation, set this value to “0” at system reset.
g D1:TEST
0:Normal operation
1:TESTmode (Do NOT use this mode )
h D0: Always input 0
Note) Underlined settings of c~g indicates default.
<Pre-E-01>
- 23 -
2006/10
[ASAHI KASEI]
[AK7740ET]
(3) Power supply startup sequence
Turn on the power by setting INIT_RESET = “L” and S_RESET = “L”. This sets up VREF (analog reference
level). Then initizlize the control registers by setting INIT_RESET = “H”.
Note 1) Only set INIT_RESET during power-up.
Note 1): Set INIT_RESET = "H" after starting oscillation when a crystal oscillator is used.
This setting time may differ depending on the crystal oscillator and its external circuit.
NOTE: Do not stop the system clock (slave mode: XTI, LRCLK, BITCLK, master mode: XTI) except when
S_RESET = "L". If these clock signals are not supplied, excess current will flow due to dynamic logic that is
used internally, and an operation failure may result.
Do not set S_RESET = "H" during INIT_RESET = "L". This will stop the oscillator or cause it to be unstable.
AVDD
DVDD
INIT_RESET
S_RESET
Power OF
F
When a crystal oscillator is
used, ensure stable
oscillation in this period.
Power supply startup sequence
<Pre-E-01>
- 24 -
2006/10
[ASAHI KASEI]
[AK7740ET]
(4) Resetting
The AK7740 has two reset pins: INIT_RESET and S_RESET .
The INIT_RESET pin sets up VREF and initializes the AK7740, as shown in "Power supply startup sequence
section 3)."
The system is reset when S_RESET =”L”. (Description of "reset" is for "system reset".)
Under of system reset, program write operation executes normally (except for write operation during running).
The ADC and DAC sections are also reset during system reset. (The ADC output is MSB first 00000h and the DAC
output is AVDD/2). However, VREF will be active and LRCLK and BITCLK in the master mode will be inactive.
Release system reset by setting S_RESET to "H", which will activate the internal counter. This counter generates
LRCLK and BITCLK in the master mode. When the system reset is released in slave mode, internal timing will be
actuated in synchronization with "Ç" of LRCLK (when the standard input format is used). Timing between the
external and internal clocks is adjusted at this time. If the phase difference between LRCLK and internal timing is
within ±1/16 of the input sampling cycle (1/fs) during the operation, the operation is performed with the internal
timing remaining unchanged. If the phase difference exceeds this range, the phase is adjusted by synchronization with
"Ç" of LRCLK (when the standard input format is used). This circuit prevents failure of synchronization with the
external circuit. For some time after returning to the normal state after loss of synchronization, normal data will not
be valid. Change the frequency of the clock, SMODE or analog input selector while the system is in reset.
When S_RESET is set to “H”, the reset state is cancelled, and the internal DRAM is cleared from the rising edge of
LRCLK. It takes 8fs (167usec at fs = 48kHz) to clear the internal DRAM.
The ADC section can output 516 cycles LRCLK after its internal counter starts. (The internal counter starts at the first
rising edge of LRCLK in master mode. In slave mode, it starts at the end of 2-LRCLK after release of system reset.)
The AK7740 is in normal operation mode when S_RESET is set to "H".
When INIT_RESET or S_RESET changes, the status of the DAC section also changes to power down or release
mode, which causes a click noise at the output. The SMUTE function does not mute this click, ao an external mute
circuit is required to avoid any click noise.
<Pre-E-01>
- 25 -
2006/10
[ASAHI KASEI]
[AK7740ET]
(5) System clock
The required system clock is XTI (384fs/512fs), LRCLK (fs) and BITCLK (64fs) in the slave mode, and it is XTI
(384 fs/512 fs) in the master mode. LRCLK corresponds to the standard digital audio rate (32 kHz, 44.1 kHz, and
48 kHz).
Fs
32.0kHz
44.1kHz
48.0kHz
XTI(Master Clock)
512fs
384fs
16.3840MHz
12.2880MHz
22.5792MHz
16.9344MHz
24.576MHz
18.4320MHz
BITCLK
64fs
2.0480MHz
2.8224MHz
3.0720MHz
5-1) Master clock (XTI pin)
The master clock is produced by connecting a crystal oscillator between the XTI pin and XTO pin or by inputting
an external clock into the XTI pin while the XTO pin is left open.
5-2) Slave mode
The required system clock is XTI, LRCLK (1 fs) and BITCLK (48/64fs).
The master clock (XTI) and LRCLK must be synchronized, but the phase is not critical.
5-3) Master mode
The required system clock is XTI (384fs/512fs). When the master clock (XTI) is input, LRCLK (1fs) and BITCLK
(64fs) will be outputted from the internal counter synchronized with the XTI. LRCLK and BITCLK will not be
active during initial reset ( INIT_RESET ="L") and system reset ( S_RESET ="L").
<Pre-E-01>
- 26 -
2006/10
[ASAHI KASEI]
[AK7740ET]
(6) Audio data interface (internal connection mode)
The serial audio data pins SDIN, SDINA, SDOUT and SDOUTA are interfaced with an external system, using
LRCLK and BITCLK. The control registers (CONT2 and CONT3) set the audio interface parameters. The default
2
data format is MSB-first two's complement. The data format can be changed to I S compatible mode by setting the
2
control register CONT0:DIF (D5) to “1” (all input/output audio data pin interfaces are in I S compatible mode.)
The input SDIN and SDINA formats are MSB justified 24-bit at initialization. Setting the control registers CONT0:
DIF1 (D4), DIF0 (D3) will cause SDIN to be compatible with LSB justified 24-bit, 20-bit and 16-bit. (SDINA is fixed
to 24-bit MSB justified only) (Note: CONT0 DIF(D5)=0). Individual setting of SDIN and SDINA is not allowed.
The output SDOUT is fixed at 24-bit MSB justified only.
In slave mode, BITCLK corresponds to both 64fs and 48fs. 64fs is the recommended BITCLK. 64fs examples are
illustrated here:
6-1) Standard input format (DIF = 0: default set value)
a) Mode 1 (DIF1, DIF0 = 0,0: default set value)
LRCLK
Right ch
Left ch
BITCLK
31 30 29
SDIN,SDINA
M 22 21
10 9 8 7 6
5 4 3 2
1 0 31 30 29
M 22 21
2 1 L
10 9 8 7 6
5 4 3 2
1 0
2 1 L
M : MSB, L : LSB
* For MSB-justified 20-bit data into SDIN, SDINA input four "0" following the LSB.
b) Mode 2, Mode 3, Mode 4
LRCLK
Right ch
Left ch
BITCLK
SDIN
mode2
23 22 21 20 19 18 17 16 15
1
0
Don't Care
M 22 21 20 19 18 17 16 15
1
L
31 30
23 22 21 20 19 18 17 16 15
1
0 31 30
Don't Care
M 22 21 20 19 18 17 16 15
1
L
SDIN
mode3
Don't Care
M 18 17 16 15
1
L
Don't Care
M 18 17 16 15
1
L
SDIN
mode4
Don't Care
M
1
L
Don't Care
M
1
L
SDIN
SDIN
SDIN
<Pre-E-01>
M : MSB, L : LSB
Mode 2: (DIF1, DIF0) = (0, 1) LSB justified 24-bit
Mode 3: (DIF1, DIF0) = (1, 0) LSB justified 20-bit
Mode 4: (DIF1, DIF0) = (1, 1) LSB justified 16-bit
- 27 -
2006/10
[ASAHI KASEI]
[AK7740ET]
6-2) I2S compatible input format (DIF=1)
LRCLK
Left ch
Right ch
BITCLK
9 8 7
31 30 29 28
SDIN,SDINA
2
M 22 21
6
5 4
3 2 1 0 31 30 29 28
1 L
9 8 7 6 5 4 3 2
2
M 22 21
1 0
1 L
M : MSB, L : LSB
Mode 1: (DIF1(D4), DIF0(D3)) = (0, 0) must be set.
6-3) Standard output format (DIF=0: default set value)
LRCLK
Right ch
Left ch
BITCLK
SDOUT
SDOUTA
31 30 29
10 9 8 7
M 22 21
2
6 5 4
3 2 1 0 31 30 29
1 L
M 22 21
10 9 8 7 6 5 4 3 2 1 0
2
1 L
M : MSB, L : LSB
6-4) I2S compatible output format (DIF=1)
LRCLK
Left ch
Right ch
BITCLK
31 30 29 28
SDOUT
SDOUTA
M 22 21
9 8 7
2
6
5 4
3 2 1 0 31 30 29 28
1 L
M 22 21
9 8 7
2
6
5 4
3 2 1 0
1 L
M : MSB, L : LSB
<Pre-E-01>
- 28 -
2006/10
[ASAHI KASEI]
[AK7740ET]
(7) Interface with microcontroller
The microcontroller interface consists of six control signals; RQ (request), SCLK (serial data input clock), SI
(serial data input), SO (serial data output), RDY (ready) and DRDY (data ready). Both write and read operations are
enabled during system reset and run modes. During reset , writing to the control register, program RAM, coefficient
RAM, offset RAM, external conditional jump code, and reading from the program RAM, coefficient RAM and offset
RAM, are enabled. During the run phase, writing of coefficient RAM, offset RAM and external conditional jump
code, and reading of data on the DBUS (data bus) from the SO, are enabled. The data is MSB first serial I/O.
To transfer data to the microcontroller, start by setting RQ “L”, which enables a data read from the DBUS. The
AK7740 reads SI data when SCLK rises, and outputs to SO when SCLK falls. The data format is command followed
by address.
When RQ changes to “H”, then one command is finished. New command requests require setting RQ to “L”
again. When the DBUS data is read, leave RQ =”H” (command code input is not required).
Conditions
for use
RESET
phase
RUN
phase
Code name
CONT0
CONT1
CONT2
CONT3
PRAM
CRAM
OFRAM
External condition jump
Test
CRAM rewrite
preparation
CRAM rewrite
OFRAM rewrite
preparation
OFRAM rewrite
External condition jump
Command Code List
Command code
Note:
WRITE
READ
60h
70h
For the function of each bit,
See the description of Control
64h
74h
Registers
68h
78h
6Ch
7Ch
C0h
C1h
A0h
A1h
90h
91h
C4h
82h
Reserved for test
A8h
Must occur before CRAM rewrite
A4h
98h
-
Must occur before OFRAM rewite
94h
C4h
-
Same command as RESET
NOTE: Do not send any other command codes.
If there is no communication with the microcontroller, set the SCLK to "H” and the SI to "L" for use.
<Pre-E-01>
- 29 -
2006/10
[ASAHI KASEI]
[AK7740ET]
7-1) Write during reset phase
7-1-a) Control register write (during reset phase)
The data is comprised of two bytes that perform control register write operations (during reset phase). When the
current data has been entered, the new data is sent when the 16th cycle of SCLK.
Data transfer procedure
c Command code
60h,64h,68h,6Ch
d Control data
(D7 D6 D5 D4 D3 D2 D1 D0)
For the function of each bit, see the description of control registers, (section 2).
S_RESET
RQ
SCLK
SI
60h
64h
D7 ***D1 D0
D7 ***D1 D0
SO
Note) It must be set always 0 to D0
Control registers write operation
<Pre-E-01>
- 30 -
2006/10
[ASAHI KASEI]
[AK7740ET]
7-1-b) Program RAM writes (during reset phase)
Write to the Program RAM during the reset phase with data consisting of a set of seven bytes. When all data has been
transferred, the RDY terminal is set "L". Upon completion of the PRAM write, RDY returns “H” to allow the next
data bit input. When writing data of continuous addresses, input the data as they are (no command code or address is
required). To write discontinuous data, shift the RQ terminal from "H" to "L" again. Then input the command code,
address and data in that order.
Data transfer procedure
c Command code C0h
d Address upper
e Address lower
f Data
g Data
h Data
i Data
( 1 1 0 0 0 0 0 0)
( 0 0 0 0 0 0 0 A8)
(A7 . . . . . . . A0)
(D31 . . . . . . D24)
(D23 . . . . . . D16)
(D15 . . . . . . D8)
(D7 . . . . . . D0)
S_RESET
RQ
SCLK
SI
11000000
0000000
A7 ****A1A0
D31***** D0
D31***** D0
RDY
SO
Input of continuous address data into PRAM
S_RESET
RQ
SCLK
SI
11000000 0000000A8 A7**A1A0 D31***D0
11000000 0000000A8 A7**A1A0
RDY
SO
Input of discontinuous address data into PRAM
<Pre-E-01>
- 31 -
2006/10
[ASAHI KASEI]
[AK7740ET]
7-1-c) Coefficient RAM write (during reset phase)
The data comprising a set of five bytes is used to perform coefficient RAM write operations (during reset phase).
When all data has been transferred, the RDY terminal goes "H". Upon completion the CRAM write, RDY goes to
"H" to allow the next data to be inputted. When writing data of continuous addresses, input the data as they are (no
command code or address is required). To write discontinuous data, shift the RQ terminal from "H" to "L". Then
input the command code, address and data in that order.
Data transfer procedure
c Command code A0h
d Address upper
e Address lower
f Data
g Data
(1 0 1 0 0 0 0 0)
( 0 0 0 0 0 0 0 A8)
(A7 . . . . . . . A0)
(D15 . . . . . . D8)
(D7 . . . . . . D0)
S_RESET
RQ
SCLK
SI
10100000
0000000 A8
A7****A1A0
D15****D0
D15****D0
RDY
SO
Input of continuous address data into CRAM
S_RESET
RQ
SCLK
SI
10100000 0000000 A8 A7***A1A0 D15****D0
10100000 0000000 A8 A7***A1A0 D15*
RDY
SO
Input of discontinuous address data into CRAM
<Pre-E-01>
- 32 -
2006/10
[ASAHI KASEI]
[AK7740ET]
7-1-d) Offset RAM write (during reset phase)
The data comprising a set of five bytes is used to perform offset RAM write operations (during reset phase). When all
data has been transferred, the RDY terminal goes to "H". Upon completion of writing into the OFRAM, RDY goes to
"H" to allow the next data to be input. When data of continuous addresses are written, input the data as they are. To
write discontinuous data, shift the RQ terminal from "H" to "L". Then input the command code, address and data in
that order.
Data transfer procedure
c Command code 90h
d Address
e Data
f Data
g Data
(1 0 0 1 0 0
( 0 0 A5 A4 .. .
(0 0 0 0 0 0
(0 0 0 D12 D11 *
(D7 . . . . .
0 0)
. A0 )
0 0)
* . D8 )
. D0 )
S_RESET
RQ
SCLK
SI
10010000
00A5****A0
00000000
000D12***D8 D7****D1D0
RDY
SO
Input of data into OFRAM
<Pre-E-01>
- 33 -
2006/10
[ASAHI KASEI]
[AK7740ET]
7-1-e) External conditional jump code write (during reset phase)
The data comprising a set of two bytes is used to perform an external conditional jump code write operation. Input the
data during either the reset or operation phase, and the input data are set to the specified register at the leading edge of
the LRCLK. When all data bits have been transferred, the RDY terminal goes to "L". Upon completion of writing, it
goes to "H". A jump command will be executed if there is any one agreement between "1" of each bit of external
condition code eight bits (soft set), plus one bit (hard set) at the external input terminal JX and "1" of each bit of the
IFCON field. The data during the reset phase can be written only before release of the reset, after all data has been
transferred. RQ Transition from "L" to "H" in the write operation during the reset phase must be executed after
three LRCLK in slave mode or one LRCLK in master mode, respectively, from the trailing edge of LRCLK after
release of the reset. Then RDY goes to "H" after capturing the rise of the next LRCLK. Write operations from the
microcontroller are disabled until RDY goes to "H". The IFCON field provides external conditions written on the
program. It resets to 00h by INIT_RESET =”L”, however, it remains previous condition even S_RESET =”L”.
2
Note: LRCLK phase is inverted in the I S-compatible mode.
7
0 JX
„„„„„„„„†
Ç
Check if there is any one agreement between the bit specified in IFCON and
"1" in the external condition code
16
È
8
IFCON field ‹‹‹‹‹‹‹‹
Data transfer procedure
c Command code
C4h ( 1 1 0 0 0 1 0 0)
d Code data
(D7 . . . . . D0)
External condition code
Max 1LRCLK
S_RESET
SCLK
SI
11000100 D7 **** D0
SO
RQ
L ch
LRCLK
RDY
R ch
2LRCLK(max)
Timing for external conditional jump write operation (during reset phase)
<Pre-E-01>
- 34 -
2006/10
[ASAHI KASEI]
[AK7740ET]
7-2) Read during reset phase
7-2-a) Control register data read (during reset phase)
To read data written into the control registers, input the command code and 16 bits of SCLK. After the command code
input, the data D7 to D1 outputs from SO synchronized with the falling edge of SCLK. D0 is invalid, so ignore this
bit.
Data transfer procedure
c Command code
70h,74h,78h,7Ch
S_RESET
RQ
SCLK
SI
SO
70h (example)
74h (example)
D7 **** D1
D7 **** D1
Reading of Control Register data
<Pre-E-01>
- 35 -
2006/10
[ASAHI KASEI]
[AK7740ET]
7-2-b) Program RAM read (during reset phase)
To read data written into PRAM, input the command code and the address to be read out. After that, set SI to "H" and
SCLK to "L". The data is clocked out from SO synchronized with the falling edge of SCLK (ignore the RDY
operation that will occur in this case). If there are continuous addresses to be read, repeat the above procedure starting
from the step where SI is set to "H".
Data transfer procedure
cCommand code input C1h ( 1 1 0 0 0 0 0 1 )
dRead address input MSB ( 0 0 0 0 0 0 0 A8)
eRead address input LSB
(A7 . . . . A0)
S_RESET
RQ
SCLK
SI
11000001
0000000 A8 A7 **** A1 A0
D31 **** D0
SO
D31 **** D0
RDY
Reading of PRAM data
<Pre-E-01>
- 36 -
2006/10
[ASAHI KASEI]
[AK7740ET]
7-2-c) CRAM data read (during reset phase)
To read out the coefficient data, input the command code and the address to be read out. After that, set SI to "H" and
SCLK to "L”. The data is clocked out from SO synchronized with the falling edge of SCLK.If there are continuous
addresses to be read, repeat the above procedure starting from the step where SI is set to "H".
Data transfer procedure
c Command code A1h
d Address upper
e Address lower
(1 0 1 0 0 0 0 1)
( 0 . . . . . . A8)
(A7 . . . . . . A0)
S_RESET
RQ
SCLK
SI
10100001
0000000A8
A7 **** A1A0
D15 **** D0
SO
D15 **** D0
RDY
Reading of CRAM data
<Pre-E-01>
- 37 -
2006/10
[ASAHI KASEI]
[AK7740ET]
7-2-d) OFRAM data read (during reset phase)
Read out the offset data during the reset phase. To read it, input the command code and the address to be read. After
that, set SI to "H" and SCLK to "L". This completes preparation for outputting the data. Set SI to "L", and the data is
clocked out synchronized with the falling edge of SCLK. If there are continuous addresses to be read, repeat the
above procedure starting from the step where SI is set to “H”.
Data transfer procedure
c Command code
d Address
91h ( 1 0 0 0 1 0 0 0 1 )
( 0 0 A5 . . . . A0)
S_RESET
RQ
SCLK
SI
SO
10010000
00 A5 **** A0
D12 *** D1 D0
D12 *** D1 D0
D12 *** D1 D0
RDY
Reading of OFRAM data
<Pre-E-01>
- 38 -
2006/10
[ASAHI KASEI]
[AK7740ET]
7-3) Write during RUN phase
7-3-a) CRAM rewrite preparation and write (during RUN phase)
This function is used to rewrite CRAM (coefficient RAM) during program execution. After inputting the command
code, input a maximum of 16 data bytes to rewrite to a continuous address. Then input the write command code and
rewrite the leading address. Every time the RAM address to be rewritten is specified, the contents of RAM are
rewritten. The following is an example to show how five data bytes from address "10" of the coefficient RAM are
rewritten:
Coefficient RAM execution address
7 8 9 10 11 13 16 11 12 13 14 15
È È
È È È
Rewrite position
} } Ç
} } }
Note that address "13" is not executed until address "12" is rewritten.
Data transfer procedure
* Preparation for rewrite c Command code A8h ( 1 0 1 0 1 0 0 0 )
d Data
( D15 . . . . D8 )
e Data
( D7 . . . . . D0 )
* Rewrite
c Command code A4h ( 1 0 1 0 0 1 0 0 )
d Address upper
( 0 0 0 0 0 0 0 A8 )
e Address lower
(A7 . . . . A0 )
S_RESET
RQ
SCLK
SI
10101000 D15 **** D0
10100100 A15 **** A0
AL
max 200ns
Longer of (16-n) x 2 MCLK
(n: number of data) and AL
RDYLG
RDY
SO
Note: The RDY signal will go to high within the maximum of two LRCLKs if the RDYLG
width is programmed to ensure a new address to be rewritten within one sampling cycle.
CRAM rewriting preparation and writing
<Pre-E-01>
- 39 -
2006/10
[ASAHI KASEI]
[AK7740ET]
7-3-b) OFRAM rewrite preparation and write (during RUN phase)
This function is used to rewrite OFRAM (offset RAM) during program execution. After inputting the command code,
input a maximum of 16 data bytes to rewrite to a continuous address. Then input the write command code and rewrite
the leading address. Every time the RAM address to be rewritten is specified, the contents of RAM are rewritten. The
following is an example to show how five data bytes from address "10" of the coefficient RAM are rewritten:
Offset RAM execution address 7 8 9 10 11 13 16 11 12 13 14 15
È È
È È È
Rewrite position
} } Ç
} } }
Note that address "13" is not executed until address "12" is rewritten.
Data transfer procedure
* Preparation for rewrite c Command code 98h ( 1 0 0 0 1 1 0 0 0 )
d Data
(D23 . . . . . . D16)
e Data
(D15 . . . . . . D8 )
f Data
( D7 . . . . . . D0 )
* Rewrite
c Command code 94h ( 1 0 0 0 1 0 1 0 0 )
d Address
( 0 0 A5A4 . . . A0)
S_RESET
RQ
SCLK
SI
10011000 D23 **** D0
10010100 00 A5***A0
AL
max 200ns
RDY
(Longer of (16-n) x 2 MCLK
(n: number of data) and AL
RDYLG
SO
Note: The RDY signal will go to high within the maximum of two LRCLKs if the RDYLG
width is programmed to ensure a new address to be rewritten within one sampling cycle.
OFRAM rewriting preparation and writing
<Pre-E-01>
- 40 -
2006/10
[ASAHI KASEI]
[AK7740ET]
7-3-c) External conditional jump code rewrite (during RUN phase)
Data comprising a set of two bytes is used to write the external conditional jump code. Data can be input during both
the reset and operation phases, and input data is set to the specified register at the rising edge of LRCLK. When all
data has been transferred, the RDY terminal goes to "L". Upon completion of writing, it goes to "H". A jump
command will be executed if there is any one agreement between each bit of the 8-bit external condition code and
"1"of each bit of the IFCON field. A write operation from the microcontroller is disabled until RDY goes to "H".
Note: The LRCLK phase is inverted in the I2S-compatible mode.
Data transfer procedure
c Command code
C4h ( 1 1 0 0 0 1 0 0 )
d Code data
(D7 . . . . . D0)
max 1LRCLK
S_RESET
SCLK
SI
11000100
D7 *** D0
SO
RQ
L ch R ch
LRCLK
RDY
max 2LRCLK
max0.25LRCLK
External condition jump write timing (during RUN phase)
<Pre-E-01>
- 41 -
2006/10
[ASAHI KASEI]
[AK7740ET]
7-4) Read-out during RUN phase (SO output )
SO outputs data on DBUS (data bus) from the DSP section. Data is set when the @MICR command is executed in the
DSP program. Setting the data allows DRDY to go to "H", and data is output synchronized with the falling edge of
SCLK. When SI goes "H", DRDY goes to "L" to wait for the next command. Once DRDY goes "H", the data from
the last @MICR command immediately before DRDY went "H" is held until SI goes "H", and subsequent commands
will be rejected. A maximum of 24 bits are output from SO. After the required number of data (not exceeding 24 bits)
is taken out by SCLK, setting SI to “H” can output the next data.
S_RESET
RQ
SI
@MICR
Data2
Data1
DRDY
SCLK
SO
DM Data1
DLSB
DM Data2
DLSB
SO read (during RUN phase)
The SI pin controls clearing the output buffer (MICR). When reading this data, be aware that state changes on SI are
asynchronous to the audio sampling clock, which may result in noise in the audio sugnal.
<Pre-E-01>
- 42 -
2006/10
[ASAHI KASEI]
[AK7740ET]
(8) ADC section high-pass filter
The AK7740 incorporates a digital high-pass filter (HPF) for cancelling DC offset in the ADC section. The HPF
cut-off frequency is 1 Hz (fs = 48 kHz). This cut-off frequency is proportional to the sampling frequency (fs).
Cut-off frequency
<Pre-E-01>
48kHz
0.93Hz
44.1kHz
0.86Hz
- 43 -
32kHz
0.62Hz
2006/10
[ASAHI KASEI]
[AK7740ET]
9. System Design
9-1) Connection example
0.1u
0.1u
0.1u
Digital +3.3V
10u
10
15
18
19
16
17
24
DVDD
SMODE
SDIN
SDINA
LRCLK
12
11
Cd
13
22
SO
26
RDY
25
29
BITCLK
SI
SCLK
XTO
XTI
AK7740
JX
Micom
I/F
27
28
14
CLKO
31 INIT RESET
RESET
CONTROL
30 S RESET
21 SDOUT
20 SDOUTA
Analog Lch+
Analog Lch-
45
44
Analog Rch+
43
Analog Rch-
42
Analog 1L
5
Analog 1R
4
Analog 2L
3
Analog 2R
2
Analog 3L
1
Analog 3R
48
Analog 4L
47
Analog 4R
46
Analog +3.3V
10u
0.1u
10u
0.1u
8
7
6
9,23,33
<Pre-E-01>
DRDY
RQ
Rd
Cd
32
AVSS
AINL+
AVDD
41
Analog +3.3V
39
AINLAINR+
VCOM
AINR-
0.1u
10u
0.1u
10u
40
AINL1
AINR1
AINL2
AINR2
AOUTL1
38
AOUTR1
37
AOUTL2
36
AOUTR2
35
AINL3
AINR3
AINL4
AINR4
AVSS
AVDD
BVSS
VREFH
34
DVSS
- 44 -
2006/10
[ASAHI KASEI]
[AK7740ET]
9-2) Peripheral circuit
9-2-3) Ground and power supply
To minimize digital noise coupling, AVDD and DVDD should be individually de-coupled at the AK7740. System
analog power is supplied to AVDD. Generally, power supply and ground wires must be connected separately
according to the analog and digital systems. Connect them at a position close to the power source on the PC board.
Decoupling capacitors, and ceramic capacitors of small values in particular, should be connected at positions as close
as possible to the AK7740.
9-2-4) Reference voltage
The input voltage difference between the VREFH pin and the AVSS pin determines the full scale of analog input,
while the potential difference between the VREFH pin and the AVSS pin determines the full scale of the analog
output. Normally, connect AVDD to VREFH, and connect 0.1µF ceramic capacitors from them to AVSS. To shut out
high frequency noise, connect a 0.1µF ceramic capacitor in parallel with an appropriate 10µF electrolytic capacitor
between this pin and AVSS. The ceramic capacitor in particular should be connected at a position as close as possible
to the pin. To avoid coupling to the AK7740, digital signals and clock signals in particular should be kept as far away
as possible from the VREFH pin.
VCOM is used as the common voltage of the analog signal.To filter out high frequency noise, connect a 0.1µF
ceramic capacitor in parallel with an appropriate 10µF electrolytic capacitor between this pin and AVSS. The
ceramic capacitor in particular should be connected at a position as close as possible to the pin. Do not lead current
from the VCOM pin.
9-2-5) Analog input
Analog input signals are applied to the modulator through the differential or single-ended input pins of each channel
selected by the input selector. When using differential inputs, the voltage is equal to the differential voltage between
AIN+ and AIN- (∆VAIN=(AIN+)-(AIN-)), and the input range is ±FS = ±(VREFH-AVSS)×(2.0/3.3). When VREFH
= 3.3V and AVSS = 0V, the input range is within ±2.0Vpp. When using single-ended inputs, the input range is FS =
(VREFH-AVSS) × (2.0/3.3). When VREFH = 3.3V and AVSS = 0V, the input range is within 2.0Vpp. The output
code format is given in terms of 2's complements.
When fs = 48 kHz, the AK7740 samples the analog input at 3.072 MHz. The digital filter eliminates noise from 30
kHz to 3.042 MHz. However, noise is not rejected in the bandwidth close to 3.072 MHz. Most audio signals do not
have large noise near 3.072 MHz, so a simple RC filter is sufficient. A/D converter reference voltage is applied to the
VREFH and AVSS pins.
The analog source voltage to the AK7740 is +3.3V (typical). Voltage of AVDD+0.3V or more, voltage of AVSS-0.3
V or less, and current of 10mA or more must not be applied to the analog input pins (AINL+, AINL-, AINR+, AINR-,
AINL1, AINR1, AINL2, AINR2, AINL3, AINR3, AINL4, AINR4 and VREFH). Excessive current will damage the
internal protection circuit and will cause latch-up, damaging the IC. Accordingly, if the surrounding analog circuit
voltage is ±15V, the analog input pins must be protected from signals with the absolute maximum rating or more.
<Pre-E-01>
- 45 -
2006/10
[ASAHI KASEI]
[AK7740ET]
10k
10k
+10V
10k
2.00Vpp
10k
+
Signal
+
+
NJM5532D
-10V
AIN+
4.7u
+
AIN4.7u
Vop = VA+ = 3.3V
2.00Vpp
Fig. 1 Example of input buffer circuit (differential input)
10k
10k
+10V
10k
2.00Vpp
10k
+
Signal
+
+
NJM5532D
AIN
4.7u
-10V
Vop = VA+ = 3.3V
Fig. 2 Example of input buffer circuit (single ended input)
An analog signal can be applied to the AK7740 in single ended mode. In this case, apply the analog signal (the full
scale is 2.0Vpp when the internal reference voltage is used). However, use of a low saturation operational amplifier is
recommended if the operational amplifier is driven by the 3.3-volt power supply.
9-2-6) Analog output
Analog output is single-ended, and the output range is 2.00Vpp (typical) with respect to VCOM voltage. The
out-of-band noise (from the noise shaper) produced by the internal ∆Σ modulator is reduced by the internal switched
capacitor filter (SCF) and continuous time filter (CTF). It is not necessary to add an external filter for normal
applications. The input code format is given in terms of two's complement with the positive full-scale output for the
7FFFFFH (@24bit) input code, and the negative full-scale output for the 800000H (@24bit) input code. VCOM
voltage is output as an ideal value for 000000H (@24bit) input code.
9-2-7) Connection to digital circuit
To minimize noise resulting from the digital circuit, connect low voltage logic to the digital output. The applicable
logic family includes the 74LV, 74LV-A, 74ALVC and 74AVC series.
<Pre-E-01>
- 46 -
2006/10
[ASAHI KASEI]
[AK7740ET]
10. Package
48pin LQFP(Unit:mm)
1.7Max
9.0 ± 0.2
0.13 ± 0.13
7.0
1.4TYP
25
24
48
13
7.0
37
1
9.0 ± 0.2
36
12
0.16 ± 0.07
0.5
0.22 ± 0.08
0.10 M
0° ∼ 10°
0.10
z
0.5 ± 0.2
Material & Lead finish
Package:
Lead-frame:
Lead-finish
<Pre-E-01>
Epoxy
Copper
Soldering plate
- 47 -
2006/10
[ASAHI KASEI]
[AK7740ET]
11. Marking
AKM
AK7740ET
XXXXXXX
1
1) Pin #1 indication
2) Date Code: XXXXXXX(7 digits)
3) Marking Code: AK7740ET
4) Asahi Kasei Logo
IMPORTANT NOTICE
z
z
z
z
z
<Pre-E-01>
These products and their specifications are subject to change without notice. Before
considering any use or application, consult the Asahi Kasei Microsystems Co.,
Ltd.(AKM) sales office or authorized distributor concerning their current status.
AKM assumes no liability for infringement of any patent, intellectual property, or other
right in the application or use of any information contained herein.
Any export of these products, or devices or systems containing them, may require an
export license or other official approval under the law and regulations of the country of
export pertaining to customs and tariffs, currency exchange, or strategic materials.
AKM products are neither intended nor authorized for use as critical components in any
safety, life support, or other hazard related device or system, and AKM assumes no
responsibility relating to any such use, except with the express written consent of the
Representative Director of AKM. As used here:
(a): A hazard related device or system is one designed or intended for life support or
maintenance of safety or for applications in medicine, aerospace, nuclear energy, or other
fields, in which its failure to function or perform may reasonably be expected to result in
loss of life or in significant injury or damage to person or property.
(b): A critical component is one whose failure to function or perform may reasonably be
expected to result, whether directly or indirectly, in the loss of the safety or effectiveness
of the device or system containing it, and which must therefore meet very high standards
of performance and reliability.
It is the responsibility of the buyer or distributor of an AKM product who distributes,
disposes of, or otherwise places the product with a third party to notify that party in
advance of the above content and conditions, and the buyer or distributor agrees to
assume any and all responsibility and liability for and hold AKM harmless from any and
all claims arising from the use of said product in the absence of such notification.
- 48 -
2006/10