TI LM3444MANOPB

LM3444
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SNVS682C – NOVEMBER 2010 – REVISED MAY 2013
AC-DC Offline LED Driver
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FEATURES
DESCRIPTION
•
•
The LM3444 is an adaptive constant off-time AC/DC
buck (step-down) constant current controller that
provides a constant current for illuminating high
power LEDs. The high frequency capable architecture
allows the use of small external passive components.
A passive PFC circuit ensures good power factor by
drawing current directly from the line for most of the
cycle, and provides a constant positive voltage to the
buck regulator. Additional features include thermal
shutdown, current limit and VCC under-voltage
lockout. The LM3444 is available in a low profile 10pin VSSOP package or an 8-lead SOIC package.
1
2
•
•
•
•
•
•
•
Application Voltage Range 80VAC – 277VAC
Capable of Controlling LED Currents Greater
than 1A
Adjustable Switching Frequency
Low Quiescent Current
Adaptive Programmable Off-time Allows for
Constant Ripple Current
Thermal Shutdown
No 120Hz Flicker
Low Profile 10-Pin VSSOP Package or 8-Lead
SOIC Package
Patent Pending Drive Architecture
APPLICATIONS
•
•
•
Solid State Lighting
Industrial and Commercial Lighting
Residential Lighting
TYPICAL LM3444 LED DRIVER APPLICATION CIRCUIT
D
3
C
7
BR1
R
2
D
4
Q
1
VAC
VBUCK
14 Series connected LEDs
D
9
+
D
8
C
9
C
1
+ 0
C
1
2
VLED
-
R
4
VLED-
D2
D
1
95.0
C
5
D1
0
Q3
L
2
90.0
EFFICIENCY (%)
V+
85.0
10 Series connected LEDs
80.0
LM344
4
1 NC
2 NC
C
4
U1
NC
75.0
80
1
0
ICOLL
VC
C
9
3
N
C
GAT
E
8
4
CO
FF
ISN
S
7
5
FILT
ER
G
N
D
6
90
100
110
120
130
140
LINE VOLTAGE (VAC)
Q2
R
3
C
1
1
1
2
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
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LM3444
SNVS682C – NOVEMBER 2010 – REVISED MAY 2013
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Connection Diagrams
NC
1
10 NC
NC
2
9 VCC
NC
3
COFF
FILTER
NC
1
8 COFF
FILTER
2
7 NC
8 GATE
GND
3
6 VCC
4
7 ISNS
ISNS
4
5 GATE
5
6 GND
Figure 1. 10-Pin VSSOP (Top View)
See DGS Package
Figure 2. 8-Lead SOIC (Top View)
See D Package
PIN DESCRIPTIONS
2
VSSOP
SOIC
Name
1
1
Description
NC
No internal connection. Leave this pin open.
2
NC
No internal connection. Leave this pin open.
3
NC
No internal connection. Leave this pin open.
4
8
COFF
OFF time setting pin. A user set current and capacitor connected from the output to this pin sets the
constant OFF time of the switching controller.
5
2
FILTER
6
3
GND
Circuit ground connection.
7
4
ISNS
LED current sense pin. Connect a resistor from main switching MOSFET source, ISNS to GND to set the
maximum LED current.
8
5
GATE
Power MOSFET driver pin. This output provides the gate drive for the power switching MOSFET of the
buck controller.
9
6
VCC
Input voltage pin. This pin provides the power for the internal control circuitry and gate driver.
10
7
NC
No internal connection. Leave this pin open.
Filter input. A low pass filter tied to this pin can filter a PWM dimming signal to supply a DC voltage to
control the LED current. Can also be used as an analog dimming input. If not used for dimming connect a
0.1µF capacitor from this pin to ground.
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These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
ABSOLUTE MAXIMUM RATINGS
(1)
If Military/Aerospace specified devices are required, contact the Texas Instruments Sales Office/Distributors for
availability and specifications.
VALUE / UNITS
VCC and GATE to GND
–0.3V to +14V
ISNS to GND
–0.3V to +2.5V
FILTER and COFF to GND
–-0.3V to +7.0V
COFF Input Current
Continuous Power Dissipation
60mA
(2)
ESD Susceptibility
Internally Limited
Human Body Model
(3)
Junction Temperature (TJ-MAX)
Storage Temperature Range
–65°C to +150°C
Maximum Lead Temperature Range (Soldering)
(1)
(2)
(3)
2 kV
150°C
260°C
Absolute maximum ratings are limits beyond which damage to the device may occur. Operating Ratings are conditions for which the
device is intended to be functional, but device parameter specifications may not be ensured. For specifications and test conditions, see
the Electrical Characteristics. All voltages are with respect to the potential at the GND pin, unless otherwise specified.
Internal thermal shutdown circuitry protects the device from permanent damage. Thermal shutdown engages at TJ = 165°C (typ.) and
disengages at TJ = 145°C (typ).
Human Body Model, applicable std. JESD22-A114-C.
RECOMMENDED OPERATING CONDITIONS
VALUE / UNITS
VCC
8.0V to 13V
−40°C to +125°C
Junction Temperature
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ELECTRICAL CHARACTERISTICS
Limits in standard type face are for TJ = 25°C and those with boldface type apply over the full Operating Temperature
Range ( TJ = −40°C to +125°C). Minimum and Maximum limits are specified through test, design, or statistical correlation.
Typical values represent the most likely parametric norm at TJ = 25°C, and are provided for reference purposes only. Unless
otherwise stated the following conditions apply: VCC = 12V.
Symbol
Parameter
Conditions
Min
Typ
Max
Units
VCC SUPPLY
IVCC
Operating supply current
1.58
2.25
mA
VCC-UVLO
Rising threshold
7.4
7.7
V
1.276
1.327
V
60
Falling threshold
6.0
Hysterisis
6.4
1
COFF
VCOFF
Time out threshold
1.22
5
RCOFF
Off timer sinking impedance
33
tCOFF
Restart timer
180
Ω
µs
CURRENT LIMIT
VISNS
ISNS limit threshold
1.17
4
tISNS
Leading edge blanking time
125
ns
Current limit reset delay
180
µs
33
ns
ISNS limit to GATE delay
ISNS = 0 to 1.75V step
1.269
1.364
V
CURRENT SENSE COMPARATOR
VFILTER
FILTER open circuit voltage
RFILTER
FILTER impedance
720
VOS
Current sense comparator offset voltage
750
780
1.12
-4.0
mV
MΩ
0.1
4.0
mV
V
GATE DRIVE OUTPUT
VDRVH
GATE high saturation
IGATE = 50 mA
0.24
0.50
VDRVL
GATE low saturation
IGATE = 100 mA
0.22
0.50
IDRV
Peak souce current
GATE = VCC/2
-0.77
Peak sink current
GATE = VCC/2
0.88
Rise time
Cload = 1 nF
15
Fall time
Cload = 1 nF
15
tDV
A
ns
THERMAL SHUTDOWN
TSD
Thermal shutdown temperature
See
(1)
Thermal shutdown hysteresis
165
°C
20
THERMAL SPECIFICATION
RθJA
VSSOP junction to ambient
124
RθJC
VSSOP junction to case
76
(1)
4
°C/W
Junction-to-ambient thermal resistance is highly application and board-layout dependent. In applications where high maximum power
dissipation exists, special care must be paid to thermal dissipation issues in board design. In applications where high power dissipation
and/or poor package thermal resistance is present, the maximum ambient temperature may have to be derated. Maximum ambient
temperature (TA-MAX) is dependent on the maximum operating junction temperature (TJ-MAX-OP = 125°C), the maximum power dissipation
of the device in the application (PD-MAX), and the junction-to ambient thermal resistance of the part/package in the application (RθJA), as
given by the following equation: TA-MAX = TJ-MAX-OP – (RθJA × PD-MAX).
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TYPICAL PERFORMANCE CHARACTERISTICS
fSW vs Input Line Voltage
Efficiency vs Input Line Voltage
95.0
300k
14 Series connected LEDs
250k
7 LEDs in Series (VO = 24.5V)
90.0
EFFICIENCY (%)
fSW (Hz)
200k
150k
100k
85.0
10 Series connected LEDs
80.0
50k
C11 = 2.2 nF, R3 = 348 k:
0
80
90
100
110
120
130
75.0
80
140
90
LINE VOLTAGE (VAC)
100
110
120
130
140
LINE VOLTAGE (VAC)
Figure 3.
Figure 4.
V UVLOCC vs Temperature
Min On-Time (tON) vs Temperature
8.0
200.0
UVLO (VCC) Rising
190.0
tON-MIN (ns)
UVLO (V)
7.5
7.0
UVLO (VCC) Falling
180.0
170.0
6.5
160.0
6.0
-50 -25
0
25
50
75
150.0
-50 -25
100 125 150
TEMPERATURE (°C)
0
25
50
75
100 125 150
TEMPERATURE (°C)
Figure 5.
Figure 6.
Off Threshold (C11) vs Temperature
Normalized Variation in fSW over VBUCK Voltage
1.50
1.29
NORMALIZED SW FREQ
Series
connected LEDs
VOFF(V)
1.28
1.27
OFF Threshold at C11
1.26
1.25
1.00
3 LEDs
5 LEDs
0.75
0.50
7 LEDs
9 LEDs
1.25
-50 -30 -10 10 30 50 70 90 110130150
0.25
0
50
100
150
200
VBUCK (V)
TEMPERATURE (°C)
Figure 7.
Figure 8.
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TYPICAL PERFORMANCE CHARACTERISTICS (continued)
Leading Edge Blanking Variation Over Temperature
15.0
100 units tested
NUMBER OF UNITS
Room (25°C)
Hot (125°C)
Cold (-40°C)
10.0
5.0
0.0
80
100
120
140
160
180
LEADING EDGE BLANKING (ns)
Figure 9.
6
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SIMPLIFIED INTERNAL BLOCK DIAGRAM
VCC
INTERNAL
REGULATORS
LM3444
VCC UVLO
MOSFET
DRIVER
THERMAL
SHUTDOWN
COFF
GATE
COFF
33Ö
1.276V
S
START
Q
R
LATCH
1M
PWM
750 mV
CONTROLLER
I-LIM
1.27V
1k
ISNS
LEADING EDGE BLANKING
FILTER
125 ns
PGND
Figure 10. Simplified Block Diagram
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APPLICATION INFORMATION
FUNCTIONAL DESCRIPTION
The LM3444 contains all the necessary circuitry to build a line-powered (mains powered) constant current LED
driver.
Theory of Operation
Refer to Figure 11 below which shows the LM3444 along with basic external circuitry.
D
3
V+
C
7
BR1
R
2
D
4
Q
1
VAC
VBUCK
D
9
+
D
8
C
9
C
1
+ 0
C
1
2
R
4
VLED-
D2
D
1
VLED
-
C
5
D1
0
Q3
L
2
LM344
4
1 NC
2 NC
C
4
U1
NC
1
0
VC
C
9
ICOLL
3
N
C
GAT
E
8
4
CO
FF
ISN
S
7
5
FILT
ER
G
N
D
6
Q2
R
3
C
1
1
Figure 11. LM3444 Schematic
VALLEY-FILL CIRCUIT
VBUCK supplies the power which drives the LED string. Diode D3 allows VBUCK to remain high while V+ cycles on
and off. VBUCK has a relatively small hold capacitor C10 which reduces the voltage ripple when the valley fill
capacitors are being charged. However, the network of diodes and capacitors shown between D3 and C10 make
up a "valley-fill" circuit. The valley-fill circuit can be configured with two or three stages. The most common
configuration is two stages. Figure 12 illustrates a two and three stage valley-fill circuit.
8
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V+
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VBUCK
D3
C7
+
VBUCK
V+ D3
R6
C7
D9
+
D8
D8
D4
R8
C10
+
C10
R6
D9
D6
R8
+
D5
R7
C9
C8
D4
D7
C9
+
R7
Figure 12. Two and Three Stage Valley Fill Circuit
The valley-fill circuit allows the buck regulator to draw power throughout a larger portion of the AC line. This
allows the capacitance needed at VBUCK to be lower than if there were no valley-fill circuit, and adds passive
power factor correction (PFC) to the application.
VALLEY-FILL OPERATION
When the “input line is high”, power is derived directly through D3. The term “input line is high” can be explained
as follows. The valley-fill circuit charges capacitors C7 and C9 in series (Figure 13) when the input line is high.
VBUCK
V+
D3
+
C7 + VBUCK
2
C10
D8
D4
+
VBUCK
2
-
+
C9
Figure 13. Two stage Valley-Fill Circuit when AC Line is High
The peak voltage of a two stage valley-fill capacitor is:
VVF-CAP =
VAC-RMS 2
2
(1)
As the AC line decreases from its peak value every cycle, there will be a point where the voltage magnitude of
the AC line is equal to the voltage that each capacitor is charged. At this point diode D3 becomes reversed
biased, and the capacitors are placed in parallel to each other (Figure 14), and VBUCK equals the capacitor
voltage.
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VBUCK
V+
D3
C7 +
+
VBUCK
D9
C10
D8
D4
+
VBUCK
-
+
C9
Figure 14. Two stage Valley-Fill Circuit when AC Line is Low
A three stage valley-fill circuit performs exactly the same as two-stage valley-fill circuit except now three
capacitors are now charged in series, and when the line voltage decreases to:
VVF-CAP =
VAC-RMS 2
3
(2)
Diode D3 is reversed biased and three capacitors are in parallel to each other.
The valley-fill circuit can be optimized for power factor, voltage hold up and overall application size and cost. The
LM3444 will operate with a single stage or a three stage valley-fill circuit as well. Resistor R8 functions as a
current limiting resistor during start-up, and during the transition from series to parallel connection. Resistors R6
and R7 are 1 MΩ bleeder resistors, and may or may not be necessary for each application.
BUCK CONVERTER
The LM3444 is a buck controller that uses a proprietary constant off-time method to maintain constant current
through a string of LEDs. While transistor Q2 is on, current ramps up through the inductor and LED string. A
resistor R3 senses this current and this voltage is compared to the reference voltage at FILTER. When this
sensed voltage is equal to the reference voltage, transistor Q2 is turned off and diode D10 conducts the current
through the inductor and LEDs. Capacitor C12 eliminates most of the ripple current seen in the inductor. Resistor
R4, capacitor C11, and transistor Q3 provide a linear current ramp that sets the constant off-time for a given
output voltage.
10
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VBUCK
R4
C12
D10
Q3
L2
ICOLL
LM3444
4 COFF
GAT
E
8
ISNS
7
PGN
D
6
Q2
R3
C11
Figure 15. LM3444 Buck Regulation Circuit
OVERVIEW OF CONSTANT OFF-TIME CONTROL
A buck converter’s conversion ratio is defined as:
VO
tON
= tON x fSW
=D=
t
VIN
ON + tOFF
(3)
Constant off-time control architecture operates by simply defining the off-time and allowing the on-time, and
therefore the switching frequency, to vary as either VIN or VO changes. The output voltage is equal to the LED
string voltage (VLED), and should not change significantly for a given application. The input voltage or VBUCK in
this analysis will vary as the input line varies. The length of the on-time is determined by the sensed inductor
current through a resistor to a voltage reference at a comparator. During the on-time, denoted by tON, MOSFET
switch Q2 is on causing the inductor current to increase. During the on-time, current flows from VBUCK, through
the LEDs, through L2, Q2, and finally through R3 to ground. At some point in time, the inductor current reaches a
maximum (IL2-PK) determined by the voltage sensed at R3 and the ISNS pin. This sensed voltage across R3 is
compared against the voltage of FILTER, at which point Q2 is turned off by the controller.
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IL2-PK
'iL
IAVE
IL2-MIN
IL2 (t)
tON
tOFF
t
Figure 16. Inductor Current Waveform in CCM
During the off-period denoted by tOFF, the current through L2 continues to flow through the LEDs via D10.
THERMAL SHUTDOWN
Thermal shutdown limits total power dissipation by turning off the output switch when the IC junction temperature
exceeds 165°C. After thermal shutdown occurs, the output switch doesn’t turn on until the junction temperature
drops to approximately 145°C.
Design Guide
DETERMINING DUTY-CYCLE (D)
Duty cycle (D) approximately equals:
VLED
VBUCK
=D=
tON
tON + tOFF
= tON x fSW
(4)
With efficiency considered:
VLED
1
u
=D
K VBUCK
(5)
For simplicity, choose efficiency between 75% and 85%.
CALCULATING OFF-TIME
The “Off-Time” of the LM3444 is set by the user and remains fairly constant as long as the voltage of the LED
stack remains constant. Calculating the off-time is the first step in determining the switching frequency of the
converter, which is integral in determining some external component values.
PNP transistor Q3, resistor R4, and the LED string voltage define a charging current into capacitor C11. A
constant current into a capacitor creates a linear charging characteristic.
dv
i=C
dt
(6)
Resistor R4, capacitor C11 and the current through resistor R4 (iCOLL), which is approximately equal to VLED/R4,
are all fixed. Therefore, dv is fixed and linear, and dt (tOFF) can now be calculated.
R4
tOFF = C11 x 1.276V x
VLED
(7)
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Common equations for determining duty cycle and switching frequency in any buck converter:
1
tOFF + tON
fSW =
D=
VLED
tON
=
V
tON + tOFF
BUCK
'¶ =
tOFF
tON + tOFF
(8)
Therefore:
fSW =
D and
1-D
,
fSW =
tON
tOFF
(9)
With efficiency of the buck converter in mind:
VLED
VBUCK
=KuD
(10)
Substitute equations and rearrange:
fSW
§
¨1
©
=
VLED ·
1
u
K VBUCK¸
¹
tOFF
(11)
Off-time, and switching frequency can now be calculated using the equations above.
SETTING THE SWITCHING FREQUENCY
Selecting the switching frequency for nominal operating conditions is based on tradeoffs between efficiency
(better at low frequency) and solution size/cost (smaller at high frequency).
The input voltage to the buck converter (VBUCK) changes with both line variations and over the course of each
half-cycle of the input line voltage. The voltage across the LED string will, however, remain constant, and
therefore the off-time remains constant.
The on-time, and therefore the switching frequency, will vary as the VBUCK voltage changes with line voltage. A
good design practice is to choose a desired nominal switching frequency knowing that the switching frequency
will decrease as the line voltage drops and increase as the line voltage increases (Figure 17).
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1.50
Series
connected LEDs
NORMALIZED SW FREQ
1.25
1.00
3 LEDs
5 LEDs
0.75
0.50
7 LEDs
9 LEDs
0.25
0
50
100
150
200
VBUCK (V)
Figure 17. Graphical Illustration of Switching Frequency vs VBUCK
The off-time of the LM3444 can be programmed for switching frequencies ranging from 30 kHz to over 1 MHz. A
trade-off between efficiency and solution size must be considered when designing the LM3444 application.
The maximum switching frequency attainable is limited only by the minimum on-time requirement (200 ns).
Worst case scenario for minimum on time is when VBUCK is at its maximum voltage (AC high line) and the LED
string voltage (VLED) is at its minimum value.
VLED(MIN)
1
1
tON(MIN) = K u
VBUCK(MAX) fSW
(12)
The maximum voltage seen by the Buck Converter is:
VBUCK(MAX) = VAC-RMS(MAX) x
2
(13)
INDUCTOR SELECTION
The controlled off-time architecture of the LM3444 regulates the average current through the inductor (L2), and
therefore the LED string current. The input voltage to the buck converter (VBUCK) changes with line variations and
over the course of each half-cycle of the input line voltage. The voltage across the LED string is relatively
constant, and therefore the current through R4 is constant. This current sets the off-time of the converter and
therefore the output volt-second product (VLED x off-time) remains constant. A constant volt-second product
makes it possible to keep the ripple through the inductor constant as the voltage at VBUCK varies.
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VBUCK
VLED
C12
-
D10
L2
VL2
Q2
R3
Figure 18. LM3444 External Components of the Buck Converter
The equation for an ideal inductor is:
di
Q=L
dt
(14)
Given a fixed inductor value, L, this equation states that the change in the inductor current over time is
proportional to the voltage applied across the inductor.
During the on-time, the voltage applied across the inductor is,
VL(ON-TIME) = VBUCK - (VLED + VDS(Q2) + IL2 x R3)
(15)
Since the voltage across the MOSFET switch (Q2) is relatively small, as is the voltage across sense resistor R3,
we can simplify this to approximately,
VL(ON-TIME) = VBUCK - VLED
(16)
During the off-time, the voltage seen by the inductor is approximately:
VL(OFF-TIME) = VLED
(17)
The value of VL(OFF-TIME) will be relatively constant, because the LED stack voltage will remain constant. If we
rewrite the equation for an inductor inserting what we know about the circuit during the off-time, we get:
VL(OFF-TIME) = VLED = L x
VL(OFF-TIME) = VLED = L x
'i
't
(I(MAX) - I(MIN))
't
(18)
Re-arranging this gives:
'i # tOFF x
VLED
L2
(19)
From this we can see that the ripple current (Δi) is proportional to off-time (tOFF) multiplied by a voltage which is
dominated by VLED divided by a constant (L2).
These equations can be rearranged to calculate the desired value for inductor L2.
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L2 # tOFF x
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VLED
'i
(20)
Where:
tOFF = 1
1 VLED
u
K VBUCK
fSW
(21)
Finally:
1 VLED
u
K VBUCK
VLED 1
L2 =
fSW x 'i
(22)
Refer to “Design Example” section of the datasheet to better understand the design process.
SETTING THE LED CURRENT
The LM3444 constant off-time control loop regulates the peak inductor current (IL2). The average inductor current
equals the average LED current (IAVE). Therefore the average LED current is regulated by regulating the peak
inductor current.
IL2-PK
'iL
IAVE
IL2-MIN
IL2 (t)
tON
tOFF
t
Figure 19. Inductor Current Waveform in CCM
Knowing the desired average LED current, IAVE and the nominal inductor current ripple, ΔiL, the peak current for
an application running in continuous conduction mode (CCM) is defined as follows:
IL2-PK = IAVE +
'iL
2
(23)
Or the LED current would then be,
IAVE(UNDIM) = IL2-PK(UNDIM) -
'iL
2
(24)
This is important to calculate because this peak current multiplied by the sense resistor R3 will determine when
the internal comparator is tripped. The internal comparator turns the control MOSFET off once the peak sensed
voltage reaches 750 mV.
IL-PK(UNDIM) =
16
750 mV
R3
(25)
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Current Limit: The trip voltage on the PWM comparator is 750 mV. However, if there is a short circuit or an
excessive load on the output, higher than normal switch currents will cause a voltage above 1.27V on the ISNS
pin which will trip the I-LIM comparator. The I-LIM comparator will reset the RS latch, turning off Q2. It will also
inhibit the Start Pulse Generator and the COFF comparator by holding the COFF pin low. A delay circuit will
prevent the start of another cycle for 180 µs.
VALLEY FILL CAPACITORS
Determining voltage rating and capacitance value of the valley-fill capacitors:
The maximum voltage seen by the valley-fill capacitors is:
VVF-CAP =
VAC(MAX) 2
#stages
(26)
This is, of course, if the capacitors chosen have identical capacitance values and split the line voltage equally.
Often a 20% difference in capacitance could be observed between like capacitors. Therefore a voltage rating
margin of 25% to 50% should be considered.
Determining the capacitance value of the valley-fill capacitors:
The valley fill capacitors should be sized to supply energy to the buck converter (VBUCK) when the input line is
less than its peak divided by the number of stages used in the valley fill (tX). The capacitance value should be
calculated for the maximum LED current.
30°
150°
tX
VBUCK
8.33 ms
0°
t
180°
Figure 20. Two Stage Valley-Ffill VBUCK Voltage
From the above illustration and the equation for current in a capacitor, i = C x dV/dt, the amount of capacitance
needed at VBUCK will be calculated as follows:
At 60Hz, and a valley-fill circuit of two stages, the hold up time (tX) required at VBUCK is calculated as follows. The
total angle of an AC half cycle is 180° and the total time of a half AC line cycle is 8.33 ms. When the angle of the
AC waveform is at 30° and 150°, the voltage of the AC line is exactly ½ of its peak. With a two stage valley-fill
circuit, this is the point where the LED string switches from power being derived from AC line to power being
derived from the hold up capacitors (C7 and C9). 60° out of 180° of the cycle or 1/3 of the cycle the power is
derived from the hold up capacitors (1/3 x 8.33 ms = 2.78 ms). This is equal to the hold up time (dt) from the
above equation, and dv is the amount of voltage the circuit is allowed to droop. From the next section
(“Determining Maximum Number of Series Connected LEDs Allowed”) we know the minimum VBUCK voltage will
be about 45V for a 90VAC to 135VAC line. At 90VAC low line operating condition input, ½ of the peak voltage is
64V. Therefore with some margin the voltage at VBUCK can not droop more than about 15V (dv). (i) is equal to
(POUT/VBUCK), where POUT is equal to (VLED x ILED). Total capacitance (C7 in parallel with C9) can now be
calculated. See “ Design Example" section for further calculations of the valley-fill capacitors.
Determining Maximum Number of Series Connected LEDs Allowed:
The LM3444 is an off-line buck topology LED driver. A buck converter topology requires that the input voltage
(VBUCK) of the output circuit must be greater than the voltage of the LED stack (VLED) for proper regulation. One
must determine what the minimum voltage observed by the buck converter will be before the maximum number
of LEDs allowed can be determined. Two variables will have to be determined in order to accomplish this.
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1. AC line operating voltage. This is usually 90VAC to 135VAC for North America. Although the LM3444 can
operate at much lower and higher input voltages a range is needed to illustrate the design process.
2. How many stages are implemented in the valley-fill circuit (1, 2 or 3).
In this example the most common valley-fill circuit will be used (two stages).
VPEAK
VAC
t
Figure 21. AC Line
Figure 21 shows the AC waveform. One can easily see that the peak voltage (VPEAK) will always be:
VAC-RMS-PK 2
(27)
The voltage at VBUCK with a valley fill stage of two will look similar to the waveforms of Figure 20.
The purpose of the valley fill circuit is to allow the buck converter to pull power directly off of the AC line when
the line voltage is greater than its peak voltage divided by two (two stage valley fill circuit). During this time, the
capacitors within the valley fill circuit (C7 and C8) are charged up to the peak of the AC line voltage. Once the
line drops below its peak divided by two, the two capacitors are placed in parallel and deliver power to the buck
converter. One can now see that if the peak of the AC line voltage is lowered due to variations in the line voltage
the DC offset (VDC) will lower. VDC is the lowest value that voltage VBUCK will encounter.
VBUCK(MIN) =
VAC-RMS(MIN) 2 x SIN(T)
#stages
(28)
Example:
Line voltage = 90VAC to 135VAC
Valley-Fill = two stage
VBUCK(MIN) =
o
90 2 x SIN(135 )
= 45V
2
(29)
Depending on what type and value of capacitors are used, some derating should be used for voltage droop when
the capacitors are delivering power to the buck converter. With this derating, the lowest voltage the buck
converter will see is about 42.5V in this example.
To determine how many LEDs can be driven, take the minimum voltage the buck converter will see (42.5V) and
divide it by the worst case forward voltage drop of a single LED.
Example: 42.5V/3.7V = 11.5 LEDs (11 LEDs with margin)
18
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OUTPUT CAPACITOR
A capacitor placed in parallel with the LED or array of LEDs can be used to reduce the LED current ripple while
keeping the same average current through both the inductor and the LED array. With a buck topology the output
inductance (L2) can now be lowered, making the magnetics smaller and less expensive. With a well designed
converter, you can assume that all of the ripple will be seen by the capacitor, and not the LEDs. One must
ensure that the capacitor you choose can handle the RMS current of the inductor. Refer to manufacture’s
datasheets to ensure compliance. Usually an X5R or X7R capacitor between 1 µF and 10 µF of the proper
voltage rating will be sufficient.
SWITCHING MOSFET
The main switching MOSFET should be chosen with efficiency and robustness in mind. The maximum voltage
across the switching MOSFET will equal:
VDS(MAX) = VAC-RMS(MAX) 2
(30)
The average current rating should be greater than:
IDS-MAX = ILED(-AVE)(DMAX)
(31)
RE-CIRCULATING DIODE
The LM3444 Buck converter requires a re-circulating diode D10 (see the Typical Application circuit Figure 11) to
carry the inductor current during the MOSFET Q2 off-time. The most efficient choice for D10 is a diode with a low
forward drop and near-zero reverse recovery time that can withstand a reverse voltage of the maximum voltage
seen at VBUCK. For a common 110VAC ± 20% line, the reverse voltage could be as high as 190V.
VD t VAC-RMS(MAX) 2
(32)
The current rating must be at least:
ID = 1 - (DMIN) x ILED(AVE)
(33)
Or:
ID = 1 -
VLED(MIN)
x ILED(AVE)
VBUCK(MAX)
(34)
Design Example
The following design example illustrates the process of calculating external component values.
Known:
1.
2.
3.
4.
Input voltage range (90VAC – 135VAC)
Number of LEDs in series = 7
Forward voltage drop of a single LED = 3.6V
LED stack voltage = (7 x 3.6V) = 25.2V
Choose:
1. Nominal switching frequency, fSW-TARGET = 250 kHz
2. ILED(AVE) = 400 mA
3. Δi (usually 15% - 30% of ILED(AVE)) = (0.30 x 400 mA) = 120 mA
4. Valley fill stages (1,2, or 3) = 2
5. Assumed minimum efficiency = 80%
Calculate:
1. Calculate minimum voltage VBUCK equals:
VBUCK(MIN) =
o
90 2 x SIN(135 )
= 45V
2
(35)
2. Calculate maximum voltage VBUCK equals:
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VBUCK(MAX) = 135 2 = 190V
(36)
3. Calculate tOFF at VBUCK nominal line voltage:
1
tOFF =
1
25.2V
u
0.8 115 2
(250 kHz)
= 3.23 Ps
(37)
4. Calculate tON(MIN) at high line to ensure that tON(MIN) > 200 ns:
1
25.2V
u
0.8 135 2
tON (MIN) =
1
u 3.23 Ps = 638 ns
1
25.2V
u
0.8 135 2
(38)
5. Calculate C11 and R4:
6. Choose current through R4: (between 50 µA and 100 µA) 70 µA
VLED
= 360 k:
R4 =
ICOLL
(39)
7. Use a standard value of 365 kΩ
8. Calculate C11:
VLED tOFF
C11 =
= 175 pF
R4 1.276
(40)
9. Use standard value of 120 pF
10. Calculate ripple current: 400 mA X 0.30 = 120 mA
11. Calculate inductor value at tOFF = 3 µs:
25.2V 1
L2 =
1
25.2V
u
0.8 115 2
(350 kHz x 0.1A)
= 580 PH
(41)
12. Choose C10: 1.0 µF 200V
13. Calculate valley-fill capacitor values:
VAC low line = 90VAC, VBUCK minimum equals 60V. Set droop for 20V maximum at full load and low line.
i=C
dv
dt
(42)
i equals POUT/VBUCK (270 mA), dV equals 20V,
dt equals 2.77 ms, and
then CTOTAL equals 37 µF.
Therefore, C7 = C9 = 22 µF
20
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LM3444 Design Example 1
Input = 90VAC to 135VAC, VLED = 7 x HB LED String Application at 400 mA
TP3
VBUCK
V+
D3
TP4
LED+
BR1
+
R6
D9
C7
R8
D8
C10
C2
+
L4
D4
R7
C9
VLED
R4
C12
C15
L3
D10
V+
C1
TP5
LEDVLED-
D12
Q3
R2
L5
TP14
Q1
D2
R10
L2
D1
C5
L1
ICOLL
RT1
LM3444
F1
U1
1
NC
NC 10
2
NC
VCC 9
3
NC
J1
VAC
TP15
GATE
8
Q2
TP16
4 COFF
ISNS 7
5 FLTR2
GND 6
R3
C4
TP7-9
C11
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LM3444
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Table 1. Bill of Materials
Qty
Ref Des
Description
Mfr
Mfr PN
1
U1
IC, CTRLR, DRVR-LED, VSSOP
TI
LM3444MM
1
BR1
Bridge Rectifiier, SMT, 400V, 800 mA
DiodesInc
HD04-T
1
L1
Common mode filter DIP4NS, 900 mA, 700 µH
Panasonic
ELF-11090E
1
L2
Inductor, SHLD, SMT, 1A, 470 µH
Coilcraft
MSS1260-474-KLB
2
L3, L4
Diff mode inductor, 500 mA 1 mH
Coilcraft
MSS1260-105KL-KLB
HI1206T161R-10
22
1
L5
Bead Inductor, 160Ω, 6A
Steward
3
C1, C2, C15
Cap, Film, X2Y2, 12.5MM, 250VAC, 20%, 10 nF
Panasonic
ECQ-U2A103ML
1
C4
Cap, X7R, 0603, 16V, 10%, 100 nF
Murata
GRM188R71C104KA01D
2
C5, C6
Cap, X5R, 1210, 25V, 10%, 22 µF
Murata
GRM32ER61E226KE15L
2
C7, C9
Cap, AL, 200V, 105C, 20%, 33 µF
UCC
EKXG201ELL330MK20S
1
C10
Cap, Film, 250V, 5%, 10 nF
Epcos
B32521C3103J
1
C12
Cap, X7R, 1206, 50V, 10%, 1.0 uF
Kemet
C1206F105K5RACTU
1
C11
Cap, C0G, 0603, 100V, 5%, 120 pF
Murata
GRM1885C2A121JA01D
1
D1
Diode, ZNR, SOT23, 15V, 5%
OnSemi
BZX84C15LT1G
2
D2, D13
Diode, SCH, SOD123, 40V, 120 mA
NXP
BAS40H
4
D3, D4, D8, D9
Diode, FR, SOD123, 200V, 1A
Rohm
RF071M2S
1
D10
Diode, FR, SMB, 400V, 1A
OnSemi
MURS140T3G
1
D12
TVS, VBR = 144V
Fairchild
SMBJ130CA
1
R2
Resistor, 1206, 1%, 100 kΩ
Panasonic
ERJ-8ENF1003V
1
R3
Resistor, 1210, 5%, 1.8Ω
Panasonic
ERJ-14RQJ1R8U
1
R4
Resistor, 0603, 1%, 576 kΩ
Panasonic
ERJ-3EKF5763V
2
R6, R7
Resistor, 0805, 1%, 1.00 MΩ
Rohm
MCR10EZHF1004
2
R8, R10
Resistor, 1206, 0.0Ω
Yageo
RC1206JR-070RL
1
R9
Resistor, 1812, 0.0Ω
1
RT1
Thermistor, 120V, 1.1A, 50Ω @ 25°C
Thermometrics
CL-140
2
Q1, Q2
XSTR, NFET, DPAK, 300V, 4A
Fairchild
FQD7N30TF
1
Q3
XSTR, PNP, SOT23, 300V, 500 mA
Fairchild
MMBTA92
1
J1
Terminal Block 2 pos
Phoenix Contact
1715721
1
F1
Fuse, 125V, 1,25A
bel
SSQ 1.25
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SNVS682C – NOVEMBER 2010 – REVISED MAY 2013
REVISION HISTORY
Changes from Revision B (May 2013) to Revision C
•
Page
Changed layout of National Data Sheet to TI format .......................................................................................................... 22
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PACKAGE OPTION ADDENDUM
www.ti.com
2-May-2013
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
(2)
MSL Peak Temp
Op Temp (°C)
Top-Side Markings
(3)
(4)
LM3444MA/NOPB
ACTIVE
SOIC
D
8
95
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
-40 to 125
L3444
MA
LM3444MAX/NOPB
ACTIVE
SOIC
D
8
2500
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
-40 to 125
L3444
MA
LM3444MM/NOPB
ACTIVE
VSSOP
DGS
10
1000
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
-40 to 125
SZTB
LM3444MMX/NOPB
ACTIVE
VSSOP
DGS
10
3500
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
-40 to 125
SZTB
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
Multiple Top-Side Markings will be inside parentheses. Only one Top-Side Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a
continuation of the previous line and the two combined represent the entire Top-Side Marking for that device.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
2-May-2013
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
20-Nov-2013
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
LM3444MAX/NOPB
SOIC
D
8
2500
330.0
12.4
6.5
5.4
2.0
8.0
12.0
Q1
LM3444MM/NOPB
VSSOP
DGS
10
1000
178.0
12.4
5.3
3.4
1.4
8.0
12.0
Q1
LM3444MMX/NOPB
VSSOP
DGS
10
3500
330.0
12.4
5.3
3.4
1.4
8.0
12.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
20-Nov-2013
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
LM3444MAX/NOPB
SOIC
D
8
2500
367.0
367.0
35.0
LM3444MM/NOPB
VSSOP
DGS
10
1000
210.0
185.0
35.0
LM3444MMX/NOPB
VSSOP
DGS
10
3500
367.0
367.0
35.0
Pack Materials-Page 2
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