TI SN65HVD11DR

SN65HVD10, SN65HVD10Q, SN75HVD10
SN65HVD11, SN65HVD11Q, SN75HVD11
SN65HVD12, SN75HVD12
SLLS505K – FEBRUARY 2002 – REVISED SEPTEMBER 2011
www.ti.com
3.3-V RS-485 TRANSCEIVERS
Check for Samples: SN65HVD10, SN65HVD10Q, SN75HVD10, SN65HVD11, SN65HVD11Q, SN75HVD11, SN65HVD12, SN75HVD12
FEATURES
DESCRIPTION
•
•
•
The SN65HVD10, SN75HVD10, SN65HVD11,
SN75HVD11,
SN65HVD12,
and
SN75HVD12
combine a 3-state differential line driver and
differential input line receiver that operate with a
single 3.3-V power supply. They are designed for
balanced transmission lines and meet or exceed
ANSI standard TIA/EIA-485-A and ISO 8482:1993.
These differential bus transceivers are monolithic
integrated circuits designed for bidirectional data
communication on multipoint bus-transmission lines.
The drivers and receivers have active-high and
active-low enables respectively, that can be externally
connected together to function as direction control.
Very low device standby supply current can be
achieved by disabling the driver and the receiver.
1
•
•
•
•
•
•
•
•
Operates With a 3.3-V Supply
Bus-Pin ESD Protection Exceeds 16 kV HBM
1/8 Unit-Load Option Available (Up to 256
Nodes on the Bus)
Optional Driver Output Transition Times for
Signaling Rates (1) of 1 Mbps, 10 Mbps, and
32 Mbps
Meets or Exceeds the Requirements of ANSI
TIA/EIA-485-A
Bus-Pin Short Circuit Protection From –7 V to
12 V
Low-Current Standby Mode . . . 1 µA Typical
Open-Circuit, Idle-Bus, and Shorted-Bus
Failsafe Receiver
Thermal Shutdown Protection
Glitch-Free Power-Up and Power-Down
Protection for Hot-Plugging Applications
SN75176 Footprint
The driver differential outputs and receiver differential
inputs connect internally to form a differential input/
output (I/O) bus port that is designed to offer
minimum loading to the bus whenever the driver is
disabled or VCC = 0. These parts feature wide positive
and negative common-mode voltage ranges, making
them suitable for party-line applications.
APPLICATIONS
•
•
•
•
•
•
•
Digital Motor Control
Utility Meters
Chassis-to-Chassis Interconnects
Electronic Security Stations
Industrial Process Control
Building Automation
Point-of-Sale (POS) Terminals and Networks
D OR P PACKAGE
(TOP VIEW)
R
RE
DE
D
1
8
2
7
3
6
4
5
VCC
B
A
GND
1
R
2
RE
DE
3
6
(1)
The signaling rate of a line is the number of voltage
transitions that are made per second expressed in the units
bps (bits per second).
4
A
D
7
B
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2002–2011, Texas Instruments Incorporated
SN65HVD10, SN65HVD10Q, SN75HVD10
SN65HVD11, SN65HVD11Q, SN75HVD11
SN65HVD12, SN75HVD12
SLLS505K – FEBRUARY 2002 – REVISED SEPTEMBER 2011
www.ti.com
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
ORDERING INFORMATION
SIGNALING
RATE
UNIT LOADS
32 Mbps
1/2
10 Mbps
1/8
1 Mbps
1/8
32 Mbps
1/2
10 Mbps
1/8
1 Mbps
1/8
32 Mbps
1/2
10 Mbps
1/8
(1)
PACKAGE
TA
PDIP
SN65HVD10D
SN65HVD10P
VP10
SN65HVD11D
SN65HVD11P
VP11
SN65HVD12D
SN65HVD12P
VP12
SN75HVD10D
SN75HVD10P
VN10
SN75HVD11D
SN75HVD11P
VN11
SN75HVD12D
SN75HVD12P
VN12
SN65HVD10QD
SN65HVD10QP
VP10Q
SN65HVD11QD
SN65HVD11QP
VP11Q
–40°C to 85°C
–0°C to 70°C
–40°C to 125°C
SOIC MARKING
SOIC (1)
The D package is available taped and reeled. Add an R suffix to the part number (i.e., SN75HVD11DR).
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range unless otherwise noted
(1) (2)
UNIT
VCC
–0.3 V to 6 V
Supply voltage range
–9 V to 14 V
Voltage range at A or B
–0.5 V to VCC + 0.5 V
Input voltage range at D, DE, R or RE
Voltage input range, transient pulse, A and B, through 100 Ω, see Figure 11
IO
Human body model (3)
Electrostatic
discharge
Charged-device model
(4)
A, B, and GND
±16 kV
All pins
±4 kV
See Dissipation Rating Table
Electrical Fast Transient/Burst (5)
(1)
(2)
(3)
(4)
(5)
±1 kV
All pins charge
Continuous total power dissipation
TJ
–50 V to 50 V
–11 mA to 11 mA
Receiver output current
±4 kV
A, B, and GND
Junction temperature
170°C
Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
All voltage values, except differential I/O bus voltages, are with respect to network ground terminal.
Tested in accordance with JEDEC Standard 22, Test Method A114-A and IEC 60749-26.
Tested in accordance with JEDEC Standard 22, Test Method C101.
Tested in accordance with IEC 61000-4-4.
PACKAGE DISSIPATION RATINGS
PACKAGE
TA ≤ 25°C
POWER RATING
DERATING FACTOR (1)
ABOVE TA = 25°C
TA = 70°C
POWER RATING
TA = 85°C
POWER RATING
TA = 125°C
POWER RATING
D (2)
597 mW
4.97 mW/°C
373 mW
298 mW
100 mW
D (3)
990 mW
8.26 mW/°C
620 mW
496 mW
165 mW
P
1290 mW
10.75 mW/°C
806 mW
645 mW
215 mW
(1)
(2)
(3)
2
This is the inverse of the junction-to-ambient thermal resistance when board-mounted and with no air flow.
Tested in accordance with the Low-K thermal metric definitions of EIA/JESD51-3.
Tested in accordance with the High-K thermal metric definitions of EIA/JESD51-7.
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Copyright © 2002–2011, Texas Instruments Incorporated
Product Folder Link(s): SN65HVD10, SN65HVD10Q, SN75HVD10 SN65HVD11, SN65HVD11Q, SN75HVD11
SN65HVD12, SN75HVD12
SN65HVD10, SN65HVD10Q, SN75HVD10
SN65HVD11, SN65HVD11Q, SN75HVD11
SN65HVD12, SN75HVD12
SLLS505K – FEBRUARY 2002 – REVISED SEPTEMBER 2011
www.ti.com
RECOMMENDED OPERATING CONDITIONS
over operating free-air temperature range unless otherwise noted
MIN
VCC
Supply voltage
VI or VIC
Voltage at any bus terminal (separately or common mode)
VIH
High-level input voltage
VIL
VID
12
VCC
Low-level input voltage
D, DE, RE
0
0.8
Differential input voltage
Figure 7
–12
12
Driver
–60
Low-level output current
RL
Differential load resistance
CL
Differential load capacitance
Signaling rate
UNIT
3.6
2
IOL
(1)
(2)
3
D, DE, RE
High-level output current
(2)
MAX
–7 (1)
IOH
TJ
NOM
V
mA
–8
Receiver
Driver
60
Receiver
mA
8
54
Ω
60
50
pF
HVD10
32
HVD11
10
HVD12
1
Junction temperature
Mbps
145
°C
The algebraic convention, in which the least positive (most negative) limit is designated as minimum is used in this data sheet.
See thermal characteristics table for information regarding this specification.
DRIVER ELECTRICAL CHARACTERISTICS
over recommended operating conditions unless otherwise noted
PARAMETER
VIK
MIN TYP (1) MAX UNIT
TEST CONDITIONS
II = –18 mA
Input clamp voltage
–1.5
IO = 0
|VOD|
Differential output voltage (2)
Δ|VOD|
Change in magnitude of differential output
voltage
VOC(PP)
Peak-to-peak common-mode output voltage
VOC(SS)
Steady-state common-mode output voltage
ΔVOC(SS)
Change in steady-state common-mode output
voltage
IOZ
High-impedance output current
V
2
RL = 54 Ω, See Figure 1
1.5
Vtest = –7 V to 12 V, See Figure 2
1.5
VCC
V
–0.2
See Figure 1 and Figure 2
0.2
400
See Figure 3
V
mV
1.4
2.5
V
–0.0
5
0.05
V
–100
0
0
100
See receiver input currents
D
μA
II
Input current
IOS
Short-circuit output current
–7 V ≤ VO ≤ 12 V
C(OD)
Differential output capacitance
VOD = 0.4 sin (4E6πt) + 0.5 V, DE at 0 V
16
RE at VCC,
Receiver disabled and
D & DE at VCC,
driver enabled
No load
9
15.5
mA
RE at VCC,
D at VCC,
DE at 0 V,
No load
1
5
μA
9
15.5
mA
ICC
DE
Supply current
–250
Receiver disabled and
driver disabled (standby)
RE at 0 V,
Receiver enabled and
D & DE at VCC,
driver enabled
No load
(1)
(2)
250
mA
pF
All typical values are at 25°C and with a 3.3-V supply.
For TA > 85°C, VCC is ±5%.
Copyright © 2002–2011, Texas Instruments Incorporated
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SN65HVD12, SN75HVD12
3
SN65HVD10, SN65HVD10Q, SN75HVD10
SN65HVD11, SN65HVD11Q, SN75HVD11
SN65HVD12, SN75HVD12
SLLS505K – FEBRUARY 2002 – REVISED SEPTEMBER 2011
www.ti.com
DRIVER SWITCHING CHARACTERISTICS
over recommended operating conditions unless otherwise noted
MIN
TYP (1)
MAX
HVD10
5
8.5
16
HVD11
18
25
40
HVD12
135
200
300
HVD10
5
8.5
16
PARAMETER
tPLH
Propagation delay time, low-to-high-level output
tPHL
Propagation delay time, high-to-low-level output
TEST CONDITIONS
HVD11
18
25
40
HVD12
135
200
300
3
4.5
10
HVD10
tr
Differential output signal rise time
tf
Differential output signal fall time
Pulse skew (|tPHL – tPLH|)
tsk(p)
tsk(pp)
tPZH
(2)
Part-to-part skew
Propagation delay time,
high-impedance-to-high-level output
HVD11
10
20
30
HVD12
100
170
300
HVD10
3
4.5
10
HVD11
10
20
30
HVD12
100
170
300
HVD10
1.5
HVD11
2.5
HVD12
7
HVD10
6
HVD11
11
HVD12
100
HVD10
31
HVD11
55
HVD12
HVD10
tPHZ
tPZL
Propagation delay time,
high-level-to-high-impedance output
Propagation delay time,
high-impedance-to-low-level output
Propagation delay time,
low-level-to-high-impedance output
RL = 110 Ω, RE at 0 V,
See Figure 5
ns
ns
ns
ns
ns
ns
25
55
HVD12
300
HVD10
26
HVD11
55
HVD12
300
RL = 110 Ω, RE at 0 V,
See Figure 6
ns
300
HVD11
HVD10
tPLZ
RL = 54 Ω, CL = 50 pF,
See Figure 4
UNIT
ns
ns
26
HVD11
75
HVD12
400
ns
tPZH
Propagation delay time, standby-to-high-level output
RL = 110 Ω, RE at 3 V,
See Figure 5
6
μs
tPZL
Propagation delay time, standby-to-low-level output
RL = 110 Ω, RE at 3 V,
See Figure 6
6
μs
(1)
(2)
4
All typical values are at 25°C and with a 3.3-V supply.
tsk(pp) is the magnitude of the difference in propagation delay times between any specified terminals of two devices when both devices
operate with the same supply voltages, at the same temperature, and have identical packages and test circuits.
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Copyright © 2002–2011, Texas Instruments Incorporated
Product Folder Link(s): SN65HVD10, SN65HVD10Q, SN75HVD10 SN65HVD11, SN65HVD11Q, SN75HVD11
SN65HVD12, SN75HVD12
SN65HVD10, SN65HVD10Q, SN75HVD10
SN65HVD11, SN65HVD11Q, SN75HVD11
SN65HVD12, SN75HVD12
SLLS505K – FEBRUARY 2002 – REVISED SEPTEMBER 2011
www.ti.com
RECEIVER ELECTRICAL CHARACTERISTICS
over recommended operating conditions unless otherwise noted
PARAMETER
TEST CONDITIONS
VIT+
Positive-going input threshold voltage IO = –8 mA
VIT–
Negative-going input threshold
voltage
Vhys
Hysteresis voltage (VIT+ - VIT-)
VIK
Enable-input clamp voltage
II = –18 mA
VOH
High-level output voltage
VID = 200 mV,
IOH = –8 mA,
See Figure 7
VOL
Low-level output voltage
VID = –200 mV,
IOL = 8 mA,
See Figure 7
IOZ
High-impedance-state output current
VO = 0 or VCC
RE at VCC
MIN
35
VCC = 0 V
VA or VB = –7 V
VA or VB = –7 V,
HVD11, HVD12,
Other input at 0 V
HVD10,
Other input at 0 V
VCC = 0 V
0.5
–0.4
–0.15
Low-level input current, RE
VIL = 0.8 V
–30
Differential input capacitance
VID = 0.4 sin (4E6πt) + 0.5 V, DE at 0 V
(1)
0.5
–0.2
CID
Supply current
0.2
0.25
–0.4
IIL
μA
0.13
–0.04
–30
1
0.06
–0.05
VIH = 2 V
V
0.11
–0.05
High-level input current, RE
0.4
0.05
–0.1
IIH
ICC
V
–1
VCC = 0 V
VCC = 0 V
V
2.4
VA or VB = 12 V
VA or VB = 12 V,
mV
–1.5
VA or VB = –7 V
VA or VB = –7 V,
UNIT
V
–0.2
IO = 8 mA
VA or VB = 12 V,
Bus input current
MAX
-0.01
VA or VB = 12 V
II
TYP (1)
mA
mA
0
μA
0
μA
15
pF
RE at 0 V,
D & DE at 0 V,
No load
Receiver enabled and driver
disabled
4
8
mA
RE at VCC,
D at VCC,
DE at 0 V,
No load
Receiver disabled and driver
disabled (standby)
1
5
μA
RE at 0 V,
D & DE at VCC,
No load
Receiver enabled and driver
enabled
9
15.5
mA
All typical values are at 25°C and with a 3.3-V supply.
Copyright © 2002–2011, Texas Instruments Incorporated
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Product Folder Link(s): SN65HVD10, SN65HVD10Q, SN75HVD10 SN65HVD11, SN65HVD11Q, SN75HVD11
SN65HVD12, SN75HVD12
5
SN65HVD10, SN65HVD10Q, SN75HVD10
SN65HVD11, SN65HVD11Q, SN75HVD11
SN65HVD12, SN75HVD12
SLLS505K – FEBRUARY 2002 – REVISED SEPTEMBER 2011
www.ti.com
RECEIVER SWITCHING CHARACTERISTICS
over recommended operating conditions unless otherwise noted
PARAMETER
TEST CONDITIONS
MIN
TYP (1)
MAX
UNIT
tPLH
Propagation delay time, low-to-high-level output
HVD10
12.5
20
25
tPHL
Propagation delay time, high-to-low-level output
HVD10
12.5
20
25
tPLH
Propagation delay time, low-to-high-level output
HVD11
HVD12
30
55
70
ns
30
55
70
ns
tPHL
Propagation delay time, high-to-low-level output
Pulse skew (|tPHL – tPLH|)
tsk(p)
tsk(pp)
(2)
Part-to-part skew
HVD11
HVD12
VID = –1.5 V to 1.5 V,
CL = 15 pF,
See Figure 8
HVD10
1.5
HVD11
4
HVD12
4
HVD10
8
HVD11
15
HVD12
tr
Output signal rise time
tf
Output signal fall time
(1)
Output enable time to high level
tPZL
(1)
Output enable time to low level
tPHZ
ns
2
5
1
2
5
ns
15
15
20
Output disable time from low level
ns
15
tPZH
(2)
Propagation delay time, standby-to-high-level output
tPZL
(2)
Propagation delay time, standby-to-low-level output
(1)
(2)
1
CL = 15 pF, DE at 3 V,
See Figure 9
Output disable time from high level
tPLZ
ns
15
CL = 15 pF,
See Figure 8
tPZH
ns
6
CL = 15 pF, DE at 0,
See Figure 10
6
μs
All typical values are at 25°C and with a 3.3-V supply
tsk(pp) is the magnitude of the difference in propagation delay times between any specified terminals of two devices when both devices
operate with the same supply voltages, at the same temperature, and have identical packages and test circuits.
THERMAL CHARACTERISTICS
over operating free-air temperature range unless otherwise noted
PARAMETER
(1)
TEST CONDITIONS
MIN
TYP
θJA
Junction−to−ambient thermal
resistance (2)
High−K board (3), No airflow
No airflow (4)
P pkg
93
θJB
Junction−to−board thermal
resistance
High−K board
D pkg
67
P pkg
57
θJC
Junction−to−case thermal
resistance
D pkg
41
PD
Device power dissipation
See
RL= 60 Ω, CL = 50 pF,
DE at VCC, RE at 0 V,
Input to D a 50% duty cycle square
wave at indicated signaling rate
6
55
250
HVD11
(10 Mbps)
141
176
HVD12
(500 kbps)
133
161
D pkg
–40
P pkg
–40
Thermal shutdown junction temperature
UNIT
°C/W
198
No airflow (4)
TJSD
MAX
HVD10
(32 Mbps)
High−K board, No airflow
Ambient air temperature
(3)
(4)
121
P pkg
TA
(1)
(2)
(4)
D pkg
mW
116
123
°C
165
See Application Information section for an explanation of these parameters.
The intent of θJA specification is solely for a thermal performance comparison of one package to another in a standardized environment.
This methodology is not meant to and will not predict the performance of a package in an application-specific environment.
JSD51−7, High Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages.
JESD51−10, Test Boards for Through-Hole Perimeter Leaded Package Thermal Measurements.
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Copyright © 2002–2011, Texas Instruments Incorporated
Product Folder Link(s): SN65HVD10, SN65HVD10Q, SN75HVD10 SN65HVD11, SN65HVD11Q, SN75HVD11
SN65HVD12, SN75HVD12
SN65HVD10, SN65HVD10Q, SN75HVD10
SN65HVD11, SN65HVD11Q, SN75HVD11
SN65HVD12, SN75HVD12
SLLS505K – FEBRUARY 2002 – REVISED SEPTEMBER 2011
www.ti.com
PARAMETER MEASUREMENT INFORMATION
VCC
DE
II
375 Ω ±1%
VCC
IOA
A
DE
VOD
0 or 3 V
B
54 Ω ±1%
0 or 3 V
D
A
VOD
IOB
60 Ω ±1%
+
_ −7 V < V(test) < 12 V
B
VI
VOB
375 Ω ±1%
VOA
Figure 1. Driver VOD Test Circuit and Voltage and
Current Definitions
VCC
DE
Input
D
Figure 2. Driver VOD With Common-Mode Loading
Test Circuit
27 Ω ± 1%
A
VA
B
VB
VOC(PP)
27 Ω ± 1%
B
A
CL = 50 pF ±20%
VOC
∆VOC(SS)
VOC
CL Includes Fixture and
Instrumentation Capacitance
Input: PRR = 500 kHz, 50% Duty Cycle,tr<6ns, tf<6ns, ZO = 50 Ω
Figure 3. Test Circuit and Definitions for the Driver Common-Mode Output Voltage
3V
VCC
DE
D
Input
Generator
VI
50 Ω
VOD
tPLH
CL Includes Fixture
and Instrumentation
Capacitance
RL = 54 Ω
± 1%
B
1.5 V
VI
CL = 50 pF ±20%
A
1.5 V
tPHL
90%
VOD
≈2V
90%
0V
10%
≈ –2 V
0V
10%
tr
tf
Generator: PRR = 500 kHz, 50% Duty Cycle, tr <6 ns, tf <6 ns, Zo = 50 Ω
Figure 4. Driver Switching Test Circuit and Voltage Waveforms
A
3V
D
3V
S1
VO
VI
1.5 V
1.5 V
B
DE
Input
Generator
VI
50 Ω
CL = 50 pF ±20%
CL Includes Fixture
and Instrumentation
Capacitance
RL = 110 Ω
± 1%
0.5 V
0V
tPZH
VOH
VO
2.3 V
tPHZ
≈0V
Generator: PRR = 500 kHz, 50% Duty Cycle, tr <6 ns, tf <6 ns, Zo = 50 Ω
Figure 5. Driver High-Level Enable and Disable Time Test Circuit and Voltage Waveforms
Copyright © 2002–2011, Texas Instruments Incorporated
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SN65HVD12, SN75HVD12
7
SN65HVD10, SN65HVD10Q, SN75HVD10
SN65HVD11, SN65HVD11Q, SN75HVD11
SN65HVD12, SN75HVD12
SLLS505K – FEBRUARY 2002 – REVISED SEPTEMBER 2011
www.ti.com
PARAMETER MEASUREMENT INFORMATION (continued)
3V
RL = 110 Ω
± 1%
A
3V
VI
1.5 V
VI
S1
D
1.5 V
VO
DE
Input
Generator
≈3V
50 Ω
0V
B
tPZL
tPLZ
≈3V
CL = 50 pF ±20%
0.5 V
CL Includes Fixture
and Instrumentation
Capacitance
VO
2.3 V
VOL
Generator: PRR = 500 kHz, 50% Duty Cycle, tr <6 ns, tf <6 ns, Zo = 50 Ω
Figure 6. Driver Low-Level Output Enable and Disable Time Test Circuit and Voltage Waveforms
IA
VA + VB
2
VID
VB
VIC
A
R
VA
IO
B
VO
IB
Figure 7. Receiver Voltage and Current Definitions
A
Input
Generator
R
VI
50 Ω
1.5 V
0V
B
VO
CL = 15 pF ±20%
RE
CL Includes Fixture
and Instrumentation
Capacitance
Generator: PRR = 500 kHz, 50% Duty Cycle, tr <6 ns, tf <6 ns, Zo = 50 Ω
3V
1.5 V
VI
1.5 V
0V
tPLH
VO
tPHL
90% 90%
1.5 V
10%
tr
VOH
1.5 V
10% V
OL
tf
Figure 8. Receiver Switching Test Circuit and Voltage Waveforms
8
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Product Folder Link(s): SN65HVD10, SN65HVD10Q, SN75HVD10 SN65HVD11, SN65HVD11Q, SN75HVD11
SN65HVD12, SN75HVD12
SN65HVD10, SN65HVD10Q, SN75HVD10
SN65HVD11, SN65HVD11Q, SN75HVD11
SN65HVD12, SN75HVD12
SLLS505K – FEBRUARY 2002 – REVISED SEPTEMBER 2011
www.ti.com
PARAMETER MEASUREMENT INFORMATION (continued)
3V
3V
A
DE
0 V or 3 V
R
D
VO
B
RE
Input
Generator
VI
A
1 kΩ ± 1%
S1
CL = 15 pF ±20%
B
CL Includes Fixture
and Instrumentation
Capacitance
50 Ω
Generator: PRR = 500 kHz, 50% Duty Cycle, tr <6 ns, tf <6 ns, Zo = 50 Ω
3V
VI
1.5 V
1.5 V
0V
tPZH(1)
tPHZ
VOH –0.5 V
VOH
D at 3 V
S1 to B
1.5 V
VO
≈0V
tPZL(1)
tPLZ
≈3V
VO
1.5 V
VOL +0.5 V
D at 0 V
S1 to A
VOL
Figure 9. Receiver Enable and Disable Time Test Circuit and Voltage Waveforms With Drivers Enabled
Copyright © 2002–2011, Texas Instruments Incorporated
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SN65HVD12, SN75HVD12
9
SN65HVD10, SN65HVD10Q, SN75HVD10
SN65HVD11, SN65HVD11Q, SN75HVD11
SN65HVD12, SN75HVD12
SLLS505K – FEBRUARY 2002 – REVISED SEPTEMBER 2011
www.ti.com
PARAMETER MEASUREMENT INFORMATION (continued)
3V
A
0 V or 1.5 V
R
B
1.5 V or 0 V
RE
Input
Generator
VI
A
1 kΩ ± 1%
VO
S1
CL = 15 pF ±20%
B
CL Includes Fixture
and Instrumentation
Capacitance
50 Ω
Generator: PRR = 100 kHz, 50% Duty Cycle, tr <6 ns, tf <6 ns, Zo = 50 Ω
3V
1.5 V
VI
0V
tPZH(2)
VOH
A at 1.5 V
B at 0 V
S1 to B
1.5 V
VO
GND
tPZL(2)
3V
1.5 V
VO
A at 0 V
B at 1.5 V
S1 to A
VOL
Figure 10. Receiver Enable Time From Standby (Driver Disabled)
0 V or 3 V
RE
A
R
Pulse Generator,
15 µs Duration,
1% Duty Cycle
tr, tf ≤ 100 ns
100 Ω
± 1%
B
D
+
_
DE
3 V or 0 V
NOTE: This test is conducted to test survivability only. Data stability at the R output is not specified.
Figure 11. Test Circuit, Transient Over Voltage Test
10
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Copyright © 2002–2011, Texas Instruments Incorporated
Product Folder Link(s): SN65HVD10, SN65HVD10Q, SN75HVD10 SN65HVD11, SN65HVD11Q, SN75HVD11
SN65HVD12, SN75HVD12
SN65HVD10, SN65HVD10Q, SN75HVD10
SN65HVD11, SN65HVD11Q, SN75HVD11
SN65HVD12, SN75HVD12
SLLS505K – FEBRUARY 2002 – REVISED SEPTEMBER 2011
www.ti.com
PARAMETER MEASUREMENT INFORMATION (continued)
FUNCTION TABLES
Table 1. DRIVER (1)
OUTPUTS
(1)
INPUT
D
ENABLE
DE
A
B
H
H
H
L
L
H
L
H
X
L
Z
Z
Open
H
H
L
H = high level; L = low level; Z = high impedance; X = irrelevant; ? =
indeterminate
Table 2. RECEIVER (1)
DIFFERENTIAL INPUTS
VID = VA – VB
ENABLE
RE
OUTPUT
R
VID ≤ –0.2 V
L
L
–0.2 V < VID < –0.01 V
L
?
−0.01 V ≤ VID
L
H
X
H
Z
Open Circuit
L
H
Short circuit
L
H
(1)
H = high level; L = low level; Z = high impedance; X = irrelevant; ? =
indeterminate
Copyright © 2002–2011, Texas Instruments Incorporated
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Product Folder Link(s): SN65HVD10, SN65HVD10Q, SN75HVD10 SN65HVD11, SN65HVD11Q, SN75HVD11
SN65HVD12, SN75HVD12
11
SN65HVD10, SN65HVD10Q, SN75HVD10
SN65HVD11, SN65HVD11Q, SN75HVD11
SN65HVD12, SN75HVD12
SLLS505K – FEBRUARY 2002 – REVISED SEPTEMBER 2011
www.ti.com
EQUIVALENT INPUT AND OUTPUT SCHEMATIC DIAGRAMS
D and RE Inputs
DE Input
VCC
VCC
100 kΩ
1 kΩ
1 kΩ
Input
Input
100 kΩ
9V
9V
A Input
B Input
VCC
VCC
16 V
16 V
R3
R1
R1
R3
Input
Input
16 V
R2
16 V
A and B Outputs
R2
R Output
VCC
VCC
16 V
5Ω
Output
Output
9V
16 V
SN65HVD10
SN65HVD11
SN65HVD12
12
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R1/R2
9 kΩ
36 kΩ
36 kΩ
R3
45 kΩ
180 kΩ
180 kΩ
Copyright © 2002–2011, Texas Instruments Incorporated
Product Folder Link(s): SN65HVD10, SN65HVD10Q, SN75HVD10 SN65HVD11, SN65HVD11Q, SN75HVD11
SN65HVD12, SN75HVD12
SN65HVD10, SN65HVD10Q, SN75HVD10
SN65HVD11, SN65HVD11Q, SN75HVD11
SN65HVD12, SN75HVD12
SLLS505K – FEBRUARY 2002 – REVISED SEPTEMBER 2011
www.ti.com
TYPICAL CHARACTERISTICS
HVD10
RMS SUPPLY CURRENT
vs
SIGNALING RATE
HVD11
RMS SUPPLY CURRENT
vs
SIGNALING RATE
70
RL = 54 Ω
CL = 50 pF
TA = 25°C
RE at VCC
DE at VCC
I CC − RMS Supply Current − mA
I CC − RMS Supply Current − mA
70
VCC = 3.6 V
60
50
VCC = 3 V
VCC = 3.3 V
40
30
0
5
10
15
20
25
30
35
TA = 25°C
RE at VCC
DE at VCC
50
VCC = 3 V
VCC = 3.3 V
40
2.5
Signaling Rate − Mbps
5
7.5
Signaling Rate − Mbps
Figure 12.
Figure 13.
HVD12
RMS SUPPLY CURRENT
vs
SIGNALING RATE
HVD10
BUS INPUT CURRENT
vs
BUS INPUT VOLTAGE
TA = 25°C
RE at VCC
DE at VCC
250
VCC = 3.6 V
60
VCC = 3.3 V
50
10
300
RL = 54 Ω
CL = 50 pF
I I − Bus Input Current − µ A
I CC − RMS Supply Current − mA
70
VCC = 3.6 V
60
30
0
40
RL = 54 Ω
CL = 50 pF
VCC = 3 V
40
TA = 25°C
DE at 0 V
200
150
VCC = 0 V
100
50
VCC = 3.3 V
0
−50
−100
−150
30
100
400
700
Signaling Rate − kbps
Figure 14.
Copyright © 2002–2011, Texas Instruments Incorporated
1000
−200
−7 −6−5 −4−3 −2−1 0 1 2 3 4 5 6 7 8 9 10 11 12
VI − Bus Input Voltage − V
Figure 15.
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SN65HVD12, SN75HVD12
13
SN65HVD10, SN65HVD10Q, SN75HVD10
SN65HVD11, SN65HVD11Q, SN75HVD11
SN65HVD12, SN75HVD12
SLLS505K – FEBRUARY 2002 – REVISED SEPTEMBER 2011
www.ti.com
TYPICAL CHARACTERISTICS (continued)
HVD11 OR HVD12
BUS INPUT CURRENT
vs
BUS INPUT VOLTAGE
HIGH-LEVEL OUTPUT CURRENT
vs
DRIVER HIGH-LEVEL OUTPUT VOLTAGE
150
90
I I − Bus Input Current − µ A
70
TA = 25°C
DE at 0 V
60
50
IOH − High-Level Output Current − mA
80
VCC = 0 V
40
30
20
10
0
VCC = 3.3 V
−10
−20
−30
100
50
0
−50
−100
−40
−50
−150
−60
−7−6 −5 −4 −3 −2 −1 0 1 2 3 4 5 6 7 8 9 10 11 12
VI − Bus Input Voltage − V
−200
140
LOW-LEVEL OUTPUT CURRENT
vs
DRIVER LOW-LEVEL OUTPUT VOLTAGE
DRIVER DIFFERENTIAL OUTPUT
vs
FREE-AIR TEMPERATURE
2.4
100
80
60
40
20
2.3
VCC = 3.3 V
DE at VCC
D at VCC
2.2
2.1
2.0
1.9
1.8
1.7
1.6
0
−2
0
2
4
6
VOL − Driver Low-Level Output Voltage − V
Figure 18.
14
6
2.5
TA = 25°C
DE at VCC
D at 0 V
VCC = 3.3 V
120
−20
−4
−2
0
2
4
VOH − Driver High-Level Output Voltage − V
Figure 17.
VOD − Driver Differential Output − V
I OL − Low-Level Output Current − mA
160
−4
Figure 16.
200
180
TA = 25°C
DE at VCC
D at VCC
VCC = 3.3 V
Submit Documentation Feedback
8
1.5
−40
−15
10
35
60
TA − Free-Air Temperature − °C
85
Figure 19.
Copyright © 2002–2011, Texas Instruments Incorporated
Product Folder Link(s): SN65HVD10, SN65HVD10Q, SN75HVD10 SN65HVD11, SN65HVD11Q, SN75HVD11
SN65HVD12, SN75HVD12
SN65HVD10, SN65HVD10Q, SN75HVD10
SN65HVD11, SN65HVD11Q, SN75HVD11
SN65HVD12, SN75HVD12
SLLS505K – FEBRUARY 2002 – REVISED SEPTEMBER 2011
www.ti.com
TYPICAL CHARACTERISTICS (continued)
ENABLE TIME
vs
COMMON-MODE VOLTAGE
(SEE Figure 22)
DRIVER OUTPUT CURRENT
vs
SUPPLY VOLTAGE
600
−40
TA = 25°C
DE at VCC
D at VCC
RL = 54 Ω
−30
500
HVD12
Enable Time − ns
I O − Driver Output Current − mA
−35
−25
−20
−15
400
HVD11
300
HVD10
200
−10
100
−5
0
0
0
0.50
1
1.50
2
2.50
3
-7
3.50
VCC − Supply Voltage − V
-2
3
8
13
V(TEST) − Common-Mode Voltage − V
Figure 20.
Figure 21.
375 W ± 1%
Y
D
0 or 3 V
-7 V < V(TEST) < 12 V
VOD
60 W
± 1%
Z
DE
375 W ± 1%
Input
Generator
V
50 W
50%
tpZH(diff)
VOD (high)
1.5 V
0V
tpZL(diff)
-1.5 V
VOD (low)
Figure 22. Driver Enable Time From DE to VOD
The time tPZL(x) is the measure from DE to VOD(x). VOD is valid when it is greater than 1.5 V.
Copyright © 2002–2011, Texas Instruments Incorporated
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SN65HVD12, SN75HVD12
15
SN65HVD10, SN65HVD10Q, SN75HVD10
SN65HVD11, SN65HVD11Q, SN75HVD11
SN65HVD12, SN75HVD12
SLLS505K – FEBRUARY 2002 – REVISED SEPTEMBER 2011
www.ti.com
APPLICATION INFORMATION
RT
Stub
Device
HVD10
HVD11
HVD12
RT
Number of Devices on Bus
64
256
256
NOTE: The line should be terminated at both ends with its characteristic impedance (RT = ZO). Stub lengths off the main line
should be kept as short as possible.
Figure 23. Typical Application Circuit
Driver Input
Driver Output
Receiver Input
Receiver Output
Figure 24. HVD12 Input and Output Through 2000 Feet of Cable
An example application for the HVD12 is illustrated in Figure 23. Two HVD12 transceivers are used to
communicate data through a 2000 foot (600 m) length of Commscope 5524 category 5e+ twisted pair cable. The
bus is terminated at each end by a 100-Ω resistor, matching the cable characteristic impedance. Figure 24
illustrates operation at a signaling rate of 250 kbps.
LOW-POWER STANDBY MODE
When both the driver and receiver are disabled (DE low and RE high) the device is in standby mode. If the
enable inputs are in this state for less than 60 ns, the device does not enter standby mode. This guards against
inadvertently entering standby mode during driver/receiver enabling. Only when the enable inputs are held in this
state for 300 ns or more, the device is assured to be in standby mode. In this low-power standby mode, most
internal circuitry is powered down, and the supply current is typically less than 1 nA. When either the driver or the
receiver is re-enabled, the internal circuitry becomes active.
16
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Product Folder Link(s): SN65HVD10, SN65HVD10Q, SN75HVD10 SN65HVD11, SN65HVD11Q, SN75HVD11
SN65HVD12, SN75HVD12
SN65HVD10, SN65HVD10Q, SN75HVD10
SN65HVD11, SN65HVD11Q, SN75HVD11
SN65HVD12, SN75HVD12
SLLS505K – FEBRUARY 2002 – REVISED SEPTEMBER 2011
www.ti.com
THERMAL CHARACTERISTICS OF IC PACKAGES
θJA (Junction-to-Ambient Thermal Resistance) is defined as the difference in junction temperature to ambient
temperature divided by the operating power.
θJA is not a constant and is a strong function of:
• the PCB design (50% variation)
• altitude (20% variation)
• device power (5% variation)
θJA can be used to compare the thermal performance of packages if the specific test conditions are defined and
used. Standardized testing includes specification of PCB construction, test chamber volume, sensor locations,
and the thermal characteristics of holding fixtures. θJA is often misused when it is used to calculate junction
temperatures for other installations.
TI uses two test PCBs as defined by JEDEC specifications. The low-k board gives average in-use condition
thermal performance, and it consists of a single copper trace layer 25 mm long and 2-oz thick. The high-k board
gives best case in-use condition, and it consists of two 1-oz buried power planes with a single copper trace layer
25 mm long and 2-oz thick. A 4% to 50% difference in θJA can be measured between these two test cards.
θJC (Junction-to-Case Thermal Resistance) is defined as difference in junction temperature to case divided by
the operating power. It is measured by putting the mounted package up against a copper block cold plate to
force heat to flow from die, through the mold compound into the copper block.
θJC is a useful thermal characteristic when a heatsink is applied to package. It is not a useful characteristic to
predict junction temperature because it provides pessimistic numbers if the case temperature is measured in a
nonstandard system and junction temperatures are backed out. It can be used with θJB in 1-dimensional thermal
simulation of a package system.
θJB (Junction-to-Board Thermal Resistance) is defined as the difference in the junction temperature and the
PCB temperature at the center of the package (closest to the die) when the PCB is clamped in a cold-plate
structure. θJB is only defined for the high-k test card.
θJB provides an overall thermal resistance between the die and the PCB. It includes a bit of the PCB thermal
resistance (especially for BGAs with thermal balls) and can be used for simple 1-dimensional network analysis of
package system, see Figure 25.
Figure 25. Thermal Resistance
Copyright © 2002–2011, Texas Instruments Incorporated
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SN65HVD12, SN75HVD12
17
SN65HVD10, SN65HVD10Q, SN75HVD10
SN65HVD11, SN65HVD11Q, SN75HVD11
SN65HVD12, SN75HVD12
SLLS505K – FEBRUARY 2002 – REVISED SEPTEMBER 2011
www.ti.com
REVISION HISTORY
Changes from Revision J (February 2009) to Revision K
•
18
Page
Added new section 'LOW-POWER STANDBY MODE', in the Application Information section ......................................... 16
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SN65HVD12, SN75HVD12
PACKAGE OPTION ADDENDUM
www.ti.com
2-Sep-2011
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package
Drawing
Pins
Package Qty
Eco Plan
(2)
Lead/
Ball Finish
MSL Peak Temp
SN65HVD10D
ACTIVE
SOIC
D
8
75
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM
SN65HVD10DG4
ACTIVE
SOIC
D
8
75
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM
SN65HVD10DR
ACTIVE
SOIC
D
8
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM
SN65HVD10DRG4
ACTIVE
SOIC
D
8
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM
SN65HVD10P
ACTIVE
PDIP
P
8
50
Pb-Free (RoHS)
CU NIPDAU N / A for Pkg Type
SN65HVD10PE4
ACTIVE
PDIP
P
8
50
Pb-Free (RoHS)
CU NIPDAU N / A for Pkg Type
SN65HVD10QD
ACTIVE
SOIC
D
8
75
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM
SN65HVD10QDG4
ACTIVE
SOIC
D
8
75
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM
SN65HVD10QDR
ACTIVE
SOIC
D
8
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM
SN65HVD10QDRG4
ACTIVE
SOIC
D
8
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM
SN65HVD11D
ACTIVE
SOIC
D
8
75
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM
SN65HVD11DG4
ACTIVE
SOIC
D
8
75
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM
SN65HVD11DR
ACTIVE
SOIC
D
8
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM
SN65HVD11DRG4
ACTIVE
SOIC
D
8
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM
SN65HVD11P
ACTIVE
PDIP
P
8
50
Pb-Free (RoHS)
CU NIPDAU N / A for Pkg Type
SN65HVD11PE4
ACTIVE
PDIP
P
8
50
Pb-Free (RoHS)
CU NIPDAU N / A for Pkg Type
SN65HVD11QD
ACTIVE
SOIC
D
8
75
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM
SN65HVD11QDG4
ACTIVE
SOIC
D
8
75
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM
Addendum-Page 1
(3)
Samples
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PACKAGE OPTION ADDENDUM
www.ti.com
Orderable Device
2-Sep-2011
Status
(1)
Package Type Package
Drawing
Pins
Package Qty
2500
Eco Plan
(2)
Green (RoHS
& no Sb/Br)
Lead/
Ball Finish
MSL Peak Temp
ACTIVE
SOIC
D
8
SN65HVD11QDRG4
ACTIVE
SOIC
D
8
SN65HVD12D
ACTIVE
SOIC
D
8
75
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM
SN65HVD12DG4
ACTIVE
SOIC
D
8
75
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM
SN65HVD12DR
ACTIVE
SOIC
D
8
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM
SN65HVD12DRG4
ACTIVE
SOIC
D
8
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM
SN65HVD12P
ACTIVE
PDIP
P
8
50
Pb-Free (RoHS)
CU NIPDAU N / A for Pkg Type
SN65HVD12PE4
ACTIVE
PDIP
P
8
50
Pb-Free (RoHS)
CU NIPDAU N / A for Pkg Type
SN75HVD10D
ACTIVE
SOIC
D
8
75
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM
SN75HVD10DG4
ACTIVE
SOIC
D
8
75
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM
SN75HVD10DR
ACTIVE
SOIC
D
8
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM
SN75HVD10DRG4
ACTIVE
SOIC
D
8
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM
SN75HVD10P
ACTIVE
PDIP
P
8
50
Pb-Free (RoHS)
CU NIPDAU N / A for Pkg Type
SN75HVD10PE4
ACTIVE
PDIP
P
8
50
Pb-Free (RoHS)
CU NIPDAU N / A for Pkg Type
SN75HVD11D
ACTIVE
SOIC
D
8
75
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM
SN75HVD11DG4
ACTIVE
SOIC
D
8
75
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM
SN75HVD11DR
ACTIVE
SOIC
D
8
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM
SN75HVD11DRG4
ACTIVE
SOIC
D
8
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM
SN75HVD12D
ACTIVE
SOIC
D
8
75
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM
SN75HVD12DG4
ACTIVE
SOIC
D
8
75
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM
Addendum-Page 2
CU NIPDAU Level-1-260C-UNLIM
Call TI
Samples
(Requires Login)
SN65HVD11QDR
TBD
(3)
Call TI
PACKAGE OPTION ADDENDUM
www.ti.com
Orderable Device
2-Sep-2011
Status
(1)
Package Type Package
Drawing
Pins
Package Qty
Eco Plan
(2)
Lead/
Ball Finish
MSL Peak Temp
SN75HVD12DR
ACTIVE
SOIC
D
8
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM
SN75HVD12DRG4
ACTIVE
SOIC
D
8
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM
SN75HVD12P
ACTIVE
PDIP
P
8
50
Pb-Free (RoHS)
CU NIPDAU N / A for Pkg Type
SN75HVD12PE4
ACTIVE
PDIP
P
8
50
Pb-Free (RoHS)
CU NIPDAU N / A for Pkg Type
(3)
Samples
(Requires Login)
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF SN65HVD10, SN65HVD11, SN65HVD12 :
• Enhanced Product: SN65HVD10-EP, SN65HVD12-EP
Addendum-Page 3
PACKAGE OPTION ADDENDUM
www.ti.com
2-Sep-2011
NOTE: Qualified Version Definitions:
• Enhanced Product - Supports Defense, Aerospace and Medical Applications
Addendum-Page 4
PACKAGE MATERIALS INFORMATION
www.ti.com
1-Sep-2011
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
SN65HVD10DR
SOIC
D
8
2500
330.0
12.4
6.4
5.2
2.1
8.0
12.0
Q1
SN65HVD10QDR
SOIC
D
8
2500
330.0
12.4
6.4
5.2
2.1
8.0
12.0
Q1
SN65HVD11DR
SOIC
D
8
2500
330.0
12.4
6.4
5.2
2.1
8.0
12.0
Q1
SN65HVD11QDR
SOIC
D
8
2500
330.0
12.4
6.4
5.2
2.1
8.0
12.0
Q1
SN65HVD12DR
SOIC
D
8
2500
330.0
12.4
6.4
5.2
2.1
8.0
12.0
Q1
SN75HVD10DR
SOIC
D
8
2500
330.0
12.4
6.4
5.2
2.1
8.0
12.0
Q1
SN75HVD11DR
SOIC
D
8
2500
330.0
12.4
6.4
5.2
2.1
8.0
12.0
Q1
SN75HVD12DR
SOIC
D
8
2500
330.0
12.4
6.4
5.2
2.1
8.0
12.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
1-Sep-2011
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
SN65HVD10DR
SOIC
D
8
2500
340.5
338.1
20.6
SN65HVD10QDR
SOIC
D
8
2500
340.5
338.1
20.6
SN65HVD11DR
SOIC
D
8
2500
340.5
338.1
20.6
SN65HVD11QDR
SOIC
D
8
2500
340.5
338.1
20.6
SN65HVD12DR
SOIC
D
8
2500
340.5
338.1
20.6
SN75HVD10DR
SOIC
D
8
2500
340.5
338.1
20.6
SN75HVD11DR
SOIC
D
8
2500
340.5
338.1
20.6
SN75HVD12DR
SOIC
D
8
2500
340.5
338.1
20.6
Pack Materials-Page 2
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