TI LMP92064

LMP92064
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SNOSCX0 – JUNE 2013
Precision Low-Side, 125 kSps Simultaneous Sampling,
Current Sensor and Voltage Monitor with SPI
Check for Samples: LMP92064
FEATURES
DESCRIPTION
•
The LMP92064 is a precision low-side digital current
sensor and voltage monitor with a digital SPI
interface. This analog front-end (AFE) includes a
precision current sense amplifier to measure a load
current across a shunt resistor and a buffered voltage
channel to measure the voltage supply of the load.
The current and voltage channels are sampled
simultaneously by independent 125 kSps 12-bit ADC
converters, allowing for very accurate power
calculations in unidirectional sensing applications.
1
•
•
•
•
•
•
Two Simultaneous Sampling 12-bit ADCs
– Conversion Rate: 125 kSps (Min)
12-bit Current Sense Channel
– Input-referred Offset: ±15 μV
– Common-mode Voltage Range: –0.2V to 2V
– Maximum Differential Input Voltage: +75 mV
– Fixed Gain: 25 V/V
– Gain Error: ±0.75 % (Max)
– Bandwidth (–3dB): 70 kHz
– DC PSRR: 100 dB
– DC CMRR: 110 dB
12-bit Voltage Channel
– INL: ±1LSB
– Offset Error: ±2 mV (Max)
– Gain Error: ±0.75% (Max)
– Maximum Input Voltage: +2.048V
– Bandwidth: 100 kHz
Internal Reference
SPI Frequency: Up to 20 MHz
Temperature Range: –40°C to +105°C
WSON-16 Package
The LMP92064 includes an internal 2.048V reference
for the ADCs, eliminating the need of an external
reference and reducing component count and board
space.
A host can communicate with the LMP92064 using a
four-wire SPI interface running at speeds of up to 20
MHz. The fast SPI interface allows the user to take
advantage of the higher bandwidth ADC to capture
fast varying signals. The four-wire interface with
dedicated unidirectional input and output lines also
allows for an easy interface to digital isolators in
applications where isolation is required.
The LMP92064 operates from a single 4.5V to 5.5V
supply and includes a separate digital supply pin. The
LMP92064 is specified over a temperature range of
–40°C to 105°C, and is available in a 5mm x 4mm
WSON-16 package.
APPLICATIONS
•
•
•
Enterprise Servers
Telecommunications
Power Management
LOAD
RDIVIDE2
+
+
48V
-
INCP
INCN
INVP
INVG
RSENSE
RDIVIDE1
VDD VDIG
SPI Bus
LMP92064
GND DGND
-
5V
System
Management
Control Unit
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2013, Texas Instruments Incorporated
LMP92064
SNOSCX0 – JUNE 2013
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FUNCTIONAL BLOCK DIAGRAM
REFC
VDD
VDIG
LMP92064
VREF
2.048V
INVP
+
-
Buffer
Av=1
CSB
ADC
12-bit
SCLK
SDI
INVG
DIGITAL
CONTROL
SDO
RESET
INCP
+
CSA
Av=25
INCN
ADC
12-bit
REFG
GND
DGND
Figure 1.
2
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CONNECTION DIAGRAM
REFC
1
16
RESET
REFG
2
15
RESERVED
INCP
3
14
CSB
INCN
4
13
SCLK
DAP
INVP
5
12
SDI
INVG
6
11
SDO
GND
7
10
DGND
VDD
8
9
VDIG
Figure 2. Top View
WSON-16 Package
Table 1. Pin Descriptions
PIN
(1)
I/O (1)
DESCRIPTION
NAME
NO.
1
REFC
n/a
2
REFG
G
Internal reference ground
3
INCP
I
Positive current channel input
4
INCN
I
Negative current channel input
5
INVP
I
Positive voltage channel input
6
INVG
G
Ground reference for the negative voltage channel input
7
GND
G
Analog ground
8
VDD
P
Analog power supply
Internal reference bypass capacitor pin
9
VDIG
P
Digital power supply
10
DGND
G
Digital ground
11
SDO
O
SPI Bus push-pull serial data digital output
12
SDI
I
SPI Bus serial data digital input
13
SCLK
I
SPI Bus clock digital input
14
CSB
I
SPI Bus chip select bar digital input
15
RESERVED
n/a
16
RESET
I
n/a
DAP
n/a
Reserved (Do not connect)
Reset (high-active)
No connection (Do not connect)
G = Ground, I = Input, O = Output, P = Power
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ABSOLUTE MAXIMUM RATINGS (1) (2)
Over operating free-air temperature range (unless otherwise noted)
MIN
MAX
UNIT
V
Analog Supply Voltage (VDD)
–0.3
6.0
Digital Supply Voltage (VDIG)
VDD-0.3
VDD+0.3
Voltage at Input Pins (3)
–0.3
VDD+0.3
V
Storage Temperature Range
–65
150
°C
Junction Temperature
150
°C
Mounting temperature
Infrared or convection (20 sec)
260
°C
ESD Tolerance
Human Body Model
2000
V
Charged Device Model
1000
V
(1)
(2)
(3)
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
All voltages are measured with respect to GND = DGND = 0V, unless otherwise specified.
When the input voltage (VIN), at any pin exceeds power supplies (VIN < GND or VIN > VDD), the current at that pin must not exceed
5mA, and the voltage (VIN) at that pin must not exceed 6.0V. See Pin Description for additional details of input circuitry.
THERMAL CHARACTERISTICS
Over operating free-air temperature range (unless otherwise noted)
UNIT
θJA
(1)
Package thermal resistance (1)
WSON-16
44
°C/W
The package thermal impedance is calculated in accordance with JESD 51-7. The maximum power dissipation must be de-rated at
elevated temperatures and is dictated by TJ(MAX) , θ JA, and the ambient temperature, TA. The maximum allowable power dissipation
PDMAX = (TJ(MAX) - TA )/ θJA or the number given in Absolute Maximum Ratings, whichever is lower.
RECOMMENDED OPERATING CONDITIONS (1) (2)
Analog Supply Voltage (VDD)
MIN
MAX
UNIT
4.5
5.5
V
Digital Supply Voltage (VDIG)
VDD
Temperature Range
(1)
(2)
4
–40
V
105
ºC
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
All voltages are measured with respect to GND = DGND = 0V, unless otherwise specified.
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ELECTRICAL CHARACTERISTICS
Typical specifications are at 25ºC. All specifications are at 4.5V ≤ VDD ≤ 5.5V, VDIG = VDD and –0.2V ≤ VCM ≤ 2V, unless
otherwise specified. Boldface limits apply at temperature extremes.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
±60
UNIT
CURRENT SENSE INPUT CHANNEL
μV
VOS
Input-referred Offset Voltage
±15
TCVOS
Input-referred Offset Voltage Drift
±280
nV/ºC
Long-term Stability
0.3
μV/mo
Resolution
12
20
Bits
μV
±1
±0.025
LSB
%
INL
Integral Non-Linearity Error
DNL
Differential Non-Linearity Error
±0.5
LSB
DC CMRR
Common-Mode Rejection Ratio
–0.2V ≤ VCM ≤ 2V
110
dB
DC PSRR
Power Supply Rejection Ratio
4.5V ≤ VDD ≤ 5.5V
100
dB
CMVR
Common-Mode Voltage Range
Low VCM
–0.2
V
VDIFF(MAX)
Maximum Differential Input Voltage
Range
75
AV
Current Shunt Amplifier Gain
25
V/V
Current Sense Channel Gain
50
kCode/V
High VCM
2
mV
GE
Gain Error (CSA, VREF and ADC)
±0.75
%
GD
Gain Drift
±25
RIN
Input Impedance
100
GΩ
BW
–3dB Bandwidth
70
kHz
ppm/°C
VOLTAGE INPUT CHANNEL
Offset Error (Buffer and ADC)
–2
Resolution
INL
Integral Non-Linearity Error
DC PSRR
Power Supply Rejection Ratio
VCHVP
Full-Scale Input Voltage
AV
2
mV
12
Bits
±1
±0.025
LSB
%
70
dB
2.048
V
Buffer Amplifier Gain
1
V/V
Voltage Sense Channel Gain
2
kCode/V
GE
Gain Error (Buffer, VREF and
ADC)
±0.75
%
RIN
Input Impedance
100
GΩ
BW
Bandwidth (1)
100
kHz
DIGITAL INPUT/OUTPUT CHARACTERISTICS
VIH
Logical “1” Input Voltage
VIL
Logical “0” Input Voltage
0.7*VDIG
VOH
Logical “1” Output Voltage
ISOURCE = 300μA
VOL
Logical “0” Output Voltage
ISINK = 300μA
V
0.3*VDIG
V
VDIG
–0.15
V
DGND
+0.15
V
SUPPLY CHARACTERISTICS
IVDD
Analog Supply Current
11
mA
IVDIG
Digital Supply Current
2
mA
(1)
No analog filter; limited by sampling rate.
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TIMING CHARACTERISTICS
Typical specifications are at 25ºC. All specifications are at 4.5V ≤ VDD ≤ 5.5V, VDIG = VDD and a 20 pF capacitive load on
SDO, unless otherwise specified.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
10
UNIT
tDS
SDI to SCLK rising edge setup time
ns
tDH
SCLK rising edge to SDI hold time
10
ns
fCLK
Frequency of SCLK
100
Hz
tHIGH
High width of SPI clock
25
ns
tLOW
Low width of SPI clock
25
ns
tS
CSB falling edge to SCLK rising edge
setup time
10
ns
tC
SCLK rising edge to CSB rising edge
hold time
30
ns
tDV
SCLK falling edge to valid SDO
readback data
tRST
Reset pin pulse width
3.5
ns
tCONV
Conversion rate of all channels
125
kSps
20
20
MHz
ns
TIMING DIAGRAMS
tC
tS
CSB
1/fCLK
tHIGH
tLOW
tDS
SCLK
tDH
BIT N
SDI
BIT N - 1
Figure 3. Serial Control Port Timing – Write
CSB
SCLK
tDV
DATA BIT N
SDO
DATA BIT N - 1
Figure 4. Serial Control Port Timing – Read
6
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tS
tDS
tC
1/fCLK
tHI
tLO
tDH
CSB
SCLK
DON’T CARE
SDI
DON’T CARE
DON’T CARE
R/W
A14
A13
A12
A11
A10
A9
A8
D2
D1
D0
DON’T CARE
Figure 5. Serial Control Port Write – MSB First, 16-bit Instruction, Timing Measurements
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TYPICAL CHARACTERISTICS
All plots at TA = 25ºC, VDD = 5.0V, VDIG = 5.0V, VCM = 0V and GND = DGND = 0V, unless otherwise specified.
INPUT-REFERRED OFFSET
vs
SUPPLY VOLTAGE
(Current Channel)
ANALOG SUPPLY CURRENT
vs
SUPPLY VOLTAGE
80
60
105°C
10.25
Input-referred Offset (µV)
Analog Supply Current (mA)
10.50
10.00
25°C
9.75
9.50
-40°C
20
0
-40
-60
9.00
-80
4.5
4.6
4.7
4.8
4.9
5.0
5.1
5.2
5.3
5.4
Supply Voltage (V)
5.5
4.5
4.8
4.9
5.0
5.1
5.2
5.3
5.4
Supply Voltage (V)
Figure 7.
INPUT-REFERRED OFFSET
vs
COMMON-MODE VOLTAGE
(Current Channel)
GAIN ERROR
vs
SUPPLY VOLTAGE
(Current Channel)
5.5
C00
0.8
0.6
-40°C
25°C
40
0.4
Gain Error (%)
Input-referred Offset (µV)
4.7
Figure 6.
20
0
105°C
-20
105°C
0.2
0.0
-0.2
-40
-0.4
-60
-0.6
25°C
-40C°
-80
-0.8
-0.2 0.0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
1.8
Common-mode Voltage (V)
2.0
4.5
4.6
4.7
4.8
4.9
5.0
5.1
5.2
Supply Voltage (V)
C00
Figure 8.
Figure 9.
GAIN ERROR
vs
COMMON-MODE VOLTAGE
(Current Channel)
GAIN
vs
FREQUENCY
(Current Channel)
0.8
30
0.6
29
5.3
5.4
5.5
C00
28
0.4
27
Gain (dB)
0.2
105°C
0.0
-0.2
26
25
24
23
-0.4
22
25°C
-0.6
-40°C
21
-0.8
20
-0.2 0.0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
Common-mode Voltage (V)
1.6
1.8
2.0
0.1
C00
Figure 10.
8
4.6
C00
80
Gain Error (%)
105°C
-20
9.25
60
-40°C
25°C
40
1
10
Frequency (kHz)
100
C00
Figure 11.
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TYPICAL CHARACTERISTICS (continued)
All plots at TA = 25ºC, VDD = 5.0V, VDIG = 5.0V, VCM = 0V and GND = DGND = 0V, unless otherwise specified.
INTEGRAL NONLINEARITY
(Current Channel)
1.0
1.0
0.8
0.8
0.6
0.6
Integral Nonlinearity
Differential Nonlinearity (LSB)
DIFFERENTIAL NONLINEARITY
(Current Channel)
0.4
0.2
0.0
-0.2
-0.4
0.4
0.2
0.0
-0.2
-0.4
-0.6
-0.6
-0.8
-0.8
-1.0
-1.0
0
1024
2048
3072
4096
Output Code
0
1024
2048
3072
4096
Output Code
C00
C00
Figure 12.
Figure 13.
COMMON-MODE REJECTION RATIO DISTRIBUTION
(Current Channel)
POWER SUPPLY REJECTION RATIO DISTRIBUTION
VCM = -0.2V
(Current Channel)
70
50
125°C
25°C
60
25°C
40
40
125°C
Count (%)
Count (%)
50
-40°C
30
30
-40°C
20
20
0
-75
-50
-25
0
25
50
0
-100
75
CMRR (µV/V)
-50
0
50
100
PSRR (µV/V)
C00
Figure 14.
Figure 15.
INPUT-REFERRED OFFSET
vs
SUPPLY VOLTAGE
(Voltage Channel)
GAIN ERROR
vs
SUPPLY VOLTAGE
(Voltage Channel)
1.5
C01
0.8
105°C
0.6
105°C
1.0
0.4
Gain Error (%)
Input-referred Offset (mV)
Vin = 10mV
10
Vin = 0mV
10
0.5
-40°C
25°C
0.0
0.2
0.0
25°C
-40°C
-0.2
-0.4
-0.5
-0.6
-1.0
-0.8
4.5
4.6
4.7
4.8
4.9
5.0
5.1
Supply Voltage (V)
5.2
5.3
5.4
5.5
4.5
C01
Figure 16.
4.6
4.7
4.8
4.9
5.0
5.1
5.2
5.3
5.4
Supply Voltage (V)
5.5
C01
Figure 17.
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TYPICAL CHARACTERISTICS (continued)
All plots at TA = 25ºC, VDD = 5.0V, VDIG = 5.0V, VCM = 0V and GND = DGND = 0V, unless otherwise specified.
INTEGRAL NONLINEARITY
(Voltage Channel)
1.0
1.0
0.8
0.8
Integral Nonlinearity (LSB)
Differential Nonlinearity (LSB)
DIFFERENTIAL NONLINEARITY
(Voltage Channel)
0.6
0.4
0.2
0.0
-0.2
-0.4
-0.6
-0.8
0.6
0.4
0.2
0.0
-0.2
-0.4
-0.6
-0.8
-1.0
-1.0
0
1024
2048
3072
Output Code
4096
0
2048
3072
Output Code
4096
C01
Figure 18.
Figure 19.
POWER SUPPLY REJECTION RATIO DISTRIBUTION
(Voltage Channel)
GAIN
vs
FREQUENCY
(Voltage Channel)
50
2
-40°C
1
25°C
40
0
30
Gain (dB)
Count (%)
1024
C01
125°C
20
-1
-2
-3
-4
10
-5
0
-6
-5
-2.5
0
PSRR (mV/V)
2.5
5
0.1
C01
Figure 20.
10
1
10
Frequency (kHz)
100
C01
Figure 21.
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APPLICATION INFORMATION
Current Sense Input Channel
The current sensing channel of the LMP92064 has a high impedance differential amplifier followed by a 12-bit
analog-to-digital converter. The binary code result of a conversion is stored as a right-justified 16-bit number as
shown in Table 2, where the 4 most significant bits are always 0. Due to an offset auto-calibration feature of the
current sense channel path, the top 256 codes are clipped at code 3840, denoted by the trailing zeros found in
the equivalent binary code of the maximum positive input voltage.
The output data of the current sense channel is accessible on registers 0x0203 and 0x0202.
Table 2. Ideal Current Channel Input Voltages and Output Codes
DESCRIPTION
ANALOG VALUE
Full scale range
VFS= 81.92 mV
DIGITAL OUTPUT
Least significant bit (LSB)
VFS / 4096
BINARY CODE
[B15:B0]
HEX CODE
Maximum Positive Input Voltage
VFS – 256 LSB
0000 1111 0000 0000
0x0F00
Zero
0V
0000 0000 0000 0000
0x0000
Selection of the Current Sense Resistor
The accuracy of the current measurement depends heavily on the accuracy of the shunt resistor RSENSE. Its
value depends on the application and it is a compromise between signal accuracy, maximum permissible voltage
loss and power dissipation in the shunt resistor. High values of RSENSE provide better accuracy at lower currents
by minimizing the effects of offset, while low values of RSENSE minimize voltage loss in the supply section, but at
the expense of low-end accuracy.
The use of a “4-terminal” or “Kelvin” sense resistor is highly recommended. See the CURRENT INPUT ERROR
SOURCES AND LAYOUT CONSIDERATIONS section for more information.
Current Sense Input Channel Common-Mode and Differential Voltage Range (Dynamic Range
Considerations)
The input voltage should be in the range of –0.2V to 2V. The input can withstand voltage up to VDD+0.3V
absolute maximum but the operational range is limited to 2V. Operation below –0.2V or above 2V on either input
pin will introduce severe gain errors and non-linearity.
The maximum differential voltage (defined as the voltage difference between INCP and INCN) for which the part
is designed to work is 75 mV. Larger differential or common mode input voltages will not damage the part (as
long as the input pins remain between GND-0.3V and VDD+0.3V), however, exposure for extended periods may
affect device reliability. The ADC output code will not roll over and will clip at min or max scale when the
maximum differential voltage is exceeded.
Current Input Error Sources and Layout Considerations
The traces leading to and from the sense resistor can be significant error sources. With small value sense
resistors (<100 mΩ), trace resistance shared with the load can cause significant errors. It is recommended to
connect the sense resistor pads directly to the LMP92064's INCP and INCN inputs using “Kelvin” or “4-wire”
connection techniques. An example is shown in Figure 22.
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Load Current Path
PCB
Source
Trace
PCB
Load
Trace
Kelvin Sense
Traces to
Amplifer
Sense Resistor
VSENSE
Figure 22. 4-Wire "Kelvin" Sensing Technique
Since the sense traces only carry the amplifier bias current, the connecting input traces can be thinner, signal
level traces. The traces should be one continuous piece of copper from the sense resistor pad to the LMP92064
input pin pad, and ideally on the same layer with minimal vias or connectors. This can be important around the
sense resistor if it is generating any significant heat. To minimize noise pickup and thermal errors, the input
traces should be treated as a signal pair and routed tightly together with a direct path to the input pins. The input
traces should be run away from noise sources, such as digital lines, switching supplies or motor drive lines.
Voltage Sense Input Channel
The voltage sensing channel of the LMP92064 has a high impedance buffer amplifier followed by a 12-bit
analog-to-digital converter. The binary code result of a conversion is also stored as a right-justified 16-bit number
as shown in Table 3, where the 4 most significant bits are always 0.
The output data of the voltage sense channel is accessible on registers 0x0201 and 0x0200.
Table 3. Ideal Voltage Channel Input Voltages and Output Codes
DESCRIPTION
ANALOG VALUE
Full scale range
VFS= 2.048V
DIGITAL OUTPUT
Least significant bit (LSB)
VFS / 4096
BINARY CODE
[B15:B0]
HEX CODE
Maximum Positive Input Voltage
VFS – 1 LSB
0000 1111 1111 1111
0x0FFF
Zero Code Voltage
0V
0000 0000 0000 0000
0x0000
Selection of the Voltage Input Resistor Divider
The input buffer amplifier of the voltage channel can tolerate high source impedances, which enables scaling the
input voltage with the use of an external resistor divider. The accuracy of the voltage measurements depends on
the accuracy of the components used for the resistor divider as well as the impedance of the divider.
Power Supply Decoupling
In order to decouple the LMP92064 from AC noise on the power supply, it is recommended to use a 0.1 μF
bypass capacitor between the VDD and GND pins. This capacitor should be placed as close as possible to the
supply pins. In some cases an additional 10 μF bypass capacitor may further reduce the supply noise. In addition
the VDIG power pin should also be decoupled to DGND with a 0.1 μF bypass capacitor. Do not forget that these
capacitors must be rated for the full supply voltage (2x the maximum voltage is recommended for the capacitor
working voltage rating).
12
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ADC Operation
The LMP92064 includes two 12-bit ADCs that are continuously running in the background. The device is
configured, and data is read, using a four-wire SPI interface: CSB, SCLK, SDO and SDI. The device outputs its
data on SDO, and the data for both channels is synchronized such that all data read would be from the same
instant in time. New conversion data for both channels will only be made available after all registers are read in
descending sequential order (addresses 0x0203-0x0200). All registers must be read otherwise new conversion
data will not be available. Three different output data formats are available as detailed in Figure 23, Figure 24
and Figure 25.
Command
1: Read
0: Write
Access of New
Conversion Data Enabled
New Conversion
Data Loaded
FRAME N
FRAME N+1
FRAME N+2
FRAME N+3
FRAME N+4
Read INC MS byte
INC read LS byte
INV read MS byte
INV read LS byte
INC read MS byte
CSB
R
SDI
R
ADDR
0
0
R
DATA
DATA
0 B11B10 B9 B8
B7 B6 B5 B4 B3 B2 B1 B0
SDO
0
ADDR-1
0
CONVERSION X DATA FOR CURRENT CHANNEL (INC)
R
ADDR-2
0
0
ADDR-3
R
DATA
DATA
0 B11B10 B9 B8
B7 B6 B5 B4 B3 B2 B1 B0
ADDR
DATA
0
0
0
0 B11B10 B9 B8
CONVERSION Y DATA FOR
CURRENT CHANNEL (INC)
CONVERSION X DATA FOR VOLTAGE CHANNEL (INV)
Figure 23. Timing Diagram with Byte Read Frames
Command
1: Read
0: Write
New Conversion Data
Loaded
Access of New
Conversion Data Enabled
FRAME N+1
FRAME N
FRAME N+2
Read INV
Read INC
Read INC
CSB
SDI
R
0
0
0
R
ADDR
SDO
ADDR-2
R
DATA
ADDR
DATA
DATA
0 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0
0
CONVERSION X DATA FOR CURRENT CHANNEL (INC)
0
0
0 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0
CONVERSION Y DATA FOR CURRENT CHANNEL (INC)
0
0
0
0 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0
CONVERSION X DATA FOR VOLTAGE CHANNEL (INV)
Figure 24. Timing Diagram with Word Read Frames
Command
1: Read
0: Write
Access of New
Conversion Data Enabled
FRAME N
New Conversion Data
Loaded
FRAME N+1
Read INC and INV
Read INC and INV
CSB
SDI
R Address n
R Address n
INC
MSB
SDO
INC
LSB
INV
MSB
INV
LSB
CONVERSION X DATA FOR CURRENT and
VOLTAGE CHANNELS (INC and INV)
INC
MSB
INC
LSB
INV
MSB
INV
LSB
CONVERSION Y DATA FOR CURRENT and
VOLTAGE CHANNELS (INC and INV)
Figure 25. Timing Diagram with All Data Read Frames
The register address to read can automatically decrement if the CSB line is kept low longer. For example, to read
all the conversion data, keep the CSB line low for 48 SPI clock cycles (16 clocks for command/address, 8 clocks
for MSB of current channel, 8 clocks for LSB of current channel, 8 clocks for MSB of voltage channel and 8
clocks for LSB of voltage channel). The read command should start from address 0x0203.
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Device Power-Up Sequence
The sources providing power to the analog and digital supply pins of the LMP92064, VDD and VDIG, must ramp
up at the same time to have a proper power-on reset (POR) event. The easiest way to achieve it is to tie VDD
and VDIG to the same power source using a star configuration.
Reference
The LMP92064 includes an internal 2.048V band-gap reference for the ADCs, which eliminates the need of an
external reference and reduces component count and board space. The REFC pin is provided to allow bypassing
this internal reference for low noise operation. A 1 µF ceramic decoupling capacitor is required between the
REFC and REFG pins of the converter. The capacitor should be placed as close as possible to the pins of the
device.
Reset
There are two methods to reset the LMP92064. A soft reset is done by setting bit7=1 in the CONFIG_A register.
In a soft reset, the SPI state machine and the contents of registers 0x0000 and 0x0001 are unnafected.
A hardware reset is done by connecting the RESET pin of the LMP92064 to VDIG. If the pin is driven by a switch
or a GPIO, it is recommended to add an external RC filter to prevent reset glitches.
Applications Diagram
A typical application of the LMP92064 is shown in Figure 26. The LMP92064 is monitoring the voltage drop
across RSENSE and the voltage across R1. The voltage across RSENSE can be used to calculate the circuitry load
current. The voltage across R1 can be used to calculate the -48V supply voltage. To prevent aliasing errors
external analog differential filters are shown for each channel.
RSENSE
-48V
To Load
C5 0.1µF
+
R5
C6 1µF
LM4040-5
C3 0.1µF
C4 1µF
+
REFC
LMP92064
Vref
2.048V
1.55k R1
47k R2
INVP
+
C1
VDD
VDIG
(4.5V to 5.5V) (4.5V to 5.5V)
CSB
ADC
12-bit
+2.048V
SCLK
SDI
INVG
100 R3
C2
1nF
100 R4
SPI
BUS
SDO
Isolator
RESET
INCP
+
+75mV
CSA
Av=25
INCN
ADC
12-bit
-0.2V to 2V
(abs max <VDD)
REFG
GND
DGND
Figure 26. Typical Applications Circuit
14
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Registers
1. If written to, Reserved bits must be written to 0 unless otherwise indicated.
2. Read back value of Reserved bits and registers is unspecified and should be discarded.
3. Recommended values must be programmed and forbidden values must not be programmed where they are
indicated in order to avoid unexpected results.
4. If written to, registers indicated as Reserved must have the indicated default value as shown in the register
map. Any other value can cause unexpected results.
Table 4. Register Map
REGISTER NAME
REGISTER DESCRIPTION
ADDRESS
ACCESS
DEFAULT
CONFIG_A
CONFIG_B
Interface Configuration A
0x0000
R/W
0x18
Interface Configuration B
0x0001
R/W
0x00
Reserved
Reserved
0x0002
R/W
0x00
CHIP_TYPE
Chip Type
0x0003
RO
0x07
CHIP_ID
Chip ID
0x0004
0x0005
RO
0x00
0x04
CHIP_REV
Chip Revision
0x0006
RO
0x01
MFR_ID
Manufacturer ID
0x000C
0x000D
RO
0x51
0x04
REG_UPDATE
Register Update
0x000F
R/W
0x00
CONFIG_REG
LMP92064 Specific Configuration Register
0x0100
R/W
0x00
STATUS
Status Register
0x0103
RO
N/A
DATA_VOUT
Voltage Channel Output Data
0x0200
0x0201
RO
N/A
DATA_COUT
Current Channel Output Data
0x0202
0x0203
RO
N/A
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Table 5. CONFIG_A: Interface Configuration A
ADDR
BIT 7
BIT 6
BIT 5
BIT 4
0x0000
RESET
DDIR
ADDRDIR
SDDIR
[7]
RESET
BIT 3
BIT 2
BIT 1
Soft reset (self-clearing)
BIT 0
R/W
0: Normal (default)
1: Reset
Note: Contents of register 0x0000 and 0x0001 and SPI state machine
are unaffected
[6]
DDIR
Data direction
RO
0: Data is transmitted MSB first (default)
[5]
ADDRDIR
Multiple-read auto-address direction
RO
0: Address auto-decrements (default)
Note: Address 0x0000 will wrap to 0x7FFF
[4]
SSDIR
Serial data direction
RO
1: Unidirectional; SDI is used for write and SDO is used for read (default)
[3:0]
Bits [3:0] should always mirror [7:4] as follows:
R/W
[3] = [4]
[2] = [5]
[1] = [6]
[0] = [7]
Table 6. CONFIG_B: Interface Configuration B
ADDR
BIT 7
BIT 6
BIT 5
0x0001
STREAM
Reserved
BUFREG_RD
[7]
STREAM
BIT 4
BIT 3
BIT 2
Reserved
BIT 1
Reserved
Stream
BIT 0
Reserved
RO
0: Streaming is on (default)
[6]
Reserved
Reserved
RO
0 (default)
[5]
BUFREG_RD
Active/buffered register read-back
R/W
0: Read back from active register (default)
1: Read back from buffered register
Note: Only double-buffered register affected: 0x0100
[4:3] Reserved
Reserved
RO
00 (default)
[2:1] Reserved
Reserved
RO
00 (default)
[0]
Reserved
Reserved
RO
0 (default)
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Table 7. CHIP_TYPE: Chip Type
ADDR
BIT 7
BIT 6
BIT 5
BIT 4
0x0003
BIT 3
BIT 2
BIT 1
BIT 0
CHIP_TYPE
[7:0] CHIP_TYPE
Chip type
RO
0x07: Precision ADC
Table 8. CHIP_ID: Chip ID
ADDR
BIT 7
BIT 6
BIT 5
BIT 4
0x0004
BIT 3
BIT 2
BIT 1
BIT 0
CHIP_ID_LSB
[7:0] CHIP_ID_LSB
Chip ID LSB
RO
0x00 (Manufacturer defined)
ADDR
BIT 7
BIT 6
BIT 5
BIT 4
0x0005
BIT 3
BIT 2
BIT 1
BIT 0
CHIP_ID_MSB
[7:0] CHIP_ID_MSB
Chip ID MSB
RO
0x04 (Manufacturer defined)
Table 9. CHIP_REV: Chip Revision
ADDR
BIT 7
BIT 6
BIT 5
0x0006
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
CHIP_REV
[7:0] CHIP_REV
Chip REV
RO
0x01
Table 10. MFR_ID: Manufacturer ID
ADDR
BIT 7
BIT 6
BIT 5
0x000C
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
MFR_ID_LSB
[7:0] MFR_ID_LSB
Manufacturer ID LSB
RO
0x51
ADDR
BIT 7
BIT 6
BIT 5
0x000D
[7:0] MFR_ID_MSB
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
MFR_ID_MSB
Manufacturer ID MSB
RO
0x04
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Table 11. REG_UPDATE: Register Update
ADDR
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
0x000F
BIT 0
BUFREG_
UPDATE
[7:1] Reserved
Reserved
RO
0 (default)
[0]
BUFREG_
Buffered register update (self clearing)
UPDATE
0: No action (default)
R/W
1: Transfer buffered register contents to active register
Note: Register 0x0100 is buffered.
Table 12. CONFIG_REG: LMP92064 Specific Configuration Register
ADDR
BIT 7
BIT 6
BIT 5
BIT 4
0x0100
BIT 3
BIT 2
BIT 1
BIT 0
Reserved
[7:0] Reserved
Reserved for future use
R/W
0x00 (default)
Note: This register is double-buffered; register 0x000F
must be set to 1 to transfer the contents from the buffer
to the active register.
Table 13. STATUS: Status Register
ADDR
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
0x0103
0
0
0
0
0
0
0
STATUS
[7:1] Unused
Unused
RO
Always read 7’b0
[0]
STATUS
Status
RO
0: Device is not ready for conversion
1: Device is ready for conversion
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Table 14. DATA_VOUT: Voltage Channel Output Data
ADDR
BIT 7
BIT 6
BIT 5
0x0200
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
VOUT_DATA_LSB
[7:0] VOUT_
Voltage output data least significant byte
RO
DATA_LSB
ADDR
BIT 7
BIT 6
BIT 5
BIT 4
0x0201
0
0
0
0
[7:4] Unused
BIT 3
BIT 2
BIT 1
BIT 0
VOUT_DATA_MSB
Unused
RO
0000 (default)
[3:0] VOUT_
Voltage output data most significant byte
RO
DATA_MSB
Table 15. DATA_COUT: Current Channel Output Data
ADDR
BIT 7
BIT 6
BIT 5
0x0202
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
COUT_DATA_LSB
[7:0] COUT_
Current output data least significant byte
RO
DATA_LSB
ADDR
BIT 7
BIT 6
BIT 5
BIT 4
0x0203
0
0
0
0
[7:4] Unused
BIT 3
BIT 2
BIT 1
BIT 0
COUT_DATA_MSB
Unused
RO
0000 (default)
[3:0] COUT_
Current output data most significant byte
RO
DATA_MSB
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PACKAGE OPTION ADDENDUM
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PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
(2)
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
LMP92064SD/NOPB
ACTIVE
WSON
NHR
16
1000
Green (RoHS
& no Sb/Br)
CU SN
Level-3-260C-168 HR
-40 to 105
L92064
LMP92064SDE/NOPB
ACTIVE
WSON
NHR
16
250
Green (RoHS
& no Sb/Br)
CU SN
Level-3-260C-168 HR
-40 to 105
L92064
LMP92064SDX/NOPB
ACTIVE
WSON
NHR
16
4500
Green (RoHS
& no Sb/Br)
CU SN
Level-3-260C-168 HR
-40 to 105
L92064
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
Addendum-Page 1
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In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
MECHANICAL DATA
NHR0016B
SDA16B (Rev A)
www.ti.com
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