INA203-Q1 www.ti.com SBOS539 – DECEMBER 2010 Unidirectional Measurement Current-Shunt Monitor with Dual Comparators Check for Samples: INA203-Q1 FEATURES DESCRIPTION • • • The INA203-Q1 is a unidirectional current-shunt monitor with voltage output, dual comparators, and voltage reference. The INA203-Q1 can sense drops across shunts at common-mode voltages from –16V to +80V. The INA203-Q1 is available with three output voltage scales: 20V/V, 50V/V, and 100V/V, with up to 500kHz bandwidth. 1 2 • • • • • • Qualified for Automotive Applications Complete Current Sense Solution Dual Comparators: – Comparator 1 with Latch – Comparator 2 with Optional Delay Common-Mode Range: –16V to +80V High Accuracy: 3.5% (max) Over Temperature Bandwidth: 500kHz Quiescent Current: 1.8mA Latch-Up Performance Meets 100 mA Per AEC-Q100, Level I Packages: SO-14, TSSOP-14, MSOP-10 The INA203-Q1 operates from a single +2.7V to +18V supply. It is specified over the extended operating temperature range of –40°C to +125°C. APPLICATIONS • • • Automotive Power Management Battery Chargers VS 1 OUT 2 The INA203-Q1also incorporates two open-drain comparators with internal 0.6V references. On 14-pin versions, the comparator references can be overridden by external inputs. Comparator 1 includes a latching capability, and Comparator 2 has a user-programmable delay. 14-pin versions also provide a 1.2V reference output. VS 1 10 VIN+ OUT 2 9 VIN- 14 VIN+ CMP1 IN+ 3 8 CMP1 OUT 13 VIN- CMP2 IN+ 4 7 CMP2 OUT GND 5 6 CMP1 RESET 1.2V REF 12 1.2V REF OUT CMP1 IN-/0.6V REF 3 CMP1 IN+ 4 11 CMP1 OUT CMP2 IN+ 5 10 CMP2 OUT CMP2 IN-/0.6V REF 6 9 GND 7 8 0.6V REF RELATED PRODUCTS CMP2 DELAY FEATURES CMP1 RESET Variant of INA203-Q1–INA205 Comparator 2 polarity INA206–INA208 Current-shunt monitor with single Comparator and VREF INA200–INA202 Current-shunt monitor only INA193–INA198 Current-shunt monitor with split stages for filter options INA270–INA271 PRODUCT 1 2 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. All trademarks are the property of their respective owners. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2010, Texas Instruments Incorporated INA203-Q1 SBOS539 – DECEMBER 2010 www.ti.com This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. Table 1. ORDERING INFORMATION (1) TA -40°C to 125°C (1) PACKAGE SOIC-8 Reel of 2000 ORDERABLE PART NUMBER TOP-SIDE MARKING INA203AQPWRQ1 I203AQ For the most current package and ordering information see the Package Option Addendum at the end of this document, or see the TI web site at www.ti.com. ABSOLUTE MAXIMUM RATINGS (1) Supply Voltage, V+ VALUE UNIT 18 V Differential (VIN+) – (VIN–) –18 to +18 V Common-Mode –16 to +80 V Comparator Analog Input and Reset Pins GND – 0.3 to (V+) + 0.3 V Analog Output, Out Pin GND – 0.3 to (V+) + 0.3 V Comparator Output, Out Pin GND – 0.3 to 18 V VREF and CMP2 Delay Pin GND – 0.3 to 10 V Input Current Into Any Pin 5 mA Storage Temperature –65 to +150 °C Junction Temperature +150 °C Human Body Model (HBM) 2000 V Charged Device Model (CDM) 500 V Current-Shunt Monitor Analog Inputs, VIN+and VIN– ESD Ratings (1) 2 Stresses above these ratings may cause permanent damage. Exposure to absolute maximum conditions for extended periods may degrade device reliability. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those specified is not supported. Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s): INA203-Q1 INA203-Q1 www.ti.com SBOS539 – DECEMBER 2010 ELECTRICAL CHARACTERISTICS: CURRENT-SHUNT MONITOR Boldface limits apply over the specified temperature range: TA = –40°C to +125°C. At TA = +25°C, VS = +12V, VCM = +12V, VSENSE = 100mV, RL = 10kΩ to GND, RPULL-UP = 5.1kΩ each connected from CMP1 OUT and CMP2 OUT to VS, and CMP1 IN+ = 1V and CMP2 IN– = GND, unless otherwise noted. CURRENT-SHUNT MONITOR PARAMETERS CONDITIONS MIN TYP MAX UNIT 0.15 (VS – 0.25)/Gain V INPUT Full-Scale Sense Input Voltage Common-Mode Input Range Common-Mode Rejection Ratio VSENSE VSENSE = VIN+ – VIN– VCM CMRR +25°C to +125°C –16 V VCM = –16V to +80V 80 100 dB VCM = +12V to +80V 100 123 dB 90 100 –40°C to +25°C Offset Voltage, RTI (1) 80 mV +25°C to +125°C ±3 mV –40°C to +25°C ±3.5 vs Power Supply Input Bias Current, VIN– Pin dVOS/dT PSR ±0.5 dB ±2.5 vs Temperature VOS mV TMIN to TMAX 5 VOUT = 2V, VCM = +18V 2.5 100 mV/V ±9 ±16 mA IB mV/°C OUTPUT (VSENSE ≥ 20mV) Gain G Gain Error Over Temperature ±0.2 VSENSE = 20mV to 100mV Total Output Error (2) VSENSE = 120mV, VS = +16V Over Temperature ±0.75 VSENSE = 120mV, VS = +16V Nonlinearity Error (3) Output Impedance, Pin 2 20 VSENSE = 20mV to 100mV VSENSE = 20mV to 100mV RO Maximum Capacitive Load OUTPUT (VSENSE < 20mV) (4) V/V ±1 % ±2 % ±2.2 % ±3.5 % ±0.002 % 1.5 Ω No Sustained Oscillation 10 nF –16V ≤ VCM < 0V 300 mV 0V ≤ VCM ≤ VS, VS = 5V VS < VCM ≤ 80V 0.4 300 V mV VOLTAGE OUTPUT (5) Output Swing to the Positive Rail VIN– = 11V, VIN+ = 12V (V+) – 0.15 (V+) – 0.25 V Output Swing to GND (6) VIN– = 0V, VIN+ = –0.5V (VGND) + 0.004 (VGND) + 0.05 V CLOAD = 5pF 500 kHz CLOAD < 10nF 40 Degrees 1 V/ms 2 ms 40 nV/√Hz FREQUENCY RESPONSE Bandwidth BW Phase Margin Slew Rate SR Settling Time (1%) VSENSE = 10mVPP to 100mVPP, CLOAD = 5pF NOISE, RTI Output Voltage Noise Density (1) (2) (3) (4) (5) (6) Offset is extrapolated from measurements of the output at 20mV and 100mV VSENSE. Total output error includes effects of gain error and VOS. Linearity is best fit to a straight line. For details on this region of operation, see the Accuracy Variations section in the Applications Information. See Typical Characteristic curve Positive Output Voltage Swing vs Output Current (Figure 8). Specified by design; not production tested. Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s): INA203-Q1 3 INA203-Q1 SBOS539 – DECEMBER 2010 www.ti.com ELECTRICAL CHARACTERISTICS: COMPARATOR Boldface limits apply over the specified temperature range: TA = –40°C to +125°C. At TA = +25°C, VS = +12V, VCM = +12V, VSENSE = 100mV, RL = 10kΩ to GND, and RPULL-UP = 5.1kΩ each connected from CMP1 OUT and CMP2 OUT to VS, unless otherwise noted. COMPARATOR PARAMETERS CONDITIONS MIN TYP MAX UNIT OFFSET VOLTAGE Offset Voltage Comparator Common-Mode Voltage = Threshold Voltage Offset Voltage Drift, Comparator 1 Offset Voltage Drift, Comparator 2 2 mV ±2 mV/°C +5.4 Threshold Rising Edge on Non-Inverting input, TA = +25°C Over Temperature 590 608 586 mV/°C 620 mV 625 mV Hysteresis (1), CMP1 TA = –40°C to +85°C –8 mV Hysteresis (1), CMP2 TA = –40°C to +85°C 8 mV INPUT BIAS CURRENT (2) CMP1 IN+, CMP2 IN+ 0.005 vs Temperature 10 nA 15 nA INPUT IMPEDANCE Pins 3 and 6 (14-pin packages only) 10 kΩ CMP1 IN+ and CMP2 IN+ 0V to VS – 1.5V V Pins 3 and 6 (14-pin packages only) (3) 0V to VS – 1.5V V INPUT RANGE OUTPUT CMP VOUT 1V to 4V, RL ≥ 15kΩ Connected to 5V 200 High-Level Output Current VID = 0.4V, VOH = VS 0.0001 1 mA Low-Level Output Voltage VID = –0.6V, IOL = 2.35mA 220 300 mV Comparator 1 RL to 5V, CL = 15pF, 100mV Input Step with 5mV Overdrive 1.3 ms Comparator 2 RL to 5V, CL = 15pF, 100mV Input Step with 5mV Overdrive, CDELAY Pin Open 1.3 ms Large-Signal Differential Voltage Gain V/mV RESPONSE TIME (4) RESET RESET Threshold (5) Logic Input Impedance Minimum RESET Pulse Width RESET Propagation Delay Comparator 2 Delay Equation (6) Comparator 2 Delay (1) (2) (3) (4) (5) (6) 4 tD CDELAY = 0.1mF 1.1 V 2 MΩ 1.5 ms 3 ms CDELAY = tD/5 mF 0.5 s Hysteresis refers to the threshold (the threshold specification applies to a rising edge of a noninverting input) of a falling edge on the noninverting input of the comparator; refer to Figure 1. Specified by design; not production tested. See the Comparator Maximum Input Voltage Range section in the Applications Information. The comparator response time specified is the interval between the input step function and the instant when the output crosses 1.4V. The CMP1 RESET input has an internal 2MΩ (typical) pull-down. Leaving the CMP1 RESET open results in a LOW state, with transparent comparator operation. The Comparator 2 delay applies to both rising and falling edges of the comparator output. Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s): INA203-Q1 INA203-Q1 www.ti.com SBOS539 – DECEMBER 2010 VTHRESHOLD 0.592 VTHRESHOLD 0.6 0.6 0.608 Input Voltage Input Voltage Hysteresis = VTHRESHOLD - 8mV Hysteresis = VTHRESHOLD - 8mV a) CMP1 b) CMP2 Figure 1. Comparator Hysteresis Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s): INA203-Q1 5 INA203-Q1 SBOS539 – DECEMBER 2010 www.ti.com ELECTRICAL CHARACTERISTICS: REFERENCE Boldface limits apply over the specified temperature range: TA = –40°C to +125°C. At TA = +25°C, VS = +12V, VCM = +12V, VSENSE = 100mV, RL = 10kΩ to GND, and RPULL-UP = 5.1kΩ each connected from CMP1 OUT and CMP2 OUT to VS, unless otherwise noted. REFERENCE PARAMETERS CONDITIONS MIN TYP MAX UNIT 1.188 1.2 1.212 V 40 100 ppm/°C 40 100 ppm/°C 0mA < ISOURCE < 0.5mA 0.4 2 mV/mA 0mA < ISINK < 0.5mA 0.4 REFERENCE VOLTAGE 1.2VREFOUT Output Voltage Reference Drift (1) dVOUT/dT TA = –40°C to +85°C 0.6VREF Output Voltage (Pins 3 and 6 of 14-pin packages only) Reference Drift (1) 0.6 dVOUT/dT LOAD REGULATION TA = –40°C to +85°C dVOUT/dILOAD VREFOUT – 1.2V Sourcing Sinking LOAD CURRENT ILOAD LINE REGULATION V mV/mA 1 mA 2.7V < VS < 18V 30 mV/V No Sustained Oscillations 10 nF 10 kΩ dVOUT/dVS CAPACITIVE LOAD Reference Output Maximum Capacitive Load OUTPUT IMPEDANCE Pins 3 and 6 of 14-Pin Packages Only (1) Specified by design; not production tested. ELECTRICAL CHARACTERISTICS: GENERAL Boldface limits apply over the specified temperature range: TA = –40°C to +125°C. All specifications at TA = +25°C, VS = +12V, VCM = +12V, VSENSE = 100mV, RL = 10kΩ to GND, RPULL-UP = 5.1kΩ each connected from CMP1 OUT and CMP2 OUT to VS, and CMP1 IN+ = 1V and CMP2 IN– = GND, unless otherwise noted. GENERAL PARAMETERS CONDITIONS MIN TYP MAX UNIT +18 V POWER SUPPLY Operating Power Supply Quiescent Current VS IQ Over Temperature +2.7 VOUT = 2V 1.8 VSENSE = 0mV Comparator Power-On Reset Threshold (1) 2.2 mA 2.8 mA 1.5 V TEMPERATURE Specified Temperature Range –40 +125 °C Operating Temperature Range –55 +150 °C Storage Temperature Range –65 +150 °C Thermal Resistance (1) 6 qJA MSOP-10 Surface-Mount 200 °C/W SO-14, TSSOP-14 Surface-Mount 150 °C/W The INA203, INA204, and INA205 are designed to power-up with the comparator in a defined reset state as long as CMP1 RESET is open or grounded. The comparator will be in reset as long as the power supply is below the voltage shown here. The comparator assumes a state based on the comparator input above this supply voltage. If CMP1 RESET is high at power-up, the comparator output comes up high and requires a reset to assume a low state, if appropriate. Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s): INA203-Q1 INA203-Q1 www.ti.com SBOS539 – DECEMBER 2010 TYPICAL CHARACTERISTICS All specifications at TA = +25°C, VS = +12V, VCM = +12V, and VSENSE = 100mV, unless otherwise noted. GAIN vs FREQUENCY 45 G = 20 25 20 30 20 15 10 10 5 5 100k G = 20 25 15 10k CLOAD = 0 10k 1M 100k Frequency (Hz) Figure 2. Figure 3. GAIN PLOT COMMON-MODE AND POWER-SUPPLY REJECTION vs FREQUENCY 140 18 130 Common-Mode and Power-Supply Rejection (dB) 100V/V 16 14 50V/V 12 10 8 20V/V 6 4 120 CMR 110 100 90 PSR 80 70 60 50 2 40 0 20 100 200 300 400 500 600 700 800 900 10 100 1k VSENSE (mV) 10k 100k Frequency (Hz) Figure 4. Figure 5. TOTAL OUTPUT ERROR vs VSENSE TOTAL OUTPUT ERROR vs COMMON-MODE VOLTAGE 4.0 0.1 3.5 0.09 3.0 Total Output Error (%) Total Output Error (% error of the ideal output value) 1M Frequency (Hz) 20 VOUT (V) G = 50 35 Gain (dB) 30 G = 100 40 G = 50 35 Gain (dB) CLOAD = 1000pF G = 100 40 GAIN vs FREQUENCY 45 2.5 2.0 1.5 1.0 0.08 0.07 0.06 0.05 0.04 0.03 0.02 0.5 0.01 0 0 50 100 150 200 250 300 350 400 450 500 0 -16 -12 -8 -4 VSENSE (mV) 0 4 8 12 16 20 ... 76 80 Common-Mode Voltage (V) Figure 6. Figure 7. Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s): INA203-Q1 7 INA203-Q1 SBOS539 – DECEMBER 2010 www.ti.com TYPICAL CHARACTERISTICS (continued) All specifications at TA = +25°C, VS = +12V, VCM = +12V, and VSENSE = 100mV, unless otherwise noted. POSITIVE OUTPUT VOLTAGE SWING vs OUTPUT CURRENT QUIESCENT CURRENT vs OUTPUT VOLTAGE 3.5 12 11 VS = 12V 10 9 6 VS = 3V 5 Sourcing Current +25°C 4 3 -40°C Output stage is designed to source current. Current sinking capability is approximately 400mA. 2 1 +125°C 0 0 2.0 1.5 1.0 0.5 0 5 10 20 15 25 30 0 1 2 3 4 5 8 9 10 9.5 10.5 11.5 17 18 Output Voltage (V) Figure 8. Figure 9. QUIESCENT CURRENT vs COMMON-MODE VOLTAGE OUTPUT SHORT-CIRCUIT CURRENT vs SUPPLY VOLTAGE 34 VSENSE = 100mV VS = 2.7V VS = 12V 1.50 1.25 VS = 12V 1.00 VS = 2.7V VSENSE = 0mV 0.75 0.50 -16 -12 -8 -4 -40°C 30 +25°C 26 +125°C 22 18 14 10 6 0 4 8 12 16 20 24 28 32 36 2.5 3.5 4.5 5.5 6.5 7.5 8.5 VCM (V) Supply Voltage (V) Figure 10. Figure 11. STEP RESPONSE STEP RESPONSE G = 20 G = 20 Output Voltage (500mV/div) Output Voltage (50mV/div) VSENSE = 10mV to 20mV 8 7 6 Output Current (mA) 1.75 IQ (mA) IQ (mA) -40°C +125°C 7 2.00 2.5 +25°C 8 Output Short-Circuit Current (mA) Output Voltage (V) 3.0 Sourcing Current VSENSE = 10mV to 100mV Time (2ms/div) Time (2ms/div) Figure 12. Figure 13. Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s): INA203-Q1 INA203-Q1 www.ti.com SBOS539 – DECEMBER 2010 TYPICAL CHARACTERISTICS (continued) All specifications at TA = +25°C, VS = +12V, VCM = +12V, and VSENSE = 100mV, unless otherwise noted. STEP RESPONSE STEP RESPONSE G = 50 Output Voltage (50mV/div) Output Voltage (100mV/div) G = 20 VSENSE = 90mV to 100mV VSENSE = 10mV to 20mV Time (2ms/div) Time (5ms/div) Figure 14. Figure 15. STEP RESPONSE STEP RESPONSE G = 50 Output Voltage (1V/div) Output Voltage (100mV/div) G = 50 VSENSE = 90mV to 100mV VSENSE = 10mV to 100mV Time (5ms/div) Time (5ms/div) Figure 16. Figure 17. STEP RESPONSE COMPARATOR VOL vs ISINK 600 G = 100 Output Voltage (2V/div) 500 VOL (mV) 400 300 200 100 VSENSE = 10mV to 100mV 0 Time (10ms/div) 0 1 2 3 4 5 6 ISINK (mA) Figure 18. Figure 19. Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s): INA203-Q1 9 INA203-Q1 SBOS539 – DECEMBER 2010 www.ti.com TYPICAL CHARACTERISTICS (continued) All specifications at TA = +25°C, VS = +12V, VCM = +12V, and VSENSE = 100mV, unless otherwise noted. COMPARATOR TRIP POINT vs SUPPLY VOLTAGE COMPARATOR TRIP POINT vs TEMPERATURE 600 602 Comparator Trip Point (mV) Comparator Trip Point (mV) 599 598 597 596 595 594 593 592 601 600 599 598 597 591 596 590 2 4 6 8 10 12 14 16 18 -25 -50 0 25 50 75 100 Supply Voltage (V) Temperature (°C) Figure 20. Figure 21. COMPARATOR 1 PROPAGATION DELAY vs OVERDRIVE VOLTAGE COMPARATOR 2 PROPAGATION DELAY vs OVERDRIVE VOLTAGE 200 125 14 Propagation Delay (ms) Propagation Delay (ns) 175 150 125 100 13 12 11 75 50 10 20 40 60 80 100 120 140 160 180 20 40 60 80 100 120 140 160 180 Overdrive Voltage (mV) Overdrive Voltage (mV) Figure 22. Figure 23. COMPARATOR RESET VOLTAGE vs SUPPLY VOLTAGE COMPARATOR 1 PROPAGATION DELAY vs TEMPERATURE 1.2 300 1.0 275 0.8 0.6 0.4 0.2 200 250 225 200 175 150 0 2 10 0 200 Propagation Delay (ns) Reset Voltage (V) 0 4 6 8 10 12 14 16 18 125 -50 -25 0 25 50 Supply Voltage (V) Temperature (°C) Figure 24. Figure 25. Submit Documentation Feedback 75 100 125 Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s): INA203-Q1 INA203-Q1 www.ti.com SBOS539 – DECEMBER 2010 TYPICAL CHARACTERISTICS (continued) All specifications at TA = +25°C, VS = +12V, VCM = +12V, and VSENSE = 100mV, unless otherwise noted. COMPARATOR 2 PROPAGATION DELAY vs CAPACITANCE COMPARATOR 1 PROPAGATION DELAY Propagation Delay (ms) 1000 100 Input 200mV/div 10 1 Output 2V/div 0.1 VOD = 5mV 0.01 0.001 0.01 0.1 1 10 2ms/div 100 Delay Capacitance (nF) Figure 26. Figure 27. COMPARATOR 2 PROPAGATION DELAY REFERENCE VOLTAGE vs TEMPERATURE 1.22 Input 200mV/div VREF (V) 1.21 Output 2V/div 1.20 1.19 VOD = 5mV 5ms/div 1.18 -50 -25 0 25 50 75 100 125 Temperature (°C) Figure 28. Figure 29. Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s): INA203-Q1 11 INA203-Q1 SBOS539 – DECEMBER 2010 www.ti.com APPLICATIONS INFORMATION BASIC CONNECTIONS Power-supply bypass capacitors are required for stability. Applications with noisy or high-impedance power supplies may require additional decoupling capacitors to reject power-supply noise. Connect bypass capacitors close to the device pins. This section addresses the accuracy of these specific operating regions: • Normal Case 1: VSENSE ≥ 20mV, VCM ≥ VS • Normal Case 2: VSENSE ≥ 20mV, VCM < VS • Low VSENSE Case 1: VSENSE < 20mV, –16V ≤ VCM <0 • Low VSENSE Case 2: VSENSE < 20mV, 0V ≤ VCM ≤ VS • Low VSENSE Case 3: VSENSE < 20mV, VS < VCM ≤ 80V POWER SUPPLY Normal Case 1: VSENSE ≥ 20mV, VCM ≥ VS The input circuitry of the INA203-Q1 can accurately measure beyond the power-supply voltage, V+. For example, the V+ power supply can be 5V, whereas the load power-supply voltage is up to +80V. The output voltage range of the OUT terminal, however, is limited by the voltages on the power-supply pin. This region of operation provides the highest accuracy. Here, the input offset voltage is characterized and measured using a two-step method. First, the gain is determined by Equation 1. VOUT1 - VOUT2 G= 100mV - 20mV (1) ACCURACY VARIATIONS AS A RESULT OF VSENSE AND COMMON-MODE VOLTAGE where: Figure 30 shows the basic connections of the INA203-Q1. The input pins, VIN+ and VIN–, should be connected as closely as possible to the shunt resistor to minimize any resistance in series with the shunt resistance. VOUT1 = Output Voltage with VSENSE = 100mV The accuracy of the INA203-Q1 current shunt monitors is a function of two main variables: VSENSE (VIN+ – VIN–) and common-mode voltage, VCM, relative to the supply voltage, VS. VCM is expressed as (VIN+ + VIN–)/2; however, in practice, VCM is seen as the voltage at VIN+ because the voltage drop across VSENSE is usually small. VOUT2 = Output Voltage with VSENSE = 20mV Then the offset voltage is measured at VSENSE = 100mV and referred to the input (RTI) of the current shunt monitor, as shown in Equation 2. VOUT1 VOSRTI (Referred-To-Input) = - 100mV G (2) RSHUNT 3mW Load Supply -18V to +80V Load 5V Supply VS Current Shunt Monitor Output CBYPASS 0.01mF INA203 x20 OUT CMP1 IN-/0.6 REF CMP1 IN+ 1.2V REF VIN+ VIN- RPULL-UP 4.7kW RPULL-UP 4.7kW 1.2V REF OUT CMP1 OUT CMP2 IN+ CMP2 IN-/0.6 REF CMP2 OUT CMP2 DELAY GND CMP1 RESET Optional Delay Capacitor 0.2mF Transparent/Reset Latch Figure 30. INA20x Basic Connection 12 Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s): INA203-Q1 INA203-Q1 www.ti.com SBOS539 – DECEMBER 2010 In the Typical Characteristics, the Output Error vs Common-Mode Voltage curve (Figure 7) shows the highest accuracy for this region of operation. In this plot, VS = 12V; for VCM ≥ 12V, the output error is at its minimum. This case is also used to create the VSENSE ≥ 20mV output specifications in the Electrical Characteristics table. Normal Case 2: VSENSE ≥ 20mV, VCM < VS This region of operation has slightly less accuracy than Normal Case 1 as a result of the common-mode operating area in which the part functions, as seen in the Output Error vs Common-Mode Voltage curve (Figure 7). As noted, for this graph VS = 12V; for VCM < 12V, the Output Error increases as VCM becomes less than 12V, with a typical maximum error of 0.005% at the most negative VCM = –16V. Low VSENSE Case 1: VSENSE < 20mV, –16V ≤ VCM < 0; and Low VSENSE Case 3: VSENSE < 20mV, VS < VCM ≤ 80V Low VSENSE Case 2: VSENSE < 20mV, 0V ≤ VCM ≤ VS This region of operation is the least accurate for the INA203-Q1. To achieve the wide input common-mode voltage range, these devices use two op amp front ends in parallel. One op amp front end operates in the positive input common-mode voltage range, and the other in the negative input region. For this case, neither of these two internal amplifiers dominates and overall loop gain is very low. Within this region, VOUT approaches voltages close to linear operation levels for Normal Case 2. This deviation from linear operation becomes greatest the closer VSENSE approaches 0V. Within this region, as VSENSE approaches 20mV, device operation is closer to that described by Normal Case 2. Figure 32 illustrates this behavior. The VOUT maximum peak for this case is tested by maintaining a constant VS, setting VSENSE = 0mV, and sweeping VCM from 0V to VS. The exact VCM at which VOUT peaks during this test varies from part to part, but the VOUT maximum peak is tested to be less than the specified VOUT Tested Limit. 2.4 (1) As VSENSE approaches 0mV, in these VCM regions, the device output accuracy degrades. A larger-than-normal offset can appear at the current shunt monitor output with a typical maximum value of VOUT = 300mV for VSENSE = 0mV. As VSENSE approaches 20mV, VOUT returns to the expected output value with accuracy as specified in the Electrical Characteristics. Figure 31 illustrates this effect (Gain = 100). 2.0 VOUT Tested Limit 2.2 VCM1 2.0 Ideal 1.8 VCM2 1.6 VOUT (V) Although the INA203-Q1 is not designed for accurate operation in either of these regions, some applications are exposed to these conditions; for example, when monitoring power supplies that are switched on and off while VS is still applied to the INA203-Q1. It is important to know what the behavior of the devices will be in these regions. 1.4 VCM3 1.2 1.0 0.8 VOUT Tested Limit at VSENSE = 0mV, 0 £ VCM1 £ VS. VCM4 0.6 VCM2, VCM3, and VCM4 illustrate the variance from part to part of the VCM that can cause maximum VOUT with VSENSE < 20mV. 0.4 0.2 0 0 2 4 6 8 10 12 14 16 18 20 22 24 VSENSE (mV) NOTE: (1) INA203-Q1 VOUT Tested Limit = 0.4V. Figure 32. Example for Low VSENSE Case 2 (Gain = 100) 1.8 SELECTING RSHUNT 1.6 VOUT (V) 1.4 1.2 Actual 1.0 0.8 Ideal 0.6 0.4 0.2 0 0 2 4 6 8 10 12 14 16 18 20 VSENSE (mV) Figure 31. Example for Low VSENSE Cases 1 and 3 (Gain = 100) The value chosen for the shunt resistor, RSHUNT, depends on the application and is a compromise between small-signal accuracy and maximum permissible voltage loss in the measurement line. High values of RSHUNT provide better accuracy at lower currents by minimizing the effects of offset, while low values of RSHUNT minimize voltage loss in the supply line. For most applications, best performance is attained with an RSHUNT value that provides a full-scale shunt voltage range of 50mV to 100mV. Maximum input voltage for accurate measurements is (VSHUNT – 0.25)/Gain. Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s): INA203-Q1 13 INA203-Q1 SBOS539 – DECEMBER 2010 www.ti.com TRANSIENT PROTECTION OUTPUT VOLTAGE RANGE The –16V to +80V common-mode range of the INA203-Q1 is ideal for withstanding automotive fault conditions ranging from 12V battery reversal up to +80V transients, since no additional protective components are needed up to those levels. In the event that the INA203-Q1 is exposed to transients on the inputs in excess of their ratings, then external transient absorption with semiconductor transient absorbers (zeners or Transzorbs) are necessary. Use of metal oxide varistors (MOVs) or video disk recorders (VDRs) is not recommended except when they are used in addition to a semiconductor transient absorber. Select the transient absorber such that it will never allow the INA203-Q1 to be exposed to transients greater than +80V (that is, allow for transient absorber tolerance, as well as additional voltage because of transient absorber dynamic impedance). Despite the use of internal zener-type ESD protection, the INA203-Q1 does not lend itself to using external resistors in series with the inputs because the internal gain resistors can vary up to ±30% but are closely matched. (If gain accuracy is not important, then resistors can be added in series with the INA203-Q1 inputs with two equal resistors on each input.) The output of the INA203-Q1 is accurate within the output voltage swing range set by the power-supply pin, V+. This performance is best illustrated when using a gain of 100 , where a 100mV full-scale input from the shunt resistor requires an output voltage swing of +10V, and a power-supply voltage sufficient to achieve +10V on the output. INPUT FILTERING An obvious and straightforward location for filtering is at the output of the INA203-Q1 series; however, this location negates the advantage of the low output impedance of the internal buffer. The only other option for filtering is at the input pins of the INA203-Q1, which is complicated by the internal 5kΩ + 30% input impedance; this configuration is illustrated in Figure 33. Using the lowest possible resistor values minimizes both the initial shift in gain and effects of tolerance. The effect on initial gain is given by Equation 3: 5kW 5kW + RFILT Gain Error % = 100 - 100 ´ (3) Total effect on gain error can be calculated by replacing the 5kΩ term with 5kΩ – 30%, (or 3.5kΩ) or 5kΩ + 30% (or 6.5kΩ). The tolerance extremes of RFILT can also be inserted into the equation. If a pair of 100Ω 1% resistors are used on the inputs, the initial gain error will be 1.96%. Worst-case tolerance conditions will always occur at the lower excursion of the internal 5kΩ resistor (3.5kΩ), and the higher excursion of RFILT – 3% in this case. RSHUNT << RFILTER 3mW VSUPPLY Load RFILTER < 100W RFILTER <100W CFILTER VIN+ VS 1 14 OUT 2 13 CMP1 IN-/0.6V REF 3 12 1.2V REF OUT CMP1 IN+ 4 11 CMP1 OUT CMP2 IN+ 5 10 CMP2 OUT CMP2 IN-/0.6V REF 6 9 CMP2 DELAY GND 7 8 CMP1 RESET VIN1.2V REF f-3dB f-3dB = 1 2p(2RFILTER)CFILTER Figure 33. Input Filter (Gain Error: 1.5% to –2.2%) 14 Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s): INA203-Q1 INA203-Q1 www.ti.com SBOS539 – DECEMBER 2010 Note that the specified accuracy of the INA203-Q1 must then be combined in addition to these tolerances. While this discussion treated accuracy worst-case conditions by combining the extremes of the resistor values, it is appropriate to use geometric mean or root sum square calculations to total the effects of accuracy variations. additional features for comparator functions. The comparator reference voltage of both Comparator 1 and Comparator 2 can be overridden by external inputs for increased design flexibility. Comparator 2 has a programmable delay. REFERENCE The Comparator 2 programmable delay is controlled by a capacitor connected to the CMP2 Delay Pin; see Figure 30. The capacitor value (in mF) is selected by using Equation 4: t CDELAY (in mF) = D 5 (4) The INA203-Q1 include an internal voltage reference that has a load regulation of 0.4mV/mA (typical), and not more than 100ppm/°C of drift. Only the 14-pin package allows external access to reference voltages, where voltages of 1.2V and 0.6V are both available. Output current versus output voltage is illustrated in the Typical Characteristics section. COMPARATOR The INA203-Q1 incorporates two open-drain comparators. These comparators typically have 2mV of offset and a 1.3ms (typical) response time. The output of Comparator 1 latches and is reset through the CMP1 RESET pin, as shown in Figure 35. This configuration applies to both the 10- and 14-pin versions. Figure 34 illustrates the comparator delay. The 14-pin versions of the INA203-Q1 include COMPARATOR DELAY (14-Pin Version Only) A simplified version of the delay circuit for Comparator 2 is shown in Figure 34. The delay comparator consists of two comparator stages with the delay between them. Note that I1 and I2 cannot be turned on simultaneously; I1 corresponds to a U1 low output and I2 corresponds to a U1 high output. Using an initial assumption that the U1 output is low, I1 is on, then U2 +IN is zero. If U1 goes high, I2 supplies 120nA to CDELAY. The voltage at U2 +IN begins to ramp toward a 0.6V threshold. When the voltage crosses this threshold, the U2 output goes high while the voltage at U2 +IN continues to ramp up to a maximum of 1.2V when given sufficient time (twice the value of the delay specified for CDELAY). This entire sequence is reversed when the comparator outputs go low, so that returning to low exhibits the same delay. 1.2V I2 120nA U1 U2 I1 120nA 0.6V CDELAY Figure 34. Simplified Model of the Comparator 2 Delay Circuit Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s): INA203-Q1 15 INA203-Q1 SBOS539 – DECEMBER 2010 www.ti.com 0.6V VIN 0V CMP Out RESET Figure 35. Comparator Latching Capability It is important to note what will happen if events occur more rapidly than the delay timeout; for example, when the U1 output goes high (turning on I2), but returns low (turning I1 back on) prior to reaching the 0.6V transition for U2. The voltage at U2 +IN ramps back down at a rate determined by the value of CDELAY, and only returns to zero if given sufficient time. whether either or both inputs are subject to the large voltage. When making this determination, consider the 20kΩ from each input back to the comparator. Figure 37 shows the maximum input voltage that avoids creating a reference error when driving both inputs (an equivalent resistance back into the reference of 10kΩ). £ 1mA In essence, when analyzing Comparator 2 for behavior with events more rapid than its delay setting, use the model shown in Figure 34. 1.2V 20kW 20kW CMP1 IN- COMPARATOR MAXIMUM INPUT VOLTAGE RANGE CMP2 IN+ The maximum voltage at the comparator input for normal operation is up to (V+) – 1.5V. There are special considerations when overdriving the reference inputs (pins 3 and 6). Driving either or both inputs high enough to drive 1mA back into the reference introduces errors into the reference. Figure 36 shows the basic input structure. A general guideline is to limit the voltage on both inputs to a total of 20V. The exact limit depends on the available voltage and Figure 36. Limit Current Into Reference ≤ 1mA RSHUNT 3mW Load Supply -18V to +80V Load 5V Supply VS Current Shunt Monitor Output CMP1 IN-/0.6 REF V < 11.2 INA203-Q1 x20 OUT CBYPASS 0.01mF 1.2V REF VIN+ VIN- RPULL-UP 4.7kW RPULL-UP 4.7kW 1.2V REF OUT CMP1 IN+ CMP1 OUT CMP2 IN+ CMP2 IN- CMP2 OUT CMP2 DELAY GND CMP1 RESET Optional Delay Capacitor 0.2mF Transparent/Reset Latch Figure 37. Overdriving Comparator Inputs Without Generating a Reference Error 16 Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s): INA203-Q1 INA203-Q1 www.ti.com SBOS539 – DECEMBER 2010 Raychem Polyswitch Load < 18V Battery +5V Supply VS+ VIN- x20 OUT 1.2V REF CMP1 IN- 3.3kW Pull-Up Resistors VIN+ INA203-Q1 1.2V REF OUT CMP1 IN+ CMP1 OUT CMP2 IN+ CMP2 IN- CMP2 OUT CMP2 DELAY GND CMP1 RESET CBYPASS 0.01mF Overlimit (1) (1) Warning Reset Latch Optional CDELAY 0.01mF NOTE: (1) Warning at half current (with optional delay). Overlimit latches when Polyswitch opens. Figure 38. Polyswitch Warning and Fault Detection Circuit RSHUNT 0.02W Load Q2 NDS8434A R1 100kW +5V Supply R7 1kW Q1 2N3904 VS+ INA203-Q1 x20 OUT R5 100kW R6 6.04kW CMP1 IN- R3 14kW R4 6.04kW 1.2V REF VIN+ VIN- CMP1 IN+ CMP1 OUT CMP2 IN+ CMP2 IN- CMP2 OUT CMP2 DELAY GND CMP1 RESET CBYPASS 0.01mF R2 1kW 1.2V REF OUT Reset Latch Figure 39. Lead-Acid Battery Protection Circuit Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s): INA203-Q1 17 PACKAGE OPTION ADDENDUM www.ti.com 10-Jan-2011 PACKAGING INFORMATION Orderable Device INA203AQPWRQ1 Status (1) Package Type Package Drawing ACTIVE TSSOP PW Pins Package Qty 14 2000 Eco Plan (2) Green (RoHS & no Sb/Br) Lead/ Ball Finish MSL Peak Temp (3) CU NIPDAU Level-2-260C-1 YEAR Samples (Requires Login) Purchase Samples (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. 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OTHER QUALIFIED VERSIONS OF INA203-Q1 : • Catalog: INA203 NOTE: Qualified Version Definitions: • Catalog - TI's standard catalog product Addendum-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 TAPE AND REEL INFORMATION *All dimensions are nominal Device INA203AQPWRQ1 Package Package Pins Type Drawing TSSOP PW 14 SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) 2000 330.0 12.4 Pack Materials-Page 1 6.9 B0 (mm) K0 (mm) P1 (mm) 5.6 1.6 8.0 W Pin1 (mm) Quadrant 12.0 Q1 PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) INA203AQPWRQ1 TSSOP PW 14 2000 367.0 367.0 35.0 Pack Materials-Page 2 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46C and to discontinue any product or service per JESD48B. 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