TI SN74ALVC16270DL

SCAS433A − OCTOBER 1993 − REVISED JULY 1995
D EPIC  (Enhanced-Performance Implanted
D
D
D
D
D
DGG OR DL PACKAGE
(TOP VIEW)
CMOS) Submicron Process
Member of the Texas Instruments
Widebus  Family
ESD Protection Exceeds 2000 V Per
MIL-STD-883C, Method 3015; Exceeds
200 V Using Machine Model
(C = 200 pF, R = 0)
Latch-Up Performance Exceeds 250 mA
Per JEDEC Standard JESD-17
Bus Hold on Data Inputs Eliminates
the Need for External Pullup/Pulldown
Resistors
Package Options Include Plastic Shrink
Small-Outline (DL) and Thin Shrink
Small-Outline (DGG) Packages
OEA
CLKEN1B
2B3
GND
2B2
2B1
VCC
A1
A2
A3
GND
A4
A5
A6
A7
A8
A9
GND
A10
A11
A12
VCC
1B1
1B2
GND
1B3
CLKEN2B
SEL
description
The SN74ALVC16270 is a 12-bit to 24-bit
registered bus exchanger, which is intended for
use in applications where data must be
transferred from a narrow high-speed bus to a
wide lower-frequency bus. This device is
designed specifically for low-voltage (3.3-V) VCC
operation.
1
56
2
55
3
54
4
53
5
52
6
51
7
50
8
49
9
48
10
47
11
46
12
45
13
44
14
43
15
42
16
41
17
40
18
39
19
38
20
37
21
36
22
35
23
34
24
33
OEB
CLKENA2
2B4
GND
2B5
2B6
VCC
2B7
2B8
2B9
GND
2B10
2B11
2B12
1B12
1B11
1B10
GND
1B9
1B8
1B7
VCC
1B6
1B5
GND
1B4
CLKENA1
CLK
The device provides synchronous data exchange
25
32
between the two ports. Data is stored in the
26
31
internal registers on the low-to-high transition of
27
30
the clock (CLK) input when the appropriate
28
29
CLKEN inputs are low. The select (SEL) line
selects 1B or 2B data for the A outputs. For data
transfer in the A-to-B direction, a two-stage
pipeline is provided in the A-to-1B path,
with a single storage register in the A to 2B path. Proper control of the CLKENA inputs allows two sequential
12-bit words to be presented synchronously as a 24-bit word on the B port. Data flow is controlled by the
active-low output enables (OEA, OEB). The control terminals are registered to synchronize the bus direction
changes with CLK.
Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level.
The SN74ALVC16270 is available in TI’s shrink small-outline (DL) and thin shrink small-outline (DGG)
packages, which provide twice the I/O pin count and functionality of standard small-outline packages in the
same printed-circuit-board area.
The SN74ALVC16270 is characterized for operation from − 40°C to 85°C.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
EPIC and Widebus are trademarks of Texas Instruments Incorporated.
Copyright  1995, Texas Instruments Incorporated
!"#$ % &'!!($ #% )'*+&#$ ,#$(!,'&$% &!" $ %)(&&#$% )(! $.( $(!"% (/#% %$!'"($%
%$#,#!, 0#!!#$1- !,'&$ )!&(%%2 ,(% $ (&(%%#!+1 &+',(
$(%$2 #++ )#!#"($(!%-
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•
1
SCAS433A − OCTOBER 1993 − REVISED JULY 1995
Function Tables
OUTPUT ENABLE
OUTPUTS
INPUTS
CLK
OEA
OEB
A
1B, 2B
↑
H
H
Z
Z
↑
H
L
Z
Active
↑
L
H
Active
Z
↑
L
L
Active
Active
A-TO-B STORAGE (OEB = L)
INPUTS
OUTPUTS
CLKENA1
CLKENA2
CLK
L
H
↑
L
H
↑
L
L
L
L
A
L
1B
L†
2B
2B0‡
H
H†
2B0‡
↑
L
L†
L
↑
H
H†
H
1B0‡
1B0‡
H
H
L
↑
L
H
L
↑
H
L
H
H
X
X
1B0‡ 2B0‡
† Two CLK edges are needed to propagate data.
‡ Output level before the indicated steady-state input
conditions were established
B-TO-A STORAGE (OEA = L)
INPUTS
OUTPUT
A
CLKEN1B
CLKEN2B
CLK
SEL
1B
2B
H
X
X
H
X
X
X
H
X
L
X
X
L
X
↑
H
L
X
L
L
X
↑
H
H
X
H
X
L
↑
L
X
L
L
A0‡
A0‡
X
L
↑
L
X
H
H
‡ Output level before the indicated steady-state input conditions were
established
2
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•
SCAS433A − OCTOBER 1993 − REVISED JULY 1995
logic diagram (positive logic)
CLK
29
2
CLKEN1B
CLKEN2B
CLKENA1
CLKENA2
OEB
SEL
OEA
27
30
55
C1
56
1D
28
1
CE
1D
C1
1D
C1
G1
A1
1B1
CE
C1
1
8
23
1
1D
1D
6
2B1
CE
CE
C1
C1
1D
1D
CE
C1
1D
1 of 12 Channels
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3
SCAS433A − OCTOBER 1993 − REVISED JULY 1995
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 4.6 V
Input voltage range, VI: Except I/O ports (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to VCC + 0.5 V
I/O ports (see Notes 1 and 2) . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to VCC + 0.5 V
Output voltage range, VO (see Notes 1 and 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to VCC + 0.5 V
Input clamp current, IIK (VI < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −50 mA
Output clamp current, IOK (VO < 0 or VO > VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 50 mA
Continuous output current, IO (VO = 0 to VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 50 mA
Continuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 100 mA
Maximum power dissipation at TA = 55°C (in still air) (see Note 3): DGG package . . . . . . . . . . . . . . . . . . 1 W
DL package . . . . . . . . . . . . . . . . . . 1.4 W
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
2. The input and output positive-voltage ratings may be exceeded up to 4.6 V if the input and output clamp-current ratings are observed.
3. The maximum package power dissipation is calculated using a junction temperature of 150°C and a board trace length of 750 mils.
For more information, refer to the Package Thermal Considerations application note in the 1994 ABT Advanced BiCMOS Technology
Data Book, literature number SCBD002B.
recommended operating conditions (see Note 4)
MIN
MAX
2.3
3.6
VCC
Supply voltage
VIH
High-level input voltage
VCC = 2.3 V to 2.7 V
VCC = 2.7 V to 3.6 V
VIL
Low-level input voltage
VCC = 2.3 V to 2.7 V
VCC = 2.7 V to 3.6 V
VI
VO
Input voltage
0
Output voltage
0
IOH
High-level output current
IOL
Low-level output current
∆t /∆v
Input transition rise or fall rate
4
•
•
V
2
0.7
0.8
VCC
VCC
−12
VCC = 3 V
VCC = 2.3 V
−24
VCC = 2.7 V
VCC = 3 V
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V
1.7
VCC = 2.3 V
VCC = 2.7 V
TA
Operating free-air temperature
NOTE 4: Unused control inputs must be held high or low to prevent them from floating.
UNIT
−12
V
V
V
mA
12
mA
24
0
10
ns / V
−40
85
°C
SCAS433A − OCTOBER 1993 − REVISED JULY 1995
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
IOH = − 100 µA
IOH = − 6 mA,
VOH
VOL
2.3 V
VCC −0.2
2
2.3 V
1.7
IOH = − 12 mA
VIH = 2 V
VIH = 2 V
2.7 V
2.2
3V
2.4
IOH = − 24 mA,
IOL = 100 µA
VIH = 2 V
3V
2
MIN to MAX
0.2
IOL = 6 mA,
VIL = 0.7 V
VIL = 0.7 V
2.3 V
0.4
2.3 V
0.7
VIL = 0.8 V
VIL = 0.8 V
2.7 V
0.4
3V
0.55
IOL = 24 mA,
VI = VCC or GND
II(hold)
2.3 V
VI = 0.8 V
VI = 2 V
3V
±5
V
µA
45
−45
µA
75
VI = VCC or GND,
One input at VCC − 0.6 V,
Control inputs
UNIT
V
3.6 V
VI = 0.7 V
VI = 1.7 V
VI = 0 to 3.6 V
VO = VCC or GND
IOZ§
ICC
nICC
Ci
MIN to MAX
TA = − 40°C to 85°C
MIN TYP‡
MAX
VIH = 1.7 V
VIH = 1.7 V
IOL = 12 mA
II
VCC†
TEST CONDITIONS
IO = 0
Other inputs at VCC or GND
3.6 V
± 500
3.6 V
± 10
µA
3.6 V
40
µA
750
µA
3 V to 3.6 V
VI = VCC or GND
VO = VCC or GND
3.3 V
Cio
A or B ports
3.3 V
† For conditions shown as MIN or MAX, use the appropriate values under recommended operating conditions.
‡ All typical values are at VCC = 3.3 V.
§ For I/O ports, the parameter IOZ includes the input leakage current.
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•
−75
3.5
pF
9
pF
5
SCAS433A − OCTOBER 1993 − REVISED JULY 1995
timing requirements over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted)
VCC = 2.5 V
± 0.2 V
MIN
fclock
tw
tsu
th
MAX
Clock frequency
Hold
time
MIN
150
Pulse duration, CLK high or low
Setup
time
VCC = 2.7 V
MAX
VCC = 3.3 V
± 0.3 V
MIN
150
150
3.3
3.3
3.3
A data before CLK↑
High or low
4.1
3.8
3.1
B data before CLK↑
High or low
0.9
1.2
0.9
CLKENA1 or CLKENA2 before CLK↑
High or low
3.5
3.2
2.7
CLKEN1B or CLKEN2B before CLK↑
High or low
3.4
3
2.6
OE data before CLK↑
High or low
4.4
3.9
3.2
A data after CLK↑
High or low
0
0
0.2
B data after CLK↑
High or low
1.4
1
1.7
CLKENA1 or CLKENA2 after CLK↑
High or low
0
0.1
0.3
CLKEN1B or CLKEN2B after CLK↑
High or low
0
0
0.6
OE after CLK↑
High or low
0
0
0.1
UNIT
MAX
MHz
ns
ns
ns
switching characteristics over recommended operating free-air temperature range (unless
otherwise noted) (see Figures 1 and 2)
PARAMETER
tpd
ten
tdis
6
FROM
(INPUT)
TO
(OUTPUT)
CLK
VCC = 2.5 V
± 0.2 V
MIN
MAX
B
2
CLK
A
SEL
A
CLK
CLK
VCC = 2.7 V
UNIT
MAX
MIN
MAX
6.5
5.8
1.1
5.1
1.7
6
5.4
1
4.7
1.9
6.8
6.4
1
5.5
A or B
1.6
7.5
6.8
1
6
ns
A or B
2.6
7.4
6.5
1.1
5.8
ns
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•
MIN
VCC = 3.3 V
± 0.3 V
ns
SCAS433A − OCTOBER 1993 − REVISED JULY 1995
PARAMETER MEASUREMENT INFORMATION
VCC = 2.5 V " 0.2 V
4.6 V
S1
500 Ω
From Output
Under Test
Open
GND
CL = 50 pF
(see Note A)
TEST
S1
tpd
tPLZ/tPZL
tPHZ/tPZH
Open
4.6 V
GND
500 Ω
tw
LOAD CIRCUIT
2.3 V
Input
2.3 V
Timing
Input
VOLTAGE WAVEFORMS
PULSE DURATION
th
2.3 V
Data
Input
1.2 V
1.2 V
0V
tPHL
Output
Waveform 2
S1 at GND
(see Note B)
VOH
1.2 V
1.2 V
VOL
1.2 V
0V
tPLZ
2.3 V
Output
Waveform 1
S1 at 4.6 V
(see Note B)
1.2 V
tPLH
1.2 V
tPZL
2.3 V
1.2 V
2.3 V
Output
Control
(low-level
enabling)
0V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
Output
1.2 V
0V
0V
tsu
Input
1.2 V
1.2 V
1.2 V
tPZH
VOL + 0.3 V
VOL
tPHZ
VOH
1.2 V
VOH − 0.3 V
0V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR v 10 MHz, ZO = 50 Ω, tr v 2.5 ns, tf v 2.5 ns.
D. The outputs are measured one at a time with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. tPZL and tPZH are the same as ten.
G. tPHL and tPLH are the same as tpd.
Figure 1. Load Circuit and Voltage Waveforms
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7
SCAS433A − OCTOBER 1993 − REVISED JULY 1995
PARAMETER MEASUREMENT INFORMATION
VCC = 2.7 V AND 3.3 V " 0.3 V
6V
S1
500 Ω
From Output
Under Test
Open
GND
CL = 50 pF
(see Note A)
TEST
S1
tpd
tPLZ/tPZL
tPHZ/tPZH
Open
6V
GND
500 Ω
tw
LOAD CIRCUIT
2.7 V
Input
2.7 V
Timing
Input
0V
0V
VOLTAGE WAVEFORMS
PULSE DURATION
th
2.7 V
Data
Input
1.5 V
1.5 V
0V
tPHL
Output
Waveform 2
S1 at GND
(see Note B)
VOH
1.5 V
1.5 V
VOL
1.5 V
0V
tPLZ
3V
Output
Waveform 1
S1 at 6 V
(see Note B)
1.5 V
tPLH
1.5 V
tPZL
2.7 V
1.5 V
2.7 V
Output
Control
(low-level
enabling)
0V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
Output
1.5 V
1.5 V
tsu
Input
1.5 V
1.5 V
tPZH
VOL + 0.3 V
VOL
tPHZ
VOH
1.5 V
VOH − 0.3 V
0V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR v 10 MHz, ZO = 50 Ω, tr v 2.5 ns, tf v 2.5 ns.
D. The outputs are measured one at a time with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. tPZL and tPZH are the same as ten.
G. tPHL and tPLH are the same as tpd.
Figure 2. Load Circuit and Voltage Waveforms
8
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•
PACKAGE OPTION ADDENDUM
www.ti.com
30-Mar-2005
PACKAGING INFORMATION
Orderable Device
Status (1)
Package
Type
Package
Drawing
Pins Package Eco Plan (2)
Qty
SN74ALVC16270DL
OBSOLETE
SSOP
DL
56
TBD
Call TI
Call TI
SN74ALVC16270DLR
OBSOLETE
SSOP
DL
56
TBD
Call TI
Call TI
Lead/Ball Finish
MSL Peak Temp (3)
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS) or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 1
MECHANICAL DATA
MSSO001C – JANUARY 1995 – REVISED DECEMBER 2001
DL (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
48 PINS SHOWN
0.025 (0,635)
0.0135 (0,343)
0.008 (0,203)
48
0.005 (0,13) M
25
0.010 (0,25)
0.005 (0,13)
0.299 (7,59)
0.291 (7,39)
0.420 (10,67)
0.395 (10,03)
Gage Plane
0.010 (0,25)
1
0°–ā8°
24
0.040 (1,02)
A
0.020 (0,51)
Seating Plane
0.110 (2,79) MAX
0.004 (0,10)
0.008 (0,20) MIN
PINS **
28
48
56
A MAX
0.380
(9,65)
0.630
(16,00)
0.730
(18,54)
A MIN
0.370
(9,40)
0.620
(15,75)
0.720
(18,29)
DIM
4040048 / E 12/01
NOTES: A.
B.
C.
D.
All linear dimensions are in inches (millimeters).
This drawing is subject to change without notice.
Body dimensions do not include mold flash or protrusion not to exceed 0.006 (0,15).
Falls within JEDEC MO-118
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Products
Applications
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amplifier.ti.com
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www.ti.com/audio
Data Converters
dataconverter.ti.com
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www.ti.com/automotive
DLP® Products
www.dlp.com
Communications and
Telecom
www.ti.com/communications
DSP
dsp.ti.com
Computers and
Peripherals
www.ti.com/computers
Clocks and Timers
www.ti.com/clocks
Consumer Electronics
www.ti.com/consumer-apps
Interface
interface.ti.com
Energy
www.ti.com/energy
Logic
logic.ti.com
Industrial
www.ti.com/industrial
Power Mgmt
power.ti.com
Medical
www.ti.com/medical
Microcontrollers
microcontroller.ti.com
Security
www.ti.com/security
RFID
www.ti-rfid.com
Space, Avionics &
Defense
www.ti.com/space-avionics-defense
RF/IF and ZigBee® Solutions www.ti.com/lprf
Video and Imaging
www.ti.com/video
Wireless
www.ti.com/wireless-apps
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