SCAS259A − NOVEMBER 1993 − REVISED JULY 1995
D EPIC (Enhanced-Performance Implanted
D
D
D
D
D
D
D
D
D
DGG OR DL PACKAGE
(TOP VIEW)
CMOS) Submicron Process
Member of the Texas Instruments
Widebus+ Family
UBE (Universal Bus Exchanger) Allows
Synchronous Data Exchange
Designed to Facilitate Incident-Wave
Switching for Line Impedances of 50 Ω
or Greater
Typical VOLP (Output Ground Bounce)
< 0.8 V at VCC = 3.3 V, TA = 25°C
Typical VOHV (Output VOH Undershoot)
> 2 V at VCC = 3.3 V, TA = 25°C
ESD Protection Exceeds 2000 V Per
MIL-STD-883C, Method 3015; Exceeds
200 V Using Machine Model
(C = 200 pF, R = 0)
Bus Hold on Data Inputs Eliminates the
Need for External Pullup/Pulldown
Resistors
Latch-Up Performance Exceeds 250 mA
Per JEDEC Standard JESD-17
Package Options Include Plastic 300-mil
Shrink Small-Outline (DL) and Thin Shrink
Small-Outline (DGG) Packages
PRE
SEL0
1A1
GND
1A2
1A3
VCC
1A4
1A5
1A6
GND
1A7
1A8
1A9
2A1
2A2
2A3
GND
2A4
2A5
2A6
VCC
2A7
2A8
GND
2A9
SEL1
SEL2
description
The SN74ALVC16409 allows synchronous data
exchange between four different buses.
1
56
2
55
3
54
4
53
5
52
6
51
7
50
8
49
9
48
10
47
11
46
12
45
13
44
14
43
15
42
16
41
17
40
18
39
19
38
20
37
21
36
22
35
23
34
24
33
25
32
26
31
27
30
28
29
CLK
SELEN
1B1
GND
1B2
1B3
VCC
1B4
1B5
1B6
GND
1B7
1B8
1B9
2B1
2B2
2B3
GND
2B4
2B5
2B6
VCC
2B7
2B8
GND
2B9
SEL4
SEL3
Data flow is controlled by the select (SEL0−SEL4) inputs. A data-flow state is stored on the rising edge of the
clock (CLK) input if the select-enable (SELEN) input is low. Once a data-flow state has been established, data
is stored in the flip-flop on the rising edge of CLK if SELEN is high.
The data-flow control logic is designed to allow glitch-free data transmission.
Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level.
The SN74ALVC16409 is available in TI’s shrink small-outline (DL) and thin shrink small-outline (DGG)
packages, which provide twice the I/O pin count and functionality of standard small-outline packages in the
same printed-circuit-board area.
The SN74ALVC16409 is characterized for operation from − 40°C to 85°C.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Widebus+, EPIC, and UBE are trademarks of Texas Instruments Incorporated.
Copyright 1995, Texas Instruments Incorporated
!"#$%! & '("")% $& ! *(+,'$%! -$%).
"!-('%& '!!"# %! &*)''$%!& *)" %/) %)"#& ! )0$& &%"(#)%&
&%$-$"- 1$""$%2. "!-('%! *"!')&&3 -!)& !% )')&&$",2 ',(-)
%)&%3 ! $,, *$"$#)%)"&.
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•
1
SCAS259A − NOVEMBER 1993 − REVISED JULY 1995
logic diagram (positive logic)
CLK
SELEN
SEL0
SEL1
56
28
55
SEL2
2
29
Flow and Storage Control
SEL3
27
30
3
3
2Ax 1Ax
CLK
D
1Ax
CLK
D
1Bx 2Ax
2Bx 2Bx
1A
1B
3
1Bx
3
CLK
D
2A
1Ax
1Ax
1Bx
2Bx
2Ax
1Bx
CLK
D
2B
2Ax
2Bx
One of Nine Channels
FUNCTION TABLE
INPUTS
CLK
SEND
PORT
X
X
OUTPUT
RECEIVE
PORT
X
L
B0†
L
X
H
H
↑
L
L
↑
H
H
X
H
B0†
B0†
† Output level before the
indicated steady-state input
conditions were established
L
2
SEL4
X
•
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•
SCAS259A − NOVEMBER 1993 − REVISED JULY 1995
DATA-FLOW CONTROL FUNCTION TABLE
INPUTS
DATA FLOW
SELEN
CLK
SEL0
SEL1
SEL2
SEL3
SEL4
H
↑
X
X
X
X
X
No change
L
↑
0
0
0
0
0
None, all I/Os off
L
↑
0
0
0
0
1
Not used
L
↑
0
0
0
1
0
Not used
L
↑
0
0
0
1
1
Not used
L
↑
0
0
1
0
0
Not used
L
↑
0
0
1
0
1
Not used
L
↑
0
0
1
1
0
Not used
L
↑
0
0
1
1
1
Not used
L
↑
0
1
0
0
0
2A to 1A and 1B to 2B
L
↑
0
1
0
0
1
2A to 1A
L
↑
0
1
0
1
0
2B to 1B
L
↑
0
1
0
1
1
2A to 1A and 2B to 1B
L
↑
0
1
1
0
0
1A to 2A and 1B to 2B
L
↑
0
1
1
0
1
1A to 2A
L
↑
0
1
1
1
0
1B to 2B
L
↑
0
1
1
1
1
1A to 2A and 2B to 1B
L
↑
1
0
0
0
0
1A to 1B and 2B to 2A
L
↑
1
0
0
0
1
1A to 1B
L
↑
1
0
0
1
0
2A to 2B
L
↑
1
0
0
1
1
1A to 1B and 2A to 2B
L
↑
1
0
1
0
0
1B to 1A and 2A to 2B
L
↑
1
0
1
0
1
1B to 1A
L
↑
1
0
1
1
0
2B to 2A
L
↑
1
0
1
1
1
1B to 1A and 2B to 2A
L
↑
1
1
0
0
0
2B to 1A and 2A to 1B
L
↑
1
1
0
0
1
1B to 2A
L
↑
1
1
0
1
0
2B to 1A
L
↑
1
1
0
1
1
2B to 1A and 1B to 2A
L
↑
1
1
1
0
0
1A to 2B and 1B to 2A
L
↑
1
1
1
0
1
1A to 2B
L
↑
1
1
1
1
0
2A to 1B
L
↑
1
1
1
1
1
1A to 2B and 2A to 1B
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3
SCAS259A − NOVEMBER 1993 − REVISED JULY 1995
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 4.6 V
Input voltage range, VI: Except I/O ports (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to VCC + 4.6 V
I/O ports (see Notes 1 and 2) . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to VCC + 0.5 V
Output voltage range, VO (see Notes 1 and 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to VCC + 0.5 V
Input clamp current, IIK (VI < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −50 mA
Output clamp current, IOK (VO < 0 or VO > VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 50 mA
Continuous output current, IO (VO = 0 to VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 50 mA
Continuous current through VCC or GND pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 100 mA
Maximum power dissipation at TA = 55°C (in still air) (see Note 3): DGG package . . . . . . . . . . . . . . . . . . 1 W
DL package . . . . . . . . . . . . . . . . . . 1.4 W
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
2. This value is limited to 4.6 V maximum.
3. The maximum package power dissipation is calculated using a junction temperature of 150°C and a board trace length of 750 mils.
For more information, refer to the Package Thermal Considerations application note in the 1994 ABT Advanced BiCMOS Technology
Data Book, literature number SCBD002B.
recommended operating conditions (see Note 4)
MIN
MAX
2.7
3.6
VCC
Supply voltage
VIH
High-level input voltage
VCC = 2.7 V to 3.6 V
VCC = 2.3 V to 2.7 V
VIL
Low-level input voltage
VCC = 2.7 V to 3.6 V
VCC = 2.3 V to 2.7 V
VI
VO
Input voltage
0
Output voltage
0
IOH
High-level output current
IOL
Low-level output current
∆t /∆v
Input transition rise or fall rate
4
•
•
V
0.8
0.7
VCC
VCC
−12
VCC = 3 V
VCC = 2.3 V
−24
VCC = 2.7 V
VCC = 3 V
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V
2
1.7
VCC = 2.3 V
VCC = 2.7 V
TA
Operating free-air temperature
NOTE 4: Unused control inputs must be held high or low to prevent them from floating.
UNIT
−12
V
V
V
mA
12
mA
24
0
10
ns / V
−40
85
°C
SCAS259A − NOVEMBER 1993 − REVISED JULY 1995
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
IOH = − 100 µA
IOH = − 6 mA
VOH
VOL
MIN to MAX
II(hold)
IOZ§
ICC
nICC
Ci
Co
TA = − 40°C to 85°C
MIN TYP‡
MAX
VIH = 1.7 V
VIH = 1.7 V
2.3 V
VCC −0.2
2
2.3 V
1.7
IOH = − 12 mA
VIH = 2 V
VIH = 2 V
2.7 V
2.2
3V
2.4
IOH = − 24 mA
IOL = 100 µA
VIH = 2 V
3V
2
MIN to MAX
0.2
IOL = 6 mA
VIL = 0.7 V
VIL = 0.7 V
2.3 V
0.4
2.3 V
0.7
VIL = 0.8 V
VIL = 0.8 V
2.7 V
0.4
3V
0.55
IOL = 12 mA
IOL = 24 mA
VI = VCC or GND
II
VCC†
TEST CONDITIONS
V
±5
3.6 V
VI = 0.7 V
VI = 1.7 V
2.3 V
VI = 0.8 V
VI = 2 V
3V
UNIT
V
µA
45
−45
µA
75
VI = 0 to 3.6 V
VO = VCC or GND
VI = VCC or GND,
One input at VCC − 0.6 V,
IO = 0
Other inputs at VCC or GND
−75
3.6 V
± 500
3.6 V
± 10
µA
3.6 V
40
µA
500
µA
3 V to 3.6 V
VI = VCC or GND
VO = VCC or GND
3.3 V
4
pF
3.3 V
8
pF
† For conditions shown as MIN or MAX, use the appropriate values under recommended operating conditions.
‡ All typical values are measured at VCC = 3.3 V, TA = 25°C.
§ For I/O ports, the parameter IOZ includes the input leakage current.
timing requirements over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted)
VCC = 2.5 V
± 0.2 V
fclock
tw
tsu
th
Clock frequency
Pulse duration, CLK high or low
Setup time
Hold time
MIN
MAX
0
120
VCC = 2.7 V
MIN
VCC = 3.3 V
± 0.3 V
MIN
MAX
0
120
4.2
4.2
3
A or B before CLK↑
1.9
1.9
1.4
S before CLK↑
5.1
4.2
3.5
SELEN before CLK↑
2.5
2.5
1.8
PRE before CLK↑
1
1
0.7
A or B after CLK↑
0.8
0.8
1
S after CLK↑
SELEN after CLK↑
•
0
0
0
0.5
0.5
0.8
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•
UNIT
MHz
ns
ns
ns
5
SCAS259A − NOVEMBER 1993 − REVISED JULY 1995
switching characteristics over recommended ranges of supply voltage and operating free-air
temperature, CL = 50 pF (unless otherwise noted) (see Figures 1 and 2)
PARAMETER
fmax
tpd
FROM
(INPUT)
VCC = 2.5 V
± 0.2 V
TO
(OUTPUT)
MIN
TYP
VCC = 3.3 V
± 0.3 V
VCC = 2.7 V
MAX
MAX
MIN
120
TYP
UNIT
MAX
120
MHz
CLK (A or B)
B or A
2
4.2
6.6
5.7
1.5
3.3
5.1
ns
ten
tdis
CLK (SEL)
A or B
2.5
4.8
7.4
6.3
2
3.8
5.7
ns
CLK (SEL)
A or B
3
5.1
7.3
6
2
4
5.7
ns
tdis
PRE
A or B
3.5
5.5
7.7
6.5
2.5
4.2
6.1
ns
operating characteristics, TA = 25°C
PARAMETER
Cpd
TEST CONDITIONS
Outputs enabled
Power dissipation capacitance
CL = 50 pF,
Outputs disabled
f = 10 MHz
VCC = 2.5 V
± 0.2 V
VCC = 3.3 V
± 0.3 V
TYP
TYP
60
60
timing diagram
CLK
tsu
th
SELEN
ÎÎÎ ÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎ
ÎÎÎ ÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
SEL
Send
Port
tsu
th
tsu th
tdis
CLK (SEL) A or B
Receive
Port
tpd
CLK A or B
6
•
ten
CLK (SEL)
A or B
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•
UNIT
pF
SCAS259A − NOVEMBER 1993 − REVISED JULY 1995
PARAMETER MEASUREMENT INFORMATION
VCC = 2.5 V " 0.2 V
4.6 V
S1
500 Ω
From Output
Under Test
Open
GND
CL = 50 pF
(see Note A)
500 Ω
TEST
S1
tpd
tPLZ/tPZL
tPHZ/tPZH
Open
4.6 V
GND
tw
LOAD CIRCUIT
2.3 V
Input
2.3 V
Timing
Input
VOLTAGE WAVEFORMS
PULSE DURATION
th
2.3 V
Data
Input
1.2 V
1.2 V
0V
tPHL
Output
Waveform 2
S1 at GND
(see Note B)
VOH
1.2 V
1.2 V
VOL
1.2 V
0V
tPLZ
2.3 V
Output
Waveform 1
S1 at 4.6 V
(see Note B)
1.2 V
tPLH
1.2 V
tPZL
2.3 V
1.2 V
2.3 V
Output
Control
(low-level
enabling)
0V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
Output
1.2 V
0V
0V
tsu
Input
1.2 V
1.2 V
1.2 V
tPZH
VOL + 0.3 V
VOL
tPHZ
1.2 V
VOH − 0.3 V
VOH
0V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR v 10 MHz, ZO = 50 Ω, tr v 2.5 ns, tf v 2.5 ns.
D. The outputs are measured one at a time with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. tPZL and tPZH are the same as ten.
G. tPLH and tPHL are the same as tpd.
Figure 1. Load Circuit and Voltage Waveforms
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•
7
SCAS259A − NOVEMBER 1993 − REVISED JULY 1995
PARAMETER MEASUREMENT INFORMATION
VCC = 2.7 V AND 3.3 V " 0.3 V
6V
S1
500 Ω
From Output
Under Test
Open
GND
CL = 50 pF
(see Note A)
500 Ω
TEST
S1
tpd
tPLZ/tPZL
tPHZ/tPZH
Open
6V
GND
tw
LOAD CIRCUIT
2.7 V
Input
2.7 V
Timing
Input
VOLTAGE WAVEFORMS
PULSE DURATION
th
2.7 V
Data
Input
1.5 V
1.5 V
0V
tPHL
Output
Waveform 2
S1 at GND
(see Note B)
VOH
1.5 V
1.5 V
VOL
1.5 V
0V
tPLZ
3V
Output
Waveform 1
S1 at 6 V
(see Note B)
1.5 V
tPLH
1.5 V
tPZL
2.7 V
1.5 V
2.7 V
Output
Control
(low-level
enabling)
0V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
Output
1.5 V
0V
0V
tsu
Input
1.5 V
1.5 V
1.5 V
tPZH
VOL + 0.3 V
VOL
tPHZ
1.5 V
VOH − 0.3 V
VOH
0V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR v 10 MHz, ZO = 50 Ω, tr v 2.5 ns, tf v 2.5 ns.
D. The outputs are measured one at a time with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. tPZL and tPZH are the same as ten.
G. tPLH and tPHL are the same as tpd.
Figure 2. Load Circuit and Voltage Waveforms
8
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PACKAGE OPTION ADDENDUM
www.ti.com
30-Mar-2005
PACKAGING INFORMATION
Orderable Device
Status (1)
Package
Type
Package
Drawing
Pins Package Eco Plan (2)
Qty
SN74ALVC16409DL
OBSOLETE
SSOP
DL
56
TBD
Call TI
Call TI
SN74ALVC16409DLR
OBSOLETE
SSOP
DL
56
TBD
Call TI
Call TI
Lead/Ball Finish
MSL Peak Temp (3)
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS) or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 1
MECHANICAL DATA
MSSO001C – JANUARY 1995 – REVISED DECEMBER 2001
DL (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
48 PINS SHOWN
0.025 (0,635)
0.0135 (0,343)
0.008 (0,203)
48
0.005 (0,13) M
25
0.010 (0,25)
0.005 (0,13)
0.299 (7,59)
0.291 (7,39)
0.420 (10,67)
0.395 (10,03)
Gage Plane
0.010 (0,25)
1
0°–ā8°
24
0.040 (1,02)
A
0.020 (0,51)
Seating Plane
0.110 (2,79) MAX
0.004 (0,10)
0.008 (0,20) MIN
PINS **
28
48
56
A MAX
0.380
(9,65)
0.630
(16,00)
0.730
(18,54)
A MIN
0.370
(9,40)
0.620
(15,75)
0.720
(18,29)
DIM
4040048 / E 12/01
NOTES: A.
B.
C.
D.
All linear dimensions are in inches (millimeters).
This drawing is subject to change without notice.
Body dimensions do not include mold flash or protrusion not to exceed 0.006 (0,15).
Falls within JEDEC MO-118
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