a FEATURES 200 MSPS Guaranteed Conversion Rate 135 MSPS Low Cost Version Available 350 MHz Analog Bandwidth 1 V p-p Analog Input Range Internal 2.5 V Reference and T/H Low Power: 500 mW 5 V Single Supply Operation TTL Output Interface Single or Demultiplexed Output Ports APPLICATIONS RGB Graphics Processing High Resolution Video Digital Data Storage Read Channels Digital Communications Digital Instrumentation Medical Imaging GENERAL DESCRIPTION The AD9054A is an 8-bit monolithic analog-to-digital converter optimized for high speed, low power, small size and ease of use. With a 200 MSPS encode rate capability and full-power analog bandwidth of 350 MHz, the component is ideal for applications requiring the highest possible dynamic performance. To minimize system cost and power dissipation, the AD9054A includes an internal 2.5 V reference and track-and-hold circuit. The user provides only a 5 V power supply and an encode clock. No external reference or driver components are required for many applications. 8-Bit, 200 MSPS A/D Converter AD9054A FUNCTIONAL BLOCK DIAGRAM VREF IN AD9054A AIN T/H AIN ENCODE ENCODE VREF OUT 2.5V REFERENCE QUANTIZER 8 ENCODE LOGIC DEMULTIPLEXER 8 TIMING VDD GND DEMUX DS DA7 –DA0 DB7 –DB0 DS The AD9054A’s encode input interfaces directly to TTL, CMOS or positive-ECL logic and will operate with single-ended or differential inputs. The user may select dual-channel or singlechannel digital outputs. The dual (demultiplexed) mode interleaves ADC data through two 8-bit channels at one-half the clock rate. Operation in demultiplexed mode reduces the speed and cost of external digital interfaces while allowing the ADC to be clocked to the full 200 MSPS conversion rate. In the singlechannel (nondemultiplexed) mode, all data is piped at the full clock rate to the Channel A outputs. Fabricated with an advanced BiCMOS process, the AD9054A is provided in a space-saving 44-lead LQFP surface mount plastic package (ST-44) and specified over the full industrial (–40°C to +85°C) temperature range. REV. D Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 www.analog.com Fax: 781/326-8703 © Analog Devices, Inc., 2001 AD9054A–SPECIFICATIONS ELECTRICAL CHARACTERISTICS (V Parameter Temp DD = 5 V, external reference, fS = max unless otherwise noted.) Test Level AD9054ABST-200 Min Typ Max RESOLUTION DC ACCURACY Differential Nonlinearity 8 ± 0.9 ± 1.0 ± 0.6 ± 0.9 Guaranteed ±2 160 8 25°C Full 25°C Full Full 25°C Full I VI I VI VI I V Full Full 25°C Full 25°C Full 25°C 25°C Full 25°C V V I VI I VI V I VI V REFERENCE OUTPUT Output Voltage Temperature Coefficient Full Full VI V 2.4 SWITCHING PERFORMANCE Maximum Conversion Rate (f S) Minimum Conversion Rate (f S) Encode Pulsewidth High (t EH) Encode Pulsewidth Low (t EL) Aperture Delay (tA) Aperture Uncertainty (Jitter) Data Sync Setup Time (t SDS) Data Sync Hold Time (t HDS) Data Sync Pulsewidth (t PWDS) Output Valid Time (t V)3 Output Propagation Delay (t PD)3 Full Full 25°C 25°C 25°C 25°C 25°C 25°C 25°C Full Full VI IV IV IV V V IV IV IV VI VI 200 DIGITAL INPUTS HIGH Level Current (I IH)4 LOW Level Current (I IL)4 Input Capacitance Full Full 25°C VI VI V DIFFERENTIAL INPUTS Differential Signal Amplitude (VID) HIGH Input Voltage (V IHD) LOW Input Voltage (V ILD) Common-Mode Input (V ICM) Full Full Full Full IV IV IV IV 400 1.5 0 1.5 VDD VDD – 0.4 DEMUX INPUT HIGH Input Voltage (V IH) LOW Input Voltage (V IL) Full Full IV IV 2.0 0 VDD 0.8 Full Full VI VI 2.4 Integral Nonlinearity No Missing Codes Gain Error1 Gain Tempco1 ANALOG INPUT Input Voltage Range (With Respect to AIN) Compliance Range AIN or AIN Input Offset Voltage Input Resistance Input Capacitance Input Bias Current Analog Bandwidth, Full Power 2 DIGITAL OUTPUTS HIGH Output Voltage (V OH) LOW Output Voltage (V OL) Output Coding AD9054ABST-135 Min Typ Max ± 0.9 ± 1.0 ± 0.6 ± 0.9 Guaranteed ±2 160 +1.5/–1.0 +2.0/–1.0 ± 1.5 ± 2.0 ±7 ± 512 1.8 36 23 ±4 ±8 62 4 25 1.8 36 23 2.6 2.4 LSB LSB LSB LSB ±7 % FS ppm/°C 3.2 ± 16 ± 19 50 75 2.5 110 2.6 135 5.1 5.9 500 500 3 25 22 22 3.0 3.0 0.5 2.3 0.5 2.3 0 0.5 2.0 2.7 7.9 5.7 7.5 8.5 V ppm/°C MSPS MSPS ns ns ns ps rms ns ns ns ns ns µA µA pF 400 1.5 0 1.5 VDD VDD – 0.4 mV V V V 2.0 0 VDD 0.8 V V 0.4 V V 500 500 3 2.4 Binary mV p-p V mV mV kΩ kΩ pF µA µA MHz 625 625 625 625 0.4 –2– +1.5/–1.0 +2.0/–1.0 ± 1.5 ± 2.0 350 25 22 22 2.0 2.0 0 0.5 2.0 2.7 ±4 ±8 62 4 25 50 75 350 2.5 110 Bits ± 512 3.2 ± 16 ± 19 Unit Binary REV. D AD9054A Parameter Temp Test Level POWER SUPPLY VDD Supply Current (IDD) Power Dissipation5, 6 Power Supply Sensitivity 7 Full Full 25°C DYNAMIC PERFORMANCE 8 Transient Response Overvoltage Recovery Time Signal-to-Noise Ratio (SNR) (Without Harmonics) fIN = 19.7 MHz fIN = 49.7 MHz fIN = 70.1 MHz Signal-to-Noise Ratio (SINAD) (With Harmonics) fIN = 19.7 MHz fIN = 49.7 MHz fIN = 70.1 MHz Effective Number of Bits fIN = 19.7 MHz fIN = 49.7 MHz fIN = 70.1 MHz 2nd Harmonic Distortion fIN = 19.7 MHz fIN = 49.7 MHz fIN = 70.1 MHz 3rd Harmonic Distortion fIN = 19.7 MHz fIN = 49.7 MHz fIN = 70.1 MHz Two-Tone Intermod Distortion (IMD) fIN = 19.7 MHz fIN = 49.7 MHz fIN = 70.1 MHz AD9054ABST-200 Min Typ Max AD9054ABST-135 Min Typ Max Unit VI VI I 128 640 0.005 120 600 0.005 mA mW V/V 25°C 25°C V V 1.5 1.5 25°C Full 25°C Full 25°C Full IV V I V I V 25°C Full 25°C Full 25°C Full IV V I V I V 25°C 25°C 25°C IV I I 25°C 25°C 25°C 42 156 781 0.015 140 700 0.015 1.5 1.5 ns ns 45 45 45 45 dB dB dB dB dB dB 43 43 43 43 dB dB dB dB dB dB 45 45 45 45 45 45 42 43 43 43 43 42 42 40 6.35 6.35 6.18 6.85 6.85 6.85 6.35 6.35 6.85 6.85 Bits Bits Bits IV I I 58 54 49 63 59 55 58 54 63 59 dBc dBc dBc 25°C 25°C 25°C IV I I 48 48 43 56 54 50 48 48 56 54 dBc dBc dBc 25°C 25°C 25°C V V V 60 55 dBc dBc dBc 42 42 40 40 39 60 55 50 42 40 NOTES 1 Gain error and gain temperature coefficient are based on the ADC only (with a fixed 2.5 V external reference). 2 3 dB bandwidth with full-power input signal. 3 tV and tPD are measured from the threshold crossing of the ENCODE input to valid TTL levels of the digital outputs. The output ac load during test is 5 pF (Refer to equivalent circuits Figures 5 and 6). 4 IIH and IIL are valid for differential input voltages of less than 1.5 V. At higher differential voltages, the input current will increase to a maximum of 1.5 mA. 5 Power dissipation is measured under the following conditions: analog input is –1 dBFS at 19.7 MHz. 6 Typical thermal impedance for the ST-44 (LQFP) 44-lead package (in still air): θJC = 20°C/W, θCA = 35°C/W, θJA = 55°C/W. 7 A change in input offset voltage with respect to a change in V DD. 8 SNR/harmonics based on an analog input voltage of –1.0 dBFS referenced to a 1.024 V full-scale input range. Specifications subject to change without notice. IV. Parameter is guaranteed by design and characterization testing. EXPLANATION OF TEST LEVELS Test Level V. Parameter is a typical value only. I. 100% production tested. VI. 100% production tested at 25°C; guaranteed by design and characterization testing for industrial temperature range. II. 100% production tested at 25°C and sample tested at specified temperatures. III. Sample tested only. REV. D –3– AD9054A Table I. Output Coding ABSOLUTE MAXIMUM RATINGS* VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 V Analog Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . VDD to 0.0 V Digital Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . VDD to 0.0 V VREF IN, VREF OUT . . . . . . . . . . . . . . . . . . . VDD to 0.0 V Digital Output Current . . . . . . . . . . . . . . . . . . . . . . . . 20 mA Operating Temperature . . . . . . . . . . . . . . . . –55°C to +125°C Storage Temperature . . . . . . . . . . . . . . . . . . –65°C to +150°C Maximum Junction Temperature . . . . . . . . . . . . . . . . 150°C Maximum Case Temperature . . . . . . . . . . . . . . . . . . . 150°C *Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions outside of those indicated in the operation sections of this specification is not implied. Exposure to absolute maximum ratings for extended periods may affect device reliability. ORDERING GUIDE Model Temperature Range Package Option* AD9054ABST-200 AD9054ABST-135 AD9054A/PCB –40°C to +85°C –40°C to +85°C 25°C ST-44 ST-44 Evaluation Board Step AIN–AIN Code Binary 255 254 253 • • • 129 128 127 126 • • • 2 1 0 ≥0.512 V 0.508 V 0.504 V • • • 0.006 V 0.002 V –0.002 V –0.006 V • • • –0.504 V –0.508 V ≤–0.512 V 255 254 253 • • • 129 128 127 126 • • • 2 1 0 1111 1111 1111 1110 1111 1101 • • • 1000 0001 1000 0000 0111 1111 0111 1110 • • • 0000 0010 0000 0001 0000 0000 *ST = Plastic Thin Quad Flatpack (LQFP). CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD9054A features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. –4– WARNING! ESD SENSITIVE DEVICE REV. D AD9054A 34 38 39 42 43 44 DB4 DB6 DB5 DB7 (MSB) VDD DB1 GND DB0 (LSB) AIN Ground Digital Outputs of ADC Channel A. DA7 is the MSB, DA0 the LSB DB0–DB7 Digital Outputs of ADC Channel B. DB7 is the MSB, DB0 the LSB VREF OUT Internal Reference Output (2.5 V typical); Bypass with 0.1 µF to Ground VREF IN Reference Input for ADC (2.5 V typical, ± 4%) AIN Analog Input—Complement. Connect to input signal midscale reference. AIN Analog Input—True DEMUX Format Select. LOW = Dual. Channel Mode, HIGH = Single. Channel Mode (Channel A Only) DS Data Sync Complement DS Data Sync—Aligns Output Channels in Dual-Channel Mode VDD AD9054A AIN GND TOP VIEW (PINS DOWN) GND GND VDD VDD DEMUX DA0 (LSB) DS DA1 SAMPLE N+3 DA3 DA4 DA5 DA2 DA6 GND PIN 1 IDENTIFIER DS SAMPLE N SAMPLE N–1 GND DB2 VDD 33 DB3 GND ENCODE 19–26 VREF IN ENCODE 3, 5, 15, 18, 28, VDD 30, 31, 36, 41 4, 6, 16, 17, 27, GND 29, 32, 35, 37, 40 14–7 DA0–DA7 VDD ENCODE DA7 (MSB) 2 Encode Clock for ADC (ADC Samples on Rising Edge of ENCODE) Encode Clock Complement (ADC Samples on Falling Edge of ENCODE) Power Supply (5 V) GND ENCODE GND 1 VDD Function VDD Mnemonic VDD Pin Number GND PIN CONFIGURATION VREF OUT PIN FUNCTION DESCRIPTIONS SAMPLE N+4 AIN SAMPLE N+1 tA tEH tEL SAMPLE N+2 1/fS ENCODE ENCODE tPD D7 –D 0 DATA N–5 DATA N–4 DATA N–3 DATA N–2 Figure 1. Timing—Single Channel Mode REV. D –5– DATA N–1 tV DATA N AD9054A SAMPLE N SAMPLE N–1 SAMPLE N+3 SAMPLE N+4 SAMPLE N+5 AIN SAMPLE N–2 SAMPLE N+1 tA tEH tEL tHDS SAMPLE N+6 1/fS ENCODE ENCODE SAMPLE N+2 tHDS tSDS tSDS DS DS tPD tPWDS PORT A D7 –D 0 DATA N–7 OR N–8 PORT B D7 –D 0 DATA N–8 OR N–7 DATA N–7 OR N–6 DATA N–6 OR N–7 INVALID IF OUT OF SYNC DATA N–4 IF IN SYNC INVALID IF OUT OF SYNC DATA N–5 IF IN SYNC tV DATA N DATA N–2 DATA N–3 DATA N+1 DATA N–1 Figure 2a. Timing—Dual Channel Mode (One-Shot Data Sync) SAMPLE N SAMPLE N–1 SAMPLE N+3 SAMPLE N+4 SAMPLE N+5 AIN SAMPLE N–2 SAMPLE N+1 tA tEH tEL SAMPLE N+2 SAMPLE N+6 1/fS ENCODE ENCODE tHDS tSDS tHDS tSDS DS DS tPWDS PORT A D7 –D 0 DATA N–7 OR N–8 PORT B D7 –D 0 DATA N–8 OR N–7 tPD DATA N–7 OR N–6 DATA N–6 OR N–7 INVALID IF OUT OF SYNC DATA N–4 IF IN SYNC INVALID IF OUT OF SYNC DATA N–5 IF IN SYNC tV DATA N DATA N–2 DATA N–3 DATA N–1 DATA N+1 Figure 2b. Timing—Dual Channel Mode (Continuous Data Sync) –6– REV. D AD9054A EQUIVALENT CIRCUITS VDD 17.5k⍀ DEMUX AIN AIN 300⍀ VDD 300⍀ 7.5k⍀ Figure 6. Equivalent DEMUX Input Circuit Figure 3. Equivalent Analog Input Circuit VDD VDD VREF IN DIGITAL OUTPUTS Figure 4. Equivalent Reference Input Circuit Figure 7. Equivalent Digital Output Circuit VDD VDD 17.5k⍀ ENCODE OR DS 300⍀ 300⍀ ENCODE OR DS VREF OUT 7.5k⍀ Figure 5. Equivalent ENCODE and Data Select Input Circuit REV. D Figure 8. Equivalent Reference Output Circuit –7– AD9054A–Typical Performance Characteristics 55 45.4 45.2 50 45.0 20MHz 50MHz 45 SNR – dB SNR – dB SNR SINAD 40 44.8 44.6 70MHz 44.4 NYQUIST FREQUENCY (100MHz) 35 44.2 30 0 20 40 60 80 fIN – MHz 100 120 44.0 –45 140 TPC 1. SNR vs. fIN: fS = 200 MSPS 0 25 TC – ⴗC 70 90 TPC 4. SNR vs. Temperature, fS = 135 MSPS 50 46.0 49 45.8 48 45.6 47 45.4 46 45.2 20MHz SNR – dB SNR – dB 50MHz SNR 45 44 SINAD 44.8 43 44.6 42 44.4 41 44.2 40 25 44.0 –60 50 75 100 125 150 175 200 225 250 270 fS – MSPS 300 TPC 2. SNR vs. fS: fIN = 19.7 MHz –40 –20 0 20 TC – ⴗC 40 60 80 100 TPC 5. SNR vs. Temperature, fS = 200 MSPS 50 50 48 SNR 45 fS = 135MSPS fIN = 10.3MHz 46 SINAD 44 SNR – dB 40 SNR – dB 70MHz 45.0 35 42 SNR 40 38 SINAD 30 36 34 25 32 20 25 50 75 30 0.0 100 125 150 175 200 225 250 270 300 fS – MSPS TPC 3. SNR vs. fS: fIN = 70.1 MHz 1.0 2.0 3.0 4.0 5.0 6.0 ENCODE PULSEWIDTH – ns 7.0 8.0 TPC 6. SNR vs. Clock Pulsewidth, (tPWH): fS = 135 MSPS –8– REV. D AD9054A 50 48 –70 fS = 200MSPS fIN = 10.3MHz –68 SNR 2ND HARMONIC –66 46 –64 44 –62 –60 dBc SNR – dB SINAD 42 40 3RD HARMONIC –58 –56 38 –54 36 –52 34 –50 32 30 0.0 –48 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 ENCODE PULSEWIDTH – ns 4.5 –46 25 5.0 TPC 7. SNR vs. Clock Pulsewidth, (tPWH): fS = 200 MSPS 50 75 100 125 150 175 200 225 250 fS – MSPS 270 300 TPC 10. Harmonic Distortion vs. fS: fIN = 19.7 MHz –60 46 45 2ND HARMONIC –50 44 –40 3RD HARMONIC dBc SINAD – dB 20MHz 43 70MHz 42 50MHz 41 –30 –20 40 –10 39 38 –60 –40 –20 0 20 40 TC – ⴗC 60 80 0 25 100 50 75 100 125 150 175 200 225 250 270 300 fS – MSPS TPC 8. SINAD vs. Temperature: fS = 135 MSPS TPC 11. Harmonic Distortion vs. fS: fIN = 70.1 MHz 46 –40 45 –45 44 –50 50MHz 42 dB SINAD – dB 20MHz 43 70MHz –55 70MHz 41 –60 50MHz 40 –65 39 38 –60 –40 –20 0 20 TC – ⴗC 40 60 80 –70 –60 100 TPC 9. SINAD vs. Temperature: fS = 200 MSPS REV. D 20MHz –40 –20 0 20 TC – ⴗC 40 60 80 100 TPC 12. 2nd Harmonic vs. Temperature: fS = 135 MSPS –9– AD9054A –40 0 –45 –1 –50 –2 dB dB 70MHz –55 –3 50MHz –4 –60 NYQUIST FREQUENCY 100MHz 20MHz –5 –65 –70 –60 –40 –20 0 20 TC – ⴗC 40 60 80 –6 100 0 TPC 13. 2nd Harmonic vs. Temperature: fS = 200 MSPS 50 100 150 200 250 300 fIN – MHz 350 400 450 500 TPC 16. Frequency Response: fS = 200 MSPS –40 0 FUNDAMENTAL = –0.5dBFS SNR = 45.8dB SINAD = 45.2dB 2ND HARMONIC = 69.8dB 3RD HARMONIC = 61.6dB –10 –45 –20 –50 –30 70MHz –40 dB dB 50MHz –55 –50 20MHz –60 –60 –70 –65 –80 –70 –60 –40 –20 0 20 TC – ⴗC 40 60 80 –90 0 100 TPC 14. 3rd Harmonic vs. Temperature: fS = 135 MSPS 10 20 30 40 50 60 MHz 70 80 90 100 TPC 17. Spectrum: fS = 200 MSPS, fIN = 19.7 MHz –40 0 FUNDAMENTAL = –0.5dBFS SNR = 44.6dB SINAD = 37.6dB 2ND HARMONIC = –63.1dB 3RD HARMONIC = –39.1dB –10 –45 –20 70MHz –50 –30 50MHz dB dB –40 –55 –50 20MHz –60 –60 –70 –65 –80 –70 –60 –40 –20 0 20 TC – ⴗC 40 60 80 –90 100 0 TPC 15. 3rd Harmonic vs. Temperature: fS = 200 MSPS 10 20 30 40 50 MHz 60 70 80 90 100 TPC 18. Spectrum: fS = 200 MSPS, fIN = 70.1 MHz –10– REV. D AD9054A 7 0 F1 = 55.0MHz F2 = 56.0MHz F1 = F2 = –7.0dBFS –10 –20 tV 5 –30 –40 4 ns dB tPD 6 –50 3 –60 –70 2 –80 1 –90 0 –60 –100 0 10 20 30 40 50 MHz 60 70 80 90 100 5.0 2.55 4.5 2.54 4.0 2.53 3.5 2.52 3.0 2.5 2.0 1.5 0 20 TC – ⴗC 40 60 80 100 2.51 2.50 2.49 2.48 1.0 2.47 0.5 2.46 0.0 0.0 –20 TPC 22. Output Delay vs. Temperature VREF OUT – Volts VOH – Volts TPC 19. Two-Tone Intermodulation Distortion –40 2.45 –20 –18 –16 –1.0 –2.0 –3.0 –4.0 –5.0 –6.0 –7.0 –8.0 –9.0 –10.0 IOH – mA –14 –12 –10 –8 –6 IREF OUT – mA –4 –2 0 2 TPC 23. Reference Voltage vs. Reference Load TPC 20. Output Voltage HIGH vs. Output Current 1.0 2.502 0.9 0.8 2.501 VREF OUT – Volts VOL – Volts 0.7 0.6 0.5 0.4 0.3 2.500 2.499 0.2 0.1 0.0 0.0 1.0 2.0 3.0 4.0 5.0 IOL – mA 6.0 7.0 2.498 3.0 8.0 TPC 21. Output Voltage LOW vs. Output Current REV. D 3.5 4.0 4.5 5.0 VDD – Volts 5.5 6.0 6.5 TPC 24. Reference Voltage vs. Power Supply Voltage –11– AD9054A 2.502 These applications require the converter to process inputs with frequency components well in excess of the sampling rate (often with subnanosecond rise times), after which the A/D must settle and sample the input in well under one pixel time. The architecture of the AD9054A is vastly superior to older flash architectures, that not only exhibit excessive input capacitance (which is very hard to drive), but can make major errors when fed a very rapidly slewing signal. The AD9054A’s extremely wide bandwidth Track/Hold circuit processes these signals without difficulty. VREF OUT – Volts 2.501 2.500 Using the AD9054A 2.499 2.498 –40 –20 0 20 40 60 80 Good high speed design practices must be followed when using the AD9054A. To obtain maximum benefit, decoupling capacitors should be physically as close to the chip as possible. We recommend placing a 0.1 µF capacitor at each power-ground pin pair (9 total) for high frequency decoupling, and including one 10 µF capacitor for local low frequency decoupling. The VREF IN pin should also be decoupled by a 0.1 µF capacitor. 100 TAMB – ⴗC TPC 25. Reference Voltage vs. Temperature APPLICATION NOTES The part should be located on a solid ground plane and output trace lengths should be short (<1 inch) to minimize transmission line effects. This avoids the need for termination resistors on the output bus and reduces the load capacitance that needs to be driven, which in turn minimizes on-chip noise due to heavy current flow in the outputs. We have obtained optimum performance on our evaluation board by tying all VDD pins to a quiet analog power supply system, and tying all GND pins to a quiet analog system ground. THEORY OF OPERATION The AD9054A combines Analog Devices’ patented MagAmp bit-per-stage architecture with flash converter technology to create a high performance, low power ADC. For ease of use the part includes an on-board reference and input logic that accepts TTL, CMOS or PECL levels. The analog input signal is buffered by a high-speed differential amplifier and applied to a track-and-hold (T/H) circuit. This T/H captures the value of the input at the sampling instant and maintains it for the duration of the conversion. The sampling and conversion process is initiated by a rising edge on the ENCODE input. Once the signal is captured by the T/H, the four Most Significant Bits (MSBs) are sequentially encoded by the MagAmp string. The residue signal is then encoded by a flash comparator string to generate the four Least Significant Bits (LSBs). The comparator outputs are decoded and combined into the 8-bit result. Minimum Encode Rate The minimum sampling rate for the AD9054A is 25 MHz. To achieve very high sampling rates, the track/hold circuit employs a very small hold capacitor. When operated below the minimum guaranteed sampling rate, the T/H droop becomes excessive. This is first observed as an increase in offset voltage, followed by degraded linearity at even lower frequencies. If the user has selected Single Channel Mode (DEMUX = HIGH), the 8-bit data word is directed to the Channel A output bank. Data are strobed to the output on the rising edge of the ENCODE input with four pipeline delays. If the user has selected Dual Channel Mode (DEMUX = LOW) the data are alternately directed between the A and B output banks and have five pipeline delays. At power-up, the N sample data can appear at either the A or B port. To align the data in a known state the user must strobe DATA SYNC (DS, DS) per the conditions described in the Timing section. Graphics Applications The high bandwidth and low power of the AD9054A make it very attractive for applications that require the digitization of presampled waveforms, wherein the input signal rapidly slews from one level to another and is relatively stable for a period of time. Examples of these include digitizing the output of computer graphic display systems and very high speed solid state imagers. Lower effective sampling rates may be easily supported by operating the converter in dual port output mode and using only one output channel. A majority of the power dissipated by the AD9054A is static (not related to conversion rate) so the penalty for clocking at twice the desired rate is not high. Reference The AD9054A internal reference, VREF, provides a simple, cost effective reference for many applications. It exhibits reasonable accuracy and excellent stability over power supply and temperature variations. The VREF OUT pin can simply be strapped to the VREF IN pin. The internal reference can be used to drive additional loads (up to several mA), including multiple A/D converters as might be required in a triple video converter application. When an external reference is desired for accuracy or other requirements, the AD9054A should be driven directly by the external reference source connected to pin VREF IN (VREF OUT can be left floating). The external reference can be set to 2.5 V ± 0.25 V. If VREF IN is raised by 10% (set to 2.75 V) the analog full-scale range will increase by 10% to 1.024 × 1.1 = 1.1264 V. The new input range will then be AIN ± 0.5632 V. –12– REV. D AD9054A Digital Inputs SNR performance is directly related to the sampling clock stability in A/D converters, particularly for high input frequencies and wide bandwidths. A low jitter clock (<10 ps @ 100 MHz) is essential for optimum performance when digitizing signals that are not presampled. When operating in Single-Channel Mode, the outputs at Port B are held static in a random state. Figure 10 shows the AD9054A used in single-channel output mode. The analog input (±0.5 V) is ac coupled and the ENCODE input is driven by a TTL level signal. The chip’s internal reference is used. ENCODE and Data Select (DS) can be driven differentially or single-ended. For single-ended operation, the complement inputs (ENCODE, DS) are internally biased to VDD/3 (~1.5 V) by a high impedance on-chip resistor divider (Figure 5), but they may be externally driven to establish an alternate threshold if desired. A 0.1 µF decoupling capacitor to ground is sufficient to maintain a threshold appropriate for TTL or CMOS logic. VREF OUT 0.1F VREF IN CLOCK ENC 5V VID a. Driving Differential Inputs Differentially ENC ENC 0.1F ENC 0.1F NC CLOCK NC = NO CONNECT Figure 10. Single Port Mode—AC-Coupled Input—SingleEnded Encode Dual Port Mode The multiplexing is controlled internally via a clock divider, which introduces a degree of ambiguity in the port assignments. Figure 2 illustrates that, prior to synchronization, either Port A or Port B may produce the even or odd samples. This is resolved by exercising the Data Sync (DS) control, a differential input (identical to the ENCODE input), which facilitates operation at high speed. VIH D VID VIC M VIL D b. Driving Differential Inputs Single-Endedly At least once after power-up, and prior to using the conversion data, the part needs to be synchronized by a falling edge (or a positive-going pulse) on DS (observing setup and hold times with respect to ENCODE). If the converter’s internal timing is in conflict with the DS signal when it is exercised, then two data samples (one on each port) are corrupted as the converter is resynchronized. The converter then produces data with a known phase relationship from that point forward. Figure 9. Input Signal Level Definitions Single Port Mode When operated in a Single Port mode (DEMUX = HIGH), the timing of the AD9054A is similar to any high speed A/D Converter (Figure 1). A sample is taken on every rising edge of ENCODE, and the resulting data is produced on the output pins following the FOURTH rising edge of ENCODE after the sample was taken (four pipeline delays). The output data are valid tPD after the rising edge of ENCODE, and remain valid until at least tV after the next rising edge of ENCODE. The maximum clock rate is specified as 100 MSPS. This is recommended because the guaranteed output data valid time equals the Clock Period (1/fS) minus the Output Propagation Delay (tPD) plus the Output Valid Time (tV), which comes to 4.8 ns at 100 MHz. This is about as fast as standard logic is able to capture the data with reasonable design margins. The AD9054A will operate faster in single-channel mode if you are able to capture the data. REV. D DS ENC In Dual Port Mode (DEMUX = LOW), the conversion results are alternated between the two output ports (Figure 2). This limits the data output rate at either port to 1/2 the conversion rate (ENCODE), and supports conversion at up to 200 MSPS with TTL/CMOS compatible interfaces. Dual Channel Mode is required for guaranteed operation above 100 MSPS, but may be enabled at any specified conversion rate. VIL D CLOCK DEMUX DS VIH D VIC M AIN 0.1F Note the 6-diode clock input protection circuitry in Figure 5. This limits the differential input voltage to ~ ± 2.1 V. When the diodes turn on, current is limited by the 300 Ω series resistor. Exceeding 2.1 V across the differential inputs will have no impact on the performance of the converter, but be aware of the clock signal distortion that may be produced by the nonlinear impedance at the converter. ENC AD9054A 1k⍀ VIN When driven differentially, ENCODE and DS will accommodate differential signals centered between 1.5 V and 4.5 V with a total differential swing ≥800 mV (VID ≥ 400 mV). CLOCK A PORT AIN Note that if the converter is already properly synchronized, the DS pulse has no effect on the output data. This allows the converter to be continuously resynchronized by a pulse at 1/2 the ENCODE rate. This signal is often available within a system, as it represents the master clock rate for the demultiplexed output data. Of course, a single DS signal may be used to synchronize multiple A/D converters in a multichannel system. –13– AD9054A Applications that call for the AD9054A to be synchronized at power-up or only periodically during calibration/reset (i.e., valid data is not required prior to synchronization), need only be concerned with the timing of the falling edge of DS. The falling edge of DS must satisfy the setup time defined by Figure 2 and the specification table. In this case the DS hold time specification on the rising edge can be ignored. In Figure 11, the converter is operating in Dual Port Mode, with data coming alternately out of Port A and Port B. The figure illustrates how the output data may be aligned with an output latch to produce a 16-bit output at 1/2 the conversion clock rate. The Data Sync input must be properly exercised to time the A Port with the synchronizing latch. Applications that will continuously update the synchronization command need to treat the DS signal as a pulse and satisfy timing requirements on both rising and falling edges. It is easiest to consider the DS signal in this case to be a pulse train at one half the encode rate, the positive pulse nominally bracketing the ENCODE falling edge on alternate cycles as shown in the timing diagram (Figure 2b). Both the falling and rising edges of DS must satisfy minimum setup (tSDS) and hold (tHDS) times with respect to the falling edges of ENCODE. This timing requirement produces a tight timing window at higher encode rates. Synchronization by a single reset edge results in a simpler timing solution in many applications. For example, synchronization may be provided at the beginning of each graphics line or frame. The data are presented at the output of the AD9054A in a pingpong (alternating) fashion to optimize the performance of the converter. It may be aligned for presentation as sixteen bits in parallel by adding a register stage to the output. In Dual Channel Mode, the converted data is produced five clock cycles after the rising edge of ENCODE on which the sample is taken (five pipeline delays). VREF OUT 0.1F VREF IN A PORT AIN '573 AD9054A 1k⍀ AIN VIN 0.1F B PORT DEMUX DS DS ENC ENC 0.1F DS NC CLOCK '74 DIVIDE BY 2 NC = NO CONNECT Figure 11. Dual Port Mode—Aligned Output Data –14– REV. D AD9054A EVALUATION BOARD Voltage Reference The AD9054A evaluation board offers an easy way to test the AD9054A. It provides dc biasing for the analog input, generates the latch clocks for both full speed and demuxed modes, and includes a reconstruction DAC. The board has several different modes of operation, and is shipped in the following configuration: The AD9054A has an internal 2.5 V voltage reference. An external reference may be employed instead. The evaluation board is configured for the internal reference. To use an external reference, connect it to the (VREF) pin on the power connector and move jumper S102. • • • • Single Port Mode DC-Coupled Analog Input Demuxed Outputs Differential Clocks Internal Voltage Reference. VREF EXT DC BIAS AIN Single Port Mode sets the AD9054A to produce data on every clock cycle on output port A only. To test in this mode, jumper S104 should be set to single channel and S106 and S107 must be set to F (for Full). The maximum speed in single port mode is 100 MSPS. S102 S103 Dual Port Mode VREF OUT Dual Port or half-speed output mode sets the ADC to produce data alternately on Port A and Port B. In this mode, the reset function should be implemented. To test in this mode, set jumper S104 to Dual Channel, and set S106 and S107 to D (for Dual Port). The maximum speed in this mode is 200 MSPS. B PORT VREF IN '574 50⍀ AIN AD9054A AIN RESET BUTTON A PORT 5V RESET '574 DEMUX D D FF RESET drives the AD9054A’s Data Sync (DS) pins. When operating in Single Port Mode, RESET is not used. In DualChannel Mode it is needed for two reasons: to synchronize the timing of Port A data and Port B data with a known clock edge, as described in the data sheet, and to synchronize the evaluation board’s latch clocks with the data coming out of the AD9054A. Reset can be driven in two ways: by pushing the reset button on the board, or externally, with a TTL pulse through connector J5 or J6. S104 C S105 CLK A DS DS ENC ENC CLK B DAC ENC 50⍀ ENC ENC CLK A DAC Out ENC CLOCKING CLK B The DAC output is a representation of the data on output Port A only. Output Port B is not reconstructed. 50⍀ Troubleshooting Figure 12. PCB Block Diagram If the board does not seem to be working correctly, try the following: Analog Input The evaluation board accepts a 1 V input signal centered at ground. The board’s input circuitry then biases this signal to 2.5 V in one of two ways: • Check that all jumpers are in the correct position for the desired mode of operation. 1. DC-coupled through an AD9631 op amp; this is the mode in which it is shipped. Potentiometer R7 provides adjustment of the bias voltage. 2. AC-coupled through C1. These two modes are selected by jumpers S101 and S103. For dc coupling, the S101 jumper is connected between the two left pins and the S103 jumper is connected between the two lower pins. For ac coupling, the S101 jumper is connected between the two right pins and the S103 jumper is connected between the two upper pins. ENCODE The AD9054A ENCODE input can be driven two ways: 1. Differential TTL, CMOS, or PECL; it is shipped in this mode. • Push the reset button. This will align the AD9054A’s data output with the half speed latch clocks. • Switch the jumper S105 from A-R to R-B or vice-versa, then push the reset button. In demuxed mode, this will have the effect of inverting the half speed latch clocks. • At high encode rates, the evaluation board’s clock generation circuitry is sensitive to the 5 V digital power supply. At high encode rates, the 5 V digital power should be kept below 5.2 V. This is an evaluation board sensitivity and not an AD9054A sensitivity. The AD9054A Evaluation Board is provided as a design example for customers of Analog Devices, Inc. ADI makes no warranties, express, statutory, or implied, regarding merchantability or fitness for a particular purpose. 2. Single-ended TTL or CMOS. To use in this mode, remove R11, the 50 Ω chip resistor located next to the ENCODE input, and insert a 0.1 µF ceramic capacitor into the C5 slot. C5 is located between the ENC connector and the ENCODE input to the DUT and is marked on the back side of the board. In this mode, ENCODE is biased with internal resistors to 1.5 V, but it can be externally driven to any dc voltage. REV. D –15– +5VA +5V ENC ENC R1 49.9⍀ 2 C23 10F C9 10F BNC J3 C4 0.1F C24 0.1F C10 0.1F C25 0.1F C11 0.1F R4 140⍀ R5 10⍀ 3 2 Q 4 5 +5V TB1 4 3 C26 0.1F 11 C27 0.1F C13 0.1F +5V GND –5.2V +5VA VREF 6 12 2 C29 0.1F C14 0.1F GND +5VA GND +5VA GND 1 3 –5.2V C30 10F UA1 AD9054ABST 1 3 2 23 22 21 20 19 18 17 16 15 14 13 12 12 5 10H125 U7 10H125 U7 4 +5VA GND GND +5VA 15 C21 0.1F 10H125 14 U7 13 10H125 U7 10 11 6 7 2 3 1 C34 0.1F C20 0.1F 2 3 S105 JUMPER 11 DB3 DB2 DB1 (LSB) DB0 VDD GND GND VDD (LSB) DA0 DA1 DA2 C33 0.1F C19 0.1F 1 3 S107 JUMPER C32 0.1F C18 0.1F 2 S106 JUMPER C5 C31 0.1F C17 0.1F Q1 3 R1 4 S1 2 D1 Q1 C16 0.1F 6 7 U6 GND 1 ENC ENC VREF OUT VREF IN GND VDD GND AIN AIN GND VDD DEMUX DS DS 33 C3 10F 5 10H131 34 35 36 37 38 39 40 41 42 43 44 1 2 3 4 5 6 5PB 510 RP1 2 C15 0.1F 1 3 S104 JUMPER –5.2V +5VA GND R9 100⍀ 1 3 6 C Q CL U2 1 74F74 D PR +5V AD96685R U3 C12 0.1F 5 4 3 2 1 R12 1k⍀ GND VREF +5V ANALOG –5.2V GROUND +5V DIGITAL R11 49.9⍀ R10 49.9⍀ C1 0.1F 2 6 C36, C37, AND R17–R20 NOT INSTALLED FOR STANDARD OPERATION 140⍀ RST +5V 1 3 S101 JUMPER R2 B1 BUTTON BNC J2 +5V AIN BNC J1 3 S103 JUMPER 2 GND +5VA +5VA GND +5VA GND GND VDD VDD GND VDD GND VDD GND VDD GND +5VA GND +5VA GND U1 AD9631R DB7 DB6 DB5 DB4 DA7 DA6 DA5 DA4 DA3 C35 0.1F C22 0.1F 1 1Q 2Q 3Q 4Q 5Q 6Q 7Q 8Q OE 12 13 14 15 16 17 18 19 11 1D 2D 3D 4D 5D 6D 7D 8D CK +5V 28 1 1Q 2Q 3Q 4Q 5Q 6Q 7Q 8Q OE GND RST 1 2 3 4 5 6 7 8 9 10 CLK 12 13 14 15 16 17 18 19 U5 74F574DW 11 1D 2D 3D 4D 5D 6D 7D 8D CK C28 0.1F 9 8 7 6 5 4 3 2 9 8 7 6 5 4 3 2 U4 74F574DW U8 AD9760AR C6 0.1F +5V C8 0.1F 17 16 15 R14 2k⍀ 18 C7 0.1F 27 24 23 19 DVDD VREF AVDD S102 JUMPER COMP2 C2 0.1F COMP1 R3 100⍀ FSADJ R8 2k⍀ REFIO R7 1k⍀ DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 (LSB) REFLO –16– SLEEP R6 2k⍀ A I OUT B 3 13 14 15 16 17 18 19 20 2 11 10 9 8 7 6 5 4 1 12 21 22 H20SM J5 R15 49.9⍀ R39 R21 21 30 31 32 33 34 35 36 37 2 29 28 27 26 25 24 23 22 BNC J4 DRA B8A B7A B6A B5A B4A B3A B2A B1A DRB B1B B2B B3B B4B B5B B6B B7B B8B DAC OUT RESET C37 DRPF J6 20 R16 49.9⍀ R21–R39 100⍀ AD9054A Figure 13. Evaluation Board Schematic REV. D AD9054A REV. D Figure 14. Assembly—Top View Figure 16. Conductors—Top View Figure 15. Assembly—Bottom View Figure 17. Conductors—Bottom View –17– AD9054A BILL OF MATERIALS GS00104 REV. D ITEM QTY PART NUMBER REFERENCE DESCRIPTION MFG/DISTRIBUTOR 11 30 GRM40Z5U104M050BL C1, C2, C4, C6–C8, C10–C22, C24–C29, C31–C35 0.1 µF CER CHIP CAP 0805 TTI 12 1 P10FBK-ND R5 10 Ω SURFACE MT RES 1206 DIGI-KEY 13 21 P100FBK-ND R3, R9, R21–R39 100 Ω SURFACE MT RES 1206 DIGI-KEY 14 4 T491C106M016AS C3, C9, C23, C30 10 µF TANTALUM CHIP CAP TTI 15 2 P140FBK-ND R2, R4 140 Ω SURFACE MT RES 1206 DIGI-KEY 16 1 P1KFBK-ND R12 1 kΩ SURFACE MT RES 1206 DIGI-KEY 17 3 P2KFBK-ND R6, R8, R14 2 kΩ SURFACE MT RES 1206 DIGI-KEY 18 1 3296W-102-ND R7 1k TRIM POT TOP ADJ, 25 TURN DIGI-KEY 19 1 K44-C37S-QJ J6 37P D CONN RT ANG PCMT FEM CENTURY ELEC 10 5 P49.9FBK-ND R1, R10, R11, R15, R16 49.9 Ω SURFACE MT RES 1206 DIGI-KEY 11 1 CSC06A-01-511G RP1 510 Ω 6P BUSED RES NETWORK TTI 12 1 51F54113 TB1 8291Z 3-PIN TERMINAL BLOCK NEWARK 13 1 51F54112 TB1 8291Z 2-PIN TERMINAL BLOCK NEWARK 14 4 AMP-227699-2 J1–J4 BNC COAX CONN PCMT 5 LEAD TIME ELEC 15 1 MC10H131P U6 DIP-16 DUAL D FLIP-FLOP HAMILTON/HALLMARK 16 1 MC10H125P U7 DIP-16 QUAD ECL TO TTL TRANS HAMILTON/HALLMARK 17 1 74F74SC-ND U2 SO-14 FAST TTL DUAL D FLIP-FLOP DIGI-KEY 18 1 TSW-120-08-G-S J5 HEADER STRIP 20P GOLD MALE SAMTEC ALT: 1/2 90F3987 J5 40P HEADER NEWARK 19 1 AD96685BR U3 HIGH SPEED COMP SOIC-16 ANALOG DEVICES, INC. 20 7 S90F9280 S101–S107 SHORTING JUMPER NEWARK 21 8 89F4700 S101–S107, GND 3-PIN HEADER (DIVIDE 1 OF THE 8 FOR 3 GND HOLES) NEWARK 22 2 MC74F574DW U4, U5 SO-20 OCTAL D TYPE FLIP-FLOP HAMILTON/HALLMARK 23 1 AD9631AR U1 SOIC-8 OP AMP ANALOG DEVICES, INC. 24 1 AD9760AR U8 10-BIT CMOS DAC SOIC-28 ANALOG DEVICES, INC. 25 1 AD9054ABST UA1 8-BIT ADC IN 44-LEAD LQFP ANALOG DEVICES, INC. 26 1 P8002SCT-ND B1 SURFACE MOUNT MOMENTARY PUSHBUTTON DIGI-KEY 27 4 90F1533 – BUMPON PROTECTIVE BUMPER NEWARK PARTS NOT ON BILL OF MATERIALS, AND NOT TO BE INSTALLED: C5, C36, C37, R17–R20. –18– REV. D AD9054A OUTLINE DIMENSIONS Dimensions shown in inches and (mm). 44-Lead Plastic Thin Quad Flatpack (LQFP) (ST-44) 0.063 (1.60) MAX 0.472 (12.00) BSC SQ 0.030 (0.75) 0.018 (0.45) 33 23 34 22 SEATING PLANE 0.394 (10.0) BSC SQ TOP VIEW (PINS DOWN) 44 0.006 (0.15) 0.002 (0.05) 0.057 (1.45) 0.053 (1.35) REV. D 12 1 11 0.031 (0.80) BSC –19– 0.018 (0.45) 0.012 (0.30) AD9054A–Revision History Location Page Data Sheet changed from REV. C to REV. D. PRINTED IN U.S.A. C00560–0–7/01(D) Edit to ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 –20– REV. D