CADEKA SPT7725AIG

SPT7725
8-BIT, 300 MSPS, FLASH A/D CONVERTER
TECHNICAL DATA
AUGUST 17, 2001
FEATURES
APPLICATIONS
• Metastable errors reduced to 1 LSB
• Low input capacitance: 10 pF
• Wide input bandwidth: 210 MHz
• 300 MSPS conversion rate
• Typical power dissipation: 2.2 watts
• Digital oscilloscopes
• Transient capture
• Radar, EW, ECM
• Direct RF down-conversion
• Medical electronics: ultrasound, CAT instrumentation
GENERAL DESCRIPTION
of 2.2 W. A proprietary decoding scheme reduces metastable errors to the 1 LSB level.
The SPT7725 is a monolithic flash A/D converter capable
of digitizing a two volt analog input signal into 8-bit digital
words at a 300 MSPS (typ) update rate.
The SPT7725 is available in 42-lead ceramic sidebrazed
DIP, surface-mount 44-lead cerquad, and 46-lead PGA
packages (all are pin-compatible with the SPT7710); the
cerquad and PGA packages allow access to additional
reference ladder taps, an overrange bit, and a data ready
output. The SPT7725 is available in the industrial temperature range.
For most applications, no external sample-and-hold is required for accurate conversion due to the device’s narrow
aperture time, wide bandwidth, and low input capacitance.
A single standard –5.2 volt power supply is required for
operation of the SPT7725, with nominal power dissipation
BLOCK DIAGRAM
Analog Input
(Force or Sense) AGND DGND
VRTS
VEE
Preamp
VRTF
LINV
MINV
Comparator
256
DRINV
Clock
Buffer
MSB D7
255
VR3
DREAD
152
Overrange
151
D7 MSB
D6
128
VR2
127
ECL
Latches
and
Buffers
256 to
8-Bit
Encoder
D5
D4
D6
64
D5
VR1
63
D3
D4
D2
D3
2
D2
D1
D1
1
D0 LSB
VRBF
LSB D0
VRBS
Convert
2
CLK
CLK
Analog Input
(Sense or Force)
VEE
AGND
These functions are
available in the PGA and
cerquad packages only.
ABSOLUTE MAXIMUM RATINGS (Beyond which damage may occur)1 25 °C
Temperature
Operating Temperature,ambient ............. –25 to +85 °C
junction ...................... +150 °C
Lead Temperature, (soldering 10 seconds) ..... +300 °C
Storage Temperature ............................ –65 to +150 °C
Supply Voltages
Negative Supply Voltage (VEE TO GND) –7.0 to +0.5 V
Ground Voltage Differential .................... –0.5 to +0.5 V
Input Voltage
Analog Input Voltage ............................... VEE to +0.5 V
Reference Input Voltage .......................... VEE to +0.5 V
Digital Input Voltage ................................ VEE to +0.5 V
Reference Current VRTF to VRBF ........................ 25 mA
Note: 1. Operation at any Absolute Maximum Rating is not implied. See
Electrical Specifications for proper nominal applied conditions
in typical applications.
Output
Digital Output Current ............................... 0 to –30 mA
ELECTRICAL SPECIFICATIONS
TA= TMIN to TMAX, VEE=–5.2 V, RSource=50 Ω, VRBF=–2.00 V, VR2=–1.00 V, VRTF=0.00 V, ƒCLK=250 MHz, Duty Cycle=50%, unless otherwise specified.
PARAMETERS
DC Accuracy
Integral Linearity Error
Differential Linearity Error
No missing codes
Analog Input
Offset Error VRT
Offset Error VRB
Input Voltage Range
Input Capacitance
Input Resistance
Input Current
Input Slew Rate
Large Signal Bandwidth
Small Signal Bandwidth
Clock Synchronous
Input Currents
TEST
CONDITIONS
ƒCLK = 100 kHz
ƒCLK = 100 kHz
TEST
LEVEL
VI
VI
VI
VI
VI
Over full
input range
VIN=F.S.
VIN=500 mVP-P
MIN
SPT7725A
TYP
MAX
–0.75 ±0.60 +0.75
–0.75
+0.75
Guaranteed
–30
–30
–2.0
+30
+30
0.0
V
V
VI
V
V
V
10
15
250
1,000
210
335
V
40
Reference Input
Ladder Resistance
Reference Bandwidth
VI
V
100
200
10
Timing Characteristics
Maximum Sample Rate
Clock to Data Delay
Output Delay Tempco
CLK-to-Data Ready Delay (tD)
Aperture Jitter
Acquisition Time
IV
V
V
V
V
V
250
VI
VI
VI
VI
VI
VI
45
39
Dynamic Performance
Signal-to-Noise Ratio
Total Harmonic Distortion
Signal-to-Noise and Distortion
(SINAD)
ƒIN = 3.58 MHz
ƒIN = 50 MHz
ƒIN = 3.58 MHz
ƒIN = 50 MHz
ƒIN = 3.58 MHz
ƒIN = 50 MHz
44
37
MIN
SPT7725B
TYP
MAX
–0.95
–0.95
±0.80
+0.95
+0.95
LSB
LSB
+30
+30
0.0
mV
mV
Volts
Guaranteed
–30
–30
–2.0
10
15
250
1,000
210
335
500
500
40
300
UNITS
pF
kΩ
µA
V/µs
MHz
MHz
µA
200
10
300
2.4
2
2.0
5
1.5
250
300
2.4
2
2.0
5
1.5
MSPS
ns
ps/°C
ns
ps
ns
47
42
–52
–43
46
39
44
38
46
41
–50
–42
44
37
dB
dB
dB
dB
dB
dB
–48
–40
42
35
300
Ω
MHz
100
–46
–39
SPT7725
2
8/17/01
ELECTRICAL SPECIFICATIONS
TA= TMIN to TMAX, VEE=–5.2 V, RSource=50 Ω, VRBF=–2.00 V, VR2=–1.00 V, VRTF=0.00 V, ƒCLK=250 MHz, Duty Cycle=50%, unless otherwise specified.
PARAMETERS
TEST
CONDITIONS
TEST
LEVEL
MIN
VI
–1.1
VI
VI
VI
–2.0
2.2
2.2
–1.1
Digital Inputs
Digital Input High Voltage
(MINV, LINV)
Digital Input Low Voltage
(MINV, LINV)
Clock Low Width, tPWL
Clock High Width, tPWH
Digital Outputs
Digital Output High Voltage
Digital Output Low Voltage
50 Ω to –2 V
50 Ω to –2 V
VI
VI
Power Supply Requirements
Supply Current
Power Dissipation
+25 °C
+25 °C
VI
VI
TEST LEVEL CODES
All electrical characteristics are subject to the
following conditions:
All parameters having min/max specifications
are guaranteed. The Test Level column indicates the specific device testing actually performed during production and Quality Assurance inspection. Any blank section in the data
column indicates that the specification is not
tested at the specified condition.
LEVEL
I
II
III
IV
V
VI
SPT7725A
TYP
MAX
MIN
SPT7725B
TYP
MAX
–0.7
–1.1
–1.5
–2.0
2
2
2.0
2.0
–0.7
Volts
–1.5
Volts
ns
ns
1.8
1.8
–1.1
–1.5
425
2.2
550
2.9
–1.5
425
2.2
UNITS
550
2.9
Volts
Volts
mA
W
TEST PROCEDURE
100% production tested at the specified temperature.
100% production tested at TA = +25 °C, and sample tested at the
specified temperatures.
QA sample tested only at the specified temperatures.
Parameter is guaranteed (but not tested) by design and characterization data.
Parameter is a typical value for information purposes only.
100% production tested at TA = +25 °C. Parameter is guaranteed
over specified temperature range.
Unless otherwise noted, all test are pulsed
tests; therefore, TJ = TC = TA.
SPT7725
3
8/17/01
TYPICAL PERFORMANCE CHARACTERISTICS
SNR vs Input Frequency
THD vs Input Frequency
52
75
50
70
ƒS = 250 MSPS
Total Harmonic Distortion (dB)
Signal-to-Noise Ratio (dB)
48
46
44
42
40
38
36
34
ƒS = 250 MSPS
65
60
55
50
45
40
35
1
10
30
100
1
10
100
Input Frequency (MHz)
Input Frequency (MHz)
SINAD vs Input Frequency
SNR, THD, SINAD vs Temperature
52
50
ƒS = 250 MSPS
ƒIN = 100 MHz
ƒS = 250 MSPS
48
SNR, THD, SINAD (dB)
Signal-to-Noise and Distortion (dB)
50
46
44
42
40
38
45
THD
SNR
40
SINAD
35
36
34
1
10
100
Input Frequency (MHz)
30
–40
–20
0
20
40
60
80
Temperature (°C)
SPT7725
4
8/17/01
Figure 1 – Typical Interface Circuit 1
L
*See below
RT
+
U1
–
Voltage
Limiter
Analog Input
Can Be Either
Force Or Sense
VEE
2.2 µF
AGND
–5.2 V
.01 µF
VIN
LINV
MINV
VRTF
Preamp
Comparator
MSB D7
256
Clock
Buffer
255
D6
152
Typical Voltage Limiter
D5
RS
49.9
151
D1
D2
–5.2
D1=D2=HP, 1N 5712
D4
128
VR2
256 To
8-Bit
Encoder
.01 µF
127
ECL
Latches
And
Buffers
D3
64
D2
63
VEE
D1
2
10
Analog Input
Can Be Either
Force Or Sense
Q1 (1N2907A)
VEE
LSB D0
VIN
CLK
50 W
100116
50 W
Convert
1
VRBF
2.2 µF
2.2
+
U2
–
.01 µF
–2 V
.01 µF
VRef
2
CLK
.01 µF
–2 V
(Analog)
50 W
50 W
AGND
DGND
.01 µF
VEE
.01 µF
–2 V (Digital)
–5.2 V
GENERAL DESCRIPTION
The SPT7725 has true differential analog and digital data
paths from the preamplifiers to the output buffers (Current
Mode Logic) for reducing potential missing codes while
rejecting common mode noise.
The SPT7725 is a fast monolithic 8-bit parallel flash A/D
converter. The nominal conversion rate is 300 MSPS and
the analog bandwidth is in excess of 200 MHz. A major advance over previous flash converters is the inclusion of
256 input preamplifiers between the reference ladder and
input comparators. (See block diagram.) This not only reduces clock transient kickback to the input and reference
ladder due to a low AC beta but also reduces the effect of
the dynamic state of the input signal on the latching characteristics of the input comparators. The preamplifiers act
as buffers and stabilize the input capacitance so that it remains constant for varying input voltages and frequencies
and, therefore, makes the part easier to drive than previous flash converters. The SPT7725 incorporates a proprietary decoding scheme that reduces metastable errors
(sparkle codes or flyers) to a maximum of 1 LSB.
Signature errors are also reduced by careful layout of the
analog circuitry. Every comparator also has a clock buffer
to reduce differential delays and to improve signal-tonoise ratio. The output drive capability of the device can
provide full ECL swings into 50 Ω loads.
TYPICAL INTERFACE CIRCUIT
The typical interface circuit is shown in figure 1. The
SPT7725 is relatively easy to apply depending on the
accuracy needed in the intended application. Wire-wrap
may be employed with careful point-to-point ground connections if desired, but to achieve the best operation, a
SPT7725
5
8/17/01
Figure 2 – Typical Interface Circuit 2 (PGA and Cerquad packages only)
*See below
RT
+
U1
–
Voltage
Limiter
VCC
10 W
VCC
22
+
U1
–
VEE
Q1
Analog
Input
Force
2.2 µF
.01 µF
VRTS
L
.01 µF
49.9
Preamp
MINV
Comparator
256
Overrange
D8
Clock
Buffer
R
D1
LINV
VIN
Typical Voltage Limiter
RS
–5.2 V
2.2 µF
D1
VRTF
VEE
DGND AGND
192
D2
MSB
D7
–5.2
+
–
U2
191
10-25 W VR3
D6
.01 µF
U1 and U2=
Rail-to-Rail Op Amp
151
R
D1=HP, 1N5712
D5
Q1=1N2222A
128
10-25 W V
+
R2
U2
–
Q2=1N2907A
R = 1 kW, .1%
.01 µF
127
R
ECL
Latches
And
Buffers
256 to
8-Bit
Encoder
D4
D3
+
U2
–
10-25 W
64
VR1
D2
.01 µF
63
D1
R
2
LSB
D0
VEE
VREF
–2 V
1
22 W
+
U2
–
VRBF
CLK
50 W
100116
50 W
Convert
DRINV
VRBS
.01 µF
2.2 µF
VEE .01 µF
–2 V
(Analog)
DREAD
2
AGND
CLK
Analog Input VIN
(Sense)
.01 µF
VEE
50 W
50 W
AGND
–2 V
.01 µF
.01 µF
.01 µF
–2 V (Digital)
–5.2 V
VEE
VEE, AGND, DGND
double-sided PC board with a ground plane on the component side separated into digital and analog sections will
give the best performance. The converter is bonded-out to
place the digital pins on the left side of the package and
the analog pins on the right side. Additionally, an RF bead
connection through a single point from the analog to digital ground planes will reduce ground noise pickup.
VEE is the supply pin with AGND as ground for the device.
The power supply pins should be bypassed as close to the
device as possible with at least a .01 µF ceramic capacitor. A 1 µF tantalum should also be used for low frequency
suppression. DGND is the ground for the ECL outputs and
is to be referenced to the output pulldown voltage and
appropriately bypassed as shown in figure 1.
The circuit in figure 2 (PGA and cerquad packages only) is
intended to show the most elaborate method of achieving
the least error by correcting for integral nonlinearity, input
induced distortion, and power supply/ground noise. This is
achieved by the use of external reference ladder tap connections, an input buffer, and supply decoupling. The function of each pin and external connections to other components is as follows:
VIN (ANALOG INPUT)
There are two analog input pins that are tied to the same
point internally. Either one may be used as an analog input
sense and the other for input force. This is convenient for
testing the source signal to see if there is sufficient drive
capability. The pins can also be tied together and driven by
SPT7725
6
8/17/01
Table I – Output Coding
ANALOG INPUT VOLTAGE
–2 V + 1/2 LSB
–1.0 V
0 V – 1/2 LSB
≥0 V
BINARY
TWOs COMPLEMENT
TRUE
INVERTED
MINV=LINV=0
MINV=LINV=1
D8
D7_____D0
D7_____D0
D7_____D0
D7_____D0
0
00000000
11111111
10000000
01111111
00000001
11111110
10000001
01111110
01111111
10000000
11111111
00000000
10000000
01111111
00000000
11111111
11111111
00000000
01111111
10000000
11111110
00000001
01111110
10000001
11111111
00000000
01111111
10000000
0
0
1
the same source. The SPT7725 is superior to similar devices, due to a preamplifier stage before the comparators.
This makes the device easier to drive because it has constant capacitance and induces less slew rate distortion.
An optional input buffer may be used.
TRUE
INVERTED
MINV=1; LINV=0 MINV=0; LINV=1
VRBF, VRBS, VR1, VR2, VR3, VRTF, VRTS REFERENCE
INPUTS (PGA AND CERQUAD PACKAGES ONLY)
These are five external reference voltage taps from –2 V
(VRBF) to AGND (VRTF) that can be used to control integral
linearity over temperature. The taps can be driven by op
amps as shown in figure 2. These voltage level inputs can
be bypassed to AGND for further noise suppression if so
desired. VRB and VRT have force and sense pins for monitoring the top and bottom voltage references.
CLK, CLK (CLOCK INPUTS)
The clock inputs are designed to be driven differentially
with ECL levels. The clock may be driven single-ended
since CLK is internally biased to –1.3 V. (See clock input
circuit.) CLK may be left open, but a .01 µF bypass capacitor from CLK to AGND is recommended. NOTE: System
performance may be degraded due to increased clock
noise or jitter.
N/C
All Not Connected pins should be tied to DGND on the left
side of the package and to AGND on the right side of the
package.
MINV, LINV (OUTPUT LOGIC CONTROL)
DREAD – DATA READY; DRINV – DATA READY
INVERSE (PGA AND CERQUAD PACKAGES ONLY)
These are ECL-compatible digital controls for changing
the output code from straight binary to two’s complement,
etc. For more information, see table I. Both MINV and
LINV are in the logic low (0) state when they are left open.
The high state can be obtained by tying to AGND through
a diode or 3.9 kΩ resistor.
The data ready pin is a flag that goes high or low at the
output when data is valid or ready to be received. It is essentially a delay line that accounts for the time necessary for information to be clocked through the SPT7725’s
decoders and latches. This function is useful for interfacing with high-speed memory. Using the data ready output
to latch the output data ensures minimum set-up and hold
times. DRINV is a data ready inverse control pin. (See the
timing diagram.)
D0 TO D7 (DIGITAL OUTPUTS)
The digital outputs can drive ECL levels into 50 Ω when
pulled down to –2 V. When pulled down to –5.2 V, the outputs can drive 150 Ω to 1 kΩ loads.
VRBF, VR2, VRTF (REFERENCE INPUTS)
D8 – OVERRANGE (PGA AND CERQUAD PACKAGES
ONLY)
There are two reference inputs and one external reference
voltage tap. These are –2 V (VRBF), mid-tap (VR2), and
AGND (VRTF). The reference pins can be driven as shown
in figure 1. VR2 should be bypassed to AGND for further
noise suppression.
This is an overrange function. When the SPT7725 is in an
overrange condition, D8 goes high and all data outputs go
high as well. This makes it possible to include the
SPT7725 into higher resolution systems.
SPT7725
7
8/17/01
OPERATION
sequence from the top comparators, closest to VRTF (0 V),
down to the point where the magnitude of the input signal
changes sign (thermometer code). The output of each
comparator is then registered into four 64-to-6 bit decoders when CLK is changed from high to low.
The SPT7725 has 256 preamp/comparator pairs that are
each supplied with the voltage from VRTF to VRBF divided
equally by the resistive ladder as shown in the block diagram. This voltage is applied to the positive input of each
preamplifier/comparator pair. An analog input voltage applied at VIN is connected to the negative inputs of each
preamplifier/comparator pair. The comparators are then
clocked through each comparator’s individual clock buffer.
When CLK pin is in the low state, the master or input stage
of the comparators compares the analog input voltage to
the respective reference voltage. When CLK changes
from low to high, the comparators are latched to the state
prior to the clock transition and output logic codes in
At the output of the decoders is a set of four 7-bit latches
that are enabled (track) when CLK changes from high to
low. From here, the outputs of the latches are coded into
6 LSBs from 4 columns, and 4 columns are coded into
2 MSBs. Next are the MINV and LINV controls for output
inversions, which consist of a set of eight XOR gates.
Finally, 8 ECL output latches and buffers are used to drive
the external loads. The conversion takes one clock cycle
from the input to the data outputs.
Figure 3 – Timing Diagram
N+2
N
Analog Input
N+1
VIN
tPW1
tPW0
Clock CLK
CLK
Master
Comparator Output
Internal Timing
Slave
6 Bit Latch Output
8 Bit Latch Output
N–1
Data Output D0–D7
Overrange D8
N
N+1
tD
Data Ready
Timing for PGA and Cerquad Packages Only
SPT7725
8
8/17/01
Figure 4 – Subcircuit Schematics
Input Circuit
Output Circuit
AGND
AGND
MINV, LINV Input Circuit
DGND
AGND
10 kW
VIN
VR
MINV
LINV
–1.3 V
Data Out
16 kW
VEE
VEE
Figure 5 – Clock Input
Figure 6 – Burn-In Circuit (42-lead DIP Package only)
VEE
AGND
1N4736
–2.0 V
VREF
R4
R4
R3
CLK
VEE
–1.3 V
VRBF
13 kW
R1 R1 R1 R1 R1 R1 R1 R1
CLK
D0
D1
13 kW
VIN
R2
D2
VIN
D3
D4
D5
VEE
D6
R2
CLK
EVALUATION BOARDS
R2
D7
CLK
CLK
LINV
DGND
AGND
VRTF
CLK
MINV
R2
The EB7725 evaluation board is available to aid designers
in demonstrating the full performance of the SPT7725.
This board includes a voltage reference circuit, clock
driver circuit, output data latches, and an on-board reconstruction of the digital data. An application note describing
the operation of this board, as well as application tips, is
also available. Contact the factory for price and delivery.
R1 = 50 W 1/4 Watt CC 5%
R2 = 1 kW 1/4 Watt CC 5%
R3 = 6.5 W 1/4 Watt CC 5%
–2.0 V
R4 = 6.5 W 1/2 Watt CC 5%
VREF = –2.0 Volts
VEE = –6.6 Volts
SPT7725
9
8/17/01
PACKAGE OUTLINES
42-Lead Sidebrazed DIP
42
SYMBOL
A
B
C
D
E
F
G
H
I
J
1
G
A
E
C
B
F
D
H
INCHES
MIN
MAX
0.081
0.099
0.016
0.020
0.095
0.105
.050 typ
.050 typ
0.275
2.080
2.120
0.585
0.605
0.008
0.015
0.600
0.620
MILLIMETERS
MIN
MAX
2.06
2.51
0.41
0.51
2.41
2.67
1.27
1.27
6.99
52.83
53.85
14.86
15.37
0.20
0.38
15.24
15.75
INCHES
MIN
MAX
0.890
0.910
0.100 typ
.045 dia
.055 dia
0.084
0.096
0.169
0.193
.020 dia
.030 dia
.050 typ
MILLIMETERS
MIN
MAX
22.61
23.11
2.54 typ
1.14
1.40
2.13
2.44
4.29
4.90
0.51
0.76
1.27 typ
I
J
46-Lead Pin Grid Array
D
A
SYMBOL
A
B
C
D
E
F
G
E
B
Pin 1
F
Stand-off Pin
C Diameter
G
SPT7725
10
8/17/01
44-Lead Cerquad
SYMBOL
A
B
C
D
E
F
G
H
C
A
D
B
INCHES
MIN
MAX
0.550 typ
0.685
0.709
0.037
0.041
0.016 typ
0.008 typ
0.027
0.051
0.006 typ
0.080
0.089
MILLIMETERS
MIN
MAX
13.97 typ
17.40
18.00
0.94
1.04
0.41 typ
0.20 typ
0.69
1.30
0.15 typ
2.03
2.26
A
B
0–5°
H
G
E
F
SPT7725
11
8/17/01
PIN ASSIGNMENTS
9
8
7
6
5
4
3
2
1
D8
D6
D5
D4
D3
D2
D1
D0
DGND
AGND
D7
A
VEE
DGND
CLK
MINV
VEE
CLK
AGND
AGND
DREAD AGND
Bottom
N/C
VEE
LINV
DRINV
B
C
D
E
View
VEE
AGND
VRTS
AGND
F
PGA
VRBS
VEE
N/C
VRTF
VRBF
VR1
VR3
VEE
G
H
J
D0
DGND
D1
N/C
VEE
N/C 42
2
N/C
VRTF 41
3
LINV
N/C 40
4
VEE
VEE
39
5
AGND
VEE
38
6
DGND
7
D0 (LSB)
8
D1
AGND 35
9
D2
VIN 34
10
D3
11
D4
VR2 32
12
D5
AGND 31
13
D6
14
D7 (MSB)
15
DGND
N/C 28
16
AGND
N/C 27
17
VEE
VEE 26
18
MINV
VEE
19
N/C
N/C 24
20
CLK
VRBF 23
21
CLK
DGND
1
33
AGND
AGND
2
32
VEE
VEE
3
31
LINV
MINV
4
30
N/C
CLK
5
29
DRINV
CLK
6
28
N/C
VEE
7
27
VEE
AGND
8
26
AGND
AGND
9
25
AGND
VRBS
10
24
VRTS
VRBF
11
23
VRTF
18
19
20
21
22
VIN
AGND
VR3
VEE
17
VR2
AGND
15
16
14
VIN
AGND
AGND
12
13
VR1
Cerquad
VEE
DIP
PIN FUNCTIONS
Name
Function
LINV
D0 through D6 Output Inversion Control Pin
N/C 37
VEE
Negative Analog Supply Nominally –5.2 V
N/C 36
DGND
Digital Ground
D0
Digital Data Output (LSB)
AGND 33
VIN
30
AGND 29
N/C
25
22
34
35
DREADY
AGND
36
38
D2
VIN
37
D4
D3
AGND
39
D6
D5
VR2
41
42
44
D8
AGND
40
VIN
D7
AGND
43
N/C
1
D1–D6
Digital Data Output
D7
Digital Data Output (MSB)
MINV
D7 Output Inversion Control Pin
CLK
Inverse ECL Clock Input Pin
CLK
ECL Clock Input Pin
AGND
Analog Ground
VIN
Analog Input; Can be Connected to the
Input Signal or Used as a Sense
VR2
Reference Voltage Tap 2 (–1.0 V typ)
VRTF
Reference Voltage Top
VRBF
Reference Voltage Bottom
The following pins are on PGA and cerquad packages only.
DRINV
Data Ready Inverse
DREAD
Data Ready Output
Overrange Overrange Output D8
VR1
Reference Voltage Tap 1 (–1.5 V typ)
VR3
Reference Voltage Tap 3 (–0.5 V typ)
VRTS
Reference Voltage Top, Sense
VRBS
Reference Voltage Bottom, Sense
ORDERING INFORMATION
PART NUMBER
SPT7725AIJ
SPT7725BIJ
SPT7725AIG
SPT7725BIG
SPT7725AIQ
SPT7725BIQ
SPT7725BCU
LINEARITY
0.75 LSB
0.95 LSB
0.75 LSB
0.95 LSB
0.75 LSB
0.95 LSB
0.95 LSB
TEMPERATURE RANGE
–25 to +85 °C
–25 to +85 °C
–25 to +85 °C
–25 to +85 °C
–25 to +85 °C
–25 to +85 °C
+25 °C
PACKAGE TYPE
42L Ceramic S/B
42L Ceramic S/B
46L PGA
46L PGA
44L Cerquad
44L Cerquad
Die*
*Please see the die specification for guaranteed electrical performance.
SPT7725
12
8/17/01