TUSB9261 USB 3.0 TO SATA BRIDGE Data Manual PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Literature Number: SLLSE67F March 2011 – Revised July 2013 TUSB9261 www.ti.com SLLSE67F – MARCH 2011 – REVISED JULY 2013 Contents 1 MAIN FEATURES 1.1 1.2 ................................................................................................................ 5 TUSB9261 Features ........................................................................................................ 5 Target Applications ......................................................................................................... 5 8 ....................................................................................................... 6 ...................................................................................... 6 INTRODUCTION .................................................................................................................. 7 3.1 System Overview ........................................................................................................... 7 3.2 Device Block Diagram ...................................................................................................... 7 OPERATION ....................................................................................................................... 9 4.1 General Functionality ....................................................................................................... 9 4.2 Firmware Support ......................................................................................................... 10 4.3 GPIO/PWM LED Designations .......................................................................................... 10 4.4 Power Up and Reset Sequence ......................................................................................... 11 SIGNAL DESCRIPTIONS ..................................................................................................... 12 CLOCK CONNECTIONS ...................................................................................................... 17 6.1 Clock Source Requirements ............................................................................................. 17 6.2 Clock Source Selection Guide ........................................................................................... 17 6.3 Oscillator .................................................................................................................... 18 6.4 Crystal ...................................................................................................................... 18 ELECTRICAL SPECIFICATIONS .......................................................................................... 19 7.1 Absolute Maximum Ratings .............................................................................................. 19 7.2 Thermal Information ....................................................................................................... 19 7.3 Recommended Operating Conditions .................................................................................. 19 7.4 DC Electrical Characteristics for 3.3-V Digital I/O ..................................................................... 20 POWER CONSUMPTION ..................................................................................................... 21 2 Contents 2 RELATED DOCUMENTS 2.1 3 4 5 6 7 TUSB9261 Related Documentation Copyright © 2011–2013, Texas Instruments Incorporated TUSB9261 www.ti.com SLLSE67F – MARCH 2011 – REVISED JULY 2013 List of Figures 3-1 Device Block Diagram ............................................................................................................. 8 6-1 Typical Crystal Connections .................................................................................................... 17 Copyright © 2011–2013, Texas Instruments Incorporated List of Figures 3 TUSB9261 SLLSE67F – MARCH 2011 – REVISED JULY 2013 www.ti.com List of Tables 4-1 GPIO/PWM LED Designations ................................................................................................. 10 5-1 I/O Definitions ..................................................................................................................... 13 5-2 Clock and Reset Signals ........................................................................................................ 13 5-3 SATA Interface Signals .......................................................................................................... 13 5-4 USB Interface Signals ........................................................................................................... 14 5-5 Serial Peripheral Interface (SPI) Signals ...................................................................................... 14 5-6 JTAG, GPIO, and PWM Signals ............................................................................................... Power and Ground Signals ..................................................................................................... Oscillator Specification .......................................................................................................... Crystal Specification ............................................................................................................. SuperSpeed USB Power Consumption ....................................................................................... High Speed USB Power Consumption ........................................................................................ 15 5-7 6-1 6-2 8-1 8-2 4 List of Tables 16 18 18 21 21 Copyright © 2011–2013, Texas Instruments Incorporated TUSB9261 www.ti.com SLLSE67F – MARCH 2011 – REVISED JULY 2013 USB 3.0 TO SATA BRIDGE Check for Samples: TUSB9261 1 MAIN FEATURES 1.1 TUSB9261 Features • Universal Serial Bus (USB) – SuperSpeed USB 3.0 Compliant - TID 340730020 • Integrated Transceiver Supports SS/HS/FS Signaling – Best in Class Adaptive Equalizer • Allows for Greater Jitter Tolerance in the Receiver – USB Class Support • USB Attached SCSI Protocol (UASP) • USB Mass Storage Class Bulk-Only Transport (BOT) • Support for Error Conditions Per the 13 Cases (Defined in the BOT Specification) • USB Bootability Support • USB Human Interface Device (HID) – Supports Firmware Update Via USB, Using a TI Provided Application • SATA Interface – Serial ATA Specification Revision 2.6 • gen1i, gen1m, gen2i, and gen2m – Support for Mass-Storage Devices Compatible With the ATA/ATAPI-8 Specification • Integrated ARM Cortex M3 Core – Customizable Application Code Loaded From EEPROM Via SPI Interface – Two Additional SPI Port Chip Selects for Peripheral Connection – Up to 12 GPIOs for End-User Configuration • 2 GPIOs Have PWM Functionality for LED Blink Speed Control – Serial Communications Interface for Debug (UART) • General Features – Integrated Spread Spectrum Clock Generation Enables Operation from a Single Low Cost Crystal or Clock Oscillator • Supports 20, 25, 30 or 40 MHz – A JTAG Interface is Used for IEEE1149.1 and IEEE1149.6 Boundary Scan – Available in a Fully RoHS Compliant Package 1 1.2 • • • • Target Applications External HDD/SSD External DVD External CD HDD-Based Portable Media Player 1 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2011–2013, Texas Instruments Incorporated TUSB9261 SLLSE67F – MARCH 2011 – REVISED JULY 2013 www.ti.com 2 RELATED DOCUMENTS 2.1 TUSB9261 Related Documentation 1. TUSB9260 Implementation Guide (SLLA301) 2. TUSB9260/TUSB9261 Flash Burner User Guide (SLLU125) 6 RELATED DOCUMENTS Copyright © 2011–2013, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TUSB9261 TUSB9261 www.ti.com SLLSE67F – MARCH 2011 – REVISED JULY 2013 3 INTRODUCTION 3.1 System Overview The TUSB9261 is an ARM cortex M3 microcontroller based USB 3.0 to serial ATA bridge. It provides the necessary hardware and firmware to implement a USB attached SCSI protocol (UASP) compliant mass storage device suitable for bridging hard disk drives (HDD), solid state disk drives (SSD), optical drives and other compatible SATA 1.5-Gbps or SATA 3.0-Gbps devices to a USB 3.0 bus. In addition to UASP support, the firmware implements the mass storage class bulk-only transport (BOT), and USB human interface device (HID) interfaces. USB 3.0 (1) SuperSpeed PC with USB 3.0 Support SATA Gen1/2 HDD USB 2.0 (1) High-speed TUSB9260 TUSB9261 (1) 3.2 USB connection is made at either SuperSpeed or High-Speed depending on the upstream connection support. Device Block Diagram The major functional blocks are as follows: • Cortex M3 microcontroller subsystem including the following peripherals: – Time interrupt modules, including watchdog timer – Universal asynchronous receive/transmit (SCI) – Serial peripheral interface (SPI) – General purpose input/output (GPIO) – PWM for support of PWM outputs (PWM) • USB 3.0 Core (endpoint controller) and integrated USB 3.0 PHY • AHCI compliant SATA controller and integrated SATA PHY – Supporting gen1i, gen1m, gen2i, and gen2m • Chip level clock generation and distribution • Support for JTAG 1149.1 and 1149.6 INTRODUCTION Copyright © 2011–2013, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TUSB9261 7 TUSB9261 SLLSE67F – MARCH 2011 – REVISED JULY 2013 ROM www.ti.com GRSTz ARM Cortex M3 VDD3.3 RAM 64 kB VDD1.1 TCK TMS TDO TDI TRST JTAG Data Path RAM 80 kB XI Clock Generation Power and Reset Distribution USB 3.0 Device Controller X0 SATA AHCI Watchdog Timer Timer USB_R1 USB_R1RTN DP/DM USB HS/FS PHY VBUS SSTX+ SSTX- SSRX+ SSRX- USB SS PHY SATARX+ SATARX- SATATX+ SATATX- PWM[1:0] CS[2:0] DATA_IN SCLK GPIO[11:0] GPIO PWM SPI DATA_OUT UartRX UartTX SCI (UART) SATA II PHY Figure 3-1. Device Block Diagram 8 INTRODUCTION Copyright © 2011–2013, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TUSB9261 TUSB9261 www.ti.com 4 OPERATION 4.1 General Functionality SLLSE67F – MARCH 2011 – REVISED JULY 2013 The TUSB9261 ROM contains boot code that executes after a global reset which performs the initial configuration required to load a firmware image from an attached SPI flash memory to local RAM. Once the firmware is loaded it configures the SATA advanced host controller interface host bus adapter (AHCI) and the USB device controller. In addition, the configuration of the AHCI includes a port reset which initiates an out of band (OOB) TX sequence from the AHCI link layer to determine if a device is connected, and if so negotiate the connection speed with the device (3.0 Gbps or 1.5 Gbps). The configuration of the USB device controller includes creation of the descriptors, configuration of the device endpoints for support of UASP and USB mass storage class bulk-only transport (BOT), allocation of memory for the transmit request blocks (TRBs), and creation of the TRBs necessary to transmit and receive packet data over the USB. In addition, the firmware provides any other custom configuration required for application specific implementation, for example a HID interface for user initiated backup. After USB device controller configuration is complete, if a SATA device was detected during the AHCI configuration the firmware connects the device to the USB bus when VBUS is detected. According to the USB 3.0 specification, the TUSB9261 will initially try to connect at SuperSpeed USB, if successful it will enter U0; otherwise, after the training time out it will enable the DP pull up and connect as a USB 2.0 high-speed or full-speed device depending on the speed supported by host or hub port. When connected, the firmware presents the BOT interface as the primary interface and the UASP interface as the secondary interface. If the host stack is UASP aware, it can enable the UASP interface using a SET_INTERFACE request for alternate interface 1. Following speed negotiation, the device should transmit a device to host (D2H) FIS with the device signature. This first D2H FIS is received by the link layer and copied to the port signature register. When firmware is notified of the device connection it queries the device for capabilities using the IDENTIFY DEVICE command. Firmware then configures the device as appropriate for its interface and features supported, for example an HDD that supports native command queuing (NCQ). OPERATION Copyright © 2011–2013, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TUSB9261 9 TUSB9261 SLLSE67F – MARCH 2011 – REVISED JULY 2013 4.2 www.ti.com Firmware Support Default firmware support is provided for the following: • SuperSpeed USB and USB 2.0 High-Speed and Full-Speed • USB Attached SCSI Protocol (UASP) • USB Mass Storage Class (MSC) Bulk-Only Transport (BOT) – Including the 13 Error Cases • USB Mass Storage Specification for Bootability • USB Device Class Definition for Human Interface Devices (HID) – Firmware Update and Custom Functionality (e.g. One-Touch Backup) • Serial ATA Advanced Host Controller Interface (AHCI) • General Purpose Input/Output (GPIO) – LED Control and Custom Functions (e.g. One-Touch Backup Control) • Pulse Width Modulation (PWM) – LED Dimming Control • Serial Peripheral Interface (SPI) – Firmware storage and storing Custom Device Descriptors • Serial Communications Interface (SCI) – Debug Output Only 4.3 GPIO/PWM LED Designations The default firmware provided by TI drives the GPIO and PWM outputs as listed in the table below. Table 4-1. GPIO/PWM LED Designations GPIO0 SW heartbeat 00: U3 state or default 01: U2 state GPIO1/GPIO5 USB3 power state (U0-U3) GPIO2 HS/FS suspend GPIO3 Push button input on customer board GPIO4 Not used GPIO6 FS/HS connected GPIO7 SS connected PWM0 Disk activity PWM1 U3 or HS/FS suspend state (fades high and low) GPIO10 (SPICS1) Not used GPIO11 (SPICS2) Not used 10: U1 state 11: U0 state The LED’s on the TUSB9261 Product Development Kit (PDK) board are connected as in the table above. Please see the TUSB9261 PDK Guide for more information on GPIO LED connection and usage. This EVM is available for purchase, contact TI for ordering information. 10 OPERATION Copyright © 2011–2013, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TUSB9261 TUSB9261 www.ti.com 4.4 SLLSE67F – MARCH 2011 – REVISED JULY 2013 Power Up and Reset Sequence The TUSB9261 does not have specific power sequencing requirements with respect to the core power (VDD), I/O power (VDD33), or analog power (VDDA33). The core power (VDD) or IO power (VDD33) may be powered up for an indefinite period of time while others are not powered up if all of these constraints are met: • All maximum ratings and recommended operating conditions are observed. • All warnings about exposure to maximum rated and recommended conditions are observed, particularly junction temperature. These apply to power transitions as well as normal operation. • Bus contention while VDD33 is powered up must be limited to 100 hours over the projected life-time of the device. • Bus contention while VDD33 is powered down may violate the absolute maximum ratings. A supply bus is powered up when the voltage is within the recommended operating range. It is powered down when it is below that range, either stable or in transition. A minimum reset duration of 2 ms is required. This is defined as the time when the power supplies are in the recommended operating range to the de-assertion of GRSTz. OPERATION Copyright © 2011–2013, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TUSB9261 11 TUSB9261 SLLSE67F – MARCH 2011 – REVISED JULY 2013 5 www.ti.com SIGNAL DESCRIPTIONS PVP PACKAGE (TOP VIEW) VDD VDDA33 USB_DM USB_DP NC USB_R1 USB_R1RTN VDDA33 VDD USB_SSTXM USB_SSTXP VSS USB_SSRXM USB_SSRXP VDD VDDA33 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 VDD USB_VBUS VDD33 XI VSSOSC XO VDD SATA_TXM SATA_TXP VSS SATA_RXM SATA_RXP VDD VDDA33 VDD NC 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 65 VSS VDD FREQSEL1 FREQSEL0 JTAG_TRSTz JTAG_TMS JTAG_TDO JTAG_TDI JTAG_TCK VDD33 SPI_CS2 / GPIO11 SPI_CS1 / GPIO10 SPI_CS0 SPI_DATA_IN VDD SPI_DATA_OUT SPI_SCLK 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 GPIO7 GPIO6 GPIO5 GPIO4 VDD GPIO3 GPIO2 GPIO1 GPIO0 VDD33 GPIO9 / UART_TX GPIO8 / UART_RX GRSTz PWM1 PWM0 VDD 12 SIGNAL DESCRIPTIONS Copyright © 2011–2013, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TUSB9261 TUSB9261 www.ti.com SLLSE67F – MARCH 2011 – REVISED JULY 2013 Table 5-1. I/O Definitions I/O TYPE DESCRIPTION I Input O Output I/O Input - Output PU Internal pull-up resistor PD Internal pull-down resistor PWR Power signal Table 5-2. Clock and Reset Signals TERMINAL NAME PIN NO. I/O DESCRIPTION GRSTz 4 I PU Global power reset. This reset brings all of the TUSB9261 internal registers to their default states. When GRSTz is asserted, the device is completely nonfunctional. XI 52 I Crystal input. This terminal is the crystal input for the internal oscillator. The input may alternately be driven by the output of an external oscillator. When using a crystal a 1-MΩ feedback resistor is required between X1 and XO. XO 54 O Crystal output. This terminal is the crystal output for the internal oscillator. If XI is driven by an external oscillator this pin may be left unconnected. When using a crystal a 1-MΩ feedback resistor is required between X1 and XO. Frequency select. These terminals indicate the oscillator input frequency and are used to configure the correct PLL multiplier. The field encoding is as follows: FREQSEL[1:0] 31, 30 I PU FREQSEL[1] FREQSEL[0] INPUT CLOCK FREQUENCY 0 0 20 MHz 0 1 25 MHz 1 0 30 MHz 1 1 40 MHz Table 5-3. SATA Interface Signals (1) TERMINAL PIN NO. I/O SATA_TXP 57 O Serial ATA transmitter differential pair (positive) SATA_TXM 56 O Serial ATA transmitter differential pair (negative) SATA_RXP 60 I Serial ATA receiver differential pair (positive) SATA_RXM 59 I Serial ATA receiver differential pair (negative) NAME (1) DESCRIPTION Note that the default firmware and reference design for the TUSB9261 have the SATA TXP/TXM swapped for ease of routing in the reference design. If you plan to use the TI default firmware please review the reference design in the TUSB9261 DEMO User’s Guide (SLLU139) for proper SATA connection. SIGNAL DESCRIPTIONS Copyright © 2011–2013, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TUSB9261 13 TUSB9261 SLLSE67F – MARCH 2011 – REVISED JULY 2013 www.ti.com Table 5-4. USB Interface Signals TERMINAL PIN NO. I/O USB_SSTXP 43 O SuperSpeed USB transmitter differential pair (positive) USB_SSTXM 42 O SuperSpeed USB transmitter differential pair (negative) USB_SSRXP 46 I SuperSpeed USB receiver differential pair (positive) USB_SSRXM 45 I SuperSpeed USB receiver differential pair (negative) USB_DP 36 I/O USB High-speed differential transceiver (positive) USB_DM 35 I/O USB High-speed differential transceiver (negative) USB_VBUS 50 I USB bus power USB_R1 38 O Precision resistor reference. A 10-kΩ ±1% resistor should be connected between R1 and R1RTN. USB_R1RTN 39 I Precision resistor reference return NAME DESCRIPTION Table 5-5. Serial Peripheral Interface (SPI) Signals TERMINAL NAME PIN NO. I/O DESCRIPTION SPI_SCLK 17 O PU SPI clock SPI_DATA_OUT 18 O PU SPI master data out SPI_DATA_IN 20 I PU SPI master data in SPI_CS0 21 O PU Primary SPI chip select for Flash RAM 23 I/O PU SPI chip select for additional peripherals. When not used for SPI chip select this pin may be used as general purpose I/O. 22 I/O PU SPI chip select for additional peripherals. When not used for SPI chip select this pin may be used as general purpose I/O. SPI_CS2/ GPIO11 SPI_CS1/ GPIO10 14 SIGNAL DESCRIPTIONS Copyright © 2011–2013, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TUSB9261 TUSB9261 www.ti.com SLLSE67F – MARCH 2011 – REVISED JULY 2013 Table 5-6. JTAG, GPIO, and PWM Signals TERMINAL NAME PIN NO. I/O DESCRIPTION JTAG_TCK 25 I PD JTAG test clock JTAG_TDI 26 I PU JTAG test data in JTAG_TDO 27 O PD JTAG test data out JTAG_TMS 28 I PU JTAG test mode select JTAG_TRSTz 29 I PD JTAG test reset GPIO9/UART_TX 6 I/O PU GPIO/UART transmitter. This terminal can be configured as a GPIO or as the transmitter for a UART channel. This pin defaults to a general purpose output. GPIO8/UART_RX 5 I/O PU GPIO/UART receiver. This terminal can be configured as a GPIO or as the receiver for a UART channel. This pin defaults to a general purpose output. GPIO7 16 I/O PD GPIO6 15 I/O PD GPIO5 14 I/O PD GPIO4 13 I/O PD GPIO3 11 I/O PD GPIO2 10 I/O PD GPIO1 9 I/O PD GPIO0 8 I/O PD PWM0 2 O PD (1) PWM1 3 O PD (1) (1) Configurable as general purpose input/outputs Pulse Width Modulation (PWM). Can be used to drive status LED's. PWM pull down resistors are disabled by default. A firmware modification is required to turn them on. All other internal pull up/down resistors are enabled by default. SIGNAL DESCRIPTIONS Copyright © 2011–2013, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TUSB9261 15 TUSB9261 SLLSE67F – MARCH 2011 – REVISED JULY 2013 www.ti.com Table 5-7. Power and Ground Signals TERMINAL NAME PIN NO. I/O DESCRIPTION VDD 1, 12, 19, 32, 33, 41, 47, 49, 55, 61, 63 PWR 1.1-V power rail VDD33 7, 24, 51 PWR 3.3-V power rail VDDA33 34, 40, 48, 62 PWR 3.3-V analog power rail VSSOSC 53 PWR Oscillator ground. If using a crystal, this should not be connected to PCB ground plane. If using an oscillator, this should be connected to PCB ground. See the Clock Source Requirements section for more details. VSS 44, 58 PWR Ground VSS 65 PWR Ground - Thermal Pad NC 37, 64 — 16 No connect, leave floating SIGNAL DESCRIPTIONS Copyright © 2011–2013, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TUSB9261 TUSB9261 www.ti.com SLLSE67F – MARCH 2011 – REVISED JULY 2013 6 CLOCK CONNECTIONS 6.1 Clock Source Requirements The TUSB9261 supports an external oscillator source or a crystal unit. If a clock is provided to XI instead of a crystal, XO is left open and VSSOSC should be connected to the PCB ground plane. Otherwise, if a crystal is used, the connection needs to follow the guidelines below. Since XI and XO are coupled to other leads and supplies on the PCB, it is important to keep them as short as possible and away from any switching leads. It is also recommended to minimize the capacitance between XI and XO. This can be accomplished by connecting the VSSOSC lead to the two external capacitors CL1 and CL2 and shielding them with the clean ground lines. The VSSOSC should not be connected to PCB ground when using a crystal. Load capacitance (Cload) of the crystal varying with the crystal vendors is the total capacitance value of the entire oscillation circuit system as seen from the crystal. It includes two external capacitors CL1 and CL2 in Figure 6-1. The trace length between the decoupling capacitors and the corresponding power pins on the TUSB9261 needs to be minimized. It is also recommended that the trace length from the capacitor pad to the power or ground plane be minimized. CL1 XI VSSOSC Crystal XO CL2 Figure 6-1. Typical Crystal Connections 6.2 Clock Source Selection Guide Reference clock jitter is an important parameter. Jitter on the reference clock will degrade both the transmit eye and receiver jitter tolerance no matter how clean the rest of the PLL is, thereby impairing system performance. Additionally, a particularly jittery reference clock may interfere with PLL lock detection mechanism, forcing the Lock Detector to issue an Unlock signal. A good quality, low jitter reference clock is required to achieve compliance with supported USB3.0 standards. For example, USB3.0 specification requires the random jitter (RJ) component of either RX or TX to be 2.42 ps (random phase jitter calculated after applying jitter transfer function - JTF). As the PLL typically has a number of additional jitter components, the Reference Clock jitter must be considerably below the overall jitter budget. CLOCK CONNECTIONS Copyright © 2011–2013, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TUSB9261 17 TUSB9261 SLLSE67F – MARCH 2011 – REVISED JULY 2013 6.3 www.ti.com Oscillator XI should be tied to the 1.8-V clock source and XO should be left floating. VSSOSC should be connected to the PCB ground plane. A 20-, 25-, 30- or 40-MHz clock can be used. Table 6-1. Oscillator Specification PARAMETER CXI XI input capacitance VIL Low-level input voltage VIH High-level input voltage Ttosc_i Frequency tolerance Tduty Duty cycle TR/TF Rise/Fall time RJ CONDITIONS MIN TYP TJ = 25°C MAX UNIT 0.414 pF 0.7 V 1.05 Operational temperature V –50 50 50 ppm 55 % 20% - 80 % 6 ns Reference clock RJ JTF (1 sigma) (1) (2) 0.8 ps TJ Reference clock TJ JTF (total p-p) (2) (3) 25 ps Tp-p Reference clock jitter (absolute p-p) (4) 50 ps (1) (2) (3) (4) 45 Sigma value assuming Gaussian distribution After application of JTF Calculated as 14.1 x RJ + DJ Absolute phase jitter (p-p) 6.4 Crystal A parallel, 20-pF load capacitor should be used if a crystal source is used. VSSOSC should not be connected to the PCB ground plane. A 20-, 25-, 30- or 40-MHz crystal can be used. Table 6-2. Crystal Specification PARAMETER CONDITIONS MIN Oscillation mode TYP MAX UNIT Fundamental 20 fO 25 Oscillation frequency MHz 30 40 ESR Ttosc_i Equivalent series resistance Frequency tolerance Frequency stability 20 MHz and 25 MHz 50 30 MHz 40 40 MHz 30 Operational temperature ±50 ppm ±50 ppm 24 pF 1 year aging CL Load capacitance CSHUNT Crystal and board stray capacitance 4.5 pF Drive level (max) 0.8 mW 18 12 CLOCK CONNECTIONS 20 Ω Copyright © 2011–2013, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TUSB9261 TUSB9261 www.ti.com SLLSE67F – MARCH 2011 – REVISED JULY 2013 7 ELECTRICAL SPECIFICATIONS 7.1 Absolute Maximum Ratings over operating free-air temperature range (unless otherwise noted) VALUE UNIT VDD Steady-state supply voltage –0.3 to 1.4 V VDD33/ VDDA33 Steady-state supply voltage –0.3 to 3.8 V 7.2 Thermal Information TUSB9261 THERMAL METRIC PVP UNITS 64 PINS Junction-to-ambient thermal resistance (1) θJA 30.2 (2) θJCtop Junction-to-case (top) thermal resistance θJB Junction-to-board thermal resistance (3) 6.1 ψJT Junction-to-top characterization parameter (4) 0.4 ψJB Junction-to-board characterization parameter (5) 6.1 (6) 0.9 θJCbot (1) (2) (3) (4) (5) (6) Junction-to-case (bottom) thermal resistance 11.0 °C/W The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, high-K board, as specified in JESD51-7, in an environment described in JESD51-2a. The junction-to-case (top) thermal resistance is obtained by simulating a cold plate test on the package top. No specific JEDECstandard test exists, but a close description can be found in the ANSI SEMI standard G30-88. The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB temperature, as described in JESD51-8. The junction-to-top characterization parameter, ψJT, estimates the junction temperature of a device in a real system and is extracted from the simulation data for obtaining θJA, using a procedure described in JESD51-2a (sections 6 and 7). The junction-to-board characterization parameter, ψJB, estimates the junction temperature of a device in a real system and is extracted from the simulation data for obtaining θJA , using a procedure described in JESD51-2a (sections 6 and 7). The junction-to-case (bottom) thermal resistance is obtained by simulating a cold plate test on the exposed (power) pad. No specific JEDEC standard test exists, but a close description can be found in the ANSI SEMI standard G30-88. Spacer 7.3 Recommended Operating Conditions over operating free-air temperature range (unless otherwise noted) MIN NOM MAX UNIT VDD Digital 1.1 supply voltage 1.045 1.1 1.155 V VDD33 Digital 3.3 supply voltage 3 3.3 3.6 V VDDA33 Analog 3.3 supply voltage 3 3.3 3.6 V VBUS Voltage at VBUS PAD 0 1.155 V 0 70 -40 85 TA Operating free-air temperature range TJ Operating junction temperature range Industrial version -40 °C 100 °C HBM ESD 2000 V CDM ESD 500 V ELECTRICAL SPECIFICATIONS Copyright © 2011–2013, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TUSB9261 19 TUSB9261 SLLSE67F – MARCH 2011 – REVISED JULY 2013 7.4 www.ti.com DC Electrical Characteristics for 3.3-V Digital I/O over operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT DRIVER TR Rise time 5 pF 1.5 TF Fall time 5 pF 1.53 IOL Low-level output current VDD33 = 3.3 V, TJ = 25°C 6 IOH High-level output current VDD33 = 3.3 V, TJ = 25°C –6 VOL Low-level output voltage IOL = 2 mA VOH High-level output voltage IOL = –2 mA VO Output voltage ns ns mA mA 0.4 2.4 V V 0 VDD33 V RECEIVER VI Input voltage 0 VDD33 V VIL Low-level input voltage 0 0.8 V VIH High-level input voltage 2 Vhys Input hysteresis tT Input transition time (TR and TF) II Input current VI = 0 V to VDD33 CI Input capacitance VDD33 = 3.3 V, TJ = 25°C 20 V 200 ELECTRICAL SPECIFICATIONS mV 0.384 10 ns 5 µA pF Copyright © 2011–2013, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TUSB9261 TUSB9261 www.ti.com 8 SLLSE67F – MARCH 2011 – REVISED JULY 2013 POWER CONSUMPTION Table 8-1. SuperSpeed USB Power Consumption POWER RAIL TYPICAL ACTIVE CURRENT (mA) (1) TYPICAL SUSPEND CURRENT (mA) (2) VDD11 291 153 65 28 VDD33 (1) (2) (3) (3) Transferring data via SS USB to a SSD SATA Gen II device. No SATA power management, U0 only. SATA Gen II SSD attached no active transfer. No SATA power management, U3 only. All 3.3-V power rails connected together. Table 8-2. High Speed USB Power Consumption (1) (2) (3) POWER RAIL TYPICAL ACTIVE CURRENT (mA) (1) TYPICAL SUSPEND CURRENT (mA) (2) VDD11 172 153 VDD33 (3) 56 28 Transferring data via HS USB to a SSD SATA Gen II device. No SATA power management. SATA Gen II SSD attached no active transfer. No SATA power management. All 3.3-V power rails connected together. POWER CONSUMPTION Copyright © 2011–2013, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TUSB9261 21 PACKAGE OPTION ADDENDUM www.ti.com 6-Jun-2013 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan Lead/Ball Finish (2) MSL Peak Temp Op Temp (°C) Device Marking (3) (4/5) TUSB9261IPVP ACTIVE HTQFP PVP 64 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR -40 to 85 TUSB9261I TUSB9261PVP ACTIVE HTQFP PVP 64 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR 0 to 70 TUSB9261 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. 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