www.cadeka.com TMC1203 Triple Video A/D Converter 8-Bit, 50Msps Features Applications • • • • • • • • • • • • • • • • • • • 8-bit resolution 50 Msps conversion rate Low power: 100mW per channel @ 20 Msps Integral track/hold Independent clock inputs Integral and differential linearity error 0.5 LSB Differential phase 0.7 degree Differential gain 1.8% Single +5V power supply Three-state TTL/CMOS-compatible outputs Low cost Video digitizing (composite and Y-C) VGA and CCD digitizing LCD projection panels Image scanners Personal computer video boards Multimedia systems Low cost, high speed data conversion Digital communications Description Incorporated into the TMC1203 are three analog-to-digital (A/D) converters, each with independent clocks and reference voltages. Analog signals are converted to Triple 8-bit digital words at sample rates up to 50 Msps (Megasamples per second) per channel. architecture and submicron CMOS technology reduce typical power dissipation to 100 mW per converter. Integral Track/Hold circuits deliver excellent performance on signals with full-scale spectral components up to 12 MHz. Innovative two-step architecture conversion TMC1203 package is a 80-lead Metric Quad Flat Pack (MQFP). Performance specifications are guaranteed from 0°C to 70°C. Power is derived from a single +5 Volt power supply. Outputs are three-state outputs and TTL/CMOS-compatible. Block Diagram RTA VINA 8-bit A/D Converter DA7-0 OEA RBA CLKA RTB VINB 8-bit A/D Converter DB7-0 OEB RBB CLKB RTC VINC 8-bit A/D Converter DA7-0 OEC RBC CLKC 65-3720-01 Rev. 1.2.0 TMC1203 PRODUCT SPECIFICATION Circuit Function Digital Inputs and Outputs Within the TMC1203 are three 8-bit A/D converters, each employing two-step architecture to convert an analog input to a digital output at rates up to 50 Msps. Input signals are held in integral track/hold stages during the conversion process. Operation is pipelined, with one input sample taken and one output word provided for each CLKX cycle. Sampling of the applied input signal occurs on the "falling" edge of the CLKX signal (Figure 1). Output data is delayed by 2 1/2 CLKX cycles and is valid following the "rising" edge of CLKX. Previous output data remains valid for tHO (Output Hold Time), satisfying any hold time requirement of the receiving circuit. New data becomes valid tD (Output Delay Time) after this rising edge of CLKX. Each of the three converters function identically. In the following descriptions ‘X’ refers to a generic input/output or clock where ‘X’ is equivalent to A, B or C. The first step in the conversion process is a coarse 4-bit quantization. This determines the range of the subsequent fine 4-bit quantization step. To eliminate spurious codes, the fine 4-bit A/D quantizer output is gray-coded and converted to binary before it is combined with the coarse result to form a complete 8-bit result. Analog Input and Voltage References Each A/D accepts analog signals in the range RBX to RTX into digital data. Input signals outside this range produce “saturated” 00h or FFh output codes. The device will not be damaged by signals within the range AGND to VDDA. Input range is very flexible and extends from the +5 Volt power supply to ground. Nominal input range is 2 Volts, extending from 0.6V to 2.6V. Characterization and performance is specified over this range. However, the part will function with a full-scale range from 1.0V to 5.0V. A smaller input range may simplify analog signal conditioning circuitry, at the expense of additional noise sensitivity and some reduced differential linearity performance. External voltage reference sources are connected to the RTX and RBX pins. RBX can be grounded. Within each A/D converter is a reference resistor ladder comprising 255 resistors that are accessed by the TMC1203 comparators. RTX is connected to the top of the ladder, RBX to the bottom. Gain and offset errors are directly related to the accuracy and stability of the applied reference voltages. Because a two-step conversion process is employed, it is important that the references remain stable during the ENTIRE conversion process (two clock cycles). The reference voltage can then be changed, but any conversion in progress during a reference change is invalid. 2 Whenever the analog input signal is sampled and found to be at a level beyond the A/D conversion range, the output limits at 00h or FFh, as appropriate. Table 1. A/D Output Coding Input Voltage Output RTX + 1 LSB FF RTX FF RTX - 1 LSB FE ••• ••• RBX + 128 LSB 80 RBX + 127 LSB 7F ••• ••• RBX + 1 LSB 01 RBX 00 RBX - 1 LSB 00 Note: 1 LSB = (RTX - RBX) / 255 The outputs of the TMC1203 are CMOS- and TTL-compatible, and are capable of driving four low-power Schottky TTL loads. An Output Enable control, OEX, places the A/D outputs in a high-impedance state when HIGH. The outputs are enabled when OEX is LOW. Power and Ground The TMC1203 operates from a single +5 Volt power supply. For optimum performance, it is recommended that AGND and DGND pins of the TMC1203 be connected to the system analog ground plane. PRODUCT SPECIFICATION TMC1203 Pin Assignments 64 41 65 40 80 25 1 24 65-3720-08 Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 Name NC DA5 DA6 DA7 OEA VDD VDD NC CLKA NC VDDA VINA AGND RTA RBA DGND DGND DGND DGND DGND Pin 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 Name DGND DGND NC NC DGND DGND VDD VDD VDD VDD NC DGND DGND DC0 DC1 DC2 DC3 DC4 DC5 DC6 Pin 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 Name DC7 OEC VDD VDD CLKC NC VDDA VINC AGND RTC RBC RBB RTB AGND VINB VDDA NC CLKB NC VDD Pin 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 Name VDD OEB DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 DGND DGND NC DGND DGND DA0 DA1 DA2 DA3 DA4 3 PRODUCT SPECIFICATION TMC1203 Pin Descriptions Pin Name Pin Number Value Pin Function Description VINA, VINB, VINC 12, 55, 48 RTX to RBX Analog Inputs. The input voltage conversion range lies between the voltage applied to the RTX and RBX pins. RTX, RBX. RTA, RTB, RTC 14, 53, 50 2.6V Reference Voltage, Top Inputs. DC voltages applied to RTA, RTB and RTC define highest value of VINX. RBA, RBB, RBC 15, 52, 51 0.6V Reference Voltage, Bottom Inputs. DC voltages applied to RBA, RBB and RBC define highest value of VINX. CLKA, CLKB, CLKC 9, 58, 45 CMOS Convert (Clock) Inputs. A/D converter clock inputs. CMOScompatible. VINX is sampled on the falling edge of CLKX. Clock inputs are separate for the three converters. DA7-0 4, 3, 2, 80, 79, 78, 77, 76 CMOS/ TTL Data outputs, Converter A (D7 = MSB). Eight-bit CMOS- and TTL-compatible digital outputs. Valid data is output on the rising edge of CLKX. DB7-0 63, 64, 65, 66, 67, 68, 69, 70 CMOS/ TTL Data outputs, Converter B (D7 = MSB). Eight-bit CMOS- and TTL-compatible digital outputs. Valid data is output on the rising edge of CLKX. DC7-0 41, 40, 39, 38, 37, 36, 35, 34 CMOS/ TTL Data outputs, Converter C (D7 = MSB). Eight-bit CMOS- and TTL-compatible digital outputs. Valid data is output on the rising edge of CLKX. 5, 62, 42 CMOS Output Enable Inputs. CMOS-compatible. When LOW, the A/D output is enabled. When HIGH, the output is in a high-impedance state. Output Enables are separate for the three converters. 11, 47, 56 +5V Analog Supply Voltage. +5 Volt power inputs. These should come from the same power source and be decoupled to AGND. 6, 7, 27, 28, 29, 30, 43, 44, 60, 61 +5V Digital Supply Voltage. +5 Volt power inputs. These should come from the same power source and be decoupled to AGND. AGND 13, 49, 54 0.0V Analog Ground. Ground connections. These pins should be connected to the system analog ground plane. DGND 16, 17, 18, 19, 20, 21, 22, 25, 26, 32, 33, 71, 72, 74, 75 0.0V Digital Ground. Ground connections. These pins should be connected to the system analog ground plane. 1, 8, 10, 23, 24, 31, 46, 57, 59, 73 open Not Connected. A/D Converters OEA, OEB, OEC Power VDDA VDD No Connect N/C 4 PRODUCT SPECIFICATION TMC1203 Specification Notes Bandwidth tion step size) = 2V/255 = 7.8mV. The input signal will slew one LSB in 124ps. To limit the error (and noise) contribution due to aperture effects to 1/2LSB, the aperture must be shorter than 62ps. Bandwidth specification of an A/D converter is somewhat different from the normal frequency-response specification used in amplifiers and filters. An understanding of the differences will help in selecting converters properly for particular applications. This is the primary reason that the signal to noise ratio drops off as full scale frequency increases. Notice that the slew rate is directly proportional to signal amplitude, A. A/Ds will handle lower-amplitude signals of higher bandwidth, but other distortion effects will be worsened. A/D conversion comprises two distinct processes: sampling and quantizing. Sampling is grabbing a snapshot of the input signal and holding it steady for quantizing. The quantizing process is approximating the analog input to its nearest numerical value within the conversion range. While sampling is a high-frequency process, quantizing operates on a dc signal, held steady by the track/hold circuit. Therefore, the sampling process relates to the dynamic characteristics of an A/D converter. All this is of particular interest in applications such as digitizing analog VGA RGB signals, or the output of a CCD imaging chip. These data are effectively pre-sampled: there is a period of rapid slewing from one pixel value to another, followed by a relatively stable dc level before the signal slews to the next pixel value. The goal is, of course, to sample on these stable pixel values, not on the slewing between pixels. During the aperture time, the A/D sees essentially a dc signal, and bandwidth considerations are less important. As long as the input circuit can slew and settle to the new value in the prescribed period, an accurate conversion will be made. Sampling involves an aperture time, the time needed for the track/hold circuit to capture the input signal and settle on a dc value to hold. It is analogous to the shutter speed of a camera: the shorter the A/D aperture (or faster the shutter) the less the signal (or picture) will be blurred, and the less uncertainty there will be in the quantized value. This is not to be confused with the camera lens opening (aperture), which is entirely different. The TMC1203 is capable of slewing a full 2V and settling between samples taken as little as 25ns apart, making it ideal for digitizing analog VGA and CCD outputs. For example, a 10 MHz sinewave with a 1V peak amplitude (2Vp-p) has a maximum slew rate of 2pfA at zero crossing, or 62.8V/ms. With an 8-bit A/D converter, q (the quantiza- Sample N+3 tSTD VINX Sample N+2 Sample N Sample N+1 tPWL tPWH 1/fS CLKX tDO tHO Hi-Z DX7-0 Data N-3 Data N-2 tDIS Data N-1 Data N tENA OEX 65-3720-02 Figure 1. Timing 5 TMC1203 PRODUCT SPECIFICATION Equivalent Circuits VDD VDD p p Digital Input Digital Output n n 27011B 27014B GND GND Figure 2. Equivalent Digital Input Circuit VDDA Figure 3. Equivalent Digital Output Circuit VRT tENA VIN tDIS OE 0.5V Three-State Outputs AGND 2.0V 0.8V Figure 4. Equivalent Analog Input Circuit 7048B 0.5V 29030 VRB High Impedance Figure 5. Threshold Levels for Three-State Measurements Absolute Maximum Ratings (beyond which the device may be damaged)1 Parameter Condition Min VDDA Measured to AGND VDDP Typ Max Unit -0.5 +7.0 V Measured to DGND -0.5 +7.0 V VDD Measured to DGND -0.5 +7.0 V VDDA Measured to VDD -0.5 +0.5 V VDDP Measured to VDD -0.5 +0.5 V AGND Measured to DGND -0.5 +0.5 V Measured to DGND2 -0.5 VDD + 0.5 V -10.0 +10.0 mA Power Supply Voltages Digital Inputs Applied Voltage Forced 6 current 3, 4 PRODUCT SPECIFICATION TMC1203 Absolute Maximum Ratings (continued) (beyond which the device may be damaged)1 Parameter Condition Min Measured to AGND2 Typ Max Unit -0.5 VDDA+0.5 V -10.0 +10.0 mA -0.5 VDD + 0.5 V -6.0 +6.0 mA Analog Inputs Applied Voltage Forced current 3, 4 Digital Outputs Applied voltage Forced current Measured to DGND2 3, 4 Short circuit duration Single output in HIGH state to ground) 1 second Temperature Operating, ambient -20 Junction 110 °C +150 °C Lead, soldering 10 seconds +300 °C Vapor Phase soldering 1 minute +220 °C +150 °C ±150 V Storage -65 5 Electrostatic Discharge Notes: 1. Absolute maximum ratings are limiting values applied individually while all other parameters are within specified operating conditions. Functional operation under any of these conditions is NOT implied. Performance and reliability are guaranteed only if Operating Conditions are not exceeded. 2. Applied voltage must be current limited to specified range. 3. Forcing voltage must be limited to specified range. 4. Current is specified as conventional current flowing into the device. 5. EIAJ test method. Operating Conditions Parameter Min. Nom Max. Units VDD, VDDA, VDDP Power Supply Voltage 4.75 5.0 5.25 V AGND Analog Ground (Measured to DGND) -0.1 0 0.1 V VRTX Reference Voltage, Top 2.6 VDDA V VRBX Reference Voltage, Bottom VRTX-VRBX VINX VIH 0 0.6 Reference Voltage Differential 1.0 2.0 5.0 V Analog Input Range VRB VRT V Input Voltage, Logic HIGH 0.7 VDD VDD V VIL Input Voltage, Logic LOW GND 0.3 VDD V IOH Output Current, Logic HIGH -4.0 mA IOL Output Current, Logic LOW 4.0 mA TA Ambient Temperature, Still Air 70 °C 0 V 7 TMC1203 PRODUCT SPECIFICATION Electrical Characteristics Parameter IDD IDDQ PD CAI Conditions 1 Power Supply Current Power Supply Current, Quiescent Total Power Dissipation Input Capacitance, Analog Min. Typ1 Max. Units VDD = VDDA = VDDP = Max., CLOAD = 35pF, fCK = fS (3 A/Ds) fS = 20 Msps 70 90 mA fS = 40 Msps 94 120 mA fS = 50 Msps 105 135 mA CLKX = LOW 29 55 mA CLKX = HIGH 45 65 mA VDD = VDDA = Max. VDD = VDDA = VDDP = Max., CLOAD = 35pF, fCK = fS (3 A/Ds) fS = 20 Msps 300 470 mW fS = 40 Msps 425 630 mW fS = 50 Msps 490 710 mW CLKX = LOW 4 pF CLKX = HIGH 12 pF RIN Input Resistance 500 kW RREF Reference Resistance 200 ICB Input Current, Analog ±1 mA IIH Input Current, HIGH VDD = Max., VIN = VDD ±5 mA IIL Input Current, LOW VDD = Max., VIN = 0V ±5 mA IOZH Hi-Z Output Leakage Current, Output HIGH VDD = Max., VIN = VDD ±5 mA IOZL Hi-Z Output Leakage Current, Output LOW VDD = Max., VIN = VDD ±5 mA IOS Short-Circuit Current -35 mA VOH Output Voltage, HIGH 270 340 W IOH = -100mA VDD-0.3 V IOH = -2.5mA 3.5 V IOH = Max. 2.4 V VOL Output Voltage, LOW IOL = Max. CDI Digital Input Capacitance 4 CDO Digital Output Capacitance 10 0.4 V 10 pF pF Note: 1. Typical values with VDD = VDDA = Nom and TA = Nom, Minimum/Maximum values with VDD = VDDA = Max. and TA = Min.. 8 PRODUCT SPECIFICATION TMC1203 Switching Characteristics Parameter fS tPWH tPWL Conversion Rate CLKX Pulsewidth, HIGH CLKX Pulsewidth, LOW Conditions Min. Typ. Max. Units TMC1203-20 20 Msps TMC1203-40 40 Msps TMC1203-50 50 Msps TMC1203-20 14 ns TMC1203-40 14 ns TMC1203-50 12 ns TMC1203-20 8 ns TMC1203-40 8 ns TMC1203-50 7 ns EAP Aperture Error 30 tSTO Sampling Time Offset tSTS Sampling Time Skew tHO Output Hold Time tDO Output Delay Time 14 ns tENA Output Enable Time 27 ns tDIS Output Disable Time 42 ns Max.2 Units 1 CLOAD = 15pF ps 2 5 ns 150 400 ps 9 ns System Performance Characteristics Parameter Conditions Min.2 Typ1 VRT = 2.6V ±0.5 Differential Linearity Error VRB = 0.6V ±0.5 Bandwidth1 TMC1203-20 10 MHz TMC1203-40 12 MHz TMC1203-50 12 MHz ELI Integral Linearity Error, Independent ELD BW LSB LSB EOT Offset Voltage, Top (RT - VIN for most positive code transition) VRT = 2.6V, VRB = 0.6V -40 80 mV EOB Offset Voltage, Bottom (RB - VIN for most negative code transition) VRT = 2.6V, VRB = 0.6V -95 -30 mV dg Differential Gain fS = 14.3Msps NTSC 40 IRE Mod Ramp VDDA = +5.0V, TA=25°C VRT = 2.6V, VRB = 0.6V 1.8 % dp Differential Phase fS = 14.3Msps NTSC 40 IRE Mod Ramp VDDA = +5.0V, TA=25°C VRT = 2.6V, VRB = 0.6V 0.7 deg XTALK Channel Crosstalk fN = 5.0 MHz 45 dB 9 TMC1203 PRODUCT SPECIFICATION System Performance Characteristics (continued) Parameter 3 SNR Signal-to-Noise Ratio Conditions Min.2 Typ1 Max.2 Units fS = 20Msps, VRT = 2.6V, VRB = 0.6V fN = 1.24MHz 46 dB fN = 2.48MHz 46 dB fN = 6.98MHz 45 dB fN = 10.0MHz 45 dB fN = 1.24MHz 42 dB fN = 6.98MHz 41 dB fN = 12.0MHz 40 dB fN = 20.0MHz 38 dB fN = 1.24MHz 40 dB fN = 6.98MHz 40 dB fN = 12.0MHz 40 dB fN = 1.24MHz 53 dB fN = 2.48MHz 48 dB fN = 6.98MHz 44 dB fN = 10.0MHz 40 dB fN = 1.24MHz 49 dB fN = 6.98MHz 44 dB fN = 12.0MHz 38 dB fN = 1.24MHz 46 dB fN = 6.98MHz 40 dB fN = 12.0MHz 37 dB fS = 40Msps, VRT = 2.6V, VRB = 0.6V fS = 50Msps, VRT = 2.6V, VRB = 0.6V SFDR4 Spurious-Free Dynamic Range fS = 20Msps, VRT = 2.6V, VRB = 0.6V fS = 40Msps, VRT = 2.6V, VRB = 0.6V fS = 50Msps, VRT = 2.6V, VRB = 0.6V Notes: 1. Values shown in Typ. column are typical for VDD = VDDA =+5V and TA = 25°C. 2. Values shown in Min. and Max. columns are for VDD = VDDA and TA over entire range specified under Operating Conditions. 3. SNR values do not include the harmonics of the fundamental frequency. 4. SFDR is the ratio in dB of fundamental amplitude to the harmonic with the highest amplitude. 5. Characteristics specified for VRT = 2.6V, VRB = 0.6V. 6. Bandwidth is the frequency up to which a full-scale sinewave can be digitized without spurious codes. 10 PRODUCT SPECIFICATION TMC1203 Typical Performance Characteristics 60 35 30 50 SFDR (dB) IDD 25 20 15 10 40 30 fS = 20Msps 20 10 5 0 0 0 10 20 30 fS (Msps) 40 50 0 15 20 25 65-3720-04 Figure 7. Typical SFDR vs fIN 50 50 40 40 SNR (dB) SNR (dB) 10 fIN (Msps) Figure 6. Typical IDD vs fS (Single A/D) 30 20 5 65-3720-03 fS = 20Msps 10 30 20 fS = 20Msps 10 0 0 0 5 10 15 fIN (MHz) Figure 8. Typical SNR vs fIN 20 25 65-3720-05 0 1 2 3 VIN 4 5 65-3720-06 Figure 9. Typical SNR vs Full Scale Input Range 11 TMC1203 PRODUCT SPECIFICATION Application Notes The voltage reference at RTX can be adjusted from 0.0 to 2.4 volts while RBX is grounded. Schottky diodes are used to restrict the wideband amplifier output to between -0.3V and VDD +0.3V. Diode protection is good practice to limit the analog input voltage at VINX to the safe operating range. The circuit in Figure 10 employs a band-gap reference to generate a variable RTX reference voltages for the TMC1203 as well as a bias voltage to offset the wideband input amplifiers to mid-range. The operational amplifier in the reference circuitry is a standard 741-type. +5V 0.1µF LM185-1.2 0.1µF 1k½ +5V 0.1µF VDDA Gain Adjust 2k½ + 0.1µF – 1k½ 0.1µF GREEN Video Input + Wideband Op-amp VINA – 75½ RTA RTB RTC RBA RBB RBC 1k½ 100 GREEN Digital Video Output DA7-0 OEA CLKA 1k½ 10k½ VDD 20½ TMC1203 1k½ +5V BLUE Digital Video Output DB7-0 100 BLUE Video Input + Wideband Op-amp VINB – 75½ OEB CLKB 1k½ 10k½ 1k½ +5V 100 RED Video Input + 75½ OEC Wideband Op-amp – 1k½ Pixel Clock CLKC VINC AGND 1k½ 10k½ RED Digital Video Output DC7-0 DGND +5V 65-3720-07 Figure 10. Typical Interface Circuit - High Performance Grounding Printed Circuit Board Layout The TMC1203 has separate analog and digital circuits. To keep digital system noise from the A/D converter, it is recommended that power supply voltages (VDD and VDDA) come from the same source, and that ground connections (DGND and AGND) be made to the analog ground plane, and as close as possible to the device pins. Power supply pins should be individually decoupled at the pin. The digital circuitry that gets its input from the TMC1203 should be referred to the system digital ground plane. Designing with high performance mixed-signal circuits demands printed circuits with ground planes. Overall system performance is strongly influenced by the board layout. Capacitive coupling from digital to analog circuits may result in poor A/D conversion. Consider the following suggestions when doing the layout: 12 1. Keep the critical analog traces (VN, RTX, RBX) as short as possible and as far as possible from all digital signals. The TMC1203 should be located close to the analog input connectors. PRODUCT SPECIFICATION 2. Segregate traces: • • • • 4. 5. Decoupling capacitors should be applied liberally to VDD pins. Remember that not all power supply pins are created equal. They supply different circuits on the integrated circuit, each of which generate varying amounts and types of noise. For best results, use 0.1mF ceramic capacitors. Lead lengths should be minimized. Ceramic chip capacitors are the best choice. 6. If the digital power supply has a dedicated power plane layer, it should not be placed under the TMC1203, the voltage reference, or the analog inputs. Capacitive coupling of digital power supply noise from this layer to the TMC1203 and its related analog circuitry can have an adverse effect on performance. 7. CLKX should be handled carefully. Jitter and noise on this clock may degrade performance. Terminate the clock line, if needed, to eliminate overshoot and ringing. A/D analog D/A analog Clocks Digital Treat analog inputs as transmission lines. Cleanly route traces over the ground plane bearing in mind that the return currents will flow through the ground plane beneath the traces. Do not route digital traces nearby. A few inches of digital trace less than a few line widths from an analog trace will cross-couple noise into adjacent analog circuits. 3. TMC1203 The power plane for the TMC1203 should be separate from that which supplies the rest of the digital circuitry. A single power plane should be used for all of the VDD pins. If the power supply for the TMC1203 is the same as that of the system's digital circuitry, power to the TMC1203 should be decoupled with ferrite beads and 0.1mF capacitors to reduce noise. The ground plane should be solid, not cross-hatched. Connections to the ground plane should have very short leads. Related Products • TMC1175A, TMC1275 8-Bit Video A/D Converters • TMC1173A, TMC1273 3V, Low-Power 8-Bit Video A/D Converters • TMC1103 Triple 8-bit A/D with Clamps and PLL • TMC3003/TMC3503 Triple Video D/A Converters • TMC2242B/TMC2243/TMC2246A Digital Filters 13 TMC1203 Notes: 14 PRODUCT SPECIFICATION PRODUCT SPECIFICATION TMC1203 Mechanical Dimensions – 80-Lead MQFP Package Inches Symbol Millimeters Min. Max. Min. Max. A A1 A2 B C D — .010 .100 .012 .005 .904 .134 — .120 .018 .009 .923 — .25 2.55 .30 .13 22.95 3.40 — 3.05 .45 .23 23.45 D1 E E1 e L N ND NE .783 .791 .667 .687 .547 .555 .0315 BSC .025 .041 80 24 16 a ccc 0¡ — Notes: Notes 2. Controlling dimension is millimeters. 3, 5 5 0¡ — 3. Dimension "B" does not include dambar protrusion. Allowable dambar protrusion shall be .08mm (.003in.) maximum in excess of the "B" dimension. Dambar cannot be located on the lower radius or the foot. 4. "L" is the length of terminal for soldering to a substrate. 5. "B" & "C" includes lead finish thickness. 19.90 20.10 16.95 17.45 13.90 14.10 .80 BSC .65 1.03 80 24 16 7¡ .004 1. All dimensions and tolerances conform to ANSI Y14.5M-1982. 4 7¡ 0.10 D D1 .20 (.008) Min. e 0¡ Min. Datum Plane .13 (.30) R .005 (.012) C E1 E Pin 1 Identifier a .13 (.005) R Min. B L 0.063" Ref (1.60mm) Lead Detail See Lead Detail A Base Plane A2 A1 Seating Plane -CLEAD COPLANARITY ccc C 15 TMC1203 PRODUCT SPECIFICATION Ordering Information Product Number Conversion Rate (Msps) Temperature Range Screening Package Package Marking TMC1203KLC20 20 Msps TA = 0°C to 70°C Commercial 80-Lead MQFP 1203KLC20 TMC1203KLC40 40 Msps TA = 0°C to 70°C Commercial 80-Lead MQFP 1203KLC40 TMC1203KLC50 50 Msps TA = 0°C to 70°C Commercial 80-Lead MQFP 1203KLC50 5/20/98 0.0m 001 Stock# DS70001203