CADEKA TMC1103

www.cadeka.com
TMC1103
Triple Video A/D Converter with Clamps
8-Bit, 50Msps
Features
Applications
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8-bit resolution
50 Msps conversion rate
Low power: 100mW per channel @ 20 Msps
Integral track/hold
Independent Input Clamps
Independent clock inputs
Integral and differential linearity error 0.5 LSB
Differential phase 0.7 degree
Differential gain 1.8%
Single +5V power supply
Three-state TTL/CMOS-compatible outputs
Low cost
Video digitizing (composite and Y-C)
VGA and CCD digitizing
LCD projection panels
Image scanners
Personal computer video boards
Multimedia systems
Low cost, high speed data conversion
Description
Incorporated into the TMC1103 are three analog-to-digital
(A/D) converters, each with an independent clock, reference
voltage and input clamp. Analog signals are converted to
Triple 8-bit digital words at sample rates up to 50 Msps
(Megasamples per second) per channel.
submicron CMOS technology reduce typical power dissipation to 100 mW per converter.
Integral Track/Hold circuits deliver excellent performance
on signals with full-scale spectral components up to
12 MHz. Innovative two-step conversion architecture and
TMC1103 package is a 80-lead Metric Quad Flat Pack
(MQFP). Performance specifications are guaranteed from
0°C to 70°C.
Power is derived from a single +5 Volt power supply. Outputs are three-state outputs and TTL/CMOS-compatible.
Block Diagram
RTA
RBA
VINA
Clamp
8-bit
A/D Converter
DA7-0
OEA
VCLPA
CLPA
CLKA
RTB
RBB
VINB
Clamp
8-bit
A/D Converter
DA7-0
OEB
VCLPB
CLPB
CLKB
RTC
RBC
VINC
VCLPC
CLPC
Clamp
8-bit
A/D Converter
DA7-0
OEC
CLKC
65-1103-01
Rev. 1.2.0
TMC1103
Circuit Function
Within the TMC1103 are three 8-bit A/D converters, each
employing two-step architecture to convert an analog input
to a digital output at rates up to 50 Msps. Input signals are
held in integral track/hold stages during the conversion process. Operation is pipelined, with one input sample taken and
one output word provided for each CLKX cycle.
PRODUCT SPECIFICATION
Analog
Input
0.1µF
VINX
A/D Converter
VCLPX
65-1103-02
CLPX
Input Clamp Circuit
Each of the three converters function identically. In the following descriptions ‘X’ refers to a generic input/output or
clock where ‘X’ is equivalent to A, B or C.
The first step in the conversion process is a coarse 4-bit
quantization. This determines the range of the subsequent
fine 4-bit quantization step. To eliminate spurious codes, the
fine 4-bit A/D quantizer output is gray-coded and converted
to binary before it is combined with the coarse result to form
a complete 8-bit result.
Analog Input and Voltage References
Each A/D accepts analog signals in the range RBX to RTX into
digital data. Input signals outside this range produce “saturated” 00h or FFh output codes. The device will not
be damaged by signals within the range AGND to VDDA.
Input range is very flexible and extends from the +5 Volt
power supply to ground. Nominal input range is 2 Volts,
extending from 0.6V to 2.6V. Characterization and
performance is specified over this range. However, the
part will function with a full-scale range from 1.0V to 5.0V.
A smaller input range may simplify analog signal conditioning circuitry, at the expense of additional noise sensitivity
and some reduced differential linearity performance.
External voltage reference sources are connected to the RTX
and RBX pins. RBX can be grounded. Within each A/D converter is a reference resistor ladder comprising 255 resistors
that are accessed by the TMC1103 comparators. RTX is connected to the top of the ladder, RBX to the bottom. Gain and
offset errors are directly related to the accuracy and stability
of the applied reference voltages.
Input Clamps
A clamp circuit is connected to the input pin VINX of each of
the three A/D converters. With CLPX LOW, the input pin is
clamped to the voltage at VCLPX. If CLPX is HIGH, the
input pin is high impedance. Clamping adds an offset voltage
to an AC coupled signal to adjust this signal’s amplitude to
the A/D converter input voltage range.
The analog input is corrected through a 0.1mF capacitor to
VINX. The source impedance of the analog source should be
less than 50 Ohms. Current pulses through the capacitor over
several clamp cycles until the voltage across the capacitor
equals the difference between VCLPX and the voltage at the
analog source during the clamping period. When the switch
is open, the voltage on the coupling capacitor is added to the
analog input, producing a a DC offset input signal.
2
Digital Inputs and Outputs
Sampling of the applied input signal occurs on the falling
edge of the CLKX signal (Figure 1). Output data is delayed
by 2 1/2 CLKX cycles and is valid following the rising edge
of CLKX. Previous output data remains valid for tHO (Output Hold Time). New data becomes valid tD (Output Delay
Time) after this rising edge of CLKX.
Whenever the analog input signal is sampled and found to be
at a level beyond the A/D conversion range, the output limits
at 00h or FFh, as appropriate.
Table 1. A/D Output Coding
Input Voltage
Output
RTX + 1 LSB
FF
RTX
FF
RTX - 1 LSB
FE
•••
•••
RBX + 128 LSB
80
RBX + 127 LSB
7F
•••
•••
RBX + 1 LSB
01
RBX
00
RBX - 1 LSB
00
Note: 1 LSB = (RTX – RBX) / 255
The outputs of the TMC1103 are CMOS- and
TTL-compatible, and are capable of driving four low-power
Schottky TTL loads. An Output Enable control, OEX, places
the A/D outputs in a high-impedance state when HIGH.
The outputs are enabled when OEX is LOW.
Power and Ground
The TMC1103 operates from a single +5 Volt power supply.
For optimum performance, an analog ground plane should
be placed under the TMC1103 the AGND and DGND pins
should be connected to the system analog ground plane.
PRODUCT SPECIFICATION
TMC1103
Pin Assignments
64
41
65
40
80
25
1
24
65-1103-03
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
Name
NC
DA5
DA6
DA7
OEA
VDD
VDD
NC
CLKA
NC
VDDA
VINA
AGND
RTA
RBA
VCLPA
VCLPB
VCLPC
DGND
DGND
Pin
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
Name
DGND
DGND
NC
NC
DGND
DGND
VDD
CLPA
CLPB
CLPC
NC
DGND
DGND
DC0
DC1
DC2
DC3
DC4
DC5
DC6
Pin
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
Name
DC7
OEC
VDD
VDD
CLKC
NC
VDDA
VINC
AGND
RTC
RBC
RBB
RTB
AGND
VINB
VDDA
NC
CLKB
NC
VDD
Pin
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
Name
VDD
OEB
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
DGND
DGND
NC
DGND
DGND
DA0
DA1
DA2
DA3
DA4
3
PRODUCT SPECIFICATION
TMC1103
Pin Descriptions
Pin Name
Pin Number
Value
Pin Function Description
VINA, VINB,
VINC
12, 55, 48
RTX to
RBX
Analog Inputs. The input voltage conversion range lies between the
voltage applied to the RTX and RBX pins.
RTA, RTB, RTC
14, 53, 50
2.6V
Reference Voltage, Top Inputs. DC voltages applied to RTA, RTB
and RTC define highest value of VINX.
RBA, RBB, RBC
15, 52, 51
0.6V
Reference Voltage, Bottom Inputs. DC voltages applied to RBA,
RBB and RBC define lowest value of VINX.
CLKA, CLKB,
CLKC
9, 58, 45
CMOS
Clock Inputs. CMOS-compatible. VINX is sampled on the falling
edge of CLKX.
DA7-0
4, 3, 2, 80, 79,
78, 77, 76
CMOS/
TTL
Data outputs, Converter A (D7 = MSB). Eight-bit CMOS- and
TTL-compatible digital outputs. Valid data is output on the rising
edge of CLKX.
DB7-0
63, 64, 65, 66,
67, 68, 69, 70
CMOS/
TTL
Data outputs, Converter B (D7 = MSB). Eight-bit CMOS- and
TTL-compatible digital outputs. Valid data is output on the rising
edge of CLKX.
DC7-0
41, 40, 39, 38,
37, 36, 35, 34
CMOS/
TTL
Data outputs, Converter C (D7 = MSB). Eight-bit CMOS- and
TTL-compatible digital outputs. Valid data is output on the rising
edge of CLKX.
5, 62, 42
CMOS
Output Enable Inputs. CMOS-compatible. When LOW, the A/D
output is enabled. When HIGH, the output is in a high-impedance
state.
VCLPA, VCLPB,
VCLPB
16, 17, 18
RTX to
RBX
Clamp Reference Voltage. One reference for each clamp. A VINX
input is clamped to VCLPX when CLPX is low.
CLPA, CLPB,
CLPC
28, 29, 30
CMOS
Clamp Pulse Inputs. One input for each A/D clamp. When CLPX is
low, the VINX input is clamped to the VCLPX clamp voltage.
11, 47, 56
+5V
Analog Supply Voltage. +5 Volt power inputs. These should come
from the same power source and be decoupled to AGND.
6, 7, 27, 28, 29,
30, 43, 44, 60,
61
+5V
Digital Supply Voltage. +5 Volt power inputs. These should come
from the same power source and be decoupled to AGND.
AGND
13, 49, 54
0.0V
Analog Ground. Ground connections. These pins should be
connected to the system analog ground plane.
DGND
16, 17, 18, 19,
20, 21, 22, 25,
26, 32, 33, 71,
72, 74, 75
0.0V
Digital Ground. Ground connections. These pins should be
connected to the system analog ground plane.
1, 8, 10, 23, 24,
31, 46, 57, 59,
73
open
Not Connected.
A/D Converters
OEA, OEB, OEC
Clamps
Power
VDDA
VDD
No Connect
N/C
4
PRODUCT SPECIFICATION
TMC1103
Sample N+3
tSTD
VINX
Sample N+2
Sample N
Sample N+1
tPWL
tPWH
1/fS
CLKX
tDO
tHO
Hi-Z
DX7-0
Data N-3
Data N-2
tDIS
Data N-1
Data N
tENA
OEX
65-1103-04
Figure 1. Timing
Equivalent Circuits and Threshold Levels
VDD
VDD
p
p
Digital
Input
Digital
Output
n
n
27011B
27014B
GND
Figure 2. Equivalent Digital Input Circuit
GND
Figure 3. Equivalent Digital Output Circuit
5
TMC1103
PRODUCT SPECIFICATION
Equivalent Circuits and Threshold Levels (continued)
VRT
VDDA
tENA
VIN
OE
tDIS
0.5V
Three-State
Outputs
AGND
Absolute Maximum Ratings
7048B
0.5V
29030
VRB
Figure 4. Equivalent Analog Input Circuit
Parameter
2.0V
0.8V
High Impedance
Figure 5. Threshold Levels for Three-State Measurements
(beyond which the device may be damaged)1
Condition
Min
VDDA
Measured to AGND
VDD
VDDA
AGND
Typ
Max
Unit
-0.5
+7.0
V
Measured to DGND
-0.5
+7.0
V
Measured to VDD
-0.5
+0.5
V
Measured to DGND
-0.5
+0.5
V
Measured to DGND
-0.5
VDD + 0.5
V
-10.0
+10.0
mA
-0.5
VDDA+0.5
V
-10.0
+10.0
mA
-0.5
VDD + 0.5
V
-6.0
+6.0
mA
Power Supply Voltages
Digital Inputs
Applied Voltage
Forced current
Analog Inputs
Applied Voltage
Measured to AGND
Forced current
Digital Outputs
Applied voltage
Measured to DGND
Forced current
Short circuit duration
Single output in HIGH state to ground)
1 second
Temperature
Operating, ambient
-20
110
°C
+150
°C
Lead, soldering
10 seconds
+300
°C
Vapor Phase soldering
1 minute
+220
°C
+150
°C
±150
V
Junction
Storage
Electrostatic Discharge
-65
EIAJ test method
Notes:
1. Absolute maximum ratings are limiting values applied individually while all other parameters are within specified operating
conditions. Functional operation under any of these conditions is NOT implied. Performance and reliability are guaranteed
only if Operating Conditions are not exceeded.
2. Applied voltage must be current limited to specified range.
3. Forcing voltage must be limited to specified range.
4. Current is specified as conventional current flowing into the device.
6
PRODUCT SPECIFICATION
TMC1103
Operating Conditions
Parameter
Min.
Nom
Max.
Units
VDD, VDDA
Power Supply Voltage
4.75
5.0
5.25
V
AGND
Analog Ground (Measured to DGND)
-0.1
0
0.1
V
VRTX
Reference Voltage, Top
2.6
VDDA
V
VRBX
Reference Voltage, Bottom
VRTX-VRBX
0
0.6
Reference Voltage Differential
1.0
2.0
VRB
V
5.0
V
VRT
V
VINX
Analog Input Range
VCLPX
Clamp Reference Voltage, 50W max source
VIH
Input Voltage, Logic HIGH
0.7 VDD
VDD
V
VIL
Input Voltage, Logic LOW
GND
0.3 VDD
V
IOH
Output Current, Logic HIGH
-4.0
mA
IOL
Output Current, Logic LOW
4.0
mA
TA
Ambient Temperature, Still Air
70
°C
0
V
0
Electrical Characteristics
Parameter
IDD
Power Supply
Conditions
Current1
Min.
PD
CAI
Power Supply Current,
Quiescent
Total Power Dissipation1
Input Capacitance, Analog
Max.
Units
70
90
mA
CLOAD = 35pF, fCK = fS (3 A/Ds)
fS = 20 Msps
IDDQ
Typ1
fS = 40 Msps
94
120
mA
fS = 50 Msps
105
135
mA
VDD = VDDA = Max.
CLKX = LOW
29
55
mA
CLKX = HIGH
45
65
mA
fS = 20 Msps
300
470
mW
fS = 40 Msps
425
630
mW
fS = 50 Msps
490
710
mW
CLKX = LOW
4
pF
CLKX = HIGH
12
pF
CLOAD = 35pF, fCK = fS (3 A/Ds)
RIN
Input Resistance
500
RREF
Reference Resistance
200
ICB
Input Current, Analog
IIH
Input Current, HIGH
VDD = Max., VIN = VDD
IIL
Input Current, LOW
IOZH
kW
340
W
±5
mA
±5
mA
VDD = Max., VIN = 0V
±5
mA
Hi-Z Output Leakage Current,
Output HIGH
VDD = Max., VIN = VDD
±5
mA
IOZL
Hi-Z Output Leakage Current,
Output LOW
VDD = Max., VIN = VDD
±5
mA
IOS
Short-Circuit Current
35
mA
270
7
TMC1103
PRODUCT SPECIFICATION
Electrical Characteristics (continued)
Parameter
VOH
Conditions
Output Voltage, HIGH
Min.
Typ1
Max.
Units
IOH = -2.5mA
3.5
V
IOH = Max.
2.4
V
VOL
Output Voltage, LOW
IOL = Max.
CDI
Digital Input Capacitance
4
CDO
Digital Output Capacitance
10
0.4
V
10
pF
pF
Note:
1. Typical values with VDD = VDDA = Nom and TA = Nom, Maximum values with VDD = VDDA = Max. and TA = Min.
Switching Characteristics
Parameter
fS
tPWH
tPWL
8
Conditions
Min.
Typ.
Max.
Units
TMC1103-20
20
Msps
TMC1103-40
40
Msps
TMC1103-50
50
Msps
Conversion Rate
CLKX Pulsewidth, HIGH
TMC1103-20
14
ns
TMC1103-40
14
ns
TMC1103-50
13
ns
TMC1103-20
8
ns
TMC1103-40
8
ns
TMC1103-50
7
ns
CLKX Pulsewidth, LOW
EAP
Aperture Error
tSTO
Sampling Time Offset
tSTS
Sampling Time Skew
Width1
tCPW
Clamp Pulse
tCDLY
Clamp Delay Time
tHO
Output Hold Time
tDO
30
1
+20 < TA < +70°C
ps
2
5
ns
150
400
ps
mS
2
100
300
ns
Output Delay Time
14
ns
tENA
Output Enable Time
27
ns
tDIS
Output Disable Time
42
ns
CLOAD = 15pF
9
ns
PRODUCT SPECIFICATION
TMC1103
System Performance Characteristics
Parameter
Conditions
Min.
Typ.
Max.
Units
ELI
Integral Linearity Error,
Independent
VRT = 2.6V
±0.5
LSB
ELD
Differential Linearity Error
VRB = 0.6V
±0.5
LSB
BW
1
Bandwidth
TMC1203-20
10
MHz
TMC1203-40
12
MHz
12
MHz
EOT
Offset Voltage, Top
(RT – VIN for most positive
code transition)
TMC1203-50
VRT = 2.6V, VRB = 0.6V
-40
80
mV
EOB
Offset Voltage, Bottom
(RB – VIN for most negative
code transition)
VRT = 2.6V, VRB = 0.6V
-95
-30
mV
OFFCL
Offset Voltage, Clamp
±20
mV
dg
Differential Gain
fS = 14.3Msps
NTSC 40 IRE Mod Ramp
VDDA = +5.0V, TA=25°C
VRT = 2.6V, VRB = 0.6V
1.8
%
dp
Differential Phase
fS = 14.3Msps
NTSC 40 IRE Mod Ramp
VDDA = +5.0V, TA=25°C
VRT = 2.6V, VRB = 0.6V
0.7
deg
XTALK
Channel Crosstalk
fN = 5.0 MHz
45
dB
SNR
Signal-to-Noise Ratio
fS = 20Msps, VRT = 2.6V, VRB = 0.6V
fN = 1.24MHz
46
dB
fN = 2.48MHz
46
dB
fN = 6.98MHz
45
dB
fN = 10.0MHz
45
dB
fN = 1.24MHz
42
dB
fN = 6.98MHz
41
dB
fN = 12.0MHz
40
dB
fN = 1.24MHz
40
dB
fN = 6.98MHz
40
dB
fN = 12.0MHz
40
dB
fS = 40Msps, VRT = 2.6V, VRB = 0.6V
fS = 50Msps, VRT = 2.6V, VRB = 0.6V
9
TMC1103
PRODUCT SPECIFICATION
System Performance Characteristics (continued)
Parameter
SFDR
Spurious-Free Dynamic Range
Conditions
Min.
Typ.
Max.
Units
fS = 20Msps, VIN = 2V p-p
fN = 1.24MHz
53
dB
fN = 2.48MHz
48
dB
fN = 6.98MHz
44
dB
fN = 10.0MHz
40
dB
fN = 1.24MHz
49
dB
fN = 6.98MHz
44
dB
fN = 12.0MHz
38
dB
fN = 1.24MHz
46
dB
fN = 6.98MHz
40
dB
fN = 12.0MHz
37
dB
fS = 40Msps, VIN = 2V p-p
fS = 50Msps, VIN = 2V p-p
Notes:
1. Bandwidth is the frequency up to which a full-scale sinewave can be digitized without spurious codes.
2. Values shown in Typ. column are typical for VDD = VDDA = +5V and TA = 25°C.
3. SNR values do not include the harmonics of the fundamental frequency.
4. SFDR is the ratio in dB of fundamental amplitude to the harmonic with the highest amplitude.
5. Characteristics specified for VRT = 2.6V, VRB = 0.6V.
10
PRODUCT SPECIFICATION
TMC1103
Typical Performance Characteristics
60
30
50
25
40
SFDR (dB)
IDD
35
20
15
10
30
fS = 20Msps
20
10
5
0
0
0
10
20
30
fS (Msps)
40
50
0
15
20
25
65-1103-06
Figure 7. Typical SFDR vs fIN
50
50
40
40
SNR (dB)
SNR (dB)
10
fIN (Msps)
Figure 6. Typical IDD vs fS (Single A/D)
30
20
5
65-1103-05
fS = 20Msps
10
30
20
fS = 20Msps
10
0
0
0
5
10
15
fIN (MHz)
Figure 8. Typical SNR vs fIN
20
25
65-1103-07
0
1
2
3
VIN
4
5
65-1103-08
Figure 9. Typical SNR vs Full Scale Input Range
11
TMC1103
PRODUCT SPECIFICATION
Application Notes
The circuit in Figure 10 employs a band-gap reference to
generate a variable RTX reference voltages for the TMC1103
as well as a bias voltage to offset the wideband input amplifiers to mid-range. The operational amplifier in the reference
circuitry is a standard 741-type.
The voltage reference at RTX can be adjusted from 0.0 to 2.4
volts while RBX is grounded. Schottky diodes can be used at
VINX to restrict the wideband amplifier output to between
-0.3V and VDD +0.3V. Diode protection is good practice to
limit the analog input voltage at VINX to the safe operating
range.
+5V
0.1µF
LM185-1.2
0.1µF
1k½
+5V
0.1µF
VDDA
Gain Adjust
2k½
+
20½
0.1µF
–
1k½
0.1µF
RBA
RBB
RBC
1k½
100
GREEN
Video
Input
+
VINA
VCLPA
CLPA
1k½
10k½
+5V
0.1µF
GREEN
Digital
Video
Output
DA7-0
0.1µF
–
75½
RTA
RTB
RTC
VDD
VDDP
OEA
CLKA
TMC1103
1k½
BLUE
Digital
Video
Output
DB7-0
100
BLUE
Video
Input
+
0.1µF
VINB
VCLPB
CLPB
–
75½
1k½
10k½
1k½
VCLPC
CLPC
+
75½
0.1µF
OEC
Pixel
Clock
CLKC
VINC
–
AGND
1k½
10k½
RED
Digital
Video
Output
DC7-0
100
RED
Video
Input
OEB
CLKB
DGND
VCLAMP
1k½
65-1103-09
CLAMP
Figure 10. Typical Interface Circuit – High Performance
Grounding
Printed Circuit Board Layout
The TMC1103 has separate analog and digital circuits. To
keep digital system noise from the A/D converter, it is recommended that power supply voltages (VDD and VDDA)
come from the same source, and that ground connections
(DGND and AGND) be made to the analog ground plane, and
as close as possible to the device pins. Power supply pins
should be individually decoupled at the pin. The digital circuitry that gets its input from the TMC1103 should be
referred to the system digital ground plane.
Designing with high performance mixed-signal circuits
demands printed circuits with ground planes. Overall system
performance is strongly influenced by the board layout.
Capacitive coupling from digital to analog circuits may
result in poor A/D conversion. Consider the following suggestions when doing the layout:
12
1.
Keep the critical analog traces (VN, RTX, RBX) as short
as possible and as far as possible from all digital signals.
The TMC1103 should be located close to the analog
input connectors.
PRODUCT SPECIFICATION
2.
Segregate traces:
•
•
•
•
TMC1103
5.
Decoupling capacitors should be applied liberally to
VDD pins. Remember that not all power supply pins
are created equal. They supply different circuits on the
integrated circuit, each of which generate varying
amounts and types of noise. For best results, use 0.1mF
ceramic capacitors. Lead lengths should be minimized.
6.
CLKX should be handled carefully. Jitter and noise on
this clock may degrade performance. Terminate the
clock line, if needed, to eliminate overshoot and ringing.
A/D analog
D/A analog
Clocks
Digital
Treat analog inputs as transmission lines. Cleanly route
traces over the ground plane bearing in mind that the
return currents will flow through the ground plane
beneath the traces. Do not route digital traces nearby.
A few inches of digital trace less than a few line widths
from an analog trace will cross-couple noise into
adjacent analog circuits.
3.
The power plane for the TMC1103 should be separate
from that which supplies the rest of the digital circuitry.
A single power plane should be used for all of the VDD
pins. If the power supply for the TMC1103 is the same
as that of the system's digital circuitry, power to the
TMC1103 should be decoupled with ferrite beads and
0.1mF capacitors to reduce noise.
4.
The ground plane should be solid, not cross-hatched.
Connections to the ground plane should have very short
leads.
Related Products
• TMC1175A, TMC1275 8-Bit Video A/D Converters
• TMC1173A, TMC1273 3V, Low-Power 8-Bit Video
A/D Converters
• TMC1203 Triple 8-bit A/D Converter
• TMC3003/TMC3503 Triple Video D/A Converters
• TMC2242B/TMC2243/TMC2246A Digital Filters
13
TMC1103
Notes:
14
PRODUCT SPECIFICATION
PRODUCT SPECIFICATION
TMC1103
Mechanical Dimensions – 80-Lead MQFP Package
Inches
Symbol
Millimeters
Min.
Max.
Min.
Max.
A
A1
A2
B
—
.010
.100
.012
—
.25
2.55
.30
C
D
D1
E
.005
.904
.783
.667
.134
—
.120
.018
.009
.923
.791
.687
3.40
—
3.05
.45
.23
23.45
20.10
17.45
E1
e
L
N
ND
NE
.547
.555
.0315 BSC
.025
.041
80
24
16
a
ccc
0¡
—
.13
22.95
19.90
16.95
Notes:
Notes
2. Controlling dimension is millimeters.
3, 5
5
0¡
—
3. Dimension "B" does not include dambar protrusion. Allowable
dambar protrusion shall be .08mm (.003in.) maximum in excess of
the "B" dimension. Dambar cannot be located on the lower radius
or the foot.
4. "L" is the length of terminal for soldering to a substrate.
5. "B" & "C" includes lead finish thickness.
13.90
14.10
.80 BSC
.65
1.03
80
24
16
7¡
.004
1. All dimensions and tolerances conform to ANSI Y14.5M-1982.
4
7¡
0.10
D
D1
.20 (.008) Min.
e
0¡ Min.
Datum Plane
.13 (.30)
R
.005 (.012)
C
E1
E
Pin 1
Identifier
a
.13 (.005) R Min.
B
L
0.063" Ref (1.60mm)
Lead Detail
See Lead Detail
A
Base Plane
A2
A1
Seating Plane
-CLEAD COPLANARITY
ccc C
15
TMC1103
PRODUCT SPECIFICATION
Ordering Information
Product Number
Conversion
Rate (Msps)
Temperature Range
Screening
Package
Package Marking
TMC1103KLC20
20 Msps
TA = 0°C to 70°C
Commercial
80-Lead MQFP
1103KLC20
TMC1103KLC40
40 Msps
TA = 0°C to 70°C
Commercial
80-Lead MQFP
1103KLC40
TMC1103KLC50
50 Msps
TA = 0°C to 70°C
Commercial
80-Lead MQFP
1103KLC50
6/22/98 0.0m 002
Stock# DS70001103