TPS7A3401 SBVS163 – JUNE 2011 www.ti.com –20-V, –200-mA, Low-Noise NEGATIVE VOLTAGE REGULATOR Check for Samples: TPS7A3401 FEATURES DESCRIPTION • • The TPS7A3401 is a negative, high-voltage (–20 V), low-noise linear regulator capable of sourcing a maximum load of 200 mA. 1 23 • • • • • • • • • Input Voltage Range: –3 V to –20 V Noise: – 80 μVRMS (10 Hz to 100 kHz) Power-Supply Ripple Rejection: – 50 dB (1 kHz) – ≥ 27 dB (10 Hz to 1 MHz) Adjustable Output: ~ –1.18 V to –18 V Maximum Output Current: 200 mA Dropout Voltage: 500 mV at 100 mA Stable with Ceramic Capacitors ≥ 2.2 μF CMOS Logic-Level-Compatible Enable Pin Built-In, Fixed, Current-Limit and Thermal Shutdown Protection Available in High Thermal Performance MSOP-8 PowerPAD™ Package Operating Tempature Range: –40°C to +125°C APPLICATIONS • • Cost-Effective Supply Rails for Op Amps, DACs, ADCs, and Other High-Precision Analog Circuitry Cost-Effective Post DC/DC Converter Regulation and Ripple Filtering These linear regulators include a CMOS logic-level-compatible enable pin. Other features available include built-in current limit and thermal shutdown protection to safeguard the device and system during fault conditions. The TPS7A3401 is designed using bipolar technology, and is ideal for instrumentation applications where clean voltage rails are critical to improve system performance. This design makes it a cost-effective choice to power operational amplifiers, analog-to-digital converters (ADCs), digital-to-analog converters (DACs), and other analog circuitry. In addition, the TPS7A3401 linear regulator is suitable for cost-effective, post dc/dc converter regulation. By filtering out the output voltage ripple inherent to dc/dc switching conversion, increased system performance is provided in instrumentation applications. Typical Application DGN PACKAGE 3mm ´ 5mm MSOP-8 PowerPAD (TOP VIEW) OUT FB GND GND 1 2 3 4 8 7 6 5 IN GND GND EN +18V IN OUT +15V TPS7A49 -18V EN GND IN OUT -15V TPS7A34 EN GND EVM Post DC/DC Converter Regulation 1 2 3 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PowerPAD is a trademark of Texas Instruments. All other trademarks are the property of their respective owners. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2011, Texas Instruments Incorporated TPS7A3401 SBVS163 – JUNE 2011 www.ti.com This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. ORDERING INFORMATION (1) PRODUCT TPS7A34xx yyy z (1) (2) VOUT XX is nominal output voltage (01 = Adjustable). (2) YYY is package designator. Z is package quantity. For the most current package and ordering information see the Package Option Addendum at the end of this document, or visit the device product folder on www.ti.com. For fixed -1.2-V operation, tie FB to OUT. ABSOLUTE MAXIMUM RATINGS (1) Over operating free-air temperature range (unless otherwise noted). VALUE MIN MAX UNIT IN pin to GND pin –22 +0.3 V OUT pin to GND pin –22 +0.3 V OUT pin to IN pin –0.3 +22 V –2 +0.3 V FB pin to IN pin –0.3 +22 V EN pin to IN pin –0.3 +22 V EN pin to GND pin –22 +22 V NR/SS pin to IN pin –0.3 +22 V –2 +0.3 V FB pin to GND pin Voltage NR/SS pin to GND pin Current Peak output Temperature Electrostatic discharge rating (1) Internally limited Operating virtual junction, TJ –40 +125 °C Storage, Tstg –65 +150 °C 1500 V 500 V Human body model (HBM) Charged device model (CDM) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated is not implied. Exposure to absolute-maximum rated conditions for extended periods may affect device reliability. THERMAL INFORMATION TPS7A3401 THERMAL METRIC (1) DGN UNITS 8 PINS θJA Junction-to-ambient thermal resistance 55.09 θJC(top) Junction-to-case(top) thermal resistance 8.47 θJB Junction-to-board thermal resistance ψJT Junction-to-top characterization parameter 0.36 ψJB Junction-to-board characterization parameter 14.6 θJC(bottom) Junction-to-case(bottom) thermal resistance — (1) 2 — °C/W For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953. Copyright © 2011, Texas Instruments Incorporated TPS7A3401 SBVS163 – JUNE 2011 www.ti.com ELECTRICAL CHARACTERISTICS (1) At TJ = –40°C to +125°C, |VIN| = |VOUT(NOM)| + 1.0 V or |VIN| = 3.0 V (whichever is greater), VEN = VIN, IOUT = 1 mA, CIN = 2.2 µF, COUT = 2.2 µF, and the FB pin tied to OUT, unless otherwise noted. TPS7A3401 PARAMETER VIN Input voltage range VREF Internal reference TEST CONDITIONS MIN TYP –20.0 TJ = +25°C, VFB = VREF (2) –1.184 UNIT –3.0 V –1.166 V –18.0 VREF V Nominal accuracy TJ = +25°C, |VIN| = |VOUT(NOM)| + 0.5 V –1.5 +1.5 %VOUT Overall accuracy |VOUT(NOM)| + 1.0 V ≤ |VIN| ≤ 20 V 1 mA ≤ IOUT ≤ 200 mA –2.5 +2.5 %VOUT DVOUT(DVIN) VOUT(NOM) Line regulation TJ = +25°C, |VOUT(NOM)| + 1.0 V ≤ |VIN| ≤ 20 V 0.14 %VOUT DVOUT(DIOUT) VOUT(NOM) Load regulation TJ = +25°C, 1 mA ≤ IOUT ≤ 200 mA 0.04 %VOUT VIN = 95% VOUT(NOM), IOUT = 100 mA 216 mV Output voltage range VOUT |VDO| Dropout voltage ILIM Current limit IGND Ground current |ISHDN| Shutdown supply current I FB Feedback current (3) |IEN| Enable current V+EN_HI Positive enable high-level voltage V+EN_LO Positive enable low- level voltage V–EN_HI Negative enable high-level voltage V–EN_LO Negative enable low- level voltage |VIN| ≥ |VOUT(NOM)| + 1.0 V –1.202 MAX VIN = 95% VOUT(NOM), IOUT = 200 mA VOUT = 90% VOUT(NOM) IOUT = 0 mA 500 800 mV 330 500 mA 55 100 μA μA IOUT = 100 mA 950 VEN = +0.4 V 1.0 5.0 μA VEN = –0.4 V 1.0 5.0 μA 14 100 nA VEN = |VIN| = |VOUT(NOM)| + 1.0 V 0.48 1.0 μA VIN = VEN = –20 V 0.51 1.0 μA VIN = –20 V, VEN = +15 V 0.50 1.0 μA V TJ = –40°C to +125°C +2.0 +15 TJ = –40°C to +85°C +1.8 +15 VNOISE Output noise voltage VIN = –3 V, VOUT(NOM) = VREF, COUT = 10 μF, BW = 10 Hz to 100 kHz PSRR Power-supply rejection ratio VIN = –6.2 V, VOUT(NOM) = –5 V, COUT = 10 μF, f = 1 kHz TSD Thermal shutdown temperature TJ Operating junction temperature range (1) (2) (3) 200 0 +0.4 V VIN –2.0 V –0.4 0 V 80 μVRMS 50 dB Shutdown, temperature increasing +170 °C Reset, temperature decreasing +150 °C –40 +125 °C At operating conditions, VIN ≤ 0 V, VOUT(NOM) ≤ VREF ≤ 0 V. At regulation, VIN ≤ VOUT(NOM) – |VDO|. IOUT > 0 flows from OUT to IN. To ensure stability at no load conditions, a current from the feedback resistive network equal to or greater than 5 μA is required. IFB > 0 flows into the device. Copyright © 2011, Texas Instruments Incorporated 3 TPS7A3401 SBVS163 – JUNE 2011 www.ti.com DEVICE INFORMATION FUNCTIONAL BLOCK DIAGRAM GND EN Enable FB Bandgap Antisaturation OUT Error Amp Pass Device Thermal Shutdown Current Limit IN TYPICAL APPLICATION CIRCUIT VIN OUT IN CIN 10 mF EN TPS7A3401 CBYP 10 nF VOUT R1 FB R2 GND Where: COUT 10 mF VOUT ³ 5 mA, and R1 + R2 R1 = R2 VOUT -1 VREF Maximize PSRR Performance and Minimize RMS Noise 4 Copyright © 2011, Texas Instruments Incorporated TPS7A3401 SBVS163 – JUNE 2011 www.ti.com PIN CONFIGURATION DGN PACKAGE MSOP-8 (TOP VIEW) OUT FB GND GND 1 2 3 4 8 7 6 5 IN GND GND EN PIN DESCRIPTIONS PIN NO. NAME 1 OUT 2 FB 3, 4, 6, 7 GND 5 EN This pin turns the regulator on or off. If VEN ≥ V+EN_HI or VEN ≤ V–EN_HI, the regulator is enabled. If V+EN_LO ≥ VEN ≥ V–EN_LO, the regulator is disabled. The EN pin can be connected to IN, if not used. |VEN| ≤ |VIN|. 8 IN Input supply PowerPAD DESCRIPTION Regulator output. A capacitor ≥ 10 µF must be tied from this pin to ground to assure stability. This pin is the input to the control-loop error amplifier. It is used to set the output voltage of the device. Ground Must either be left open or tied to GND. Solder to printed circuit board (PCB) plane to enhance thermal performance. Copyright © 2011, Texas Instruments Incorporated 5 TPS7A3401 SBVS163 – JUNE 2011 www.ti.com TYPICAL CHARACTERISTICS At TJ = –40°C to +125°C, |VIN| = |VOUT(NOM)| + 1.0 V or |VIN| = 3.0 V (whichever is greater), VEN = VIN, IOUT = 1 mA, CIN = 2.2 μF, COUT = 2.2 μF, and the FB pin tied to OUT, unless otherwise noted. FEEDBACK VOLTAGE vs INPUT VOLTAGE FEEDBACK CURRENT vs TEMPERATURE 100 -1.165 90 80 70 IFB (nA) VFB (V) -1.17 -1.175 +125°C +105°C +85°C +25°C -40°C -1.18 60 50 40 30 20 10 0 -1.185 -25 -20 -15 -10 0 -5 -40 -25 -10 5 VIN (V) Figure 1. 80 95 110 125 Figure 2. GROUND CURRENT vs INPUT VOLTAGE GROUND CURRENT vs INPUT VOLTAGE 2500 1200 0 mA 10 mA 50 mA 100 mA 200 mA 2000 TJ = +25°C 1000 800 1500 IGND (mA) IGND (mA) 20 35 50 65 Temperature (°C) 1000 600 +125°C +105°C +85°C +25°C -40°C 400 500 200 IOUT = 100 mA 0 0 -25 -20 -15 -10 0 -5 -25 -20 -15 -10 VIN (V) VIN (V) Figure 3. Figure 4. GROUND CURRENT vs OUTPUT CURRENT 0 -5 ENABLE CURRENT vs ENABLE VOLTAGE 2500 1000 +125°C +25°C -40°C 800 2000 600 IEN (nA) IGND (mA) 400 1500 1000 +125°C +105°C +85°C +25°C -40°C 500 0 0 -200 -400 -600 -800 -1000 0 20 40 60 80 100 120 140 160 180 200 IOUT (mA) Figure 5. 6 200 -35 -25 -15 5 -5 VEN (V) 15 25 35 Figure 6. Copyright © 2011, Texas Instruments Incorporated TPS7A3401 SBVS163 – JUNE 2011 www.ti.com TYPICAL CHARACTERISTICS (continued) At TJ = –40°C to +125°C, |VIN| = |VOUT(NOM)| + 1.0 V or |VIN| = 3.0 V (whichever is greater), VEN = VIN, IOUT = 1 mA, CIN = 2.2 μF, COUT = 2.2 μF, and the FB pin tied to OUT, unless otherwise noted. QUIESCENT CURRENT vs INPUT VOLTAGE SHUTDOWN CURRENT vs INPUT VOLTAGE 100 3.5 90 +125°C +105°C +85°C +25°C -40°C 3 80 2.5 ISHDN (mA) IQ (mA) 70 60 50 40 +125°C +105°C +85°C +25°C -40°C 30 20 10 IOUT = 0 mA 0 -25 -20 -15 -10 2 1.5 1 0.5 VEN = -0.4 V 0 0 -5 -25 -20 -15 0 -5 Figure 7. Figure 8. DROPOUT VOLTAGE vs OUTPUT CURRENT DROPOUT VOLTAGE vs TEMPERATURE 450 500 400 450 350 400 350 VDO (mV) 300 VDO (mV) -10 VIN (V) VIN (V) 250 200 +125°C +105°C +85°C +25°C -40°C 150 100 50 10 mA 50 mA 100 mA 200 mA 300 250 200 150 100 50 0 0 0 20 40 60 80 100 120 140 160 180 200 IOUT (mA) -40 -25 -10 5 Figure 9. 80 95 110 125 Figure 10. CURRENT LIMIT vs INPUT VOLTAGE CURRENT LIMIT vs TEMPERATURE 450 500 VOUT = 90% VOUT(NOM) 400 20 35 50 65 Temperature (°C) 450 350 400 ILIM (mA) ILIM (mA) 300 250 200 +125°C +105°C +85°C +25°C -40°C 150 100 50 350 300 250 0 200 -10 -9 -8 -7 -6 VIN (V) Figure 11. Copyright © 2011, Texas Instruments Incorporated -5 -4 -3 -40 -25 -10 5 20 35 50 65 Temperature (°C) 80 95 110 125 Figure 12. 7 TPS7A3401 SBVS163 – JUNE 2011 www.ti.com TYPICAL CHARACTERISTICS (continued) At TJ = –40°C to +125°C, |VIN| = |VOUT(NOM)| + 1.0 V or |VIN| = 3.0 V (whichever is greater), VEN = VIN, IOUT = 1 mA, CIN = 2.2 μF, COUT = 2.2 μF, and the FB pin tied to OUT, unless otherwise noted. ENABLE THRESHOLD VOLTAGE vs TEMPERATURE LINE REGULATION 1 2 ON 1.5 +125°C +105°C +85°C +25°C -40°C 0.8 0.6 1 VOUT(NOM) (%) 0.4 VEN (V) 0.5 0 OFF -0.5 0.2 0 -0.2 -0.4 -1 -0.6 -1.5 -0.8 ON -1 -2 -40 -25 -10 5 20 35 50 65 Temperature (°C) 80 95 110 125 -25 -20 -15 Figure 13. POWER-SUPPLY REJECTION RATIO LOAD REGULATION 1 80 0.8 VOUT(NOM) (%) PSRR (dB) 0.4 60 50 20 10 +125°C +105°C +85°C +25°C -40°C 0.6 70 30 VOUT = -5 V VIN = -6.2 V IOUT = 200 mA COUT = 10 mF CBYP = 0 mF 10 100 0 -5 Figure 14. 90 40 -10 VIN (V) 0.2 0 -0.2 -0.4 -0.6 -0.8 -1 1k 100k 10k Frequency (Hz) 1M 0 10M 20 40 60 Figure 15. 80 100 120 140 160 180 200 IOUT (mA) Figure 16. Output Spectral Noise Density (mV/ÖHz) OUTPUT SPECTRAL NOISE DENSITY 10 VOUT = -1.2 V VIN = -3 V IOUT = 200 mA COUT = 10 mF 1 0.1 0.01 10 100 1k Frequency (Hz) 10k 100k Figure 17. 8 Copyright © 2011, Texas Instruments Incorporated TPS7A3401 SBVS163 – JUNE 2011 www.ti.com THEORY OF OPERATION GENERAL DESCRIPTION The TPS7A3401 belongs to a new generation of linear regulators that use an innovative bipolar process to achieve low noise and high PSRR levels at a wide input voltage range. These features, combined with a high thermal performance MSOP-8 with PowerPAD package, make this device ideal for analog applications. This functionality allows for different system power management topologies: • Connecting the EN pin directly to a negative voltage, such as VIN, or • Connecting the EN pin directly to a positive voltage, such as the output of digital logic circuitry. ADJUSTABLE OPERATION The TPS7A3001 has an output voltage range of –1.184 V to –17 V. The nominal output voltage of the device is set by two external resistors, as shown in Figure 18. VEN VOUT VIN OUT IN CIN 10 mF VOUT EN TPS7A3401 CBYP 10 nF VIN R1 FB R2 COUT 10 mF Time (20 ms/div) GND Figure 19. Enable Pin Positive/Negative Threshold Figure 18. Adjustable Operation for Maximum AC Performance R1 and R2 can be calculated for any output voltage range using the formula shown in Equation 1. To ensure stability under no load conditions, this resistive network must provide a current equal to or greater than 5 μA. VOUT VOUT ³ 5 mA R1 = R2 - 1 , where R1 + R2 VREF (1) If greater voltage accuracy is required, take into account the output voltage offset contributions because of the feedback pin current and use 0.1% tolerance resistors. ENABLE PIN OPERATION The TPS7A3401 provides a dual polarity enable pin (EN) that turns on the regulator when |VEN| > 2.0 V, whether the voltage is positive or negative, as shown in Figure 19. Copyright © 2011, Texas Instruments Incorporated CAPACITOR RECOMMENDATIONS Low equivalent series resistance (ESR) capacitors should be used for the input, output, noise reduction, and bypass capacitors. Ceramic capacitors with X7R and X5R dielectrics are preferred. These dielectrics offer more stable characteristics. Ceramic X7R capacitors offer improved over-temperature performance, while ceramic X5R capacitors are more cost-effective and are available in higher values. Note that high ESR capacitors may degrade PSRR. INPUT AND OUTPUT CAPACITOR REQUIREMENTS The TPS7A3401 negative, high-voltage linear regulator achieves stability with a minimum input and output capacitance of 2.2 μF. TRANSIENT RESPONSE As with any regulator, increasing the size of the output capacitor reduces over/undershoot magnitude but increases duration of the transient response. 9 TPS7A3401 SBVS163 – JUNE 2011 www.ti.com APPLICATION INFORMATION POWER FOR PRECISION ANALOG One of the primary TPS7A3401 applications is to provide low-noise voltage rails to analog circuitry in order to improve system accuracy and precision. The TPS7A3401 negative high-voltage linear regulator provides a low-noise voltage rail to analog circuitry, such as operational amplifiers, ADCs, and DACs. Because of the low noise levels at high voltages, analog circuitry with high-voltage input supplies can be used. This characteristic allows for analog solutions to optimize the voltage range, thereby maximizing system accuracy. POST DC/DC CONVERTER FILTERING Most of the time, the voltage rails available in a system do not match the voltage specifications demanded by one or more of its circuits; these rails must be stepped up or down, depending on specific voltage requirements. 10 DC/DC converters are generally the preferred solution to step up or down a voltage rail when current consumption is not negligible. They offer high efficiency with minimum heat generation, but they have one primary disadvantage: they introduce a high-frequency component, and the associated harmonics, on top of the dc output signal. This high-frequency component, if not filtered properly, degrades analog circuitry performance, reducing overall system accuracy and precision. The TPS7A3401 offers a wide-bandwidth, high power-supply rejection ratio (PSRR). It is highly recommended to use the maximum performance schematic shown in Figure 18. Also, verify that the fundamental frequency (and its first harmonic, if possible) is within the bandwidth of the regulator PSRR, shown in Figure 15. Copyright © 2011, Texas Instruments Incorporated TPS7A3401 SBVS163 – JUNE 2011 www.ti.com LAYOUT PACKAGE MOUNTING Solder pad footprint recommendations for the TPS7A3401 are available at the end of this product datasheet and at www.ti.com. BOARD LAYOUT RECOMMENDATIONS TO IMPROVE PSRR AND NOISE PERFORMANCE To improve ac performance such as PSRR, output noise, and transient response, it is recommended that the board be designed with separate ground planes for IN and OUT, with each ground plane connected only at the GND pin of the device. In addition, the ground connection for the output capacitor should connect directly to the GND pin of the device. Equivalent series inductance (ESL) and equivalent series resistance (ESR) must be minimized in order to maximize performance and ensure stability. Every capacitor (CIN, COUT, CBYP) must be placed as close as possible to the device and on the same side of the printed circuit board (PCB) as the regulator itself. Do not place any of the capacitors on the opposite side of the PCB from where the regulator is installed. The use of vias and long traces is strongly discouraged because they may impact system performance negatively and even cause instability. If possible, and to ensure the maximum performance denoted in this product data sheet, use the same layout pattern used for the TPS7A30 evaluation board, available at www.ti.com. THERMAL PROTECTION complete design (including heatsink), increase the ambient temperature until the thermal protection is triggered; use worst-case loads and signal conditions. For good reliability, thermal protection should trigger at least +35°C above the maximum expected ambient condition of your particular application. This configuration produces a worst-case junction temperature of +125°C at the highest expected ambient temperature and worst-case load. The internal protection circuitry of the TPS7A3401 has been designed to protect against overload conditions. It was not intended to replace proper heatsinking. Continuously running the TPS7A3401 into thermal shutdown degrades device reliability. POWER DISSIPATION The ability to remove heat from the die is different for each package type, presenting different considerations in the PCB layout. The PCB area around the device that is free of other components moves the heat from the device to the ambient air. Using heavier copper increases the effectiveness in removing heat from the device. The addition of plated through-holes to heat dissipating layers also improves the heatsink effectiveness. Power dissipation depends on input voltage and load conditions. Power dissipation (PD) is equal to the product of the output current times the voltage drop across the output pass element, as shown in Equation 2: PD = (VIN - VOUT) IOUT (2) Thermal protection disables the output when the junction temperature rises to approximately +170°C, allowing the device to cool. When the junction temperature cools to approximately +150°C, the output circuitry is enabled. Depending on power dissipation, thermal resistance, and ambient temperature, the thermal protection circuit may cycle on and off. This cycling limits the dissipation of the regulator, protecting it from damage as a result of overheating. SUGGESTED LAYOUT AND SCHEMATIC Any tendency to activate the thermal protection circuit indicates excessive power dissipation or an inadequate heatsink. For reliable operation, junction temperature should be limited to a maximum of +125°C. To estimate the margin of safety in a The GND pin should be tied directly to the PowerPAD under the IC. The PowerPAD should be connected to any internal PCB ground planes using multiple vias directly under the IC. Copyright © 2011, Texas Instruments Incorporated Layout is a critical part of good power-supply design. There are several signal paths that conduct fast-changing currents or voltages that can interact with stray inductance or parasitic capacitance to generate noise or degrade the power-supply performance. To help eliminate these problems, the IN pin should be bypassed to ground with a low ESR ceramic bypass capacitor with an X5R or X7R dielectric. 11 PACKAGE OPTION ADDENDUM www.ti.com 8-Jul-2011 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/ Ball Finish MSL Peak Temp (3) TPS7A3401DGNR ACTIVE MSOPPowerPAD DGN 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR TPS7A3401DGNT ACTIVE MSOPPowerPAD DGN 8 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR Samples (Requires Login) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. 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Addendum-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 6-Jul-2011 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant TPS7A3401DGNR MSOPPower PAD DGN 8 2500 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1 TPS7A3401DGNT MSOPPower PAD DGN 8 250 180.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 6-Jul-2011 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TPS7A3401DGNR MSOP-PowerPAD DGN 8 2500 346.0 346.0 29.0 TPS7A3401DGNT MSOP-PowerPAD DGN 8 250 190.5 212.7 31.8 Pack Materials-Page 2 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. 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