TLV320AIC1103 SLAS356 – DECEMBER 2001 PCM CODEC D D D D D D D Differential Earphone Output, and One Single-Ended Earphone Output Programmable Gain Amplifiers for Transmit, Receive, Sidetone, and Volume Control Earphone Mute and Microphone Mute On-Chip I2C Bus, Which Provides a Simple, Standard, Two-Wire Serial Interface With Digital ICs Programmable for 15-Bit Linear Data or 8-Bit Companded (µ-Law or A-Law) Data Available in a 32-Pin Thin Quad Flatpack (TQFP) Package and an 80-Pin GQE MicroStar Juniort Ball Grid Array (BGA) Designed for Analog and Digital Wireless Handsets and Telecommunications Applications Dual-Tone Multifrequency (DTMF) and Single Tone Generator Pulse Density Modulated (PDM) Buzzer Output APPLICATIONS D Digital Handset D Digital Headset D Cordless Phones D Digital PABX D Digital Voice Recording The PCM codec is designed to perform transmit encoding analog/digital (A/D) conversion, receive decoding digital/analog (D/A) conversion, and transmit and receive filtering for voice-band communications systems. The device operates in either the 15-bit linear or 8-bit companded (µ-law or A-Law) mode, which is selectable through the I2C interface. The PCM codec generates its own internal clocks from a 2.048-MHz master clock input. PBS PACKAGE (TOP VIEW) 24 23 22 21 20 19 18 17 PLLVDD EARVSS EAR1ON EARVDD EAR1OP EARVSS EAR2O AVDD 25 16 26 15 14 13 PCMO PCMI DVSS DVDD 12 SCL 11 SDA 10 NC 9 NC 27 28 29 30 31 32 1 2 3 4 5 6 7 8 MBIAS MIC1P MIC1N MIC2P MIC2N REXT NC AVSS D DESCRIPTION PLLVSS VSS MCLK RESET PWRUPSEL BUZZCON PCMSYN PCMCLK FEATURES D 2.7-V Operation D Two Differential Microphone Inputs, One NC – No internal connection This device contains circuits to protect its inputs and outputs against damage due to high static voltages or electrostatic fields. These circuits have been qualified to protect this device against electrostatic discharges (ESD) of up to 2 kV according to MIL-STD-883C, Method 3015; however, it is advised that precautions be taken to avoid application of any voltage higher than maximum-rated voltages to these high-impedance circuits. During storage or handling, the device leads should be shorted together or the device should be placed in conductive foam. In a circuit, unused inputs should always be connected to an appropriated logic voltage level, preferably either VCC or ground. Specific guidelines for handling devices of this type are contained in the publication Guidelines for Handling Electrostatic-Discharge-Sensitive (ESDS) Devices and Assemblies available from Texas Instruments. MicroStar Junior is a trademark of Texas Instruments. All other trademarks are the property of their respective owners. Copyright 2001, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. www.ti.com 1 TLV320AIC1103 SLAS356 – DECEMBER 2001 EARVSS PLLVDD PLLVSS 6 7 8 9 B NC NC NC NC NC NC NC VSS C NC NC NC NC NC NC MCLK D NC NC NC NC NC NC NC RESET MIC2P E NC NC NC NC NC NC NC PWRUPSEL MIC2N F NC NC NC NC NC NC NC REXT G NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC H J 2 BUZZCON PCMSYN PCMCLK PCMO SDA AVSS NC www.ti.com PCMI MIC1N A DVSS MIC1P EAR1ON 5 DVDD MBIAS EARVDD 4 SCL AVDD EAR1OP 3 EAR2O 2 1 EARVSS MicroStar Junior (GQE) PACKAGE (TOP VIEW) TLV320AIC1103 SLAS356 – DECEMBER 2001 functional block diagram PCMO (16) EAR1OP (29) EAR1ON (27) EAR2O (31) Ear Amp1 BUZZCON (19) Ear Amp2 PWRUPSEL (20) Digital Modulator and Filter Buzzer Control Power and RESET VSS (23) AV DD (32) AVSS (8) DV DD (13) DVSS (14) PLLV DD (25) PLLV SS (24) EARV DD (28) RX Filter and PGA g = –6 dB to +6 dB EARV SS (30, 26) RESET (21) RX Volume Control g = –18 dB to 0 dB PLL MCLK (22) Sidetone g = –24 dB to –12 dB PCM Interface DTMF Generator TX Filter and PGA g = –10 dB to 0 dB REF REXT (6) MBIAS (1) Analog Modulator Control Bus MIC Amplifier 2 g = 12 dB or 0 dB I 2C I/F SDA (11) SCL (12) MIC Amplifier 1 g = 23.5 dB PCMCLK (17) PCMI (15) PCMSYN (18) MIC1P (2) MIC1N (3) MIC2P (4) MIC2N (5) www.ti.com 3 TLV320AIC1103 SLAS356 – DECEMBER 2001 functional description power on/reset The power for the various digital and analog circuits is separated to improve the noise performance of the device. An external reset must be applied to the active low RESET terminal to assure reset upon power on. After the initial power-on sequence the TLV320AIC1103 can be functionally powered up and down by writing to the power control register through the I2C interface. There is a hardwired selectable power-up terminal in default mode option. The PWRUPSEL function allows the VBAP to power up in the default mode and allows use without a microcontroller. reference A precision band gap reference voltage is generated internally and supplies all required voltage references to operate the transmit and receive channels. The reference system also supplies bias voltage for use with an electret microphone at terminal MBIAS. An external precision resistor is required for reference current setting at terminal REXT. control interface The I2C interface is a two-wire bidirectional serial interface that controls the PCM codec by writing data to the six control registers: D D D D D D Power control Mode control Transmit PGA and sidetone control Receive PGA gain and volume control DTMF high tone DTMF low tone There are two power-up modes which may be selected at the PWRUPSEL terminal: D The PWRUPSEL state (VDD at terminal 20) causes the device to power up in the default mode when power is applied. In the default mode, the I2C interface is not required, and the device may be used without an I2C interface. The programmable functions are fixed in the default modes. D The PWRUPSEL state (ground at terminal 20) causes the device to go to a power-down state when power is applied. In this mode an I2C interface is required to power up the device. phase-locked loop The internal digital filters and modulators require a 10.24-MHz clock that is generated by phase locking to the 2.048-MHz master clock input. PCM interface The PCM interface transmits and receives data at the PCMO and PCMI terminals respectively. The data is transmitted or received at the PCMCLK speed once every PCMSYN cycle. The PCMCLK can be tied directly to the 2.048-MHz master clock (MCLK). The PCMSYN can be driven by an external source or derived from the master clock and used as an interrupt to the host controller. microphone amplifiers The microphone input is a switchable interface for two differential microphone inputs. The first stage is a lownoise differential amplifier that provides a gain of 23.5 dB. The second stage amplifier has a selectable gain of 0 dB or 12 dB. 4 www.ti.com TLV320AIC1103 SLAS356 – DECEMBER 2001 functional description (continued) analog modulator The transmit channel modulator is a third-order sigma-delta design. transmit filter and PGA The transmit filter is a digital filter designed to meet CCITT G.714 requirements. The device operates in either the 15-bit linear or 8-bit companded µ-law or A-law mode that is selectable through the I2C interface. The transmit PGA defaults to 0 dB. sidetone A portion of the transmitted audio is attenuated and fed back to the receive channel through the sidetone path. The sidetone path defaults to –12 dB. The sidetone path can be enabled by writing to the power control register. receive volume control The receive volume control block acts as an attenuator with a range of –18 dB to 0 dB in 2 dB steps for control of the receive channel volume. The receive volume control gain defaults to 0 dB. receive filter and PGA The receive filter is a digital filter that meets CCITT G.714 requirements with a high-pass filter that is selectable through the I2C interface. The device operates in either the 15-bit linear or 8-bit µ-law or A-law companded mode, which is selectable through the I2C interface. The gain defaults to –1 dB representing a 3-dBm0 level for a 32-Ω load impedance and the corresponding digital full scale PCMI code. The gain may be set to –2 dB for the respective 3-dBm0 level for a 16-Ω load impedance. digital modulator and filter The second-order digital modulator and filter convert the received digital PCM data to the analog output required by the earphone interface. earphone amplifiers The analog signal can be routed to either of two earphone amplifiers, one with differential output (EAR1ON and EAR1OP) and one with single-ended output (EAR2O). Clicks and pops are suppressed for EAR1 differential output only. tone generator The tone generator provides generation of standard DTMF tones and single tone frequencies which are output to the following devices: 1) the buzzer driver, as a pulse density modulation (PDM) signal, and 2) the receive path digital/analog converter (DAC) for outputting through the earphone. There are 255 possible single tones. The tone integer value is determined by the following formula: Round (Tone Freq (Hz)/7.8135 Hz) The value is loaded into one of two 8-bit registers, the high-tone register (04), or the low-tone register (05). The tone output is 2 dB higher when applied to the high-tone register (04). When generating DTMF tones, the high DTMF tone must be applied to the high-tone register and the low frequency tone to the low-tone register. www.ti.com 5 TLV320AIC1103 SLAS356 – DECEMBER 2001 Terminal Functions TERMINAL NO. NAME I/O DESCRIPTION µBGA PBS AVDD AVSS A1 32 I Analog positive power supply J1 8 I Analog negative power supply BUZZCON F9 19 O Buzzer output, a pulse-density modulated signal to apply to external buzzer driver DVDD J6 13 I Digital positive power supply DVSS J7 14 I Digital negative power supply EAR1ON A6 27 O Earphone 1 amplifier output (–) EAR1OP A4 29 O Earphone 1 amplifier output (+) EAR2O A2 31 O Earphone 2 amplifier output EARVDD EARVSS A5 28 I Analog positive power supply for the earphone amplifiers A3, A7 30, 26 I Analog negative power supply for the earphone amplifiers MBIAS B1 1 O Microphone bias supply output, no decoupling capacitors MCLK C9 22 I Master system clock input (2.048 MHz) (digital) MIC1P C1 2 I MIC1 input (+) MIC1N D1 3 I MIC1 input (–) MIC2P E1 4 I MIC2 input (+) MIC2N F1 5 I MIC2 input (–) PCMI J8 15 I Receive PCM input PCMO J9 16 O Transmit PCM output PCMSYN G9 18 I PCM frame synchronization PCMCLK H9 17 I PCM data clock PLLVSS PLLVDD A9 24 I PLL negative power supply A8 25 I PLL digital power supply PWRUPSEL E9 20 I Selects the power-up default mode REXT G1 6 I/O Internal reference current setting terminal—use precision 100-kΩ resistor and no filtering capacitors RESET D9 21 I SCL J5 12 I Active low reset I2C-bus serial clock—this input is used to synchronize the data transfer from and to the PCM codec SDA J4 11 I/O VSS B9 23 I 6 I2C-bus serial address/data input/output—this is a bidirectional terminal used to transfer register control addresses and data into and out of the CODEC. It is an open-drain terminal and therefore requires a pullup resistor to VDD (typical 10 kΩ for 100 kHz) Ground return for bandgap internal reference www.ti.com TLV320AIC1103 SLAS356 – DECEMBER 2001 absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range, AVDD, DVDD, PLLVDD, EARVDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.5 V to 4 V Output voltage range, VO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.5 V to 4 V Input voltage range, VF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.5 V to 4 V Continuous total power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Dissipation Rating Table Operating free air temperature range, TA (industrial temperature) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 40°C to 85°C Storage temperature range, testing, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 65°C to 150°C Lead temperature 1,6 mm from case for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. DISSIPATION RATING TABLE PACKAGE TA ≤ 25°C POWER RATING PBS 680 mW DERATING FACTOR ABOVE TA = 25°C 6.8 mW/°C TA = 85°C POWER RATING 270 mW recommended operating conditions (see Notes 1 and 2) MIN Supply voltage, AVDD, DVDD, PLLVDD, EARVDD NOM 2.7 High-level input voltage, VIH MAX UNIT 3.3 V 0.7 x VDD V Low-level input voltage, (VIL Load impedance between EAR1OP and EAR1ON-RL 16 Load impedance for EAR2OP-RL 0.3 x VDD V 32 Ω 85 _C Ω 32 Operating free-air temperature, TA – 40 NOTES: 1. To avoid possible damage and resulting reliability problems to these CMOS devices, the power-on initialization paragraph should be followed, which is described in the Principles of Operations. 2. Voltages are with respect to AVSS, DVSS, PLLVSS, and EARVSS. www.ti.com 7 TLV320AIC1103 SLAS356 – DECEMBER 2001 electrical characteristics, VDD = 2.7 V, TA = 25°C (unless otherwise noted) supply current PARAMETER IDD Supply current from VDD TEST CONDITIONS MIN TYP MAX UNIT Operating, EAR1 selected, MicBias disabled 6 7 mA Operating, EAR2 selected, MicBias disabled 5.4 6 mA Power down, Reg 2 bit 7 = 1, MCLK not present (see Note 3) 0.5 10 µA Power down, Reg 2 bit 7 = 0, MCLK not present (see Note 3) 25 40 µA 5 10 ms ton(i) Power-up time from power down NOTE 3: VIH = VDD, VIL = VSS digital interface PARAMETER VOH VOL High-level output voltage, PCMO and BUZZCON IIH IIL High-level input current, any digital input CI Co RL Load impedance (BuzzCon) TEST CONDITIONS IOH = – 3.2 mA, IOL = 3.2 mA, Low-level output voltage, PCMO and BUZZCON VDD = 3 V VDD = 3 V MIN TYP MAX DVDD UNIT V 0 V 10 µA 10 µA Input capacitance 10 pF Output capacitance 20 pF 5 kΩ VI = VDD VI = VSS Low-level input current, any digital input microphone interface PARAMETER TEST CONDITIONS VIO IIB Input offset voltage at MIC1N, MIC2N Ci Input capacitance at MIC1N, MIC2N Vn Microphone input referred noise, psophometric weighted (C-message weighted is similar) IOmax V(mbias) See Note 4 Input bias current at MIC1N, MIC2N MIN TYP MAX –5 5 mV – 200 200 nA 5 Micamp 1 gain = 23.5 dB Micamp 2 gain = 0 dB Output source current MBIAS 2.4 MICMUTE pF 3 7.7 µVrms 1.2 mA 2.5 2.55 V 60 100 kΩ 1 Microphone bias supply voltage (see Note 5) – 80 Input impedance Fully differential UNIT 35 dB NOTES: 4. Measured while MIC1P and MIC1N are connected together. Less than 5-mV offset results in 0 value code on PCMOUT. 5. Not a JEDEC symbol. speaker interface PARAMETER Earphone AMP1 output power (See Note 6) VOO IOmax TYP MAX UNIT VDD = 2.7 V, fully differential, 16-Ω load, 3-dBm0 output, RGXPA = – 2 dB TEST CONDITIONS 120.9 151.1 mW VDD = 2.7 V, fully differential, 32-Ω load, 3-dBm0 output, RGXPA = –1 dB 76.1 95.1 mW 10 12.5 mW mV Earphone AMP2 output power (See Note 6) VDD = 2.7 V, single ended, 32-Ω load, 3-dBm0 output Output offset voltage at EAR1 Fully differential Maximum output current for EAR1(rms) Maximum output current for EAR2 (rms) ±5 ±30 3-dBm0 input, 16-Ω load 86.9 108.6 3-dBm0 input, 32-Ω load 48.7 60.8 3-dBm0 input 17.7 22.1 EARMUTE – 80 NOTE 6: Maximum power is with a load impedance of approximately 12 Ω. 8 MIN www.ti.com mA dB TLV320AIC1103 SLAS356 – DECEMBER 2001 electrical characteristics, VDD = 2.7 V, TA = 25°C (unless otherwise noted) (continued) transmit gain and dynamic range, companded mode (µ-law or A-law) or linear mode selected, transmit slope filter bypassed (see Notes 7 and 8) PARAMETER Transmit reference-signal level (0 dB) Overload signal level (3 dBm0) Overload-signal Absolute gain error MAX UNIT Differential TEST CONDITIONS 175 mVpp Differential, normal mode TYP 248 Differential, extended mode 0-dBm0 input signal, VDD = 2.7 V (minimum) 63 mVpp dB –1 1 – 0.5 0.5 MIC1N, MIC1P to PCMO at – 31 dBm0 to – 45 dBm0 –1 1 MIC1N, MIC1P to PCMO at – 46 dBm0 to – 55 dBm0 – 1.2 1.2 MIC1N, MIC1P to PCMO at 3 dBm0 to –30 dBm0 Gain G i error with ith iinputt llevell relative l ti tto gain i att – 10 dBm0 MIC1N MIC1N, MIC1P to PCMO MIN dB NOTES: 7. Unless otherwise noted, the analog input is 0 dB, 1020-Hz sine wave, where 0 dB is defined as the zero-reference point of the channel under test. 8. The reference signal level, which is input to the transmit channel, is defined as a value 3 dB below the full-scale value of 88-mVrms. transmit gain and dynamic range, companded mode (µ-law or A-law) or linear mode selected, transmit slope filter enabled (see Notes 7 and 8) PARAMETER Transmit reference-signal level (0dB) Overload signal level (3 dBm0) Overload-signal Absolute gain error TEST CONDITIONS MAX UNIT Differential 175 mVpp Differential, normal mode 248 TYP Differential, extended mode 0-dBm0 input signal, VDD = 2.7 V (minimum) MIC1N, MIC1P to PCMO at 3 dBm0 to –30 dBm0 Gain G i error with ith iinputt llevell relative l ti tto gain i att – 10-dBm0 MIC1N, MIC1N MIC1P to PCMO MIN 63 mVpp dB –1 1 – 0.5 0.5 MIC1N, MIC1P to PCMO at – 31 dBm0 to – 45 dBm0 –1 1 MIC1N, MIC1P to PCMO at – 46 dBm0 to – 55 dBm0 – 1.2 1.2 dB NOTES: 7. Unless otherwise noted, the analog input is 0 dB, 1020-Hz sine wave, where 0 dB is defined as the zero-reference point of the channel under test. 8. The reference signal level, which is input to the transmit channel, is defined as a value 3 dB below the full-scale value of 88-mVrms. transmit filter transfer, companded mode (µ-law or A-law) or linear mode selected, transmit slope filter bypassed, external high pass filter bypassed (MCLK = 2.048 MHz) PARAMETER G i relative l ti tto iinputt signal i l gain i att 1020 H t l hi h Gain Hz, iinternal high-pass filter disabled input high-pass Gain relative to in ut signal gain at 1020 Hz, internal high ass filter enabled TEST CONDITIONS MIN TYP MAX fMIC1 or fMIC2 <100 Hz fMIC1 or fMIC2 = 200 Hz – 0.5 0.5 – 0.5 0.5 fMIC1 or fMIC2 = 300 Hz to 3 kHz fMIC1 or fMIC2 = 3.4 kHz – 0.5 0.5 – 1.5 0 fMIC1 or fMIC2 = 4 kHz fMIC1 or fMIC2 = 4.6 kHz – 14 fMIC1 or fMIC2 = 8 k Hz fMIC1 or fMIC2 <100 Hz – 47 fMIC1 or fMIC2 = 200 Hz –5 www.ti.com UNIT dB – 35 – 15 dB 9 TLV320AIC1103 SLAS356 – DECEMBER 2001 electrical characteristics, VDD = 2.7 V, TA = 25°C (unless otherwise noted) (continued) transmit filter transfer, companded mode (µ-law or A-law) or linear mode selected, transmit slope filter selected (MCLK = 2.048 MHz) (see Note 9) PARAMETER TEST CONDITIONS MIN MAX UNIT –27 dB –8 dB fMIC1 or fMIC2 = 250 Hz fMIC1 or fMIC2 = 300 Hz –4 dB – 1.80 dB fMIC1 or fMIC2 = 400 Hz fMIC1 or fMIC2 = 500 Hz – 1.50 dB – 1.30 dB fMIC1 or fMIC2 = 600 Hz fMIC1 or fMIC2 = 700 Hz – 1.1 dB – 0.8 dB fMIC1 or fMIC2 = 800 Hz fMIC1 or fMIC2 = 900 Hz – 0.57 dB – 0.25 dB fMIC1 or fMIC2 = 1000 Hz fMIC1 or fMIC2 = 1500 Hz Gain relative to input signal gain at 1000 Hz, Hz with slope filter selected TYP fMIC1 or f MIC2 =100 Hz fMIC1 or fMIC2 = 200 Hz 0 dB 1.8 dB fMIC1 or fMIC2 = 2000 Hz fMIC1 or fMIC2 = 2500 Hz 4.0 dB 6.5 dB fMIC1 or fMIC2 = 3000 Hz fMIC1 or fMIC2 = 3100 Hz 7.6 dB 7.7 dB fMIC1 or fMIC2 = 3300 Hz fMIC1 or fMIC2 = 3500 Hz 8.0 dB 6.48 dB fMIC1 or fMIC2 = 4000 Hz fMIC1 or fMIC2 = 4500 Hz – 13 dB – 35 dB fMIC1 or fMIC2 = 5000 Hz fMIC1 or fMIC2 = 8000 Hz – 45 dB – 50 dB NOTE 9: The pass-band tolerance is ± 0.25 dB from 300 Hz to 3500 Hz. transmit idle channel noise and distortion, companded mode (µ-law or A-law) selected, slope filter bypassed PARAMETER Transmit idle channel noise, psophometrically weighted signal-to-distortion 1020-Hz Transmit signal to distortion ratio with 1020 Hz sine-wave input 2-tone Intermodulation distortion, 2 tone CCITT method, composite power level, – 13 dBm0 10 TEST CONDITIONS MIN TXPGA gain= 0 dB, micamp 1 gain = 23.5 dB, micamp 2 gain = 0 dB MIC1N, MIC1P to PCMO at 3 dBm0 27 MIC1N, MIC1P to PCMO at 0 dBm0 30 MIC1N, MIC1P to PCMO at – 5 dBm0 33 MIC1N, MIC1P to PCMO at – 10 dBm0 36 MIC1N, MIC1P to PCMO at – 20 dBm0 35 MIC1N, MIC1P to PCMO at – 30 dBm0 26 MIC1N, MIC1P to PCMO at – 40 dBm0 24 MIC1N, MIC1P to PCMO at – 45 dBm0 19 CCITT G.712 (7.1), R2 49 CCITT G.712 (7.2), R2 51 www.ti.com TYP MAX – 86.6 – 78 UNIT dBm0p dB dB TLV320AIC1103 SLAS356 – DECEMBER 2001 electrical characteristics, VDD = 2.7 V, TA = 25°C (unless otherwise noted) (continued) transmit idle channel noise and distortion, companded mode (µ-law or A-law) selected, slope filter enabled PARAMETER Transmit idle channel noise, psophometrically weighted signal-to-total 1020-Hz Transmit signal to total distortion ratio with 1020 Hz sine-wave input 2-tone Intermodulation distortion, 2 tone CCITT method, composite power level, – 13 dBm0 TEST CONDITIONS MIN TXPGA gain= 0 dB, micamp 1 gain = 23.5 dB, micamp 2 gain = 0.0 dB MIC1N, MIC1P to PCMO at 3 dBm0 27 MIC1N, MIC1P to PCMO at 0 dBm0 30 MIC1N, MIC1P to PCMO at – 5 dBm0 33 MIC1N, MIC1P to PCMO at – 10 dBm0 36 MIC1N, MIC1P to PCMO at – 20 dBm0 35 MIC1N, MIC1P to PCMO at – 30 dBm0 26 MIC1N, MIC1P to PCMO at – 40 dBm0 24 MIC1N, MIC1P to PCMO at – 45 dBm0 19 CCITT G.712 (7.1), R2 49 CCITT G.712 (7.2), R2 51 TYP MAX – 86.6 – 78 UNIT dBm0p dB dB transmit idle channel noise and distortion, linear mode selected, slope filter bypassed PARAMETER Transmit idle channel noise Transmit signal signal-to-total to total distortion ratio with 1020 1020-Hz Hz sine-wave input TEST CONDITIONS MIN TXPGA gain = 0 dB, micamp 1 gain = 23.5 dB, micamp 2 gain = 0 dB TYP MAX – 86.6 – 78 MIC1N, MIC1P to PCMO at 3 dBm0 40 50 MIC1N, MIC1P to PCMO at 0 dBm0 50 65 MIC1N, MIC1P to PCMO at – 5 dBm0 60 68 MIC1N, MIC1P to PCMO at – 10 dBm0 55 70 MIC1N, MIC1P to PCMO at – 20 dBm0 58 65 MIC1N, MIC1P to PCMO at – 30 dBm0 50 60 MIC1N, MIC1P to PCMO at – 40 dBm0 38 50 MIC1N, MIC1P to PCMO at – 45 dBm0 30 45 UNIT dBm0p dB transmit idle channel noise and distortion, linear mode selected, slope filter enabled PARAMETER Transmit idle channel noise Transmit signal signal-to-total to total distortion ratio with 1020 1020-Hz Hz sine-wave input TEST CONDITIONS MIN TXPGA gain = 0 dB, micamp 1 gain = 23.5 dB, micamp 2 gain = 0 dB TYP MAX – 86.6 – 78 MIC1N, MIC1P to PCMO at 3 dBm0 40 50 MIC1N, MIC1P to PCMO at 0 dBm0 50 65 MIC1N, MIC1P to PCMO at – 5 dBm0 60 68 MIC1N, MIC1P to PCMO at – 10 dBm0 55 70 MIC1N, MIC1P to PCMO at – 20 dBm0 58 65 MIC1N, MIC1P to PCMO at – 30 dBm0 50 60 MIC1N, MIC1P to PCMO at – 40 dBm0 38 50 MIC1N, MIC1P to PCMO at – 45 dBm0 30 45 www.ti.com UNIT dBm0p dB 11 TLV320AIC1103 SLAS356 – DECEMBER 2001 electrical characteristics, VDD = 2.7 V, TA = 25°C (unless otherwise noted) (continued) receive gain and dynamic range, EAR1 selected, linear or companded (µ-law or A-law) mode selected (see Note 10) PARAMETER Overload signal level (3.0 (3 0 dB) Overload-signal Absolute gain error TEST CONDITIONS TYP 3.93 32-Ω load RXPGA = – 1 dB (default gain) 4.41 0-dBm0 input signal, VDD = 2.7 V (minimum) PCMIN to EAR1ON, EAR1OP at 3 dBm0 to – 40 dBm0 Gain G i error with ith output t t llevell relative l ti tto gain i at –10 dBm0 MIN 16-Ω load RXPGA = – 2 dB MAX UNIT Vpp –1 1 – 0.5 0.5 PCMIN to EAR1ON, EAR1OP at – 41 dBm0 to – 50 dBm0 –1 1 PCMIN to EAR1ON, EAR1OP at – 51 dBm0 to – 55 dBm0 – 1.2 1.2 dB dB NOTE 10: RXPGA = -1 dB for 32 Ω default mode or RXPGA = -2 dB for 16 Ω, RXVOL = 0 dB, 1020 Hz input signal at PCMI, output measured differentially between EAR1ON and EAR1OP receive gain and dynamic range, EAR2 selected, linear or companded (µ-law or A-law) mode selected (see Note 11) PARAMETER Receive reference-signal level (0 dB) TEST CONDITIONS MIN 0-dBm0 PCM input signal PCMIN to EAR2O at 3 dBm0 to – 40 dBm0 UNIT Vpp Vpp 1.6 0-dBm0 input signal, VDD = 2.7 V (minimum) Gain G i error with ith output t t llevell relative l ti tto gain i att –10 dBm0 MAX 1.1 Overload-signal level (3 dB) Absolute gain error TYP –1 1 – 0.5 0.5 PCMIN to EAR2O at – 41 dBm0 to – 50 dBm0 –1 1 PCMIN to EAR2O at – 51 dBm0 to – 55 dBm0 – 1.2 1.2 dB dB NOTE 11: RXPGA = -1 dB, RXVOL = 0 dB receive filter transfer, companded mode (µ-law or A-law) or linear mode selected (MCLK = 2.048 MHz) (see Note 11) PARAMETER G i relative l ti tto iinputt signal i l gain i att 1020 H t l Gain Hz, iinternal high-pass filter disabled input Gain relative to in ut signal gain at 1020 Hz, internal high-pass filter enabled TEST CONDITIONS TYP MAX – 0.5 0.5 – 0.5 0.5 fEAR1 or fEAR2 = 300 Hz to 3 kHz fEAR1 or fEAR2 = 3.4 kHz – 0.5 0.5 –1.5 0 fEAR1 or fEAR2 = 4 kHz fEAR1 or fEAR2 = 4.6 kHz – 14 fEAR1 or fEAR2 = 8 kHz fEAR1 or fEAR2 < 100 Hz – 47 fEAR1 or fEAR2 = 200 Hz –5 NOTE 11: RXPGA = -1 dB, RXVOL = 0 dB 12 MIN fEAR1 or fEAR2 < 100 Hz fEAR1 or fEAR2 = 200 Hz www.ti.com UNIT dB – 35 –15 dB TLV320AIC1103 SLAS356 – DECEMBER 2001 electrical characteristics, VDD = 2.7 V, TA = 25°C (unless otherwise noted) (continued) receive idle channel noise and distortion, EAR1 selected, companded mode (µ-law or A-law) selected (see Note 12) PARAMETER TEST CONDITIONS Receive noise, psophometrically weighted PCMIN = 11010101 (Α–law) Receive noise, C-message weighted PCMIN = 11111111 (µ–law) Receive signal signal-to-distortion to distortion ratio with 1020 1020-Hz Hz sine-wave input MIN PCMIN to EAR1ON, EAR1OP at 3 dBm0 21 PCMIN to EAR1ON, EAR1OP at 0 dBm0 25 PCMIN to EAR1ON, EAR1OP at – 5 dBm0 36 PCMIN to EAR1ON, EAR1OP at –10 dBm0 43 PCMIN to EAR1ON, EAR1OP at – 20 dBm0 40 PCMIN to EAR1ON, EAR1OP at – 30 dBm0 38 PCMIN to EAR1ON, EAR1OP at – 40 dBm0 28 PCMIN to EAR1ON, EAR1OP at – 45 dBm0 23 TYP MAX – 89 – 86 36 50 UNIT dBm0p µVrms dB NOTE 12: RXPGA = -1 dB for 32-Ω default mode or RXPGA = -2 dB for 16 Ω, RXVOL = 0 dB, 1020 Hz input signal at PCMI, output measured differentially between EAR1ON and EAR1OP. receive idle channel noise and distortion, EAR1 selected, linear mode selected (see Note 12) PARAMETER Receive noise, (20-Hz to 20-kHz brickwall window) Receive signal signal-to-distortion to distortion ratio with 1020 1020-Hz Hz sine-wave input Intermodulation distortion, 2 2-tone tone CCITT method, composite power level, – 13 dBm0 TEST CONDITIONS MIN PCMIN = 0000000000000 TYP MAX UNIT – 86 – 83 dBm0 PCMIN to EAR1ON, EAR1OP at 3 dBm0 65 78 PCMIN to EAR1ON, EAR1OP at 0 dBm0 73 80 PCMIN to EAR1ON, EAR1OP at – 5 dBm0 72 78 PCMIN to EAR1ON, EAR1OP at –10 dBm0 70 78 PCMIN to EAR1ON, EAR1OP at – 20 dBm0 60 76 PCMIN to EAR1ON, EAR1OP at – 30 dBm0 50 67 PCMIN to EAR1ON, EAR1OP at – 40 dBm0 40 60 PCMIN to EAR1ON, EAR1OP at – 45 dBm0 35 55 CCITT G.712 (7.1), R2 50 CCITT G.712 (7.2), R2 54 dB dB NOTE 12: RXPGA = -1 dB for 32-Ω default mode or RXPGA = -2 dB for 16 Ω, RXVOL = 0 dB, 1020 Hz input signal at PCMI, output measured differentially between EAR1ON and EAR1OP. receive idle channel noise and distortion, EAR2 selected, companded mode (µ-law or A-law) selected (see Note 111) PARAMETER TEST CONDITIONS MIN TYP MAX Receive noise, psophometrically weighted PCMIN = 11010101 (Α-law) – 81 – 78 Receive noise, C-message weighted PCMIN = 11111111 (µ-law) 36 50 Receive signal-to-distortion ratio with 1020-Hz sine-wave input PCMIN to EAR2O at 3 dBm0 21 PCMIN to EAR2O at 0 dBm0 25 PCMIN to EAR2O at – 5 dBm0 36 PCMIN to EAR2O at –10 dBm0 43 PCMIN to EAR2O at – 20 dBm0 40 PCMIN to EAR2O at – 30 dBm0 38 PCMIN to EAR2O at – 40 dBm0 28 PCMIN to EAR2O at – 45 dBm0 23 UNIT dBm0p µVrms dB NOTE 11: RXPGA = -1 dB, RXVOL = 0 dB www.ti.com 13 TLV320AIC1103 SLAS356 – DECEMBER 2001 electrical characteristics, VDD = 2.7 V, TA = 25°C (unless otherwise noted) (continued) receive idle channel noise and distortion, EAR2 selected, linear mode selected (see Note 11) PARAMETER TEST CONDITIONS Receive noise, (20-Hz to 20-kHz brickwall window) MIN PCMIN = 0000000000000 Receive signal signal-to-distortion to distortion ratio with 1020 1020-Hz Hz sine sine-wave wave in input ut Intermodulation distortion, 2 2-tone tone CCITT method, com composite osite power level, – 13 dBm0 TYP MAX UNIT – 86 – 83 dBm0 PCMIN to EAR2O at 3 dBm0 45 60 PCMIN to EAR2O at 0 dBm0 60 65 PCMIN to EAR2O at – 5 dBm0 58 62 PCMIN to EAR2O at – 10 dBm0 55 60 PCMIN to EAR2O at – 20 dBm0 53 60 PCMIN to EAR2O at – 30 dBm0 52 58 PCMIN to EAR2O at – 40 dBm0 50 57 PCMIN to EAR2O at – 45 dBm0 45 52 CCITT G.712 (7.1), R2 50 CCITT G.712 (7.2), R2 54 dB dB NOTE 11: RXPGA = -1 dB, RXVOL = 0 dB power supply rejection and crosstalk attenuation PARAMETER TYP MAX Supply voltage rejection, transmit channel MIC1N, MIC1P =0 V, VDD = 2.7 V + 100 mVpeak to peak, f = 0 to 50 kHz TEST CONDITIONS MIN UNIT – 80 – 45 dB Supply voltage rejection, receive channel, EAR1 selected (differential) PCM code = positive zero, VDD = 2.7 V + 100 mVpeak to peak, f = 0 to 50 kHz – 90 – 45 dB Crosstalk attenuation, transmit-to-receive (differential) MIC1N, MIC1P = 0 dB, f = 300 to 3400 Hz measured differentially between EAR1ON and EAR1OP 70 dB Crosstalk attenuation, receive-to-transmit PCMIN = 0 dBm0, f = 300 to 3400 Hz measured at PCMO, EAR1 amplifier 70 dB DTMF generator PARAMETER TEST CONDITIONS DTMF high to low tone relative amplitude (pre-emphasis) Tone frequency accuracy Harmonic distortion MIN TYP MAX 1.5 2 2.5 – 1.5% UNIT dB 1.5% Measured from lower tone group to highest parasitic – 20 dB MICBIAS PARAMETER TEST CONDITIONS Load impedance 14 MIN 2 www.ti.com TYP MAX 2.5 UNIT kΩ TLV320AIC1103 SLAS356 – DECEMBER 2001 timing requirements clock MIN tt NOM Transition time, MCLK 10 MCLK frequency 2.048 2.048 MCLK jitter tc(PCMCLK) MAX UNIT ns MHz 37% Number of PCMCLK clock cycles per PCMSYN frame 256 PCMCLK clock period 156 488 256 512 Duty cycle, PCMCLK 45% 50% 68% ns transmit (see Figure 6) MIN tsu(PCMSYN) th(PCMSYN) Setup time, PCMSYN high before PCMCLK↓ 20 Hold time, PCMSYN high after PCMCLK↓ 20 MAX UNIT tc(PCMCLK)– 20 tc(PCMCLK)– 20 ns receive (see Figure 5) MIN MAX UNIT tsu(PCSYN) th(PCSYN) Setup time, PCMSYN high before PCMCLK↓ 20 ns Hold time, PCMSYN high after PCMCLK↓ 20 tc(PCMCLK)– 20 tc(PCMCLK)– 20 tsu(PCMI) th(PCMI) Setup time, PCMI high or low before PCMCLK↓ 20 ns Hold time, PCMI high or low after PCMCLK↓ 20 ns ns I2C bus (see Figure 6) MIN MAX UNIT 400 kHz SCL Clock frequency tHIGH tLOW Clock high time 600 ns Clock low time 1300 ns tr tf SDA and SCL rise time 300 ns SDA and SCL fall time 300 ns th(STA) tsu(STA) Hold time (repeated) START condition. After this period the first clock pulse is generated. 600 ns Setup time for repeated START condition 600 ns th(DAT) tsu(DAT) Data input hold time 0 ns Data input setup time 100 ns tsu(STO) tBUF STOP condition setup time 600 ns 1300 ns Bus free time switching characteristics propagation delay times, CL(max) = 10 pF (see Figure 5) MIN MAX UNIT tpd1 tpd2 From PCMCLK bit 1 high to PCMO bit 1 valid 35 ns From PCMCLK high to PCMO valid, bits 2 to n 35 ns tpd3 From PCMCLK bit n low to PCMO bit n Hi-Z 30 www.ti.com ns 15 TLV320AIC1103 SLAS356 – DECEMBER 2001 PARAMETER MEASUREMENT INFORMATION SCL SDA A6 A5 A4 A0 R/W 0 ACK R7 R5 R0 ACK 0 D7 D6 D5 D0 ACK 0 Slave Address Start R6 0 Register Address Stop Data NOTE: SLAVE = Voice Codec Figure 1. I2C Bus Write to Voice Codec SCL SDA A6 A5 A0 R/W ACK 0 Start R7 R6 R0 ACK A6 A0 0 R/W ACK 1 Slave Address Register Address D7 D6 D0 0 Slave Address Slave Drives The Data Repeated Start NOTE: SLAVE = Voice Codec ACK Stop Master Drives ACK and Stop Figure 2. I2C Read From Voice Codec: Protocol A SCL SDA Start A6 A5 A0 R/W ACK 0 Slave Address R7 R6 R0 ACK 0 A6 A5 A0 R/W ACK D7 Stop Start Register Address Slave Address NOTE: SLAVE = Voice Codec Figure 3. I2C Read From Voice Codec: Protocol B 16 www.ti.com D0 ACK Slave Drives The Data Stop Master Drives ACK and Stop TLV320AIC1103 SLAS356 – DECEMBER 2001 PARAMETER MEASUREMENT INFORMATION register map addressing REG 07 06 05 04 03 02 01 00 Power control 00 Sidetone En TXEn RXEn MICSEL BIASEn RXEn EAROUT Sel PWRUP Mode control 01 Comp Sel TMEn PCMLB Comp En BUZZEn RXFLTR En TXFLTR En TXSLOPE En TXPGA 02 PD0 TP3 TP2 TP1 TP0 ST2 ST1 ST0 RXPGA 03 RP3 RP2 RP1 RP0 RV3 RV2 RV1 RV0 High DTMF 04 HIFREQ Sel7 HIFREQ Sel6 HIFREQ Sel5 HIFREQ Sel4 HIFREQ Sel3 HIFREQ Sel2 HIFREQ Sel1 HIFREQ Sel0 Low DTMF 05 LOFREQ Sel7 LOFREQ Sel6 LOFREQ Sel5 LOFREQ Sel4 LOFREQ Sel3 LOFREQ Sel2 LOFREQ Sel1 LOFREQ Sel0 register power-up defaults REG 07 06 05 04 03 02 01 00 Power control† Power control‡ 00 1 1 1 1 0 1 1 0 00 1 0 0 1 1 0 1 1 Mode control 01 0 0 0 0 0 0 1 0 TXPGA 02 0 1 0 0 0 0 0 0 RXPGA 03 0 1 1 1 0 0 0 0 High DTMF 04 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Low DTMF 05 † Value when PWRUPSEL = 0 ‡ Value when PWRUPSEL = 1 www.ti.com 17 TLV320AIC1103 SLAS356 – DECEMBER 2001 PARAMETER MEASUREMENT INFORMATION register map Table 1. Power Control Register: Address {00} HEX BIT NUMBER 5 4 3 2 1 DEFINITIONS 7 6 0 1 1 1 1 0 1 1 0 Default setting PWRUPSEL = 0 1 0 0 1 1 0 1 1 Default setting PWRUPSEL = 1 X X X X X X X 0 Reference system, power down X X X X X X X 1 Reference system, power up X X X X X X 1 X EAR AMP1 selected, EAR AMP2 power down X X X X X X 0 X EAR AMP2 selected, EAR AMP1 power down X X X X X 0 X X Receive channel enabled X X 0 X X 1 X X Receive channel muted X X 1 X X 1 X 0 Receive channel, power down X X X X 1 X X X MICBIAS selected X X X X 0 X X X MICBIAS power down X X X 1 X X X X MIC1 selected X X X 0 X X X X MIC2 selected X 0 X X X X X X Transmit channel enabled X 1 0 X X X X X Transmit channel muted X 1 1 X X X X X Transmit channel power down 0 X X X X X X X Sidetone enabled 1 X X X X X X X Sidetone muted Table 2. Mode Control Register: Address {01} HEX BIT NUMBER 18 DEFINITIONS 7 6 5 4 3 2 1 0 0 0 0 0 0 0 1 0 Default setting X X X X X X 0 0 TX channel high-pass filter enabled and slope filter enabled X X X X X X 0 1 TX channel high-pass filter enabled and slope filter disabled X X X X X X 1 0 TX channel high-pass filter disabled and slope filter enabled X X X X X X 1 1 TX channel high-pass filter disabled and slope filter disabled X X X X X 0 X X RX channel high-pass filter disabled (low pass only) X X X X X 1 X X RX channel high-pass filter enabled X X X X 0 X X X BUZZCON disabled X X X X 1 X X X BUZZCON enabled X X X 0 X X X X Linear mode selected 1 X X 1 X X X X A-law companding mode selected 0 X X 1 X X X X µ-law companding mode selected X X 0 X X X X X TX and RX channels normal mode X X 1 X X X X X PCM loopback mode X 0 X X X X X X Tone mode disabled X 1 X X X X X X Tone mode enabled www.ti.com TLV320AIC1103 SLAS356 – DECEMBER 2001 PARAMETER MEASUREMENT INFORMATION Transmit PGA and sidetone control register: Address {02}HEX Bit definitions: 7 6 5 4 3 2 1 0 DEFINITION PDO TP3 TP2 TP1 TP0 ST2 ST1 ST0 See Table 2 and Table 4 0 1 0 0 0 0 0 0 Default setting Receive volume control register: Address {03}HEX Bit definitions : 7 6 5 4 3 2 1 0 DEFINITION RP3 RP2 RP1 RP0 RV3 RV2 RV1 RV0 See Table 3 and Table 5 0 1 1 1 0 0 0 0 Default setting High tone selection control register: Address {04}HEX Bit definitions: 7 6 5 4 3 2 1 0 DEFINITION X X X X X X X X DTMF (see Table 7) 0 0 0 0 0 0 0 0 Default setting Low tone selection control register: Address {05}HEX Bit definitions: 7 6 5 4 3 2 1 0 DEFINITION X X X X X X X X DTMF (see Table 7) 0 0 0 0 0 0 0 0 Default setting Transmit Time Slot 0 1 2 3 4 N–2 N–1 N N+1 80% PCMCLK 80% 20% 20% ÎÎÎÎÎÎ ÎÎÎÎÎÎ ÎÎÎÎÎÎ ÎÎÎÎÎÎ ÎÎÎÎÎÎ ÎÎÎÎÎÎ tsu(PCMSYN) th(PCMSYN) PCMSYN tpd2 See Note A PCMO 1 2 tpd3 4 N–2 N–1 N See Note C tpd1 NOTES: A. B. C. D. 3 See Note B See Note D tsu(PCMO) This window is allowed for PCMSYN high. This window is allowed for PCMSYN low (th(PCMSYN) max determined by data collision considerations). Transitions are measured at 50%. Bit 1 = MSB, Bit N = LSB Figure 4. Transmit Timing Diagram www.ti.com 19 TLV320AIC1103 SLAS356 – DECEMBER 2001 PARAMETER MEASUREMENT INFORMATION Receive Time Slot 0 1 2 3 4 N –2 N –1 N N +1 80% 80% PCMCLK 20% 20% ÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎ tsu(PCMSYN) PCMSYN th(PCMSYN) See Note A PCMI 1 See Note C See Note B See Note D th(PCMI) 2 3 4 N –2 N –1 N tsu(PCMI) A. B. C. D. This window is allowed for PCMSYN high. This window is allowed for PCMSYN low. Transitions are measured at 50%. Bit 1 = MSB, Bit N = LSB Figure 5. Receive Timing Diagram SDA tBUF tLOW tr th(STA) tf SCL STO STA th(STA) th(DAT) tHIGH tsu(STA) tsu(DAT) tsu(STO) STA Figure 6. I2C Bus Timing Diagram 20 www.ti.com STO TLV320AIC1103 SLAS356 – DECEMBER 2001 PRINCIPLES OF OPERATION power-on initialization An external reset with a minimum pulse width of 500 ns must be applied to the active low RESET terminal to assure reset upon power on. All registers are set with default values upon external reset initialization. The desired selection for all programmable functions can be initialized prior to a power-up command using the I2C interface. Table 3. Power-Up and Power-Down Procedures (VDD = 2.7 V, Earphone Amplifier Unloaded) DEVICE STATUS Power up Power down PROCEDURE MAXIMUM POWER CONSUMPTION Set bit 1 = 1 in power control register, EAR1 enabled 16.2 mW Set bit 1 = 0 in power control register, EAR2 enabled 14.6 mW Set bit 7 = 1 in TXPGA control register and bit 0 = 0 1.35 µW Set bit 7 = 0 in TXPGA control register and bit 0 = 0 67.5 µW In addition to resetting the power-down bit in the power control register, loss of MCLK (no transition detected) automatically enters the device into a power-down state with PCMO in the high impedance state. If during a pulse code modulation (PCM) data transmit cycle an asynchronous power down occurs, the PCM interface remains powered up until the PCM data is completely transferred. An additional power-down mode overrides the MCLK detection function. This allows the device to enter the power-down state without regard to MCLK. Setting bit 7 of the TX filter and PGA sidetone register to logic high enables this function. conversion laws The device can be programmed either for a 15-bit linear or 8-bit (µ-law or A-law) companding mode. The companding operation approximates the CCITT G.711 recommendation. The linear mode operation uses a 15-bit twos-complement format. transmit operation microphone input The microphone input stage is a low-noise differential amplifier that provides a preamplifier gain of 23.5 dB. A microphone can be capacitively connected to the MIC1N and MIC1P inputs, while the MIC2N and MIC2P inputs can be used to capacitively connect a second microphone or an auxiliary audio circuit. www.ti.com 21 TLV320AIC1103 SLAS356 – DECEMBER 2001 PRINCIPLES OF OPERATION transmit operation (continued) _ MBIAS + Rmic Vref 510 kΩ Ci MIC1N 34 kΩ _ M I C + 34 kΩ Ci MIC1P Rmic 510 kΩ Figure 7. Typical Microphone Interface microphone mute function Transmit channel muting provides 80-dB attenuation of input microphone signal. The MICMUTE function can be selected by setting bit 6 of the power control register through the I2C interface. transmit channel gain control The values in the transmit PGA control registers control the gain in the transmit path. The total TX channel gain can vary from 35.5 dB to 13.5 dB. The default total TX channel gain is 23.5 dB Table 4. Transmit Gain Control BIT NAME 22 MIC AMP1 MIC AMP2 TX PGA GAIN GAIN MODE TOTAL TX GAIN TP3 TP2 TP1 TP0 GAIN GAIN MIN TYP MAX UNIT 0 0 0 0 23.5 12 0 Extended 35.3 35.5 35.7 dB 0 0 0 1 23.5 12 –2 Extended 33.3 33.5 33.7 dB 0 0 1 0 23.5 12 –4 Extended 31.3 31.5 31.7 dB 0 0 1 1 23.5 12 –6 Extended 29.3 29.5 29.7 dB 0 1 0 0 23.5 12 –8 Extended 27.3 27.5 27.7 dB 0 1 0 1 23.5 12 –10 Extended 25.3 25.5 25.7 dB 1 0 0 0 23.5 0 0 Normal 23.3 23.5 23.7 dB 1 0 0 1 23.5 0 –2 Normal 21.3 21.5 21.7 dB 1 0 1 0 23.5 0 –4 Normal 19.3 19.5 19.7 dB 1 0 1 1 23.5 0 –6 Normal 17.3 17.5 17.7 dB 1 1 0 0 23.5 0 –8 Normal 15.3 17.5 17.7 dB 1 1 0 1 23.5 0 –10 Normal 13.3 13.5 13.7 dB www.ti.com TLV320AIC1103 SLAS356 – DECEMBER 2001 PRINCIPLES OF OPERATION receive operation receive channel gain control The values in the receive PGA control registers control the gain in the receive path. PGA gain is set from – 6 dB to 6 dB in 1-dB steps through the I2C interface. The default receive channel gain is –1 dB. Table 5. Receive PGA Gain Control BIT NAME RELATIVE GAIN RP3 RP2 RP1 RP0 MIN TYP MAX UNIT 0 0 0 0 5.8 6 6.2 dB 0 0 0 1 4.8 5 5.2 dB 0 0 1 0 3.8 4 4.2 dB 0 0 1 1 2.8 3 3.2 dB 0 1 0 0 1.8 2 2.2 dB 0 1 0 1 0.8 1 1.2 dB 0 1 1 0 – 0.2 0 0.2 dB 0 1 1 1 –1.2 –1 – 0.8 dB 1 0 0 0 – 2.2 –2 –1.8 dB 1 0 0 1 – 3.2 –3 – 2.8 dB 1 0 1 0 – 4.2 –4 – 3.8 dB 1 0 1 1 – 5.2 –5 – 4.8 dB 1 1 0 0 – 6.2 –6 – 5.8 dB sidetone gain control The values in the sidetone PGA control registers control the sidetone gain. Sidetone gain is set from –12 dB to – 24 dB in 2-dB steps through the I2C interface. Sidetone can be muted by setting bit 7 of the power control register. The default sidetone gain is –12 dB. Table 6. Sidetone Gain Control BIT NAME RELATIVE GAIN ST2 ST1 ST0 MIN TYP MAX UNIT 0 0 0 –12.2 0 0 1 –14.2 –12 –11.8 dB –14 –13.8 0 1 0 –16.2 dB –16 –15.8 dB 0 1 1 1 0 0 –18.2 –18 –17.8 dB – 20.2 – 20 –19.8 1 0 1 dB – 22.2 – 22 – 21.8 dB 1 1 0 – 24.2 – 24 – 23.8 dB www.ti.com 23 TLV320AIC1103 SLAS356 – DECEMBER 2001 PRINCIPLES OF OPERATION receive operation (continued) receive volume control The values in the volume control PGA control registers provide volume control into the earphone. Volume control gain is set from 0 dB to –18 dB in 2-dB steps through the I2C interface. The default RX volume control gain is 0 dB. Table 7. RX Volume Control BIT NAME RELATIVE GAIN RV3 RV2 RV1 RV0 MIN TYP MAX 0 0 0 0 – 0.2 0 0.2 UNIT dB 0 0 0 1 – 2.2 –2 –1.8 dB 0 0 1 0 – 4.2 –4 – 3.8 dB 0 0 1 1 – 6.2 –6 – 5.8 dB 0 1 0 0 – 8.2 –8 –7.8 dB 0 1 0 1 –10.2 –10 – 9.8 dB 0 1 1 0 –12.2 –12 –11.8 dB 0 1 1 1 –14.2 –14 –13.8 dB 1 0 0 0 –16.2 –16 –15.8 dB 1 0 0 1 –18.2 –18 –17.8 dB earphone amplifier The analog signal can be routed to one of two earphone amplifiers: one with differential output (EAR1ON and EAR1OP) capable of driving a 16-Ω load or one with single-ended output (EAR2O) capable of driving a 32-Ω load. earphone mute function Muting can be selected by setting bit 3 of the power control register through the I2C interface. receive PCM data format D Companded mode: eight bits are received, the most significant (MSB) first. D Linear mode: 15 bits are received, MSB first. 24 www.ti.com TLV320AIC1103 SLAS356 – DECEMBER 2001 PRINCIPLES OF OPERATION receive operation (continued) Table 8. Receive-Data Bit Definitions BIT NO. COMPANDED MODE LINEAR MODE 1 CD7 LD14 2 CD6 LD13 3 CD5 LD12 4 CD4 LD11 5 CD3 LD10 6 CD2 LD9 7 CD1 LD8 8 CD0 LD7 9 – LD6 10 – LD5 11 – LD4 12 – LD3 13 – LD2 14 – LD1 15 – LD0 16 – –– Transmit channel gain control bits always follow the PCM data in time: CD7– CD0 = data word in companded mode LD14– LD0 = data word in linear mode DTMF generator operation and interface The dual-tone multifrequency generator (DTMF) circuit generates the summed DTMF tones for push button dialing and provides the PDM output for the BUZZCON user-alert tone. There are 255 possible single tones. The tone integer value is determined by the formula: Round (tone frequency (Hz)/7.8125 Hz) The integer value is loaded into either one of two 8-bit registers, high-tone register (04), or low-tone register (05). The tone output is 2 dB higher when applied to the high-tone register (04). When generating DTMF tones, the high frequency value must be applied to the high-tone register (04) and the low DTMF value to the low-tone register. www.ti.com 25 TLV320AIC1103 SLAS356 – DECEMBER 2001 PRINCIPLES OF OPERATION DTMF generator operation and interface (continued) Table 9. Typical DTMF and Single Tone Control 26 INTEGER VALUE TONE FUNCTION 0 0 OFF 0 1 45 F 349 1 1 47 F# 370 0 1 0 50 G 392 1 0 1 53 G# 415 1 0 0 0 56 A 440 1 1 1 0 0 60 A# 466 1 1 1 1 1 1 63 B 494 1 0 0 0 0 1 1 67 C 523 1 0 0 0 1 1 1 71 C# 554 0 1 0 0 1 0 1 1 75 D 587 0 1 0 1 0 0 0 0 80 D# 622 0 1 0 1 0 1 0 0 84 E 659 0 1 0 1 1 0 0 1 89 F 698 0 1 0 1 1 1 1 1 95 F# 740 0 1 1 0 0 1 0 0 100 G 784 0 1 1 0 1 0 1 0 106 G# 831 0 1 1 1 0 0 0 1 113 A 880 0 1 1 1 0 1 1 1 119 A# 932 0 1 1 1 1 1 1 0 126 B 988 1 0 0 0 0 1 1 0 134 C 1047 1 0 0 0 1 1 1 0 142 C# 1109 1 0 0 1 0 1 1 0 150 D 1175 1 0 0 1 1 1 1 1 159 D# 1245 1 0 1 0 1 0 0 1 169 E 1319 1 0 1 1 0 0 1 1 179 F 1397 1 0 1 1 1 1 0 1 189 F# 1480 1 1 0 0 1 0 0 1 201 G 1568 1 1 0 1 0 1 0 1 213 G# 1661 1 1 1 0 0 0 0 1 225 A 1760 1 1 1 0 1 1 1 1 239 A# 1865 1 1 1 1 1 1 0 1 253 B 1976 0 1 0 1 1 0 0 1 89 DTMF Low 697 0 1 1 0 0 0 1 1 99 DTMF Low 770 0 1 1 0 1 1 0 1 109 DTMF Low 852 0 1 1 1 1 0 0 0 120 DTMF Low 941 1 0 0 1 1 0 1 1 155 DTMF HIgh 1209 1 0 1 0 1 0 1 1 171 DTMF HIgh 1336 1 0 1 1 1 1 0 1 189 DTMF HIgh 1477 1 1 0 1 0 0 0 1 209 DTMF HIgh 1633 DT7 DT6 DT5 DT4 DT3 DT2 DT1 DT0 0 0 0 0 0 0 0 0 0 1 0 1 1 0 0 0 1 0 1 1 0 0 1 1 0 0 0 1 1 0 0 0 1 1 0 0 1 0 0 0 0 www.ti.com TONE/HZ TLV320AIC1103 SLAS356 – DECEMBER 2001 PRINCIPLES OF OPERATION DTMF generator operation and interface (continued) Tones from the DTMF generator block are present at all outputs and are controlled by enabling or disabling the individual output ports. The values that determine the tone frequency are loaded into the tone registers (high and low) as two separate values. The values loaded into the tone registers initiate an iterative table look-up function, placing a 6 bit or 7 bit in twos complement value into the the tone registers. There is a 2 dB difference in the resulting output of the two registers, the high-tone register having the greater result. The resulting range of a tone set into the low register value is +31 {1F}HEX to –32 {20}HEX for a range of six bits and is in twos complement format. The resulting range of a tone set into the high register value is +39 {27}HEX to –40 {D8}HEX in twos-complement format, as well. The maximum range is six bits having a maximum value of {31}HEX. The value {31} is represented as 011111. Two zeros are added to the leading side of the value and then the value is padded with seven LSB zeros to create a value of 000 1111 1000 0000. Because the maximum full scale value is 000 1111 1000 0000, the resulting output magnitude is 20 log (input value/maximum value) or 20 log (3968/16783) or –12.31 dB below full scale. This is the result when all gains are set at default. buzzer logic section The single-ended output BUZZCON is a PDM signal intended to drive a buzzer through an external driver transistor. The PDM begins as a selected tone, is generated and passed through the receive D/A channel, and is fed back to the transmit channel analog modulator, where a PDM signal is generated and routed to the BUZZCON output. support section The clock generator and control circuit uses the master clock input (MCLK) to generate internal clocks to drive internal counters, filters, and converters. Register control data is written into and read back from the VBAP registers via the control interface. I2C- bus protocols The PCM codec serial interface is designed to be I2C bus-compatible and operates in the slave mode. This interface consists of the following terminals: SCL: I2C bus serial clock—This input synchronizes the control data transfer from and to the CODEC. SDA: I2C bus serial address/data input/output—This is a bidirectional terminal that transfers register control addresses and data into and out of the codec. It is an open drain terminal and therefore requires a pullup resistor to VCC (typical 10 kΩ for 100 kHz). TLV320AIC1103 has a fixed device select address of {E2}HEX for write mode and {E3}HEX for read mode. For normal data transfer, SDA is allowed to change only when SCL is low. Changes when SCL is high are reserved for indicating the start and stop conditions. Data transfer may be initiated only when the bus is not busy. During data transfer, the data line must remain stable whenever the clock line is at high. Changes in the data line while the clock line is at high are interpreted as a start or stop condition. www.ti.com 27 TLV320AIC1103 SLAS356 – DECEMBER 2001 PRINCIPLES OF OPERATION Table 10. I2C Bus Conditions CONDITION STATUS DESCRIPTION A Bus not busy Both data and clock lines remain at high. B Start data transfer A high to low transition of the SDA line while the clock (SCL) is high determines a start condition. All commands must proceed from a start condition. C Stop data transfer A low to high transition of the SDA line while the clock (SCL) is high determines a stop condition. All operations must end with a stop condition. D Data valid The state of the data line represents valid data when, after a start condition, the data line is stable for the duration of the high period of the clock signal. I2C bus protocols The data on the line must be changed during the low period of the clock signal. There is one clock pulse per bit of data. Each data transfer is initiated with a start condition and terminated with a stop condition. When addressed, the PCM codec generates an acknowledge after the reception of each byte. The master device (microprocessor) must generate an extra clock pulse that is associated with this acknowledge bit. The PCM codec must pull down the SDA line during the acknowledge clock pulse so that the SDA line is at stable low state during the high period of the acknowledge related clock pulse. Setup and hold times must be taken into account. During read operations, a master must signal an end of data to the slave by not generating an acknowledge bit on the last byte that was clocked out of the slave. In this case, the slave (PCM codec) must leave the data line high to enable the master to generate the stop condition. clock frequencies and sample rates A fixed PCMSYN rate of 8 kHz determines the sampling rate. 28 www.ti.com TLV320AIC1103 SLAS356 – DECEMBER 2001 MECHANICAL DATA PBS (S-PQFP-G32) PLASTIC QUAD FLATPACK 0,23 0,17 0,50 24 0,08 M 17 25 16 32 9 0,13 NOM 1 8 3,50 TYP Gage Plane 5,05 SQ 4,95 0,25 7,10 SQ 6,90 0,10 MIN 0°–ā7° 0,70 0,40 1,05 0,95 Seating Plane 0,08 1,20 MAX 4087735/A 11/95 NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. www.ti.com 29 TLV320AIC1103 SLAS356 – DECEMBER 2001 MECHANICAL DATA GQE (S-PBGA-N80) PLASTIC BALL GRID ARRAY 5,20 SQ 4,80 4,00 TYP 0,50 J 0,50 H G F E D C B A 1 0,68 0,62 2 3 4 5 6 7 8 9 1,00 MAX Seating Plane 0,35 0,25 ∅ 0,05 M 0,21 0,11 NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. C. 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