TWL1110 VOICE-BAND AUDIO PROCESSOR (VBAP) SLWS103 – NOVEMBER 2000 2.7 to 3.3-V Operation Designed for Analog and Digital Wireless Handsets and Telecommunications Applications Two Differential Microphone Inputs Differential Earphone Outputs and One Single-Ended Earphone Output Earphone and Microphone Mute Programmable Transmit, Receive, and Sidetone Paths With Extended Gain and Attenuation Ranges Programmable for 15-Bit Linear Data or 8-Bit Companded (µ-law and A-law) Mode Supports PCM Clock Rates of 128 kHz and 2.048 MHz Pulse Density Modulated (PDM) Buzzer Output On-Chip I2C Bus, Which Provides Simple, Standard, Two-Wire Serial Interface With Digital ICs Dual-Tone Multifrequency (DTMF) and Single-Tone Generator Capable of Up to 8-kHz Tone With Three Selectable Resolutions of 7.8125 Hz, 15.625 Hz, and 31.25 Hz 2-Channel Auxiliary Multiplexer (MUX) (Analog Switch) Capable of Driving 32 Ω Down to a 8-Ω Speaker Programmable Power Down Modes Pin Compatible to TI’s TWL1102, TWL1103, and TWL1109 Devices for TQFP only Available in a 32-Pin Thin Quad Flatpack (TQFP) Package and MicroStar Junior BGA description The TWL1110 provides extended gain and attenuation flexibility for transmit, receive, and sidetone paths. A differential earphone output is capable of driving speaker loads as low as 8 Ω for use in speaker phone applications. The single tone function on the TWL1110 generates a single tone output of up to 8 kHz. The resolution of the DTMF tone is also selectable to 7.8125 Hz, 15.625 Hz, or 31.250 Hz through the interface control. The analog switch provides more control capabilities for voice-band audio processor (VBAP). The VBAP is an analog-digital interface for voice band signals designed with a combination of coders and decoders (codecs) and filters. It is a low-power device with companding options and programming features, and it meets the requirements for communication systems, including the cellular phone. The device operates in either the 15-bit linear or 8-bit companded (µ-law or A-Law) mode, which is selectable through the I2C interface. A coder, an analog-to-digital converter or ADC, digitizes the analog voice signal, and a decoder, an digital-to-analog converter or DAC, analogs the digital-voice signal. VBAP provides a companding option to overcome the bandwidth limitations of telephone networks without degradation in sound quality. The human auditory system is a logarithmic system in which high amplitude signals require less resolution than low amplitude signals. Therefore, an 8-bit code word with nonuniform quantization (µ-law or A-law) has the same quality as 13-bit linear coding. VBAP provides better digital code words by generating a 15-bit linear coding option. This device contains circuits to protect its inputs and outputs against damage due to high static voltages or electrostatic fields. These circuits have been qualified to protect this device against electrostatic discharges (ESD) of up to 2 kV according to MIL-STD-883C, Method 3015; however, it is advised that precautions be taken to avoid application of any voltage higher than maximum-rated voltages to these high-impedance circuits. During storage or handling, the device leads should be shorted together or the device should be placed in conductive foam. In a circuit, unused inputs should always be connected to an appropriated logic voltage level, preferably either VCC or ground. Specific guidelines for handling devices of this type are contained in the publication Guidelines for Handling Electrostatic-Discharge-Sensitive (ESDS) Devices and Assemblies available from Texas Instruments. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. † These options are available on some devices. Please see the table of comparison for the last two generations of VBAPs. MicroStar Junior and VBAP are trademarks of Texas Instruments. All other trademarks are the property of their respective owners. Copyright 2000, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 TWL1110 VOICE-BAND AUDIO PROCESSOR (VBAP) SLWS103 – NOVEMBER 2000 description (continued) The human voice is effective from a frequency range of 300 Hz to 3300 Hz in telephony applications. In order to eliminate unwanted signals, the VBAP design has two types of filters that operate in both the transmit and receive path. A low-pass filter attenuates the signals over 4 kHz. A selectable high-pass filter cleans up the signals under 100 Hz. This reduces noise that may have coupled in from 50/60-Hz power cables. The high-pass filter is bypassed by selecting the corresponding register bit. VBAP has many programming features that are controlled using a 2-wire standard serial I2C interface. This allows the device to interface with many digital ICs such as a DSP or a microprocessor. The device has seven registers: power control, mode control, transmit PGA, receive PGA, high DTMF, low DTMF, and auxiliary mode control. Some of the programmable features that can be controlled by I2C interface include: Transmit amplifier gain Receive amplifier gain Sidetone gain Volume control Earphone control PLL power control Microphone selection Transmit channel high-pass filter control Receive channel high-pass filter control Companding options and selection control PCM loopback DTMF control Pulse density modulated control The VBAP is also capable of generating its own internal clocks from a 2.048-MHz master clock input. 2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 TWL1110 VOICE-BAND AUDIO PROCESSOR (VBAP) SLWS103 – NOVEMBER 2000 PLLVSS VSS MCLK RESET PWRUPSEL BUZZCON PCMSYN PCMCLK PBS PACKAGE (TOP VIEW) 24 23 22 21 20 19 18 17 PLLVDD EARVSS EAR1ON EARVDD EAR1OP EARVSS EAR2O AVDD 16 25 PCMO PCMI DVSS DVDD 12 SCL 11 SDA 10 MUXOUT2 9 MUXOUT1 26 15 14 13 27 28 29 30 31 32 2 3 4 5 6 7 8 MBIAS MIC1P MIC1N MIC2P MIC2N REXT MUXIN AVSS 1 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3 4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 IN MIC2N MIC2P MIC1N MIC1P PCMCLK PCMSYN PCMIN MUX MIC Amplifier 1 g= 23.5 dB OUT OUT I/F 2 I C Control Bus MIC Amplifier 2 g=6 or 18 dB Analog Modulator DTMF Sidetone g = –24 db to –12 dB REF Generator TX Filter and PGA g = –10 dB to 0 dB PCM Interface PLL RX Vol Control g = –18 dB to 0 dB RX Filter and PGA g = – 6 dB to +6 dB Buzzer Control Digital Modulator and Filter Power and RESET DTMF –12 to 12 dB in 6dB Steps DTMF GAIN MUX Voice 0 dB or 6 dB Ear Amp2 Ear Amp1 BUZZCON EAR2O EAR1ON EAR1OP PCMOUT TWL1110 VOICE-BAND AUDIO PROCESSOR (VBAP) SLWS103 – NOVEMBER 2000 functional block diagram PWRUPSEL V SS AVDD DVDD AV SS PLLVDD DV SS PLLV SS EARVDD EARV SS RESET MCLK REXT MBIAS SDATA SCLK TWL1110 VOICE-BAND AUDIO PROCESSOR (VBAP) SLWS103 – NOVEMBER 2000 functional description power on/reset The power for the various digital and analog circuits is separated to improve the noise performance of the device. An external reset must be applied to the active low/RESET terminal to guarantee reset upon power on and to bring the device to an operational state. After the initial power-on sequence the device can be functionally powered up and powered down by writing to the power control register through the I2C interface. The device has a pin-selectable power up in the default mode option. The hardwired pin-selectable PWRUPSEL function allows the VBAP to power up in the default mode and to be used without a microcontroller. reference A precision band gap reference voltage is generated internally and supplies all required voltage references to operate the transmit and receive channels. The reference system also supplies bias voltage for use with an electret microphone at terminal MBIAS. An external precision resistor is required for reference current setting at terminal REXT. I2C control interface The I2C interface is a two-wire bidirectional serial interface. The I2C interface controls the VBAP by writing data to seven control registers: Power control Mode control Transmit PGA and sidetone control Receive PGA gain and volume control DTMF routing Tone selection control Auxiliary control There are two power up modes which may be selected at the PWRUPSEL terminal: (1) The PWRUPSEL state (VDD at terminal 20) causes the device to power up in the default mode when power is applied. Without an I2C interface or controlling device, the programmable functions are fixed at the default gain levels, and functions such as the sidetone and DTMF are not accessible. (2) The PWRUPSEL state (ground at terminal 20) causes the device to go to a power down state when power is applied. In this mode an I2C interface is required to power up the device. phase-locked loop (PLL) The phase-lock loop generates the internal clock frequency required for digital filters and modulators by phase locking to 2.048 MHz master clock input. PCM interface The PCM interface transmits and receives data at the PCMO and PCMI terminals respectively. The data is transmitted or received at the PCMCLK speed once every PCMSYN cycle. The PCMCLK can be tied directly to the 128-kHz or 2.048-MHz master clock (MCLK). The PCMSYN can be driven by an external source or derived from the master clock and used as an interrupt to the host controller. microphone amplifiers The microphone input is a switchable interface for two differential microphone inputs. The first stage is a low-noise differential amplifier that provides a gain of 23.5 dB. The second-stage amplifier has a selectable gain of 6 or 18 dB. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 5 TWL1110 VOICE-BAND AUDIO PROCESSOR (VBAP) SLWS103 – NOVEMBER 2000 functional description (continued) analog modulator The transmit channel modulator is a third-order sigma-delta design. transmit filter and PGA The transmit filter is a digital filter designed to meet CCITT G.714 requirements. The device operates either in the 15-bit linear or 8-bit companded µ-law or in the A-law mode, which is selectable through the I2C interface. The transmit PGA defaults to 0 dB. sidetone A portion of the transmitted audio is attenuated and fed back to the receive channel through the sidetone path. The sidetone path defaults to the mute condition. The default gain of -12 dB is set in the sidetone control register. The sidetone path can be enabled by writing to the power control register. receive volume control The receive volume control block acts as an attenuator with a range of –18 dB to 0 dB in 2-dB steps for control of the receive channel volume. The receive volume control gain defaults to 0 dB. receive filter and PGA The receive filter is a digital filter that meets CCITT G.714 requirements with a high-pass filter that is selectable through the I2C interface. The device operates either in the 15-bit linear or the 8-bit µ-law or the A-law companded mode, which is selectable through the I2C interface. The gain defaults to –4 dB, representing a 3-dBm level for a 32-Ω load impedance and the corresponding digital full scale PCMI code. digital modulator and filter The second-order digital modulator and filter convert the received digital PCM data to the analog output required by the earphone interface. earphone amplifiers The analog signal can be routed to either of two earphone amplifiers, one with differential output (EAR1ON and EAR1OP) and one with single-ended output (EAR2O). Clicks and pops are suppressed for EAR1 differential output only. tone generator The tone generator provides generation of standard DTMF tones which are output to (1) the buzzer driver, as a PDM signal, (2) the receive path DAC for outputting through the earphone, or (3) as PCMO data. The integer value is loaded into one of two 8-bit registers, the high-tone register (04), or the low-tone register (05) (see the Register Map Addressing section). The tone output is 2 dB higher when applied to the high tone register (04). The high DTMF tones must be applied to the high-tone register, and the low DTMF tones to the low-tone register. The tone signals can be generated with 3 different resolutions at ∆F= 7.8125 Hz, 15.625 Hz, and 31.250 Hz. The resolution option can be selected by setting the register (06). analog mux The analog switch can be used to source an analog signal to two different loads. The output can be reselected by setting the auxiliary register (06). 6 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 TWL1110 VOICE-BAND AUDIO PROCESSOR (VBAP) SLWS103 – NOVEMBER 2000 functional description (continued) DTMF gain MUX The DTMF gain MUX selects the signal path and applies the appropriate gain setting. Therefore the device is either in tone mode or in voice mode. When set in the voice mode, the gain is controlled by the auxiliary register and is set to 0 dB or 6 dB. When set in the tone mode, the gain is from –12 dB to 12 dB in 6-dB steps which is set by the volume control register. The gain setting is controlled by the RXPGA register. This will not create any control contention since the device is working in one mode at a time. Terminal Functions TERMINAL† NO. NAME I/O µBGA TQFP AVDD AVSS A1 32 J1 BUZZCON F9 DVDD J6 13 DVSS J7 EAR1ON A6 EAR1OP EAR2O EARVDD EARVSS DESCRIPTION I Analog positive power supply 8 I Analog negative power supply (use for ground connection) 19 O Buzzer output, a pulse-density modulated signal to apply to external buzzer driver I Digital positive power supply 14 I Digital negative power supply 27 O Earphone 1 amplifier output (–) A4 29 O Earphone 1 amplifier output (+) A2 31 O Earphone 2 amplifier output A5 28 I Analog positive power supply for the earphone amplifiers A3, A7 30, 26 I Analog negative power supply for the earphone amplifiers MBIAS B1 1 O Microphone bias supply output, no decoupling capacitors MCLK C9 22 I Master system clock input (2.048 MHz, digital) MIC1P C1 2 I MIC1 input (+) MIC1N D1 3 I MIC1 input (–) MIC2P E1 4 I MIC2 input (+) MIC2N F1 5 I MIC2 input (–) MUXIN H1 7 I Analog MUX input MUXOUT1 J2 9 I Analog MUX output MUXOUT2 J3 10 I Analog MUX output PCMI J8 15 I Receive PCM input PCMO J9 16 O Transmit PCM output PCMSYN G9 18 I PCM frame sync PCMCLK H9 17 I PCM data clock PLLVSS PLLVDD A9 24 I PLL negative power supply A8 25 I PLL digital power supply PWRUPSEL E9 20 I Selects the power-up default mode REXT G1 6 I/O RESET D9 21 I SCL J5 12 I SDA J4 11 I/O Internal reference current setting terminal (use precision 100-kΩ resistor and no filtering capacitors) Active low reset I2C-bus serial clock (this input is used to synchronize the data transfer from and to the VBAP) I2C-bus serial address/data input/output. This is a bidirectional terminal used to transfer register control addresses and data into and out of the codec. It is an open-drain terminal and therefore requires a pullup resistor to VDD (typical 10 kΩ for 100 kHz). VSS B9 23 I Ground return for bandgap internal reference (use for ground connection) † All MicroStar Junior BGA pins that are not mentioned have no internal connection. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 7 TWL1110 VOICE-BAND AUDIO PROCESSOR (VBAP) SLWS103 – NOVEMBER 2000 absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 3.6 V Output voltage range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 3.6 V Input voltage range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 3.6 V Continuous total power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Dissipation Rating Table Operating free air temperature range (industrial temperature) . . . . . . . . . . . . . . . . . . . . . . . . . . . – 40°C to 85°C Storage temperature range, testing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 65°C to 150°C Lead temperature 1,6 mm from case for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. DISSIPATION RATING TABLE PACKAGE TA ≤ 25°C POWER RATING DERATING FACTOR ABOVE TA = 25°C TA = 85°C POWER RATING TQFP 702 mW 7.2 mW/°C 270 mW MicroStar Junior BGA 660 mW 164 mW/°C 220 mW low dissipation PCB MicroStar Junior BGA 2.75 W 36 mW/°C 917 mW high dissipation PCB COMMENTS low dissipation printed circuit board (PCB) recommended operating conditions (see Notes 1 and 2) MIN Supply voltage, AVDD, DVDD, PLLVDD, EARVDD NOM 2.7 High-level input voltage (VIHMIN) MAX UNIT 3.3 V 0.7 x VDD V Low-level input voltage (VILMAX) 0.3 x VDD Load impedance between EAR1OP and EAR1ON-RL Load impedance for EAR2OP-RL V 8 to 32 Ω 32 Ω Operating free-air temperature, TA – 40 85 C NOTES: 1. To avoid possible damage and resulting reliability problems to these CMOS devices, follow the power on initialization paragraph, described in the Principles of Operation. 2. Voltages are with respect to AVSS, DVSS, PLLVSS , and EARVSS. electrical characteristics over recommended ranges of supply voltage and free-air temperature (unless otherwise noted) supply current PARAMETER I ton(i) Supply current from VDD TEST CONDITIONS TYP MAX Operating, EAR1 selected, MicBias disabled 4.5 6 mA Operating, EAR2 selected, MicBias disabled 4.5 6 mA Power down room temperature, VDD = 3.0 V, Reg 6 bit 7 = 1, MClk not present (see Note 3) 2 10 µA Power down room temperature, VDD = 3.0 V, , Reg 6 bit 7 = 0, MClk not present (see Note 3) 10 30 µA 5 10 ms Power-up time from power down 3. VIHMIN = VDD, VILMAX = VSS. 8 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 MIN UNIT TWL1110 VOICE-BAND AUDIO PROCESSOR (VBAP) SLWS103 – NOVEMBER 2000 electrical characteristics over recommended ranges of supply voltage and free-air temperature (unless otherwise noted) (continued) digital interface PARAMETER TEST CONDITIONS VDD = 3 V VDD = 3 V TYP MAX UNIT VOH VOL High-level output voltage PCMO (BuzzCon) IIH IIL High-level input current, any digital input CI Input capacitance CO Output capacitance 20 pF RL Load impedance (BuzzCon) 5 kΩ Low-level output voltage PCMO IOH = – 3.2 mA, IOL = 3.2 mA, MIN DVDD – 0.25 V VI = VDD VI = VSS Low-level input current, any digital input SUPPLY CURRENT vs FREE AIR TEMPERATURE (Detector OFF) 0.25 V 10 µA 10 µA 10 pF SUPPLY CURRENT vs FREE AIR TEMPERATURE (Detector ON) 45 30 40 I DD – Supply Current – µ A I DD – Supply Current – µ A 25 20 VDD = 3.3 V 15 10 VDD = 3.0 V 35 30 25 VDD = 3.3 V 20 15 10 VDD = 3.0 V 5 5 0 –50 VDD = 2.7 V VDD = 2.7 V 0 50 TA – Free-Air Temperature – °C 0 –50 100 0 50 TA – Free-Air Temperature – °C 100 microphone interface PARAMETER TEST CONDITIONS VIO IIB Input offset voltage at MIC1N, MIC2N Ci Input capacitance at MIC1N, MIC2N Vn Microphone input referred noise, psophometrically weighted, (C-message weighted is similar) IOmax V(mbias) See Note 4 Input bias current at MIC1N, MIC2N MIN TYP MAX UNIT –5 5 mV – 300 300 nA 5 MIC Amp 1 gain = 23.5 dB MIC Amp 2 gain = 0 dB Output source current – MBIAS 3 1 Microphone bias supply voltage (see Note 5) 2.3 MICMUTE – 80 Input impedance Fully differential 35 2.5 pF 4.7 µVrms 1.2 mA 2.65 V dB 60 100 kΩ NOTES: 4. Measured while MIC1P and MIC1N are connected together. Less than 0.5-mV offset results in 0 value code on PCMOUT. 5. Not a JEDEC symbol. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 9 TWL1110 VOICE-BAND AUDIO PROCESSOR (VBAP) SLWS103 – NOVEMBER 2000 electrical characteristics over recommended ranges of supply voltage and free-air temperature (unless otherwise noted) (continued) speaker interface PARAMETER TEST CONDITIONS TYP MAX VDD = 2.7 V, fully differential, 8-Ω load, 3-dBm0 output, volume control = – 3 dB, RXPGA = – 4 dB level 161 200 VDD = 2.7 V, fully differential, 16-Ω load, 3-dBm0 output, volume control = – 3 dB, RXPGA = – 2 dB level 128 160 VDD = 2.7 V, fully differential, 32-Ω load, 3-dBm0 output, volume control = – 3 dB, RXPGA = – 1 dB level 81 100 Earphone AMP2 output power (see Note 6) VDD = 2.7 V, single-ended, 32-Ω load, 3-dBm0 output 10 12.5 mW Output offset voltage at EAR1 Fully differential ±5 ± 30 mV 3-dBm0 input, 8-Ω load 141 178 Maximum out output ut current for EAR1 (rms) 3-dBm0 input, 16-Ω load 90 112 3-dBm0 input, 32-Ω load 50 63 17.7 22.1 Earphone AMP1 output power (see Note 6) VOO IOmax Maximum output current for EAR2 (rms) MIN 3-dBm0 input EARMUTE – 80 UNIT mW mA dB NOTE 6: Maximum power is with a load impedance of –25%. transmit gain and dynamic range, companded mode (µ-law or A-law) or linear mode selected, transmit slope filter bypassed (see Notes 7 and 8) PARAMETER Transmit reference-signal level (0 dB) Overload signal level (3 dBm0) Overload-signal Absolute gain error TEST CONDITIONS TYP MAX UNIT 87.5 mVpp Differential, normal mode 124 Differential, extended mode 31.5 0 dBm0 input signal, VDD ±10% MIC1N, MIC1P to PCMO at 3 dBm0 to –30 dBm0 G i error with ith iinputt llevell relative l ti tto gain i att Gain –10 dBm0 MIC1N MIC1N, MIC1P to PCMO MIN Differential –1 1 – 0.5 0.5 MIC1N, MIC1P to PCMO at –31 dBm0 to –45 dBm0 –1 1 MIC1N, MIC1P to PCMO at –46 dBm0 to –55 dBm0 –1.2 1.2 mVpp dB dB NOTES: 7. Unless otherwise noted, the analog input is 0 dB, 1020-Hz sine wave, where 0 dB is defined as the zero-reference point of the channel under test. 8. The reference signal level, which is input to the transmit channel, is defined as a value 3 dB below the full-scale value of 88-mVrms. transmit gain and dynamic range, companded mode (µ-law or A-law) or linear mode selected, transmit slope filter enabled (see Notes 7 and 8) PARAMETER Transmit reference-signal level (0 dB) Overload signal level (3 dBm0) Overload-signal Absolute gain error TEST CONDITIONS TYP MAX UNIT 87.5 mVpp mVpp Differential, normal mode 124 Differential, extended mode 31.5 0 dBm0 input signal, VDD ±10% –1 1 – 0.5 0.5 MIC1N, MIC1P to PCMO at – 31 dBm0 to – 45 dBm0 –1 1 MIC1N, MIC1P to PCMO at – 46 dBm0 to – 55 dBm0 –1.2 1.2 MIC1N, MIC1P to PCMO at 3 dBm0 to – 30 dBm0 Gain G i error with ith iinputt llevell relative l ti tto gain i att –10 dBm0 MIC1N MIC1N, MIC1P to PCMO MIN Differential mVpp dB dB NOTES: 7. Unless otherwise noted, the analog input is 0 dB, 1020-Hz sine wave, where 0 dB is defined as the zero-reference point of the channel under test. 8 The reference signal level, which is input to the transmit channel, is defined as a value 3 dB below the full-scale value of 88-mVrms. 10 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 TWL1110 VOICE-BAND AUDIO PROCESSOR (VBAP) SLWS103 – NOVEMBER 2000 electrical characteristics over recommended ranges of supply voltage and free-air temperature (unless otherwise noted) (continued) transmit filter transfer, companded mode (µ-law or A-law) or linear mode selected, transmit slope filter bypassed (MCLK = 2.048 MHz) PARAMETER TEST CONDITIONS Gain G i relative l ti tto iinputt signal i l gain i att 1020 H Hz, iinternal t l hi high-pass h filter disabled Gain relative to in input ut signal gain at 1020 Hz, internal high high-pass ass filter enabled MIN TYP MAX fMIC1 or fMIC2 <100 Hz fMIC1 or fMIC2 = 200 Hz – 0.5 0.5 – 0.5 0.5 fMIC1 or fMIC2 = 300 Hz to 3 kHz fMIC1 or fMIC2 = 3.4 kHz – 0.5 0.5 – 1.5 0 fMIC1 or fMIC2 = 4 kHz fMIC1 or fMIC2 = 4.6 kHz – 14 fMIC1 or fMIC2 = 8 k Hz fMIC1 or fMIC2 <100 Hz – 47 fMIC1 or fMIC2 = 200 Hz –5 UNIT dB – 35 – 15 dB transmit filter transfer, companded mode (µ-law or A-law) or linear mode selected, transmit slope filter selected, transmit high-pass filter enabled (MCLK = 2.048 MHz) (see Note 9) PARAMETER TEST CONDITIONS MIN TYP fMIC1 or f MIC2 =100 Hz fMIC1 or fMIC2 = 200 Hz fMIC1 or fMIC2 = 250 Hz fMIC1 or fMIC2 = 300 Hz UNIT – 27 dB –8 dB –4 dB –1.80 dB fMIC1 or fMIC2 = 400 Hz fMIC1 or fMIC2 = 500 Hz –1.50 dB –1.30 dB fMIC1 or fMIC2 = 600 Hz fMIC1 or fMIC2 = 700 Hz –1.1 dB fMIC1 or fMIC2 = 800 Hz fMIC1 or fMIC2 = 900 Hz fMIC1 or fMIC2 = 1000 Hz fMIC1 or fMIC2 = 1500 Hz Gain relative to input signal gain at 1.02 1 02 kHz, kHz with slope filter selected MAX – 0.8 dB – 0.57 dB – 0.25 dB 0 dB 1.8 dB fMIC1 or fMIC2 = 2000 Hz fMIC1 or fMIC2 = 2500 Hz 4.0 dB 6.5 dB fMIC1 or fMIC2 = 3000 Hz fMIC1 or fMIC2 = 3100 Hz 7.6 dB 7.7 dB 8.0 dB 6.48 dB fMIC1 or fMIC2 = 3300 Hz fMIC1 or fMIC2 = 3500 Hz fMIC1 or fMIC2 = 4000 Hz fMIC1 or fMIC2 = 4500 Hz –13 dB –35 dB fMIC1 or fMIC2 = 5000 Hz fMIC1 or fMIC2 = 8000 Hz – 45 dB – 50 dB NOTE 9: The pass-band tolerance is ± 0.25 dB from 300 Hz to 3500 Hz. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 11 TWL1110 VOICE-BAND AUDIO PROCESSOR (VBAP) SLWS103 – NOVEMBER 2000 electrical characteristics over recommended ranges of supply voltage and free-air temperature (unless otherwise noted) (continued) RELATIVE GAIN vs FREQUENCY RELATIVE GAIN vs FREQUENCY 5 20 Both Filters Disabled 0 Relative Gain – dB Relative Gain – dB 0 –20 –40 Both Filters Disabled High Pass Filter Selected and Slope Filter Disabled –60 –5 –10 –15 –20 High Pass Filter and Slope Filter Selected –80 –100 100 1000 f – Frequency – Hz High Pass Filter Selected and Slope Filter Disabled High Pass Filter and Slope Filter Selected –25 –30 100 10000 1000 f – Frequency – Hz Figure 1. Transmit Gain Response With Respect to Gain of 1 kHz Tone transmit idle channel noise and distortion, companded mode (µ-law or A-law) selected, slope filter bypassed PARAMETER TEST CONDITIONS Transmit idle channel noise, psophometrically weighted Transmit signal signal-to-distortion to distortion ratio with 1020-Hz sine-wave input Intermodulation distortion, 2 2-tone tone CCITT method, composite power level, –13 dBm0 12 MIN TXPGA gain= 0 dB, MIC Amp 1 gain = 23.5 dB, MIC Amp 2 gain = 6 dB MIC1N, MIC1P to PCMO at 3 dBm0 27 MIC1N, MIC1P to PCMO at 0 dBm0 30 MIC1N, MIC1P to PCMO at – 5 dBm0 33 MIC1N, MIC1P to PCMO at – 10 dBm0 36 MIC1N, MIC1P to PCMO at – 20 dBm0 35 MIC1N, MIC1P to PCMO at – 30 dBm0 26 MIC1N, MIC1P to PCMO at – 40 dBm0 24 MIC1N, MIC1P to PCMO at – 45 dBm0 19 CCITT G.712 (7.1), R2 49 CCITT G.712 (7.2), R2 51 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 TYP MAX – 83.5 – 78 UNIT dBm0p dBm0 dB TWL1110 VOICE-BAND AUDIO PROCESSOR (VBAP) SLWS103 – NOVEMBER 2000 electrical characteristics over recommended ranges of supply voltage and free-air temperature (unless otherwise noted) (continued) transmit idle channel noise and distortion, companded mode (µ-law or A-law) selected, slope filter enabled PARAMETER TEST CONDITIONS Transmit idle channel noise, psophometrically weighted MIN TXPGA gain= 0 dB, MIC Amp 1 gain = 23.5 dB, MIC Amp 2 gain = 6 dB Transmit signal signal-to-total to total distortion ratio with 1020 1020-Hz Hz sine-wave input Intermodulation distortion, 2 2-tone tone CCITT method, composite power level, –13 dBm0 MIC1N, MIC1P to PCMO at 3 dBm0 27 MIC1N, MIC1P to PCMO at 0 dBm0 30 MIC1N, MIC1P to PCMO at – 5 dBm0 33 MIC1N, MIC1P to PCMO at –10 dBm0 36 MIC1N, MIC1P to PCMO at –20 dBm0 35 MIC1N, MIC1P to PCMO at – 30 dBm0 26 MIC1N, MIC1P to PCMO at – 40 dBm0 24 MIC1N, MIC1P to PCMO at – 45 dBm0 19 CCITT G.712 (7.1), R2 49 CCITT G.712 (7.2), R2 51 TYP MAX – 83.5 – 78 UNIT dBm0p dBm0 dB transmit idle channel noise and distortion, linear mode selected, slope filter bypassed PARAMETER TEST CONDITIONS MIN TXPGA gain = 0 dB, MIC Amp 1 gain = 23.5 dB, MIC Amp 2 gain = 6 dB Transmit idle channel noise Transmit signal signal-to-total to total distortion ratio with 1020 1020-Hz Hz sine-wave input TYP MAX – 83.5 – 78 MIC1N, MIC1P to PCMO at 3 dBm0 50 50 MIC1N, MIC1P to PCMO at 0 dBm0 50 65 MIC1N, MIC1P to PCMO at – 5 dBm0 52 61 MIC1N, MIC1P to PCMO at –10 dBm0 56 65 MIC1N, MIC1P to PCMO at –20 dBm0 50 59 MIC1N, MIC1P to PCMO at – 30 dBm0 51 63 MIC1N, MIC1P to PCMO at – 40 dBm0 43 55 MIC1N, MIC1P to PCMO at – 45 dBm0 38 52 UNIT dBm0p dB transmit idle channel noise and distortion, linear mode selected, slope filter enabled PARAMETER TEST CONDITIONS MIN TXPGA gain = 0 dB, MIC Amp 1 gain = 23.5 dB, MIC Amp 2 gain = 6 dB Transmit idle channel noise Transmit signal signal-to-total to total distortion ratio with 1020 1020-Hz Hz sine-wave input TYP MAX – 83.5 – 78 MIC1N, MIC1P to PCMO at 3 dBm0 40 50 MIC1N, MIC1P to PCMO at 0 dBm0 50 65 MIC1N, MIC1P to PCMO at – 5 dBm0 50 68 MIC1N, MIC1P to PCMO at –10 dBm0 64 70 MIC1N, MIC1P to PCMO at –20 dBm0 58 65 MIC1N, MIC1P to PCMO at – 30 dBm0 50 60 MIC1N, MIC1P to PCMO at – 40 dBm0 38 50 MIC1N, MIC1P to PCMO at – 45 dBm0 30 45 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 UNIT dBm0p dB 13 TWL1110 VOICE-BAND AUDIO PROCESSOR (VBAP) SLWS103 – NOVEMBER 2000 electrical characteristics over recommended ranges of supply voltage and free-air temperature (unless otherwise noted) (continued) receive gain and dynamic range, EAR1 selected, linear or companded (µ-law or A-law) mode selected (see Note 10) PARAMETER Overload signal level (3 dB) TEST CONDITIONS 16-Ω load RXPGA = – 4 dB 4.05 32-Ω load RXPGA = – 4 dB 4.54 PCMIN to EAR1ON, EAR1OP at 3 dBm0 to – 40 dBm0 Gain G i error with ith output t t llevell relative l ti tto gain i at –10 dBm0 TYP 3.20 0 dBm0 input signal, VDD ±10% Absolute gain error MIN 6-Ω load RXPGA = – 4 dB MAX UNIT Vpp –1 1 – 0.5 0.5 PCMIN to EAR1ON, EAR1OP at – 41 dBm0 to – 50 dBm0 –1 1 PCMIN to EAR1ON, EAR1OP at – 51 dBm0 to – 55 dBm0 –1.2 1.2 dB dB NOTE 10: RXPGA = – 4 dB for 32 Ω , 16 Ω , or 8 Ω, RXVOL = 0 dB, 1020-Hz input signal at PCMI, output measured differentially between EAR1ON and EAR1OP receive gain and dynamic range, EAR2 selected, linear or companded (µ-law or A-law) mode selected (see Note 11) PARAMETER TEST CONDITIONS Receive reference signal level (0 dB) MIN 0 dBm0 PCM input signal TYP MAX 1.36 Overload-signal level (3 dB) Vpp Vpp 1.925 0 dBm0 input signal, VDD ±10% Absolute gain error –1 1 – 0.5 0.5 PCMIN to EAR2O at – 41 dBm0 to – 50 dBm0 –1 1 PCMIN to EAR2O at – 51 dBm0 to – 55 dBm0 – 1.2 1.2 PCMIN to EAR2O at 3 dBm0 to – 40 dBm0 Gain G i error with ith output t t llevell relative l ti tto gain i att –10 dBm0 UNIT dB dB NOTE 11: RXPGA = – 1 dB, RXVOL = 0 dB receive filter transfer, companded mode (µ-law or A-law) or linear mode selected (MCLK = 2.048 MHz) (see Note 11) PARAMETER TEST CONDITIONS Gain G i relative l ti tto iinputt signal i l gain i att 1020 H Hz, iinternal t l high-pass filter disabled Gain relative to in input ut signal gain at 1020 Hz, internal high-pass filter enabled TYP MAX – 0.5 0.5 – 0.5 0.5 fEAR1 or fEAR2 = 300 Hz to 3 kHz fEAR1 or fEAR2 = 3.4 kHz – 0.5 0.5 –1.5 0 fEAR1 or fEAR2 = 4 kHz fEAR1 or fEAR2 = 4.6 kHz – 14 fEAR1 or fEAR2 = 8 kHz fEAR1 or fEAR2 < 100 Hz – 47 fEAR1 or fEAR2 = 200 Hz –5 NOTE 11. RXPGA = – 1 dB, RXVOL = 0 dB 14 MIN fEAR1 or fEAR2 < 100 Hz fEAR1 or fEAR2 = 200 Hz POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 UNIT dB – 35 –15 dB TWL1110 VOICE-BAND AUDIO PROCESSOR (VBAP) SLWS103 – NOVEMBER 2000 electrical characteristics over recommended ranges of supply voltage and free-air temperature (unless otherwise noted) (continued) RELATIVE GAIN RESPONSE vs FREQUENCY 5 0 Relative Gain – dB –5 –10 –15 –20 –25 –30 –35 10 100 1k 10 k f – Frequency – Hz Figure 2. Receive Gain Response With Respect to Gain of 1 kHz Tone With High Pass Filter Selected and High Pass Filter Disabled receive idle channel noise and distortion, EAR1 selected, companded mode (µ-law or A-law) selected (see Note 10) TYP MAX Receive noise, psophometrically weighted PARAMETER PCMIN = 11010101 (A-law) – 89 – 86 Receive noise, C-message weighted PCMIN = 11111111 (µ-law) 36 50 Receive signal signal-to-distortion to distortion ratio with 1020 1020-Hz Hz sinewave input TEST CONDITIONS MIN PCMIN to EAR1ON, EAR1OP at 3 dBm0 21 PCMIN to EAR1ON, EAR1OP at 0 dBm0 25 PCMIN to EAR1ON, EAR1OP at – 5 dBm0 36 PCMIN to EAR1ON, EAR1OP at –10 dBm0 43 PCMIN to EAR1ON, EAR1OP at – 20 dBm0 40 PCMIN to EAR1ON, EAR1OP at – 30 dBm0 38 PCMIN to EAR1ON, EAR1OP at – 40 dBm0 28 PCMIN to EAR1ON, EAR1OP at – 45 dBm0 23 UNIT dBm0p µVrms dB NOTE 10: RXPGA = – 4 dB for 32 Ω , RXVOL = 0 dB, 1020-Hz input signal at PCMI, output measured differentially between EAR1ON and EAR1OP. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 15 TWL1110 VOICE-BAND AUDIO PROCESSOR (VBAP) SLWS103 – NOVEMBER 2000 electrical characteristics over recommended ranges of supply voltage and free-air temperature (unless otherwise noted) (continued) receive idle channel noise and distortion, EAR1 selected, linear mode selected (see Note 10) PARAMETER TEST CONDITIONS Receive noise, (20-Hz to 20-kHz brickwall window) 1020-Hz Receive signal-to-distortion signal to distortion ratio with 1020 Hz sine-wave input 2-tone Intermodulation distortion, 2 tone CCITT method, composite power level, –13 dBm0 MIN PCMIN = 000000000000000 TYP MAX UNIT – 88 – 83 dBm0 PCMIN to EAR1ON, EAR1OP at 3 dBm0 53 61 PCMIN to EAR1ON, EAR1OP at 0 dBm0 63 75 PCMIN to EAR1ON, EAR1OP at – 5 dBm0 60 72 PCMIN to EAR1ON, EAR1OP at –10 dBm0 56 67 PCMIN to EAR1ON, EAR1OP at – 20 dBm0 50 63 PCMIN to EAR1ON, EAR1OP at – 30 dBm0 45 50 PCMIN to EAR1ON, EAR1OP at – 40 dBm0 40 51 PCMIN to EAR1ON, EAR1OP at – 45 dBm0 38 49 CCITT G.712 (7.1), R2 50 CCITT G.712 (7.2), R2 54 dB dB NOTE 10: RXPGA = – 4 dB for 32 Ω , RXVOL = 0 dB, 1020-Hz input signal at PCMI, output measured differentially between EAR1ON and EAR1OP. receive idle channel noise and distortion EAR2 selected, companded mode (µ-law or A-law) selected (see Note 11) PARAMETER TEST CONDITIONS Receive noise, psophometrically weighted PCMIN = 11010101 (A-law) Receive noise, C-message weighted PCMIN = 11111111 (µ-law) Receive signal-to-distortion ratio with 1020-Hz sinewave input MIN PCMIN to EAR2O at 3 dBm0 21 PCMIN to EAR2O at 0 dBm0 25 PCMIN to EAR2O at – 5 dBm0 36 PCMIN to EAR2O at –10 dBm0 43 PCMIN to EAR2O at – 20 dBm0 40 PCMIN to EAR2O at – 30 dBm0 38 PCMIN to EAR2O at – 40 dBm0 28 PCMIN to EAR2O at – 45 dBm0 23 TYP MAX – 82 – 78 36 50 UNIT dBmop µVrms dB NOTE 11. RXPGA = – 1 dB, RXVOL = 0 dB receive idle channel noise and distortion, EAR2 selected, linear mode selected (see Note 11) PARAMETER TEST CONDITIONS Receive noise, (20 Hz to 20 kHz brickwall window) Receive signal-to-noise + distortion ratio with 1020-Hz sinewave input Intermodulation distortion, distortion 2-tone 2 tone CCITT method POST OFFICE BOX 655303 TYP MAX UNIT – 83 – 86 dBm0 PCMIN to EAR2O at 3 dBm0 53 60 PCMIN to EAR2O at 0 dBm0 60 65 PCMIN to EAR2O at – 5 dBm0 58 62 PCMIN to EAR2O at –10 dBm0 55 60 PCMIN to EAR2O at – 20 dBm0 53 60 PCMIN to EAR2O at – 30 dBm0 51 58 PCMIN to EAR2O at – 40 dBm0 50 57 PCMIN to EAR2O at – 45 dBm0 48 52 CCITT G.712 (7.1), R2 50 CCITT G.712 (7.2), R2 54 NOTE 11: RXPGA = – 1 dB, RXVOL = 0 dB 16 MIN PCMIN = 000000000000000 • DALLAS, TEXAS 75265 dB dB TWL1110 VOICE-BAND AUDIO PROCESSOR (VBAP) SLWS103 – NOVEMBER 2000 electrical characteristics over recommended ranges of supply voltage and free-air temperature (unless otherwise noted) (continued) power supply rejection and crosstalk attenuation PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Supply voltage rejection, transmit channel MIC1N, MIC1P =0 V, VDD = 3 Vdc + 100 mVpeak to peak, f = 0 to 50 kHz – 86 – 70 dB Supply voltage rejection, receive channel, EAR1 selected (differential) PCM code = positive zero, VDD = 3 Vdc + 100 mVpeak to peak, f = 0 to 50 kHz – 98 – 70 dB Crosstalk attenuation, transmit-to-receive (differential) MIC1N, MIC1P = 0 dB, f = 300 to 3400 Hz measured differentially between EAR1ON and EAR1OP 70 dB Crosstalk attenuation, receive-to-transmit PCMIN = 0 dBm0, f = 300 to 3400 Hz measured at PCMO, EAR1 amplifier 70 dB switching characteristics clock timing requirements for 2.048-MHz CLK PARAMETER tt f(mclk) MIN NOM MAX Transition time, MCLK 10 MCLK frequency 2.048 ns MHz MCLK jitter 37% Number of PCMCLK clock cycles per PCMSYN frame tc(PCMCLK) UNIT 256 256 PCMCLK clock period 156 488 512 Duty cycle, PCMCLK 45% 50% 68% ns transmit timing requirements for 2.048-MHz CLK (see Figure 8) MIN MAX tsu(PCMSYN) Setup time, PCMSYN high before falling edge of PCMCLK PARAMETER 20 tc(PCMCLK)– 20 UNIT th(PCMSYN) Hold time, PCMSYN high after falling edge of PCMCLK 20 tc(PCMCLK)– 20 ns receive timing requirements for 2.048-MHz CLK (see Figure 9) MIN MAX UNIT tsu(PCSYN) th(PCSYN) Setup time, PCMSYN high before falling edge of PCMCLK PARAMETER 20 ns Hold time, PCMSYN high after falling edge of PCMCLK 20 tc(PCMCLK)– 20 tc(PCMCLK)– 20 tsu(PCMI) th(PCMI) Setup time, PCMI high or low before falling edge of PCMCLK 20 ns Hold time, PCMI high or low after falling edge of PCMCLK 20 ns ns clock timing requirements for 128-kHz CLK PARAMETER tt f(mclk) MIN NOM Transition time, MCLK 10 MCLK frequency 128 MCLK jitter 16 PCMCLK clock period Duty cycle, PCMCLK tc(PCMSYN) UNIT ns kHz 5% Number of PCMCLK clock cycles per PCMSYN frame tc(PCMCLK) MAX 16 742.19 781.25 820.31 40% 50% 60% PCMSYN clock period µs 125 Duty cycle, PCMCLK 49.5% POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 50% ns 50.5% 17 TWL1110 VOICE-BAND AUDIO PROCESSOR (VBAP) SLWS103 – NOVEMBER 2000 switching characteristics (continued) transmit timing requirements for 128-kHz CLK (see Figure 12) MIN MAX UNIT tsu(PCMSYN) th(PCMSYN) Setup time, PCMSYN high before rising edge of PCMCLK PARAMETER 20 Hold time, PCMSYN high after falling edge of PCMCLK 20 tc(PCMCLK)/4 tc(PCMCLK)/4 ns tv(PCMO) Data valid time after the rising edge of PCMSYNC 50 ns receive timing requirements for 128-kHz CLK (see Figure 11) MIN MAX UNIT tsu(PCSYN) th(PCSYN) Setup time, PCMSYN high before rising edge of PCMCLK PARAMETER 20 ns Hold time, PCMSYN high after falling edge of PCMCLK 20 tc(PCMCLK)/4 tc(PCMCLK)/4 tsu(PCMI) th(PCMI) Setup time, PCMI high or low before falling edge of PCMCLK 20 ns Hold time, PCMI high or low after falling edge of PCMCLK 20 ns ns propagation delay times, CLmax = 10 pF (see Figure 8) PARAMETER MIN MAX UNIT tpd1 tpd2 From PCMCLK bit 1 high to PCMO bit 1 valid 35 ns From PCMCLK high to PCMO valid, bits 2 to n 35 ns tpd3 From PCMCLK bit n low to PCMO bit n Hi-Z 30 ns I2C bus timing requirements (see Figure 10) PARAMETER MIN MAX UNIT 400 kHz SCL Clock frequency t(HIGH) t(LOW) Clock high time 600 ns Clock low time 1300 ns th(STA) tsu(STA) Hold time (repeated) START condition. After this period the first clock pulse is generated. 600 ns Setup time for repeated START condition 600 ns th(DAT) tsu(DAT) Data input hold time 0 ns Data input setup time 100 ns tsu(STO) t(BUF) STOP condition setup time 600 ns tr tf SDA and SCL rise time 300 ns SDA and SCL fall time 300 ns UNIT Bus free time 1300 ns DTMF generator characteristics PARAMETER TEST CONDITIONS DTMF high to low tone relative amplitude (pre-emphasis) Tone frequency accuracy (for DTMF) Resolution of 7.8125 Hz Harmonic distortion Measured from lower tone group to highest parasitic MIN TYP MAX 1.5 2 2.5 dB 1.5 % – 20 dB –1.5 MICBIAS characteristics PARAMETER TEST CONDITIONS Load impedance (bias mode) 18 MIN TYP 5 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 MAX UNIT kΩ TWL1110 VOICE-BAND AUDIO PROCESSOR (VBAP) SLWS103 – NOVEMBER 2000 PARAMETER MEASUREMENT INFORMATION SCL SDA A6 A5 A4 A0 R/W 0 ACK R7 R5 R0 ACK D7 D6 D5 D0 ACK 0 Slave Address Start R6 0 0 Register Address Stop Data NOTE: SLAVE = VBAP Figure 3. I2C-Bus Write to VBAP SCL SDA A6 A5 A0 R/W ACK 0 Start R7 R6 R0 ACK A6 A0 0 R/W ACK 1 Slave Address Register Address Slave Address D7 D6 D0 ACK 0 Slave Drives The Data Repeated Start NOTE: SLAVE = VBAP Stop Master Drives ACK and Stop Figure 4. I2C Read From VBAP: Protocol A SCL SDA A6 A5 A0 R/W ACK 0 Start Slave Address R7 R6 R0 ACK 0 A0 R/W ACK D7 A6 A5 Stop Start Register Address Slave Address NOTE: SLAVE = VBAP D0 ACK Slave Drives The Data Stop Master Drives ACK and Stop Figure 5. I2C Read From VBAP: Protocol B POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 19 TWL1110 VOICE-BAND AUDIO PROCESSOR (VBAP) SLWS103 – NOVEMBER 2000 PRINCIPLES OF OPERATION power-on initialization An external reset with a minimum pulse width of 500 ns must be applied to the active low RESET terminal to guarantee reset upon power on. All registers are set with default values upon external reset initialization. The desired selection for all programmable functions can be initialized prior to a power-up command using the control interface. Table 1. Power Up and Power Down Procedures (VDD = 2.7 V, earphone amplifier unloaded) DEVICE STATUS Power up Power down PROCEDURE MAXIMUM POWER CONSUMPTION Set bit 1 = 1 in power control register, EAR1 enabled 16.2 mW Set bit 1 = 0 in power control register, EAR2 enabled 14.6 mW Set bit 7 = 1 in TXPGA control register and bit 0 = 0 1.35 µW Set bit 7 = 0 in TXPGA control register and bit 0 = 0 67.5 µW In addition to resetting the power down bit in the power control register, loss of MCLK (no transition detected) automatically enters the device into a power down state with PCMO in the high impedance state. If during a pulse code modulation (PCM) data transmit cycle an asynchronous power down occurs, the PCM interface remains powered up until the PCM data is completely transferred. An additional power down mode overrides the MCLK detection function. This allows the device to enter the power down state without regard to MCLK. Setting bit 7 of the TXPGA sidetone register to logic high enables this function. internal reference current setting terminal Use a 100-kΩ precision resistor to connect the REXT pin to GND. conversion laws The device can be programmed for either a 15-bit linear or and 8-bit (µ-law or A-law) companding mode. The companding operation approximates the CCITT G.711 recommendation. The linear mode operation uses a 15-bit twos-complement format. transmit operation microphone input The microphone input stage is a low-noise differential amplifier that provides a preamplifier gain of 23.5 dB. It is recommended that a microphone capacitively connected to the MIC1N and MIC1P inputs, while the MIC2N and MIC2P inputs can be used to capacitively connect a second microphone or an auxiliary audio circuit. 20 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 TWL1110 VOICE-BAND AUDIO PROCESSOR (VBAP) SLWS103 – NOVEMBER 2000 PRINCIPLES OF OPERATION transmit operation (continued) _ MBIAS + Rmic Vref 510 kΩ Ci MIC1N 34 kΩ _ M I C + 34 kΩ Ci MIC1P Rmic 510 kΩ Figure 6. Typical Microphone Interface microphone mute function Transmit channel muting provides 80-dB attenuation of the input microphone signal. The MICMUTE function can be selected by setting bit 6 of the power control register through the I2C interface. transmit channel gain control The values in the transmit PGA control registers control the gain in the transmit path. The total TX channel gain can vary from 41.5 dB to 19.5 dB. The default total TX channel gain is 23.5 dB. Table 2. Transmit Gain Control BIT NAME MIC AMP1 MIC AMP2 TX PGA GAIN GAIN MODE TOTAL TX GAIN TP3 TP2 TP1 TP0 GAIN GAIN MIN TYP MAX UNIT 0 0 0 0 23.5 18 0 Extended 41.3 41.5 41.7 dB 0 0 0 1 23.5 18 –2 Extended 39.3 39.5 39.7 dB 0 0 1 0 23.5 18 –4 Extended 37.3 37.5 37.7 dB 0 0 1 1 23.5 18 –6 Extended 35.3 35.5 35.7 dB 0 1 0 0 23.5 18 –8 Extended 33.3 33.5 33.7 dB 0 1 0 1 23.5 18 –10 Extended 31.3 31.5 31.7 dB 1 0 0 0 23.5 6 0 Normal 29.3 29.5 29.7 dB 1 0 0 1 23.5 6 –2 Normal 27.3 27.5 27.7 dB 1 0 1 0 23.5 6 –4 Normal 25.3 25.5 25.7 dB 1 0 1 1 23.5 6 –6 Normal 23.3 23.5 23.7 dB 1 1 0 0 23.5 6 –8 Normal 21.3 21.5 21.7 dB 1 1 0 1 23.5 6 –10 Normal 19.3 19.5 19.7 dB POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 21 TWL1110 VOICE-BAND AUDIO PROCESSOR (VBAP) SLWS103 – NOVEMBER 2000 PRINCIPLES OF OPERATION receive operation receive channel gain control The values in the receive PGA control registers control the gain in the receive path. PGA gain is set from – 6 to 6 dB in 1-dB steps through the I2C interface. The default receive channel gain is – 4 dB. Table 3. Receive PGA Gain Control BIT NAME RELATIVE GAIN, VOICE MODE RP3 RP2 RP1 RP0 0 0 0 0 0 0 0 1 0 0 1 0 0 1 0 1 0 1 0 MIN DTMF GAIN GAIN, TONE NODE TYP MAX UNIT 5.8 6 6.2 dB 12 4.8 5 5.2 dB 12 0 3.8 4 4.2 dB 12 1 2.8 3 3.2 dB 6 0 0 1.8 2 2.2 dB 6 0 1 0.8 1 1.2 dB 6 1 1 0 – 0.2 0 0.2 dB 0 0 1 1 1 –1.2 –1 – 0.8 dB 0 1 0 0 0 – 2.2 –2 –1.8 dB 0 1 0 0 1 – 3.2 –3 – 2.8 dB –6 1 0 1 0 – 4.2 –4 – 3.8 dB –6 1 0 1 1 – 5.2 –5 – 4.8 dB –6 1 1 0 0 – 6.2 –6 – 5.8 dB –12 1 1 0 1 X dB –12 1 1 1 0 X dB –12 sidetone gain control The values in the sidetone PGA control registers control the sidetone gain. Sidetone gain is set from –12 dB to – 24 dB in 2-dB steps through the I2C interface. Sidetone can be muted by setting bit 7 of the power control register. The default sidetone gain is –12 dB. Table 4. Sidetone Gain Control BIT NAME 22 RELATIVE GAIN ST2 ST1 ST0 MIN TYP MAX UNIT 0 0 0 –12.2 –12 –11.8 dB 0 0 1 –14.2 –14 –13.8 dB 0 1 0 –16.2 –16 –15.8 dB 0 1 1 –18.2 –18 –17.8 dB 1 0 0 – 20.2 – 20 –19.8 dB 1 0 1 – 22.2 – 22 – 21.8 dB 1 1 0 – 24.2 – 24 – 23.8 dB POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 TWL1110 VOICE-BAND AUDIO PROCESSOR (VBAP) SLWS103 – NOVEMBER 2000 PRINCIPLES OF OPERATION receive operation (continued) receive volume control The values in the volume control PGA control registers provide volume control for the earphone. Volume control gain is set from 0 dB to –18 dB in 2-dB steps through the I2C interface. The default RX volume control gain is 0 dB. Table 5. RX Volume Control BIT NAME RELATIVE GAIN RV3 RV2 RV1 RV0 MIN TYP MAX 0 0 0 0 – 0.2 0 0.2 UNIT dB 0 0 0 1 – 2.2 –2 –1.8 dB 0 0 1 0 – 4.2 –4 – 3.8 dB 0 0 1 1 – 6.2 –6 – 5.8 dB 0 1 0 0 – 8.2 –8 –7.8 dB 0 1 0 1 –10.2 –10 – 9.8 dB 0 1 1 0 –12.2 –12 –11.8 dB 0 1 1 1 –14.2 –14 –13.8 dB 1 0 0 0 –16.2 –16 –15.8 dB 1 0 0 1 –18.2 –18 –17.8 dB earphone amplifier The analog signal can be routed to either of two earphone amplifiers: one with a differential output (EAR1ON and EAR1OP) capable of driving a 8-Ω load, or one with a single-ended output (EAR2O) capable of driving a 8-Ω load. earphone mute function Muting can be selected by setting bit 3 of the power control register through the I2C interface. receive PCM data format Companded mode: 8 bits are received, the most significant (MSB) first. Linear mode: 15 bits are received, MSB first. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 23 TWL1110 VOICE-BAND AUDIO PROCESSOR (VBAP) SLWS103 – NOVEMBER 2000 PRINCIPLES OF OPERATION receive operation (continued) Table 6. Receive-Data Bit Definitions BIT NO. COMPANDED MODE LINEAR MODE 1 CD7 LD14 2 CD6 LD13 3 CD5 LD12 4 CD4 LD11 5 CD3 LD10 6 CD2 LD9 7 CD1 LD8 8 CD0 LD7 9 – LD6 10 – LD5 11 – LD4 12 – LD3 13 – LD2 14 – LD1 15 – LD0 16 – –– Transmit channel gain control bits always follow the PCM data in time: CD7-CD0 = data word in companded mode LD14-LD0 = data word in linear mode DTMF generator operation and interface The DTMF circuit generates the summed DTMF tones for push button dialing and provides the PDM output for the BUZZCON user-alert tone. The integer value is determined by the formula round tone [Freq (Hz)/resolution (Hz)]. The integer value is loaded into one of two 8-bit registers, high tone register (04) or low tone register (05). The tone output is 2 dB higher when applied to the high tone register (04). When generating DTMF tones, the high frequency value must be applied to the high tone register (04) and the low DTMF value to the low tone register. The DTMF frequency resolution is controlled by the auxiliary register (06) bits 2, 3, 4, and 5. When the resolution is set to 7.8125 Hz, the frequency range can be up to 1992.2 Hz. A wider range can be accomplished (for example, 2x or 4x) by selecting lower resolutions of 15.625 Hz or 31.250 Hz. The gain setting is controlled by the RXPGA gain control. This register applies the required gain to obtain MUX control during tone mode operation. Table 3 shows the relationship of the two gain settings. 24 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 TWL1110 VOICE-BAND AUDIO PROCESSOR (VBAP) SLWS103 – NOVEMBER 2000 PRINCIPLES OF OPERATION DTMF generator operation and interface (continued) Table 7. Typical DTMF and Single Tone Control DT7 DT6 DT5 DT4 DT3 DT2 DT1 DT0 INTEGER VALUE TONE FUNCTION TONE/HZ 0 1 0 1 1 0 0 1 89 DTMF Low 697 0 1 1 0 0 0 1 1 99 DTMF Low 770 0 1 1 0 1 1 0 1 109 DTMF Low 852 0 1 1 1 1 0 0 0 120 DTMF Low 941 1 0 0 1 1 0 1 1 155 DTMF HIgh 1209 1 0 1 0 1 0 1 1 171 DTMF HIgh 1336 1 0 1 1 1 1 0 1 189 DTMF HIgh 1477 1 1 0 1 0 0 0 1 209 DTMF HIgh 1633 Tones from the DTMF generator block are present at all outputs and are controlled by enabling or disabling the individual output ports. The values that determine the tone frequency are loaded into the tone registers (high and low) as two separate values. The values loaded into the tone registers initiate an iterative table look-up function, placing a 6-bit or 7-bit in twos-complement value into the the tone registers. There is a 2-dB difference in the resulting output of the two registers, the high-tone register having the greater result. In the case of low-tone signal, the tone generator outputs a 6-bit integer with a maximum code of 31 (011111). However, the DTMF output is an 8-bit integer. Therefore, two zeros are padded to the MSB position which results in 31 (00011111). On the other hand, the receive channel requires a 15-bit integer, the input 3968 (000111110000000). Since the maximum digital value of receive channel is 16383 (011111111111111), the maximum low-tone signal is designed to be – 12.32 dB below the full digital scale. 20 log 3968 16383 2 –12.32 dB (1) In the case of high-tone signal, the tone generator outputs a 7-bit integer with a maximum code of 39 (0100111). The DTMF, therefore, pads a zero to the MSB and generates an 8-bit integer (00100111). In order to send the digital code to receive channel, it is converted to a 15-bit integer with seven more zeros padded to LSB position and biased as 4992 (001001110000000). Therefore, the maximum high-tone signal is designed to be – 10.32 dB below the full digital scale. 20 log 4992 16383 2 –10.32 dB (2) In the case of DTMF output, the tone generator outputs an 8-bit integer with the maximum code level of 70 (01000110). This output is converted to a 15-bit code with the value of 8960 (010001100000000). Therefore, the maximum output of DTMF is designed to be – 5.24 dB below the full digital scale. 20 log 8960 16383 2 –5.24 dB (3) POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 25 TWL1110 VOICE-BAND AUDIO PROCESSOR (VBAP) SLWS103 – NOVEMBER 2000 PRINCIPLES OF OPERATION buzzer logic section The single-ended output BUZZCON is a PDM signal intended to drive a buzzer through an external driver transistor. The PDM begins as a selected DTMF tone, generated and passed through the receive D/A channel and fed back to the transmit channel analog modulator, where a PDM signal is generated and routed to the BUZZCON output. DTMF Gain Mux DTMF Digital Modulator and Filter Analog Modulator Buzzer Control Buzzcon Figure 7. Buzzer Driver System Architecture support section The clock generator and control circuit use the master clock input (MCLK) to generate internal clocks to drive internal counters, filters, and convertors. Register control data is written into and read back from the VBAP registers via the control interface. I2C- bus protocols The VBAP serial interface is designed to be I2C bus-compatible and operates in the slave mode when CE is high. This interface consists of the following terminals: SCL: I2C-bus serial clock—This input synchronizes the control data transfer to and from the codec. SDA: I2C-bus serial address/data input/output—This is a bidirectional terminal that transfers register control addresses and data into and out of the codec. It is an open drain terminal and therefore requires a pullup resistor to VCC (typical 10 kΩ for 100 kHz). TWL1110 has a fixed device select address of (E2)HEX for write mode and (E3)HEX for read mode. For normal data transfer, SDA is allowed to change only when SCL is low. Changes when SCL is high are reserved for indicating the start and stop conditions. Data transfer may be initiated only when the bus is not busy. During data transfer, the data line must remain stable whenever the clock line is at high. Changes in the data line while the clock line is at high are interpreted as a start or stop condition. Table 8. I2C-Bus Conditions CONDITION STATUS DESCRIPTION A Bus not busy Both data and clock lines remain at high. B Start data transfer A high to low transition of the SDA line while the clock (SCL) is high determines a start condition. All commands must proceed from a start condition. C Stop data transfer A low to high transition of the SDA line while the clock (SCL) is high determines a stop condition. All operations must end with a stop condition. D Data valid The state of the data line represents valid data when, after a start condition, the data line is stable for the duration of the high period of the clock signal. The data on the line must be changed during the low period of the clock signal. There is one clock pulse per bit of data. 26 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 TWL1110 VOICE-BAND AUDIO PROCESSOR (VBAP) SLWS103 – NOVEMBER 2000 PRINCIPLES OF OPERATION I2C- bus protocols (continued) Each data transfer is initiated with a start condition and terminated with a stop condition. The number of data bytes, transferred between the start and stop conditions, is determined by the master device (microprocessor). When addressed, the VBAP generates an acknowledge after the reception of each byte. The master device must generate an extra clock pulse that is associated with this acknowledge bit. The VBAP must pull down the SDA line during the acknowledge clock pulse so that the SDA line is at stable low state during the high period of the acknowledge related clock pulse. Setup and hold times must be taken into account. During read operations, the master device must signal an end of data to the slave by not generating an acknowledge bit on the last byte that was clocked out of the slave. In this case, the slave (VBAP) must leave the data line high to enable the master device to generate the stop condition. clock frequencies and sample rates A fixed PCMSYN rate of 8 kHz determines the sampling rate. register map addressing BITS REG 07 06 05 04 03 02 01 00 PWRUP TXSLOPE En Power control 00 Sidetone En TXEn RX TX En MICSEL BIASEn RXEn EAROUT Sel Mode control 01 Comp Sel TMEn PCMLB Comp En BUZZEn RXFLTR En TXFLTR En TXPGA 02 X TP3 TP2 TP1 TP0 ST2 ST1 ST0 RXPGA 03 RP3 RP2 RP1 RP0 RV3 RV2 RV1 RV0 High DTMF 04 HIFREQ Sel7 HIFREQ Sel6 HIFREQ Sel5 HIFREQ Sel4 HIFREQ Sel3 HIFREQ Sel2 HIFREQ Sel1 HIFREQ Sel0 Low DTMF 05 LOFREQ Sel7 LOFREQ Sel6 LOFREQ Sel5 LOFREQ Sel4 LOFREQ Sel3 LOFREQ Sel2 LOFREQ Sel1 LOFREQ Sel0 AUX 06 MCLK Detect RXPGA2† DTMFH1 DTMFH0 DTML1 DTMFL0 AMVX MCLK sel † For voice mode only POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 27 TWL1110 VOICE-BAND AUDIO PROCESSOR (VBAP) SLWS103 – NOVEMBER 2000 PRINCIPLES OF OPERATION register power-up defaults BITS REG 07 06 05 04 03 02 01 00 Power control (1)† Power control (2)‡ 00 1 1 1 1 0 1 1 0 00 1 0 0 1 1 0 1 1 Mode control 01 0 0 0 0 0 0 1 0 TXPGA 02 0 1 0 0 0 0 0 0 RXPGA 03 1 0 1 0 0 0 0 0 High DTMF 04 0 0 0 0 0 0 0 0 Low DTMF 05 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AUX 06 † 1. Value when PWRUPSEL = 0 ‡ 2. Value when PWRUPSEL = 1 register map Table 9. Power Control Register: Address (00) HEX BIT NUMBER 28 7 6 5 4 3 2 1 0 1 1 1 1 0 1 1 0 DEFINITIONS Default setting PWRUPSEL = 0 1 0 0 1 1 0 1 1 Default setting PWRUPSEL = 1 X X X X X X X 0 Reference system, power down X X X X X X X 1 Reference system, power up X X X X X X 1 X EAR AMP1 selected, EAR AMP2 power down X X X X X X 0 X EAR AMP2 selected, EAR AMP1 power down X X X X X 0 X X Receive channel enabled X X 0 X X 1 X X Receive channel muted X X 1 X X 1 X 0 Receive channel, power down X X X X 1 X X X Micbias enable X X X X 0 X X X Micbias disable X X X 1 X X X X MIC1 selected X X X 0 X X X X MIC2 selected X 0 X X X X X X Transmit channel enabled X 1 0 X X X X X Transmit channel muted X 1 1 X X X X X Transmit channel power down 0 X X X X X X X Sidetone enabled 1 X X X X X X X Sidetone muted POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 TWL1110 VOICE-BAND AUDIO PROCESSOR (VBAP) SLWS103 – NOVEMBER 2000 PRINCIPLES OF OPERATION register map (continued) Table 10. Mode Control Register: Address (01) HEX BIT NUMBER 7 6 5 4 3 2 1 0 DEFINITIONS 0 0 0 0 0 0 1 0 Default setting X X X X X X 0 0 TX channel high-pass filter enabled and slope filter enabled X X X X X X 0 1 TX channel high-pass filter enabled and slope filter disabled X X X X X X 1 0 TX channel high-pass filter disabled and slope filter enabled X X X X X X 1 1 TX channel high-pass filter disabled and slope filter disabled X X X X X 0 X X RX channel high-pass filter disabled (low pass only) X X X X X 1 X X RX channel high-pass filter enabled X X X X 0 X X X BUZZCON disabled X X X X 1 X X X BUZZCON enabled X X X 0 X X X X Linear mode selected 1 X X 1 X X X X A-law companding mode selected 0 X X 1 X X X X µ-law companding mode selected X X 0 X X X X X TX and RX channels normal mode X X 1 X X X X X PCM loopback mode X 0 X X X X X X Tone mode disabled X 1 X X X X X X Tone mode enabled POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 29 TWL1110 VOICE-BAND AUDIO PROCESSOR (VBAP) SLWS103 – NOVEMBER 2000 PRINCIPLES OF OPERATION register map (continued) Transmit PGA and sidetone control register: Address (02)HEX Bit definitions: 7 6 5 4 3 2 1 0 DEFINITION X TP3 TP2 TP1 TP0 ST2 ST1 ST0 See Table 2 and Table 4 0 1 0 0 0 0 0 0 Default setting Receive volume control register: Address (03)HEX Bit definitions: 7 6 5 4 3 2 1 0 DEFINITION RP3 RP2 RP1 RP0 RV3 RV2 RV1 RV0 See Table 3 and Table 5 1 0 1 0 0 0 0 0 Default setting High tone selection control register: Address (04)HEX Bit definitions: 7 6 5 4 3 2 1 0 DEFINITION X X X X X X X X DTMF (see Table 7) 0 0 0 0 0 0 0 0 Default setting Low tone selection control register: Address (05)HEX Bit definitions : 7 6 5 4 3 2 1 0 DEFINITION X X X X X X X X DTMF (see Table 7) 0 0 0 0 0 0 0 0 Default setting Auxiliary register: Address (06)HEX Bit definitions: 30 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 Default DEFINITION X X X X X X X 0 MCLK is set to 2.048 MHz X X X X X X X 1 MCLK is set to 128 MHz X X X X X X 0 X Analog switch output is set to OUT2 X X X X X X 1 X Analog switch output is set to OUT1 X X X X 0 0 X X Low tone frequency resolution is set to 7.8125 Hz X X X X 0 1 X X Low tone frequency resolution is set to 15.625 Hz X X X X 1 0 X X Low tone frequency resolution is set to 31.250 Hz X X 0 0 X X X X High tone frequency resolution is set to 7.8125 Hz X X 0 1 X X X X High tone frequency resolution is set to 15.625 Hz X X 1 0 X X X X High tone frequency resolution is set to 31.250 Hz X 0 X X X X X X Receiver channel gain, RXPGA2 is equal to 0 dB, voice mode only X 1 X X X X X X Receiver channel gain, RXPGA2 is equal to 6 dB, voice mode only 0 X X X X X X X MCLK detector is powered ON 1 X X X X X X X MCLK detector is powered OFF POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 TWL1110 VOICE-BAND AUDIO PROCESSOR (VBAP) SLWS103 – NOVEMBER 2000 PRINCIPLES OF OPERATION using VBAP as a general purpose voice codec In situations when a general purpose voice codec is needed and programming features are not necessary, the receive and transmit channels can be enabled for voice mode only by setting the powerup select pin to VCC level. When set to default, the following features are activated: REF is powered up Ear Amp1 selected, Ear Amp 2 = OFF Receive channel enabled MIC bias enabled MIC 2 selected Transmit channel enabled Side tone enabled – Gain = – 12 dB TX channel high pass filter disabled TX channel slope filter enabled RX channel HP filter disabled (low pass only) Buzzcon disabled Linear mode only TX and RX channel normal mode (no loopback) Tone mode disabled (voice mode only) MIC Amp 1 gain MIC Amp 2 gain TX PGA gain Total TX gain Receive PGA Receive PGA 2 Volume Total RX gain = = = = 23.5 dB 6 dB 0 dB 29.5 dB = = = = – 4 dB 0 dB 0 dB – 4 dB Clock = 2.048 MHz POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 31 TWL1110 VOICE-BAND AUDIO PROCESSOR (VBAP) SLWS103 – NOVEMBER 2000 PRINCIPLES OF OPERATION Transmit Time Slot 0 1 2 3 4 N–2 N–1 N N+1 80% PCMCLK 80% 20% 20% tsu(PCMSYN) ÎÎ ÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎ ÎÎÎ ÎÎÎ ÎÎÎÎ th(PCMSYN) PCMSYN tpd2 See Note A 1 PCMO 2 tpd3 3 4 N–2 N–1 N See Note C tpd1 NOTES: A. B. C. D. See Note B tsu(PCMO) See Note D This window is allowed for PCMSYN high. This window is allowed for PCMSYN low (th(PCMSYN)max determined by data collision considerations). Transitions are measured at 50%. Bit 1 = MSB, Bit N = LSB Figure 8. Transmit Timing Diagram (2.048 MHz) Receive Time Slot 0 1 2 3 4 N –2 N –1 N N +1 80% 80% PCMCLK 20% 20% ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎÎ tsu(PCMSYN) PCMSYN th(PCMSYN) See Note A PCMI 1 See Note C See Note B See Note D th(PCMI) 2 3 4 N –2 N –1 N tsu(PCMI) NOTES: A. B. C. D. This window is allowed for PCMSYN high. This window is allowed for PCMSYN low. Transitions are measured at 50%. Bit 1 = MSB, Bit N = LSB Figure 9. Receive Timing Diagram (2.048 MHz) SDA t(BUF) t(Low) tr thd(STA) tf SCL STO STA thd(STA) thd(DAT) t(HIGH) tsu(STA) tsu(DAT) tsu(STO) STA Figure 10. I2C-Bus Timing Diagram 32 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 STO TWL1110 VOICE-BAND AUDIO PROCESSOR (VBAP) SLWS103 – NOVEMBER 2000 PRINCIPLES OF OPERATION PCMCLK th(PCMSYN) tsu(PCMSYN) PCMSYNC th(PCMI) PCMI MSB LSB tsu(PCMI) Figure 11. Receive Timing Diagram, 128 kHz PCMCLK th(PCMSYN) tsu(PCMSYN) PCMSYNC tv(PCMO) PCMO MSB LSB Figure 12. Transmit Timing Diagram, 128 kHz tc(PCMSYNC) Figure 13. PCMSYNC Timing, 128 kHz POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 33 TWL1110 VOICE-BAND AUDIO PROCESSOR (VBAP) SLWS103 – NOVEMBER 2000 PRINCIPLES OF OPERATION VBAP device comparisons TWL1102, 03 TWL1110 TWL1112 Single tone frequency range To 2 kHz To 8 kHz To 8 kHz Transmit channel gain range 13.5 dB to 35.5 dB 19.5 dB to 41.5 dB 19.5 dB to 41.5 dB Receive channel gain range – 24 dB to 6 dB – 24 dB to 12 dB – 24 dB to 12 dB 128 kHz or 2.048 MHz 128 kHz or 2.048 MHz PCMCLK rate 2.048 MHz Device pin out Backward compatible (TQFP) Control registers Number of registers Control interface Analog switch Backward compatible 6 I2C 7 I2C 7 DISB No Yes No Earout driving impedance 32 Ω 8-32 Ω 8-32 Ω DTMF Yes Yes Yes Tone resolution (Hz) 7.8125 7.8125 15.625 31.250 7.8125 15.625 31.250 Packages TQFP TQFP, MicroStar Junior BGA TQFP, MicroStar Junior BGA MicroStar Junior BGA is a trademark of Texas Instruments. 34 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 TWL1110 VOICE-BAND AUDIO PROCESSOR (VBAP) SLWS103 – NOVEMBER 2000 MECHANICAL DATA PBS (S-PQFP-G32) PLASTIC QUAD FLATPACK 0,23 0,17 0,50 24 0,08 M 17 25 16 32 9 0,13 NOM 1 8 3,50 TYP Gage Plane 5,05 SQ 4,95 7,10 SQ 6,90 0,25 0,10 MIN 0°–7° 0,70 0,40 1,05 0,95 Seating Plane 0,08 1,20 MAX 4087735/A 11/95 NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 35 TWL1110 VOICE-BAND AUDIO PROCESSOR (VBAP) SLWS103 – NOVEMBER 2000 MECHANICAL DATA GQE (S-PBGA-N80) PLASTIC BALL GRID ARRAY 5,20 SQ 4,80 4,00 TYP 0,50 J 0,50 H G F E D C B A 1 0,68 0,62 2 3 4 5 6 7 8 9 1,00 MAX Seating Plane 0,35 0,25 ∅ 0,05 M 0,21 0,11 0,08 4200461/B 04/00 NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. C. MicroStar Junior BGA configuration MicroStar Junior BGA is a trademark of Texas Instruments. 36 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 IMPORTANT NOTICE Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgment, including those pertaining to warranty, patent infringement, and limitation of liability. TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily performed, except those mandated by government requirements. Customers are responsible for their applications using TI components. In order to minimize risks associated with the customer’s applications, adequate design and operating safeguards must be provided by the customer to minimize inherent or procedural hazards. TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property right of TI covering or relating to any combination, machine, or process in which such semiconductor products or services might be or are used. TI’s publication of information regarding any third party’s products or services does not constitute TI’s approval, warranty or endorsement thereof. Copyright 2000, Texas Instruments Incorporated