TI TWL1101

TWL1101
VOICE-BAND AUDIO PROCESSOR (VBAP)
SLWS074A – MAY 1998 REVISED MARCH 1999
D
D
D
D
D
3-V Operation
Two Differential Microphone Inputs, One
Differential Earphone Output, and One
Single-Ended Earphone Output
Programmable Gain Amplifiers for
Transmit, Receive, Sidetone, and Volume
Control
Earphone Mute and Microphone Mute
On-chip I2C-Bus, Which Provides a Simple,
Standard, Two-Wire Serial Interface with
Digital ICs
D
D
D
D
Programmable for 13-Bit Linear Data or
8-Bit Companded (µ-Law) Data
Available in a 48-Pin TQFP Package, a
64-Pin µ*BGA Package, and a
Designed for Analog and Digital Wireless
Handsets and Telecommunications
Applications
TX Channel AGC Function Available
Through PCM Interface or I2C Bus
description
The voice-band audio processor (VBAP) is designed to perform the transmit encoding analog/digital (A/D)
conversion and receive decoding digital/analog (D/A) conversion, together with transmit and receive filtering
for voice-band communications systems.
The device operates in either the 13-bit linear or 8-bit companded µ-law mode, which is selectable through the
I2C interface.
From a 2.048-MHz master clock input, the VBAP generates its own internal clocks.
The TWL1101 device is characterized for operation from –40°C to 85°C.
This device contains circuits to protect its inputs and outputs against damage due to high static voltages or electrostatic fields. These
circuits have been qualified to protect this device against electrostatic discharges (ESD) of up to 2 kV according to MIL-STD-883C,
Method 3015; however, it is advised that precautions be taken to avoid application of any voltage higher than maximum-rated
voltages to these high-impedance circuits. During storage or handling, the device leads should be shorted together or the device
should be placed in conductive foam. In a circuit, unused inputs should always be connected to an appropriated logic voltage level,
preferably either VCC or ground. Specific guidelines for handling devices of this type are contained in the publication Guidelines for
Handling Electrostatic-Discharge-Sensitive (ESDS) Devices and Assemblies available from Texas Instruments.
VBAP is a trademark of Texas Instruments Incorporated.
Copyright  1999, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
POST OFFICE BOX 655303
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1
TWL1101
VOICE-BAND AUDIO PROCESSOR (VBAP)
SLWS074A – MAY 1998 REVISED MARCH 1999
AVSS
MBIAS
AVDD
EAR20
EARVSS
EAR1OP
EAR1ON
EARVDD
NC
NC
NC
NC
PFB PACKAGE
(TOP VIEW)
48 47 46 45 44 43 42 41 40 39 38 37
MIC1P
MIC1N
MIC2N
MIC2P
MICOUTN
MICOUTP
MICFBP
MICFBN
MICINP
MICINN
DECBG
VSS
1
36
2
35
3
34
4
33
5
32
6
31
7
30
8
29
9
28
10
27
11
26
12
25
REFVSS
REXT
NC
DECCOD
SDA
SCL
DVDD
DVSS
DVSS
PCMI
PCMO
PCMSYN
13 14 15 16 17 18 19 20 21 22 23 24
NC – No internal connection
GGV PACKAGE
(BOTTOM VIEW)
H
G
F
E
D
C
B
A
1
2
2
3
4
POST OFFICE BOX 655303
5
6
7
8
• DALLAS, TEXAS 75265
NC
MCLK
NC
NC
NC
NC
NC
PLLVSS
PLLVDD
NC
RESET
PCMCLK
TWL1101
VOICE-BAND AUDIO PROCESSOR (VBAP)
SLWS074A – MAY 1998 REVISED MARCH 1999
Microphone Amplifier
Gain = –2.62 dB to 5.38 db
1 Step
Microphone
Amplifier 2
Externally Set Gain
RESET
DVDD
DVSS
AV DD
AV SS
PLLVDD
PLLVSS
VSS
EARVDD
EARVSS
MICFBP
MICFBN
MICINP
MICINN
MICOUTN
MICOUTP
MIC2N
MIC2P
MIC1P
MIC1N
functional block diagram
Power/Reset
S1
TX Filter and PGA
Gain = –6dB to 0 dB
2 dB Steps
Analog
Modulator
Gain = 0.62 dB
PCMO
PCMSYN
Sidetone
Gain = –24 dB to –12 dB
2 dB Steps or Mute
PCM
Interface
PCMI
PCMCLK
RX Volume Control
Gain = –18 dB to 0 dB
2 dB Steps
• DALLAS, TEXAS 75265
PLL
MCLK
REFVSS
MBIAS
REXT
POST OFFICE BOX 655303
SDA
Serial Interface
I2C
REF
SCL
Low Noise
Filter
DECOD
EAR
Amplifier 2
RX Filter and PGA
Gain = –6 dB to 6 dB
1 dB Steps
DECBG
EAR1ON
EAR1OP
EAR
Amplifier 1
EAR2O
S2
Digital
Modulator
and Filter
3
TWL1101
VOICE-BAND AUDIO PROCESSOR (VBAP)
SLWS074A – MAY 1998 REVISED MARCH 1999
functional description
power-on/reset
The power for the various digital and analog circuits is separated to improve the noise performance of the
device. When digital power (DVDD) is first applied, power-on reset circuitry initializes the device and puts it into
the power-down state. An external reset must be applied to the active low RESET pin to guarantee reset upon
power on. After the initial power-on sequence the TWL1101 can be functionally powered up and down by writing
to the Power Control register through the I2C interface.
reference
A precision band gap reference voltage is generated internally and supplies all required references to operate
the transmit and receive channels. The reference system also supplies bias current for use with an electret
microphone at pin MBIAS. An external precision resistor is required for reference current setting at pin REXT.
A separate reference system ground is also provided at pin REFVSS .
low noise filter
The VBAP requires external decoupling capacitors at pins DECBG and DECOD.
I2C serial interface
The I2C bus is a simple two-wire bidirectional serial interface. It controls the VBAP by writing data to the following
five control registers: 1) power control, 2) mode control, 3) transmit PGA and sidetone control, 4) receive volume
control, 5) receive PGA gain control.
phase-locked loop
The internal digital filters and modulators require a 10.24-MHz clock that is generated by phase locking to the
2.048-MHz master clock input.
PCM interface
The PCM interface transmits and receives data at the PCMO and PCMI pins respectively. The data is
transmitted or received at the PCMCLK speed once every PCMSYN cycle. The PCMCLK may be tied directly
to the 2.048-MHz master clock (MCLK).
microphone amplifiers
The microphone input is a switchable interface for two differential microphone inputs. The first stage is a low
noise differential amplifier that provides a selectable gain of –2.62 dB or 5.38 dB, which is routed to output pins
MICOUTP and MICOUTN. The second stage amplifier gain is set externally. The first and second stages may
be tied directly together with a specified gain or an external filter may be added to enhance the transmit channel
performance.
analog modulator
The transmit channel modulator is a third-order sigma-delta design.
transmit filter and PGA
The transmit filter is a digital filter designed to meet CCITT G.714 requirements. The device operates in either
the 13-bit linear or 8-bit companded µ-law mode that is selectable through the I2C interface. The transmit PGA
defaults to 0 dB.
sidetone
A portion of the transmitted audio is attenuated and fed back to the receive channel through the sidetone path.
The sidetone path defaults to –12 dB. The sidetone path can be muted by writing to the Power Control register.
4
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• DALLAS, TEXAS 75265
TWL1101
VOICE-BAND AUDIO PROCESSOR (VBAP)
SLWS074A – MAY 1998 REVISED MARCH 1999
receive volume control
The receive volume control block acts as an attenuator with a range of –18 dB to 0 dB in two dB steps for control
of the receive channel volume. The receive volume control gain defaults to 0 dB.
receive filter and PGA
The receive filter is a digital filter that meets CCITT G.714 requirements with a high-pass filter that is selectable
through the I2C interface. The device operates in either the 13-bit linear or 8-bit µ-law companded mode, which
is selectable through the I2C interface. The gain defaults to –6 dB.
digital modulator and filter
The second-order digital modulator and filter convert the received digital PCM data to the analog output required
by the earphone interface.
earphone amplifiers
The analog signal can be routed to either one of two earphone amplifiers, one with differential output (EAR1ON
and EAR1OP) and one with single-ended output (EAR2O). Clicks and pops are suppressed for EAR1
differential output only.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
5
TWL1101
VOICE-BAND AUDIO PROCESSOR (VBAP)
SLWS074A – MAY 1998 REVISED MARCH 1999
Terminal Functions
TERMINAL
NAME
NO.
I/O
DESCRIPTION
PFB
GGV
AVDD
AVSS
46
C3
I
Analog positive power supply
48
B2
I
Analog negative power supply
DECBG
11
F2
I/O
Bypass capacitor decoupling pin – bypass with 0.1 µF capacitor
DECCOD
16
G3
I/O
Bypass capacitor decoupling pin – bypass with 0.1 µF capacitor
DVDD
19
G4
I
Digital positive power supply
DVSS
20,21
G5, H5
I
Digital negative power supply
EAR1ON
42
B5
O
Earphone 1 amplifier output (–)
EAR1OP
43
A4
O
Earphone 1 amplifier output (+)
EAR2O
45
B3
O
Earphone 2 amplifier output
EARVDD
EARVSS
41
A5
I
Analog positive power supply for the earphone amplifiers
44
A3
I
Analog negative power supply for the earphone amplifiers
MBIAS
47
A2
O
Microphone bias supply output, no decoupling capacitors
MCLK
35
C8
I
Master system clock input (2.048 MHz) (digital)
MIC1N
2
B1
I
MIC1 input (–)
MIC1P
1
A1
I
MIC1 input (+)
MIC2N
3
C2
I
MIC2 input (–)
MIC2P
4
C1
I
MIC input (+)
MICOUTN
5
D3
O
Microphone differential output to external TX high-pass filter
MICOUTP
6
D1
O
Microphone differential output to external TX high-pass filter
MICINN
10
F1
I
Microphone differential input from external TX high-pass filter
MICINP
9
E1
I
Microphone differential input from external TX high-pass filter
MICFBN
8
E2
I
Microphone differential amp feedback from external TX high-pass filter
MICFBP
7
D2
I
Microphone differential amp feedback from external TX high-pass filter
PCMI
22
H6
I
Receive PCM input
PCMO
23
G6
O
Transmit PCM output
PCMSYN
24
H7
I
PCM frame sync
PCMCLK
25
F7
I
PCM data clock
PLLVSS
PLLVDD
29
E7
I
PLL negative power supply
28
E8
I
PLL digital power supply
REFVSS
RESET
13
H1
I
Analog negative power supply for the reference system
26
F8
I
Active low reset
REXT
14
H2
I/O
SCL
18
H4
I
SDA
17
H3
I/O
I2C-bus serial address/data input/output – this is a bidirectional pin used to transfer register control
addresses and data into and out of the codec. It is an open-drain terminal and therefore requires a
pull-up resistor to VDD (typical 10 kΩ for 100 kHz)
VSS
12
G1
I
Ground return for all internal circuits. To minimize noise sources, ground connections to each device
must meet as close as possible to the VSS pin.
6
Internal 10-mA reference current setting pin – use precision 100-kΩ resistor and no filtering capacitors
I2C-bus serial clock – this input is used to synchronize the data transfer from and to the CODEC
POST OFFICE BOX 655303
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TWL1101
VOICE-BAND AUDIO PROCESSOR (VBAP)
SLWS074A – MAY 1998 REVISED MARCH 1999
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to 7.5 V
Output voltage range at DOUT,VO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to 7.5 V
Input voltage range at DIN, VI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to 7.5 V
Continuous total power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Dissipation Rating Table
Operating free air temperature range (industrial temp) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –40°C to 85°C
Storage temperature range, testing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
Lead temperature 1,6 mm from case for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
DISSIPATION RATING TABLE
PACKAGE
TA ≤25°C
POWER RATING
GGV
PFB
DERATING FACTOR
ABOVE TA = 25°C
TA = 85°C
POWER RATING
809 mW
9 mW/°C
270 mW
916 mW
6.1 mW/°C
552 mW
recommended operating conditions (see Notes 1 and 2)
MIN
Supply voltage, AVDD, DVDD, PLLVDD, EARVDD
High-level input voltage (VIH)
NOM
2.7
MAX
UNIT
3.5
V
0.7 x VDD
V
Low-level input voltage (VIL)
Load impedance between EAR1OP and EAR1ON-RL (similar for EAR20)
Operating free-air temperature, TA (Industrial temp)
0.3 x VDD
V
85
_C
Ω
32
–40
NOTES: 1. To avoid possible damage and resulting reliability problems to these CMOS devices, the power-up sequence detailed in the system
reliability features paragraph should be followed.
2. Voltages at analog inputs, outputs and VDD are with respect to VSS.
electrical characteristics over recommended ranges of supply voltage and free-air temperature
PARAMETER
TEST CONDITIONS
I(dd)
I(dd)
Supply current from VDD
Operating, EAR1 selected
Supply current from VDD
Operating, EAR2 selected
I(dd)
t(pu)
Supply current from VDD
Power down
MIN
TYP
Power-up time from power down
MAX
UNIT
11
mA
9
mA
30
µA
60
ms
digital interface
PARAMETER
TEST CONDITIONS
VOH
VOL
High-level output voltage PCMO
IOH = –3.2 mA VDD = 3 V
IOL = 3.2 mA VDD = 3 V
IIH
IIL
High-level input current, any digital input
C(i)
C(o)
Low-level output voltage PCMO
MIN
TYP
MAX
DVDD –0.2
UNIT
V
0.2
V
10
µA
10
µA
Input capacitance
10
pF
Output capacitance
20
pF
Low-level input current, any digital input
VI = 2.2V to VDD
VI = 0 to .8 V
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
7
TWL1101
VOICE-BAND AUDIO PROCESSOR (VBAP)
SLWS074A – MAY 1998 REVISED MARCH 1999
microphone interface
PARAMETER
TEST CONDITIONS
VIO
IIB
Input offset voltage at MIC1N, MIC2N
C(i)
Input capacitance at MIC1N, MIC2N
Vn
Microphone input referred noise, C-message
weighted
IO(max)
V(m)bias
VI = 0 V to 3 V
Input bias current at MIC1N, MIC2N
MIN
–200
MAX
Differential, external 18-dB gain setting,
microphone amplifier gain = 5.38 dB
mV
200
nA
1
1.88
MICMUTE
–80
Fully differential
pF
10
Microphone bias supply voltage
UNIT
5
5
Output source current – MBIAS
Input impedence
TYP
–5
µVrms
mA
2
2.12
V
dB
50
72
94
MIN
TYP
kΩ
speaker interface
PARAMETER
MAX
UNIT
Earphone AMP1 output power
VDD = 3 V, fully differential, 32-Ω load,
3-dBm0 output
TEST CONDITIONS
35
mW
Earphone AMP2 output power
VDD = 3 V, single ended, 32-Ω load,
3-dBm0 output
10
mW
VOO(1)
VOO(2)
Output offset voltage at EAR1
Fully differential
–50
50
mV
Output offset voltage at EAR2
Single ended
–30
30
mV
IO(max)
IO(max)
Maximum output current for EAR1(rms)
3-dBm0 input
33
mA
Maximum output current for EAR2 (rms)
3-dBm0 input
17.7
mA
THD
Total harmonic distortion
VDD = 3 V, 35-mW output, 32-Ω load
EARMUTE
5%
–80
dB
transmit gain and dynamic range, companded mode (µ-law) or linear mode selected, transmit
slope filter bypassed (see Notes 3 and 4)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Transmit reference-signal level (0dB)
Differential
62
Overload-signal level (3 dBm0)
Differential
248
mVrms
mVpp
Overload-signal level (3 dBm0) at the analog modulator
input (MICFBN, MICFBP)
Differential
3.66
Vpp
Absolute gain error
0 dBm0 input signal, VDD ±10%,
TA = –40°C to 85°C
–1
1
dB
Gain error with input level relative to gain at –10 dBm0
MIC1N, MIC1P to PCMO
MIC1N, MIC1P to PCMO at 3 dBm0 to
–30 dBm0
–0.5
0.5
dB
Gain error with input level relative to gain at –10 dBm0
MIC1N, MIC1P to PCMO
MIC1N, MIC1P to PCMO at –31 dBm0 to
–45 dBm0
–1
1
dB
Gain error with input level relative to gain at –10 dBm0
MIC1N, MIC1P to PCMO
MIC1N, MIC1P to PCMO at –46 dBm0 to
–55 dBm0
–1.2
1.2
dB
NOTES: 3. Unless otherwise noted, the analog input is 0 dB, 1020-Hz sine wave, where 0 dB is defined as the zero-reference point of the channel
under test.
4. The reference signal level, which is input to the transmit channel, is defined as a value 3 dB below the full-scale value of 88-mVrms.
The transmit channel gain is 24 dB (External gain is 18 dB, the default setting for the TXPGA is 0 dB and microphone amplifier is
set to 6 dB).
8
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
TWL1101
VOICE-BAND AUDIO PROCESSOR (VBAP)
SLWS074A – MAY 1998 REVISED MARCH 1999
transmit gain and dynamic range, companded mode (µ-law) or linear mode selected, transmit
slope filter enabled (see Notes 3 and 4)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
Transmit reference-signal level (0 dB)
Differential
62
Overload-signal level (3 dBm0)
Differential
248
Absolute gain error
0 dBm0 input signal, VDD ±10%, TA = –40°C to 85°C
Gain error with input level relative to gain at
–10 dBm0 MIC1N, MIC1P to PCMO
MIC1N, MIC1P to PCMO at 3 dBm0 to –30 dBm0
Gain error with input level relative to gain at
–10 dBm0 MIC1N, MIC1P to PCMO
Gain error with input level relative to gain at
–10 dBm0 MIC1N, MIC1P to PCMO
UNIT
mVrms
mVpp
–1
1
dB
–0.5
0.5
dB
MIC1N, MIC1P to PCMO at –31 dBm0 to –45 dBm0
–1
1
dB
MIC1N, MIC1P to PCMO at –46 dBm0 to –55 dBm0
–1.2
1.2
dB
NOTES: 3. Unless otherwise noted, the analog input is 0 dB, 1020-Hz sine wave, where 0 dB is defined as the zero-reference point of the
channel under test.
4. The reference signal level, which is input to the transmit channel, is defined as a value 3 dB below the full-scale value of 88 mVrms.
The transmit channel gain is 24 dB (External gain is 18 dB, the default setting for the TXPGA is 0 dB and microphone amplifier is
set to 6 dB).
transmit filter transfer, companded mode (µ-law) or linear mode selected, transmit slope filter
bypassed, external high pass filter bypassed (MCLK = 2.048 MHz)
PARAMETER
TEST CONDITIONS
Gain
G
i relative
l ti to
t input
i
t signal
i
l gain
i att 1
1.02
02 kH
kHz, iinternal
t
l hi
high-pass
h
filter disabled.
disabled
Gain relative to input signal
g
g
gain at 1.02 kHz,, internal high-pass
g
filter enabled.
MIN
TYP
MAX
UNIT
fMIC1 or fMIC2 <100 Hz
fMIC1 or fMIC2 = 200 Hz
–0.5
0.5
dB
–0.5
0.5
dB
fMIC1 or fMIC2 = 300 Hz to 3 kHz
fMIC1 or fMIC2 = 3.4 kHz
–0.5
0.5
dB
0
dB
fMIC1 or fMIC2 = 4 kHz
fMIC1 or fMIC2 = 4.6 kHz
–14
dB
–35
dB
fMIC1 or fMIC2 = 8 k Hz
fMIC1 or fMIC2 <100 Hz
–47
dB
–15
dB
fMIC1 or fMIC2 = 200 Hz
–5
dB
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
–1.5
9
TWL1101
VOICE-BAND AUDIO PROCESSOR (VBAP)
SLWS074A – MAY 1998 REVISED MARCH 1999
transmit filter transfer, companded mode (µ-law) or linear mode selected, transmit slope filter
selected (MCLK = 2.048 MHz)
PARAMETER
TEST CONDITIONS
MIN
TYP
fMIC1 or f MIC2 =100 Hz
fMIC1 or fMIC2 = 200 Hz
fMIC1 or fMIC2 = 250 Hz
fMIC1 or fMIC2 = 300 Hz
UNIT
–27
dB
–8
dB
–4
dB
–1.80
dB
fMIC1 or fMIC2 = 400 Hz
fMIC1 or fMIC2 = 500 Hz
–1.50
dB
–1.30
dB
fMIC1 or fMIC2 = 600 Hz
fMIC1 or fMIC2 = 700 Hz
–1.1
dB
–0.8
dB
fMIC1 or fMIC2 = 800 Hz
fMIC1 or fMIC2 = 900 Hz
–0.57
dB
–0.25
dB
fMIC1 or fMIC2 = 1000 Hz
fMIC1 or fMIC2 = 1000 Hz
Gain relative to input signal
g
gain
g
at 1.02 kHz,, with slope filter selected,,
external high-pass filter disabled.
MAX
0
dB
1.8
dB
fMIC1 or fMIC2 = 2000 Hz
fMIC1 or fMIC2 = 2500 Hz
4.0
dB
6.5
dB
fMIC1 or fMIC2 = 3000 Hz
fMIC1 or fMIC2 = 3100 Hz
7.6
dB
7.7
dB
8.0
dB
fMIC1 or fMIC2 = 3300 Hz
fMIC1 or fMIC2 = 3500 Hz
6.48
dB
fMIC1 or fMIC2 = 4000 Hz
fMIC1 or fMIC2 = 4500 Hz
–13
dB
–35
dB
fMIC1 or fMIC2 = 5000 Hz
fMIC1 or fMIC2 = 8000 Hz
–45
dB
–50
dB
NOTE 5: The pass-band tolerance is ± 0.25 dB from 300 Hz to 3500 Hz.
transmit idle channel noise and distortion, companded mode (µ-law) selected, slope filter
bypassed
PARAMETER
TEST CONDITIONS
MIN
TXPGA gain= 0 dB, external gain = 18 dB,
microphone amplifier gain = 5.38 dB
Transmit noise, C-message weighted
TYP
MAX
UNIT
10
µVrms
MIC1N, MIC1P to PCMO at 3 dBm0
25
dBm0
MIC1N, MIC1P to PCMO at 0 dBm0
33
dBm0
MIC1N, MIC1P to PCMO at –5 dBm0
33
dBm0
MIC1N, MIC1P to PCMO at –10 dBm0
36
dBm0
MIC1N, MIC1P to PCMO at –20 dBm0
35
dBm0
MIC1N, MIC1P to PCMO at –30 dBm0
30
dBm0
MIC1N, MIC1P to PCMO at –40 dBm0
28
dBm0
MIC1N, MIC1P to PCMO at –45 dBm0
23
dBm0
Intermodulation distortion, 2-tone CCITT method,
composite power level, –13 dBm0
CCITT G.712 (7.1), R2
49
dB
Intermodulation distortion, 2-tone CCITT method,
composite power level, –13 dBm0
CCITT G.712 (7.2), R2
51
dB
Transmit signal-to-distortion
g
ratio with 1020-Hz
sine-wave input
10
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• DALLAS, TEXAS 75265
TWL1101
VOICE-BAND AUDIO PROCESSOR (VBAP)
SLWS074A – MAY 1998 REVISED MARCH 1999
transmit idle channel noise and distortion, companded mode (µ-law) selected, slope filter enabled
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
10
µVrms
TXPGA gain = 0 dB, external gain = 18 dB,
microphone amplifier gain = 5.38 dB
Transmit noise, C-message weighted
MIC1N, MIC1P to PCMO at 3 dBm0
25
dBm0
MIC1N, MIC1P to PCMO at 0 dBm0
33
dBm0
MIC1N, MIC1P to PCMO at –5 dBm0
33
dBm0
MIC1N, MIC1P to PCMO at –10 dBm0
36
dBm0
MIC1N, MIC1P to PCMO at –20 dBm0
35
dBm0
MIC1N, MIC1P to PCMO at –30 dBm0
30
dBm0
MIC1N, MIC1P to PCMO at –40 dBm0
28
dBm0
MIC1N, MIC1P to PCMO at –45 dBm0
23
dBm0
Intermodulation distortion, 2-tone CCITT method,
composite power level, –13 dBm0
CCITT G.712 (7.1), R2
49
dB
Intermodulation distortion, 2-tone CCITT method,
composite power level, –13 dBm0
CCITT G.712 (7.2), R2
51
dB
Transmit signal-to-distortion
ratio with 1020-Hz
g
sine-wave input
transmit idle channel noise and distortion, linear mode selected, slope filter bypassed
PARAMETER
Transmit noise, C-message weighted
Transmit signal-to-distortion
g
ratio with 1020-Hz
sine-wave input
TEST CONDITIONS
MIN
TYP
TXPGA gain = 0 dB, external gain = 18 dB,
microphone amplifier gain = 5.38 dB
MAX
UNIT
10
µVrms
MIC1N, MIC1P to PCMO at 3 dBm0
26
dB
MIC1N, MIC1P to PCMO at 0 dBm0
50
dB
MIC1N, MIC1P to PCMO at –5 dBm0
50
dB
MIC1N, MIC1P to PCMO at –10 dBm0
46
dB
MIC1N, MIC1P to PCMO at –20 dBm0
45
dB
MIC1N, MIC1P to PCMO at –30 dBm0
40
dB
MIC1N, MIC1P to PCMO at –40 dBm0
30
dB
MIC1N, MIC1P to PCMO at –45 dBm0
25
dB
transmit idle channel noise and distortion, linear mode selected, slope filter enabled
PARAMETER
Transmit noise, C-message weighted
Transmit signal-to-distortion
g
ratio with 1020-Hz
sine-wave input
TEST CONDITIONS
MIN
TXPGA gain = 0 dB, external gain = 18 dB,
microphone amplifier gain = 5.38 dB
TYP
MAX
UNIT
10
µVrms
MIC1N, MIC1P to PCMO at +3 dBm0
26
dB
MIC1N, MIC1P to PCMO at 0 dBm0
50
dB
MIC1N, MIC1P to PCMO at –5 dBm0
50
dB
MIC1N, MIC1P to PCMO at –10 dBm0
46
dB
MIC1N, MIC1P to PCMO at –20 dBm0
45
dB
MIC1N, MIC1P to PCMO at –30 dBm0
40
dB
MIC1N, MIC1P to PCMO at –40 dBm0
30
dB
MIC1N, MIC1P to PCMO at –45 dBm0
25
dB
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
11
TWL1101
VOICE-BAND AUDIO PROCESSOR (VBAP)
SLWS074A – MAY 1998 REVISED MARCH 1999
receive gain and dynamic range, EAR1 selected, linear or companded (µ-law) mode selected
(see Note 6)
PARAMETER
TEST CONDITIONS
Receive reference-signal level (0dB)
MIN
TYP
0dBm0 output signal
MAX
750
UNIT
3
mVrms
Vpp
–1
1
dB
Overload-signal level (3 dB)
Absolute gain error
0 dBm0 input signal, VDD ±10%,
TA = –40°C to 85°C
Gain error with output level relative to gain at –10 dBm0
PCMIN to EAR1ON, EAR1OP at 3 dBm0 to
–40 dBm0
–0.5
0.5
dB
Gain error with output level relative to gain at –10 dBm0
PCMIN to EAR1ON, EAR1OP at –41 dBm0
to –50 dBm0
–1
1
dB
Gain error with output level relative to gain at –10 dBm0
PCMIN to EAR1ON, EAR1OP at –51 dBm0
to –55 dBm0
–1.2
1.2
dB
NOTE 6: RXPGA = 0 dB, RXVOL = 0 dB, 1020 Hz input signal at PCMI, output measured differentially between EAR1ON and EAR1OP
receive gain and dynamic range, EAR2 selected, linear or companded (µ-law) mode selected
(see Note 7)
PARAMETER
TEST CONDITIONS
Receive reference-signal level (0 dB)
MIN
TYP
0 dBm0 output signal
Overload-signal level (3 dB)
MAX
UNIT
400
mVrms
Vpp
1.6
Absolute gain error
0 dBm0 input signal, VDD ±10%,
TA = –40°C to 85°C
Gain error with output level relative to gain at –10 dBm0
PCMIN to EAR2O at 3 dBm0 to –40 dBm0
Gain error with output level relative to gain at –10 dBm0
PCMIN to EAR2O at –41 dBm0 to –50 dBm0
Gain error with output level relative to gain at –10 dBm0
PCMIN to EAR2O at –51 dBm0 to –55 dBm0
–1
1
dB
–0.5
0.5
dB
–1
1
dB
–1.2
1.2
dB
NOTE 7: RXPGA = 0 dB, RXVOL = 0 dB
receive filter transfer, companded mode (µ-law) or linear mode selected (MCLK = 2.048 MHz)
(see Note 7)
PARAMETER
TEST CONDITIONS
Gain
G
i relative
l ti tto iinputt signal
i
l gain
i att 1
1.02
02 kH
kHz, iinternal
t
l
highass filter disabled
disabled.
high-pass
Gain relative to input signal
g
gain
g
at 1.02 kHz,, internal
high-pass filter enabled.
TYP
MAX
UNIT
–0.5
0.5
dB
–0.5
0.5
dB
fEAR1 or fEAR2 = 300 Hz to 3 kHz
fEAR1 or fEAR2 = 3.4 kHz
–0.5
0.5
dB
–1.5
0
dB
fEAR1 or fEAR2 = 4 kHz
fEAR1 or fEAR2 = 4.6 kHz
–14
dB
–35
dB
fEAR1 or fEAR2 = 8 kHz
fEAR1 or fEAR2 <100 Hz
–47
dB
–15
dB
fEAR1 or fEAR2 = 200 Hz
–5
dB
NOTE 7: RXPGA = 0 dB, RXVOL = 0 dB
12
MIN
fEAR1 or fEAR2 <100 Hz
fEAR1 or fEAR2 = 200 Hz
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
TWL1101
VOICE-BAND AUDIO PROCESSOR (VBAP)
SLWS074A – MAY 1998 REVISED MARCH 1999
receive idle channel noise and distortion, EAR1 selected, companded mode (µ-law) selected
(see Note 6)
PARAMETER
TEST CONDITIONS
Receive noise, C-message weighted
MIN
TYP
Receive signal-to-distortion
g
ratio with 1020-Hz
sine-wave input
MAX
UNIT
102
PCMIN to EAR1ON, EAR1OP at 3 dBm0
23
µVrms
dB
PCMIN to EAR1ON, EAR1OP at 0 dBm0
34
dB
PCMIN to EAR1ON, EAR1OP at –5 dBm0
35
dB
PCMIN to EAR1ON, EAR1OP at –10 dBm0
36
dB
PCMIN to EAR1ON, EAR1OP at –20 dBm0
35
dB
PCMIN to EAR1ON, EAR1OP at –30 dBm0
32
dB
PCMIN to EAR1ON, EAR1OP at –40 dBm0
26
dB
PCMIN to EAR1ON, EAR1OP at –45 dBm0
24
dB
PCMIN = 11111111 (µ–law)
NOTE 6: RXPGA = 0 dB, RXVOL = 0 dB, 1020-Hz input signal at PCMI, output measured differentially between EAR1ON and EAR1OP
receive idle channel noise and distortion, EAR1 selected, linear mode selected (see Note 6)
PARAMETER
TEST CONDITIONS
Receive noise, C–message weighted
MIN
TYP
UNIT
150
PCMIN to EAR1ON, EAR1OP at 3 dBm0
26
µVrms
dB
PCMIN to EAR1ON, EAR1OP at 0 dBm0
50
dB
PCMIN to EAR1ON, EAR1OP at –5 dBm0
47
dB
PCMIN to EAR1ON, EAR1OP at –10 dBm0
46
dB
PCMIN to EAR1ON, EAR1OP at –20 dBm0
42
dB
PCMIN to EAR1ON, EAR1OP at –30 dBm0
33
dB
PCMIN to EAR1ON, EAR1OP at –40 dBm0
24
dB
PCMIN = 0000000000000
Receive signal-to-distortion
g
ratio with 1020 Hz
sine-wave input
MAX
PCMIN to EAR1ON, EAR1OP at –45 dBm0
18
dB
Intermodulation distortion, 2-tone CCITT method,
composite power level, –13 dBm0
CCITT G.712 (7.1), R2
50
dB
Intermodulation distortion, 2-tone CCITT method,
composite power level, –13 dBm0
CCITT G.712 (7.2), R2
54
dB
NOTE 6: RXPGA = 0dB, RXVOL = 0dB, 1020-Hz input signal at PCMI, output measured differentially between EAR1ON and EAR1OP
receive idle channel noise and distortion, EAR2 selected, companded mode (µ-law) selected
(see Note 7)
PARAMETER
TEST CONDITIONS
Receive noise, C-message weighted
MIN
Receive signal
signal-to-distortion
to distortion ratio with 1020
1020-Hz
Hz sine
sine-wave
wave input
TYP
MAX
UNIT
72
PCMIN to EAR2O at 3 dBm0
20
µVrms
dB
PCMIN to EAR2O at 0 dBm0
33
dB
PCMIN to EAR2O at –5 dBm0
34
dB
PCMIN to EAR2O at –10 dBm0
34
dB
PCMIN to EAR2O at –20 dBm0
33
dB
PCMIN to EAR2O at –30 dBm0
32
dB
PCMIN to EAR2O at –40 dBm0
21
dB
PCMIN to EAR2O at –45 dBm0
17
dB
PCMIN = 11111111 (µ–law)
NOTE 7: RXPGA = 0dB, RXVOL = 0dB
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
13
TWL1101
VOICE-BAND AUDIO PROCESSOR (VBAP)
SLWS074A – MAY 1998 REVISED MARCH 1999
receive idle channel noise and distortion, EAR2 selected, linear mode selected (see Note 7)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
106
PCMIN to EAR2O at 3 dBm0
24
µVrms
dB
PCMIN to EAR2O at 0 dBm0
45
dB
PCMIN to EAR2O at –5 dBm0
44
dB
PCMIN to EAR2O at –10 dBm0
42
dB
PCMIN to EAR2O at –20 dBm0
39
dB
PCMIN to EAR2O at –30 dBm0
32
dB
PCMIN to EAR2O at –40 dBm0
20
dB
PCMIN to EAR2O at –45 dBm0
16
dB
Intermodulation distortion, 2-tone CCITT method, composite power
level, –13 dBm0
CCITT G.712 (7.1), R2
50
dB
Intermodulation distortion, 2-tone CCITT method, composite power
level, –13 dBm0
CCITT G.712 (7.2), R2
54
dB
Receive noise, C-message weighted
PCMIN = 0000000000000
Receive signal
signal-to-distortion
to distortion ratio with 1020
1020-Hz
Hz sine
sine-wave
wave input
NOTE 7: RXPGA = 0 dB, RXVOL = 0 dB
power supply rejection and crosstalk attenuation
MIN
TYP
Supply voltage rejection, transmit channel
PARAMETER
MIC1N, MIC1P =0 V, VDD = 3 Vdc + 100 mVrms,
f = 0 –30 KHz
TEST CONDITIONS
–45
–50
MAX
UNIT
dB
Supply voltage rejection, receive channel
PCM code = positive zero, VDD = 3 Vdc + 100 mVrms,
f = 0 –30 KHz
–45
–50
dB
Crosstalk attentuation, transmit-to-receive
(differential)
MIC1N, MIC1P = 0 dB, f = 300 – 3400 Hz measured
differentially between EAR1ON and EAR1OP
70
dB
Crosstalk attenuation, receive-to-transmit
PCMIN = 0 dBm0, f = 300 – 3400 Hz measured at
PCMO, EAR1 amplifier unloaded
70
dB
clock timing requirements
PARAMETER
tt
fmclk
MIN
NOM
MAX
10
ns
2.048
2.5
MHz
37
%
Transition time, MCLK
MCLK frequency
MCLK jitter
tc(PCMCLK)
Number of MCLK clock cycles per PCMSYN frame
256
PCMCLK clock period
156
488
512
Duty cycle, PCMCLK
45
50
68%
UNIT
256
ns
transmit timing requirements (see Figure 6)
PARAMETER
tsu(PCMSYN)
th(PCMSYN)
MIN
Setup time, PCMSYN high before falling edge of PCMCLK
20
Hold time, PCMSYN high after falling edge of PCMCLK
20
MAX
UNIT
tc(PCMCLK)–20
tc(PCMCLK)–20
ns
ns
receive timing requirements (see Figure 7)
MIN
MAX
UNIT
tsu(PCSYN)
th(PCSYN)
Setup time, PCMSYN high before falling edge of PCMCLK
PARAMETER
20
ns
Hold time, PCMSYN high after falling edge of PCMCLK
20
tc(PCMCLK)–20
tc(PCMCLK)–20
tsu(PCMI)
th(PCMI)
Setup time, PCMI high or low before falling edge of PCMCLK
20
ns
Hold time, PCMI high or low after falling edge of PCMCLK
20
ns
14
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
ns
TWL1101
VOICE-BAND AUDIO PROCESSOR (VBAP)
SLWS074A – MAY 1998 REVISED MARCH 1999
switching characteristics
propagation delay times, CLmax = 10 pF (see Figure 6)
PARAMETER
tpd1
tpd2
From PCMCLK bit 1 high to PCMO bit 1 valid
tpd3
From PCMCLK bit n low to PCMO bit n Hi-Z
MIN
From PCMCLK high to PCMO valid, bits 2 to n
MAX
UNIT
35
ns
35
ns
30
ns
I2C bus timing requirements (see Figure 8)
PARAMETER
MIN
MAX
UNIT
400
kHz
SCL
Clock frequency
tHIGH
tLOW
Clock high time
4000
Clock low time
4700
tR
tF
SDA and SCL rise time
tHD:STA
tSU:STA
Start condition setup time
4000
ns
Start condition setup time
4700
ns
tHD:DAT
tSU:DAT
Data input hold time
tSU:STO
tBUF
SDA and SCL fall time
ns
ns
1000
ns
300
ns
0
ns
250
ns
Stop condition setup time
4000
ns
Bus free time
4700
ns
Data input setup time
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
15
TWL1101
VOICE-BAND AUDIO PROCESSOR (VBAP)
SLWS074A – MAY 1998 REVISED MARCH 1999
PARAMETER MEASUREMENT INFORMATION
SCL
SDA
A6
A5
A4
A0 R/W
0
ACK
R7
R5
R0 ACK
0
D7
D6
D5
D0
0
Slave Address
Start
R6
ACK
0
Register Address
Stop
Data
NOTE: SLAVE = VBAP
Figure 1. I2C-Bus Write to VBAP
SCL
A6
SDA
Start
A5
A0 R/W ACK
0
R7
R6
R0 ACK
A6
A0
0
R/W ACK
1
Slave Address
Register Address
D7
D6
D0 ACK
0
Slave Address
Slave Drives
The Data
Repeated
Start
NOTE: SLAVE = VBAP
Stop
Master
Drives
ACK and Stop
Figure 2. I2C Read From VBAP: Protocol A
SCL
A6 A5
SDA
A0 R/W ACK
0
Start
Slave Address
R7
R6
R0 ACK
0
A0 R/W ACK D7
A6 A5
Stop Start
Register Address
Slave Address
NOTE: SLAVE = VBAP
Figure 3. I2C Read From VBAP: Protocol B
SCL
SDA
Stop
Start
Figure 4. I2C Stop – Start Clock Timing
16
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
D0 ACK
Slave Drives
The Data
Stop
Master
Drives
ACK and Stop
TWL1101
VOICE-BAND AUDIO PROCESSOR (VBAP)
SLWS074A – MAY 1998 REVISED MARCH 1999
PRINCIPLES OF OPERATION
power-on initialization
When digital power (DVDD) is first applied, power-on reset circuitry initializes the device and puts it into the
power-down state. An external reset with a minimum pulse width of 500 ns must be applied to the active low
RESET pin to guarantee reset upon power on. Bit 0 of the power control register defaults to logic 0 upon reset
(codec, reference system, and phase-locked loop (PLL) in power-down state). Gain control registers for the
programmable gain amplifiers are initialized as indicated in the corresponding registers. The TWL1101 can be
powered up by writing a logic 1 to bit 0 of the power control register through the I2C interface. The earphone
and microphone amplifiers can be selected during the same I2C write sequence.
The desired selection for all programmable functions can be initialized prior to a power-up command using the
I2C-bus interface.
Table 1. Power-Up and Power-Down Procedures (VDD = 3 V, Earphone Amplifier Unloaded)
DEVICE STATUS
PROCEDURE
MAXIMUM POWER
CONSUMPTION
Power-up
Set bit zero = 1 in power control register, EAR1 enabled
33 mW
Power-up
Set bit zero = 1 in power control register, EAR2 enabled
27 mW
Power-down
Set bit zero = 0 in power control register
90 µW
In addition to resetting the power-down bit in the power control register, loss of MCLK (no transition detected)
automatically enters the device into power-down state with PCMO in the high impedance state. If during a pulse
code modulation (PCM) data transmit cycle an asynchronous power down occurs, the PCM interface remains
powered up until the PCM data is completely transferred.
conversion laws
The device can be programmed either for 13-bit linear or 8-bit µ-law companding mode. The µ-law companding
operation approximates the CCITT G.711 recommendation. The linear mode operation uses a 13-bit twos
complement format.
transmit operation
microphone input
The microphone input stage is a low noise differential amplifier that provides a selectable preamplifier gain of
5.38 dB or –2.62 dB. A microphone can be capacitively connected to the MIC1N and MIC1P inputs, while the
MIC2N and MIC2P inputs can be used to capacitively connect a second microphone or an auxiliary audio circuit.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
17
TWL1101
VOICE-BAND AUDIO PROCESSOR (VBAP)
SLWS074A – MAY 1998 REVISED MARCH 1999
PARAMETER MEASUREMENT INFORMATION
C3
R3
Component
C2
C1
R1
R2
R3
C1
C2
C3
Ci
R1
R2
R1
C2
R3
Typical Value
10 kW
500 kW
180 kW
0.1 µF
0.1 µF
12.3 nF
0.1 µF
C1
C3
MICOUTP
MBIAS
Microphone
MICINP
26.6 kW
MIC1N
36 kW
Ci MIC1P
36 kW
MICFBM
1 pF
_
+
_
+
+
_
+
_
Rmic
MICFBP
MICINN
1 pF
66.8 kW
Rmic
Ci
MICOUTN
66.8 kW
26.6 kW
VBAP
Figure 5. Typical Microphone Interface
microphone mute function
Transmit channel muting provides 80-dB attenuation of input microphone signal. The micmute function can be
selected by setting bit 6 of the power control register through the serial control interface.
transmit channel gain control
The MIC AMP gain is changed along with the TX PGA block gain to perform the loud talker AGC function. The
total TX channel gain can vary from 24 dB to 10 dB assuming an externally set gain of 18 dB at MIC AMP2. The
AGC function can be controlled through the PCM interface or the I2C bus. The default total TX channel gain is
24 dB.
18
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
TWL1101
VOICE-BAND AUDIO PROCESSOR (VBAP)
SLWS074A – MAY 1998 REVISED MARCH 1999
PARAMETER MEASUREMENT INFORMATION
Table 2. Transmit Gain Control
BIT NAME
MIC AMP
MIC AMP2
TX PGA
AMOD
GAIN
GAIN
GAIN
GAIN
MIN
TYP
MAX
UNIT
18
0
0.62
23.8
24
24.2
dB
18
–2
0.62
21.8
22
22.2
dB
5.38
18
–4
0.62
19.8
20
20.2
dB
1
5.38
18
–6
0.62
17.8
18
18.2
dB
0
–2.62
18
0
0.62
15.8
16
16.2
dB
0
1
–2.62
18
–2
0.62
14.8
14
14.2
dB
1
1
0
–2.62
18
–4
0.62
12.8
12
12.2
dB
1
1
1
–2.62
18
–6
0.62
9.8
10
10.2
dB
TP2
TP1
TP0
0
0
0
5.38
0
0
1
5.38
0
1
0
0
1
1
0
1
TOTAL TX GAIN
receive operation
receive channel gain control
The values in the receive PGA control registers control the gain in the receive path. PGA gain is set from
–6 dB to 6 dB in 1-dB steps through the I2C interface. The default receive channel gain is –6 dB.
Table 3. Receive PGA Gain Control
BIT NAME
RELATIVE GAIN
RP3
RP2
RP1
RP0
MIN
TYP
MAX
UNIT
0
0
0
0
5.8
6
6.2
dB
0
0
0
1
4.8
5
5.2
dB
0
0
1
0
3.8
4
4.2
dB
0
0
1
1
2.8
3
3.2
dB
0
1
0
0
1.8
2
2.2
dB
0
1
0
1
0.8
1
1.2
dB
0
1
1
0
–0.2
0
0.2
dB
0
1
1
1
–1.2
–1
–0.8
dB
1
0
0
0
–2.2
–2
–1.8
dB
1
0
0
1
–3.2
–3
–2.8
dB
1
0
1
0
–4.2
–4
–3.8
dB
1
0
1
1
–5.2
–5
–4.8
dB
1
1
0
0
–6.2
–6
–5.8
dB
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
19
TWL1101
VOICE-BAND AUDIO PROCESSOR (VBAP)
SLWS074A – MAY 1998 REVISED MARCH 1999
PARAMETER MEASUREMENT INFORMATION
sidetone gain control
The values in the sidetone PGA control registers control the sidetone gain. Sidetone gain is set from –12 dB
to –24 dB in 2-dB steps through the I2C interface. Sidetone can be muted by setting bit 7 of the power control
register. The default sidetone gain is –12 dB.
Table 4. Sidetone Gain Control
BIT NAME
RELATIVE GAIN
ST2
ST1
ST0
MIN
TYP
MAX
UNIT
0
0
0
–12.2
–12
–11.8
dB
0
0
1
–14.2
–14
–13.8
dB
0
1
0
–16.2
–16
–15.8
dB
0
1
1
–18.2
–18
–17.8
dB
1
0
0
–20.2
–20
–19.8
dB
1
0
1
–22.2
–22
–21.8
dB
1
1
0
–24.2
–24
–23.8
dB
receive volume control
The values in the volume control PGA control registers provide volume control into the earphone. Volume
control gain is set from 0 dB to –18 dB in 2-dB steps through the I2C interface. The default RX volume control
gain is 0 dB.
Table 5. rx Volume Control
BIT NAME
RELATIVE GAIN
RV3
RV2
RV1
RV0
MIN
TYP
MAX
0
0
0
0
–0.2
0
0.2
UNIT
dB
0
0
0
1
–2.2
–2
–1.8
dB
0
0
1
0
–4.2
–4
–3.8
dB
0
0
1
1
–6.2
–6
–5.8
dB
0
1
0
0
–8.2
–8
–7.8
dB
0
1
0
1
–10.2
–10
–9.8
dB
0
1
1
0
–12.2
–12
–11.8
dB
0
1
1
1
–14.2
–14
–13.8
dB
1
0
0
0
–16.2
–16
–15.8
dB
1
0
0
1
–18.2
–18
–17.8
dB
earphone amplifier
The analog signal can be routed to one of two earphone amplifiers: one with differential output (EAR1ON and
EAR1OP), or one with single-ended output (EAR2O) .
20
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TWL1101
VOICE-BAND AUDIO PROCESSOR (VBAP)
SLWS074A – MAY 1998 REVISED MARCH 1999
PARAMETER MEASUREMENT INFORMATION
VBAP
_
+
+
VMID
Generator
– EAR1ON
+
_
+
_
–
+ EAR1OP
Figure 6. Differential Earphone Amplifier Configuration
earphone mute function
Muting can be selected by setting bit 3 of the power control register through the serial control interface.
receive PCM data format
1. Companded mode:
a. Transmit channel gain control through I2C: 8 bits are received, the most significant (MSB) first.
b. Transmit channel gain control through PCM interface: 11 bits are received, first eight bits are
companded data, next three bits are transmit channel gain control bits.
2. Linear mode:
a. Transmit channel gain control through I2C: 13 bits are received, MSB first.
b. Transmit channel gain control through PCM interface: 16 bits are received, first 13 bits are linear data,
next three bits are transmit channel gain control bits.
POST OFFICE BOX 655303
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21
TWL1101
VOICE-BAND AUDIO PROCESSOR (VBAP)
SLWS074A – MAY 1998 REVISED MARCH 1999
PARAMETER MEASUREMENT INFORMATION
Table 6. Receive-Data Bit Definitions
BIT NO.
COMPANDED
MODE
COMPANDED MODE WITH
TX GAIN CONTROL
LINEAR
MODE
LINEAR MODE WITH
TX GAIN CONTROL
1
CD7
CD7
LD12
LD12
2
CD6
CD6
LD11
LD11
3
CD5
CD5
LD10
LD10
4
CD4
CD4
LD9
LD9
5
CD3
CD3
LD8
LD8
6
CD2
CD2
LD7
LD7
7
CD1
CD1
LD6
LD6
8
CD0
CD0
LD5
LD5
9
–
TP2
LD4
LD4
10
–
TP1
LD3
LD3
11
–
TP0
LD2
LD2
12
–
–
LD1
LD1
13
–
–
LD0
LD0
14
–
–
–
TP2
15
–
–
––
TP1
16
–
–
––
TP0
Transmit channel gain control bits always follow the PCM data in time:
CD7–CD0 = Data word in companded mode
LD12–LD0 = Data word in linear mode
TP2, TP1, TP0 : TXPGA gain control ( see Table 2 )
support section
The clock generator and control circuit use the MCLK input to generate internal clocks that drive internal
counters, filters, and converters. Register control information is written into and read back from the VBAP
registers through the I2C–bus serial control interface.
22
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TWL1101
VOICE-BAND AUDIO PROCESSOR (VBAP)
SLWS074A – MAY 1998 REVISED MARCH 1999
PARAMETER MEASUREMENT INFORMATION
I2C–bus protocol
The VBAP serial interface is designed to be I2C-bus compatible. This interface consists of the following
terminals:
SCL: I2C-bus serial clock – This input synchronizes the data transfer from and to the codec.
SDA: I2C-bus serial address/data input/output – This is a bidirectional pin that transfers register control
addresses and data into and out of the codec. It is an open drain terminal and therefore requires a
pullup resistor to VCC (typical 10 kΩ for 100 KHz).
TWL1101 has a fixed device select address of {E2}HEX for write mode and {E3}HEX for read mode.
For normal data transfer, SDA is allowed to change only when SCL is low. Changes when SCL is high are
reserved for indicating the start and stop conditions.
Data transfer may be initiated only when the bus is not busy. During data transfer, the data line must remain
stable whenever the clock line is at high. Changes in the data line while the clock line is at high are interpreted
as a start or stop condition.
Table 7. I2C-Bus Conditions
CONDITION
STATUS
DESCRIPTION
A
Bus not busy
Both data and clock lines remain at high
B
Start data transfer
A high to low transition of the SDA line while the clock (SCL) is high determines a start condition.
All commands must proceed from a start condition.
C
Stop data transfer
A low to high transition of the SDA line while the clock (SCL) is high determines a stop condition.
All operations must end with a stop condition.
D
Data valid
The state of the data line represents valid data when, after a start condition, the data line is stable
for the duration of the high period of the clock signal.
The data on the line must be changed during the low period of the clock signal. There is one clock pulse per
bit data.
Each data transfer is initiated with a start condition and terminated with a stop condition. No consecutive stop
and start conditions are allowed in a single clock high period (see Figure 4). The number of data bytes
transferred between the start and stop conditions is determined by the master device.
When addressed, the VBAP generates an acknowledge after the reception of each byte. The master device
(microprocessor) must generate an extra clock pulse that is associated with this acknowledge bit.
The VBAP must pull down the SDA line during the acknowledge clock pulse so that the SDA line is at stable
low state during the high period of the acknowledge related clock pulse. Setup and hold times must be taken
into account. During read operations, a master must signal an end of data to the slave by not generating an
acknowledge bit on the last byte that was clocked out of the slave. In this case, the slave (VBAP) must leave
the data line high to enable the master to generate the stop condition.
current reference
An external current setting resistance of 100 kΩ ±1% must be connected from REXT to ground. No capacitance
should be connected to this pin, and stray capacitance should be minimized.
clock frequencies and sample rates
A fixed PCMSYN rate of 8 KHz determines the sampling rate.
POST OFFICE BOX 655303
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23
TWL1101
VOICE-BAND AUDIO PROCESSOR (VBAP)
SLWS074A – MAY 1998 REVISED MARCH 1999
PARAMETER MEASUREMENT INFORMATION
register map
Table 8. Power Control Register: Address {00} HEX
BIT NUMBER
7
6
5
4
3
2
1
DEFINITIONS
0
1
1
0
0
1
0
0
0
Default setting
X
X
X
X
X
X
X
0
Codec, reference system, PLL power down
X
X
X
X
X
X
X
1
Codec, reference system, PLL power up
X
X
X
X
X
0
0
X
EAR AMPS 1 and 2 power down
X
X
X
X
X
0
1
X
EAR AMP1 selected, EAR AMP2 power down
X
X
X
X
X
1
0
X
EAR AMP2 selected, EAR AMP1 power down
X
X
X
X
0
X
X
X
Receive channel enabled
X
X
X
X
1
X
X
X
Receive channel muted
X
X
0
0
X
X
X
X
MIC AMP, microphone bias amp power down
X
X
0
1
X
X
X
X
MIC1 selected
X
X
1
0
X
X
X
X
MIC2 selected
X
0
X
X
X
X
X
X
Transmit channel enabled
X
1
X
X
X
X
X
X
Transmit channel muted
0
X
X
X
X
X
X
X
Sidetone enabled
1
X
X
X
X
X
X
X
Sidetone muted
Table 9. Mode Control Register: Address {01} HEX
BIT NUMBER
7
24
6
5
4
3
2
1
DEFINITIONS
0
0
1
0
0
0
0
1
0
Default setting
X
X
X
X
X
X
0
0
TX channel high-pass filter enabled and slope filter enabled
X
X
X
X
X
X
0
1
TX channel high-pass filter enabled and slope filter disabled
X
X
X
X
X
X
1
0
TX channel high-pass filter disabled and slope filter enabled
X
X
X
X
X
X
1
1
TX channel high-pass filter disabled and slope filter disabled
X
X
X
X
X
0
X
X
RX channel high-pass filter disabled (low pass only)
X
X
X
X
X
1
X
X
X
X
X
X
0
X
X
X
RX channel high-pass filter enabled
TX channel gain control through I2C
X
X
X
X
1
X
X
X
TX channel gain control through PCMIN
X
X
X
0
X
X
X
X
Linear mode selected
X
X
X
1
X
X
X
X
µ–law companding mode selected
X
X
0
X
X
X
X
X
TX and RX channels normal mode
X
X
1
X
X
X
X
X
PCM loopback mode (TX gain control through I2C)
X
0
X
X
X
X
X
X
TX channel gain control enabled,
X
1
X
X
X
X
X
X
TX channel gain control disabled (MIC AMP gain = 6 dB and TXPGA gain = 0 dB)
POST OFFICE BOX 655303
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TWL1101
VOICE-BAND AUDIO PROCESSOR (VBAP)
SLWS074A – MAY 1998 REVISED MARCH 1999
PARAMETER MEASUREMENT INFORMATION
Transmit PGA and sidetone control register: Address {02}HEX
Bit definitions :
7
6
5
4
3
2
1
0
X
X
TP2
TP1
TP0
ST2
ST1
ST0
Receive volume control register: Address {03}HEX
Bit definitions :
7
6
5
4
3
2
1
0
X
X
X
X
RV3
RV2
RV1
RV0
Receive PGA gain control register: Address {04}HEX
Bit definitions :
7
6
5
4
3
2
1
0
X
X
X
X
RP3
RP2
RP1
RP0
Transmit Time Slot
0
2
3
N–1
N
N+1
80%
20%
ÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎ
th(PCMSYN)
tpd2
See Note A
See Note C
1
tpd1
NOTES: A.
B.
C.
D.
N–2
20%
tsu(PCMSYN)
PCMO
4
80%
PCMCLK
PCMSYN
1
2
3
See Note B
tpd2
4
See Note D
N–2
N–1
N
tsu(PCMO)
This window is allowed for PCMSYN high.
This window is allowed for PCMSYN low (th(PCMSYN)max determined by data collision considerations).
Transitions are measured at 50%.
Bit 1 = MSB, Bit N = LSB
Figure 7. Transmit Timing Diagram
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
25
TWL1101
VOICE-BAND AUDIO PROCESSOR (VBAP)
SLWS074A – MAY 1998 REVISED MARCH 1999
PARAMETER MEASUREMENT INFORMATION
Receive Time Slot
0
1
2
3
4
N–2
N–1
N
N+1
80%
PCMCLK
80%
20%
20%
ÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎ
tsu(PCMSYN)
PCMSYN
th(PCMSYN)
See Note B
See Note A
PCMI
th(PCMI)
1
See Note C
2
3
4
N–2
N–1
N
See Note D
tsu(PCMI)
A.
B.
C.
D.
This window is allowed for PCMSYN high.
This window is allowed for PCMSYN low.
Transitions are measured at 50%.
Bit 1 = MSB, Bit N = LSB
Figure 8. Receive Timing Diagram
SDA
tBUF
tLOW
tf
tr
thd(STA)
SCL
thd(STA)
tHIGH
thd(DAT)
STO
tsu(STA)
tsu(STO)
tsu(DAT)
STA
STA
Figure 9. I2C-Bus Timing Diagram
26
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
STO
TWL1101
VOICE-BAND AUDIO PROCESSOR (VBAP)
SLWS074A – MAY 1998 REVISED MARCH 1999
APPLICATION INFORMATION
C5
R9
C7
180 kΩ
0.1 µF
0.1 µF
C8
0.12 µF
R6
R10
10 kΩ
R7
510 kΩ
10 kΩ
C6
R9
C9
0.1 µF
180 kΩ
0.1 µF
C10
MICFBP
MICFBN
EARVSS
MIC1P
EAR1OP
EAR1ON
MIC1N
EAR20
3
0.1 µF
C4
4 MIC2P
R3
2 kΩ
MICINP
MBIAS
0.1 µF
C3
0.1 µF
R2
2 kΩ
2
8
26
17
18
35
23
22
24
25
U1
TWL1101
MIC2N
RESET
SDA
SCL
MCLK
PCMO
PCMI
PCMSYN
PCMCLK
PLLVDD
PLLVSS
DVDD
AVDD
EARVDD
REXT
DECCOD
14
R5
100 k Ω
0.1%
C11
0.1 µF
DECBG
16
11
44
43
42
45
28
29
19
46
41
DVSS
AVSS
0.1 µF
C2
1
7
VSS
REFVSS
DVSS
C1
47
10
MICINN
R4
2 kΩ
MICOUTP
R1
2 kΩ
0.12 µF
9
5
MICOUTN
6
12 13 20 21 48
C12
0.1 µF
NOTE: Pin numbers represent the 48-pin QFP package.
Figure 10. TWL1101 EVM Schematic with Filter and Mic Interface Components
POST OFFICE BOX 655303
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27
TWL1101
VOICE-BAND AUDIO PROCESSOR (VBAP)
SLWS074A – MAY 1998 REVISED MARCH 1999
PCM Interface
VDD
RESET
EAR1
Differential Out
EAR2 S–E Out
1 RESET
2
PLLVDD
3
PLLVSS
4
NC
5
EAR1ON
6
EAR1OP
7
EARVDD
8
NC
9
EAR20
10
MIC1P
11 MIC1N
12
AVSS
MIC1
Differential In
PCMCLK
MCLK
PCMI
PCMO
24
23
2.048 MHz
22
21
20
DVSS
19
DVDD
PCMSYN 18
SDA
SCLK
MIC2P
MIC2N
AVSS
17
16
I2C Interface
15
14
13
MIC2
Differential In
Figure 11. Typical EVM Interface to Support Circuitry
28
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
TWL1101
VOICE-BAND AUDIO PROCESSOR (VBAP)
SLWS074A – MAY 1998 REVISED MARCH 1999
MECHANICAL DATA
PFB (S-PQFP-G48)
PLASTIC QUAD FLATPACK
0,27
0,17
0,50
36
0,08 M
25
37
24
48
13
0,13 NOM
1
12
5,50 TYP
7,20
SQ
6,80
9,20
SQ
8,80
Gage Plane
0,25
0,05 MIN
0°– 7°
1,05
0,95
Seating Plane
0,75
0,45
0,08
1,20 MAX
4073176 / B 10/96
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Falls within JEDEC MS–026
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
29
TWL1101
VOICE-BAND AUDIO PROCESSOR (VBAP)
SLWS074A – MAY 1998 REVISED MARCH 1999
GGV (S-PBGA-N64)
PLASTIC BALL GRID ARRAY
5,60 TYP
8,10
SQ
7,90
0,40
0,80
0,80
H
G
F
E
D
C
0,40
B
A
1
0,95
0,85
2
3
4
5
6
7
8
1,40 MAX
Seating Plane
0,12
0,08
0,55
0,45
0,08 M
0,45
0,35
0,10
4073224/B 11/97
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. MicroStar BGA configuration
30
POST OFFICE BOX 655303
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