TI TLC6C598QPWRQ1

TLC6C598-Q1
www.ti.com
SLIS142B – DECEMBER 2012 – REVISED MARCH 2013
Power Logic 8-BIT SHIFT REGISTER LED DRIVER
Check for Samples: TLC6C598-Q1
FEATURES
1
•
•
•
•
•
•
•
•
•
•
•
•
Qualified for Automotive Applications
AEC-Q100 Qualified With the Following
Results:
– Device Temperature Grade 1: –40°C to
125°C Ambient Operating Temperature
Range
– Device HBM ESD Classification Level H2
– Device CDM ESD Classification Level C3B
Wide Vcc From 3 V to 5.5 V
Output Maximum Rating of.40 V
Eight Power DMOS Transistor Outputs of 50mA Continuous Current With Vcc = 5 V
Thermal Shutdown Protection
Enhanced Cascading for Multiple Stages
All Registers Cleared With Single Input
Low Power Consumption
Slow Switching Time (tr and tf), Which Helps
Significantly With Reducing EMI
16-Pin TSSOP-PW Package
16-Pin SOIC-D Package
APPLICATIONS
•
•
•
Instrumentation Cluster
Tell-Tale Lamps
LED Illumination and Control
DESCRIPTION
The TLC6C598-Q1 is a monolithic, medium-voltage,
low-current power 8-bit shift register designed for use
in systems that require relatively moderate load
power, such as LEDs.
This device contains an 8-bit serial-in, parallel-out
shift register that feeds an 8-bit D-type storage
register. Data transfers through both the shift and
storage registers on the rising edge of the shiftregister clock (SRCK) and the register clock (RCK),
respectively. The storage register transfers data to
the output buffer when shift register clear (CLR) is
high. A low on CLR clears all registers in the device.
Holding the output enable (G) high, holds all data in
the output buffers low, and all drain outputs are off.
Holding G low makes data from the storage register
transparent to the output buffers. When data in the
output buffers is low, the DMOS transistor outputs are
off. When data is high, the DMOS transistor outputs
have sink-current capability. The serial output (SER
OUT) clocks out of the device on the falling edge of
SRCK to provide additional hold time for cascaded
applications. This provides improved performance for
applications where clock signals may be skewed,
devices are not located near one another, or the
system must tolerate electromagnetic interference.
The device contains built-in thermal shutdown
protection.
Outputs are low-side, open-drain DMOS transistors
with output ratings of 40 V and 50 mA continuous
sink-current capabilities when Vcc = 5 V. The current
limit decreases as the junction temperature increases
for additional device protection. The device also
provides up to 2000 V of ESD protection when tested
using the human-body model and 200 V when using
the machine model.
The TLC6C598-Q1 characterization is for for
operation over the operating ambient temperature
range of −40°C to 125°C.
APPLICATION SCHEMATIC
Battery 9 V–40 V
30 mA
4/3
MCU Serial I/F
30 mA
8-Bit Shift Register
LED Driver
Figure 1. Typical Application Schematic
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2012–2013, Texas Instruments Incorporated
TLC6C598-Q1
SLIS142B – DECEMBER 2012 – REVISED MARCH 2013
www.ti.com
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
ORDERING INFORMATION
For the most-current package and ordering information, see the Package Option Addendum at the end of this
document, or see the TI Web site at www.ti.com.
Logic Diagram (Positive Logic)
G
RCK
DRAIN0
CLR
D
SRCK
D
C1
CLR
C1
CLR
DRAIN1
SER IN
D
D
C1
CLR
C1
CLR
DRAIN2
D
D
C1
CLR
C1
CLR
DRAIN3
D
D
C1
CLR
C1
CLR
DRAIN4
D
D
C1
CLR
C1
CLR
DRAIN5
D
D
C1
CLR
C1
CLR
DRAIN6
D
D
C1
CLR
C1
CLR
DRAIN7
D
D
C1
CLR
C1
CLR
GND
D
C1
SER OUT
CLR
Figure 2. Logic Diagram of TLC6C598-Q1
2
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SLIS142B – DECEMBER 2012 – REVISED MARCH 2013
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range (unless otherwise noted) (1)
VALUE
MIN
MAX
UNIT
VCC
Logic supply voltage
–0.3
8
V
VI
Logic input-voltage range
–0.3
8
V
VDS
Power DMOS drain-to-source voltage
–0.3
42
V
See Thermal Information
table
Continuous total dissipation
ESD (2)
Electrostatic discharge HBM
TA
Operating ambient temperature
Tstg
Storage temperature range
TJ
Operating junction temperature range
(1)
(2)
2
kV
–40
125
°C
–55
165
°C
–40
150
°C
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
The human-body model is a 100-pF capacitor discharged through a 1.5-kΩ resistor into each pin.
THERMAL INFORMATION
THERMAL METRIC (1)
TLC6C598-Q1
PW (16 PINS)
D (16 PINS)
UNIT
θJA
Junction-to-ambient thermal resistance
129.4
100
°C/W
θJCtop
Junction-to-case (top) thermal resistance
55.4
45
°C/W
θJB
Junction-to-board thermal resistance
65.8
40
°C/W
ψJT
Junction-to-top characterization parameter
9.9
10
°C/W
ψJB
Junction-to-board characterization parameter
65.2
40
°C/W
θJCbot
Junction-to-case (bottom) thermal resistance
NA
NA
°C/W
(1)
For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
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SLIS142B – DECEMBER 2012 – REVISED MARCH 2013
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RECOMMENDED OPERATING CONDITIONS
MIN MAX
3
UNIT
VCC
Supply voltage
5.5
VIH
High-level input voltage
V
VIL
Low-level input voltage
tsu
Setup time, SER IN high before SRCK↑
15
ns
th
Hold time, SER IN high after SRCK↑
15
ns
tw
Pulse duration
40
ns
TA
Operating ambient temperature
2.4
V
0.7
–40
V
125
°C
ELECTRICAL CHARACTERISTICS
VCC = 5 V, TC = 25°C (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
DRAIN0 to DRAIN7. Drain-tosource voltage
40
VOH
High-level output voltage, SER
OUT
IOH = –20 μA
VOL
Low-level output voltage, SER
OUT
IOH = 20 μA
IIH
High-level input current
VCC = 5 V, VI = VCC
IIL
Low-level input current
VCC = 5 V, VI = 0
IOH = −4 mA
IOH = 4 mA
VCC = 5 V
VCC = 5 V
Hysteresis
4
μA
0.3
6
7.41
8.6
ID = 20 mA, VCC = 5 V, TA = 25°C,
All channels ON
6.7
8.3
9.6
ID = 20 mA, VCC = 3.3 V, TA = 25°C,
Single channel ON
7.9
9.34
11.2
ID = 20 mA, VCC = 3.3 V, TA = 25°C,
All channels ON
8.7
10.25
12.3
ID = 20 mA, VCC = 5 V, TA = 125°C,
Single channel ON
9.1
11.13
12.9
ID = 20 mA, VCC = 5 V, TA = 125°C,
All channels ON
10.3
12.28
14.5
ID = 20 mA, VCC = 3.3 V, TA = 125°C,
Single channel ON
11.6
13.69
16.4
ID = 20 mA, VCC = 3.3 V, TA = 125°C,
All channels ON
12.8
14.89
18.2
150
175
200
μA
Ω
15
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μA
0.1
0.15
ID = 20 mA, VCC = 5 V, TA = 25°C,
Single channel ON
V
μA
200
VDS = 30 V, TC = 125°C
V
μA
160
VCC = 5 V
Thys
0.4
88
All outputs on
Thermal shutdown trip point
0.01
0.25
All outputs on
VDS = 30 V
TSHUTDOWN
0.001
1
fSRCK = 5 MHz, CL = 30 pF
rDS(on)
V
0.1
Logic supply current at frequency
Static drain-source on-state
resistance
V
4.69
–0.2
ICC(FRQ)
Off-state drain current
4.99
All outputs off
VCC = 5 V, no clock signal
V
4.5
0.2
Logic supply current
UNIT
4.9
VCC = 5 V
ICC
IDSX
MAX
ºC
ºC
Copyright © 2012–2013, Texas Instruments Incorporated
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SLIS142B – DECEMBER 2012 – REVISED MARCH 2013
SWITCHING CHARACTERISTICS
VCC = 5 V, TJ = 25°C
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
tPLH
Propagation delay time, low-to-high-level output from G
220
ns
tPHL
Propagation delay time, high-to-low-level output from G
75
ns
tr
Rise time, drain output
210
ns
tf
Fall time, drain output
128
ns
tpd
Propagation delay time, SRCK↓ to SEROUT
CL = 30 pF, ID = 48 mA
49.4
ns
tor
SEROUT rise time (10% to 90%)
CL = 30 pF
20
ns
tof
SEROUT fall time (90% to 10%)
CL = 30 pF
20
ns
f(SRCK)
Serial clock frequency
CL = 30 pF, ID = 20 mA
tSRCK_WH
SRCK pulse duration, high
30
ns
tSRCK_WL
SRCK pulse duration, low
30
ns
CL = 30 pF, ID = 48 mA; see
10
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MHz
5
TLC6C598-Q1
SLIS142B – DECEMBER 2012 – REVISED MARCH 2013
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DEVICE INFORMATION
PIN CONFIGURATIONS
TLC6C598-Q1
D Package
(Top View)
TLC6C598-Q1
PW Package
(Top View)
VCC
1
16
GND
SER IN
2
15
SRCK
DRAIN0
3
14
DRAIN7
DRAIN1
4
13
DRAIN6
DRAIN2
5
12
DRAIN5
DRAIN3
6
11
DRAIN4
CLR
7
10
RCK
G
8
9
VCC
1
16
GND
SER IN
2
15
SRCK
DRAIN0
3
14
DRAIN7
DRAIN1
4
13
DRAIN6
DRAIN2
5
12
DRAIN5
DRAIN3
6
11
DRAIN4
CLR
7
10
RCK
G
8
9
SER OUT
Figure 3. PW-Package Pin Configuration of
TLC6C598-Q1
SER OUT
Figure 4. D-Package Pin Configuration of
TLC6C598-Q1
PIN FUNCTIONS
NO.
I/O
CLR
NAME
7
I
Shift register clear, active-low
DESCRIPTION
DRAIN0
3
O
Open-drain output
DRAIN1
4
O
Open-drain output
DRAIN2
5
O
Open-drain output
DRAIN3
6
O
Open-drain output
DRAIN4
11
O
Open-drain output
DRAIN5
12
O
Open-drain output
DRAIN6
13
O
Open-drain output
DRAIN7
14
O
Open-drain output
Output enable, active-low
G
8
I
GND
16
—
Power ground
RCK
10
I
Register clock
SER IN
2
I
Serial data input
SER OUT
9
O
Serial data output
SRCK
15
I
Shift register clock
VCC
1
I
Power supply
PIN DESCRIPTIONS
CLR is the signal used to clear all the registers. The storage register transfers data to the output buffer when
shift register clear (CLR) is high. Driving CLR low clears all the registers in the device.
DRAIN0–DRAIN7 are the LED current-sink channels. These pins connect to LED cathodes, and can survive up
to 40-V LED supply voltage. This is quite helpful during automotive load-dump conditions.
6
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G is the LED-channel enable and disable input pin. Having G low enables all drain channels according to the
output-latch register content. When high, all channels are off.
GND is the ground reference pin for the device. This pin must connect to the ground plane on the PCB.
RCK is the storage-register clock. The data in each shift register stage transfers to the storage register at the
rising edge of RCK. Data in the storage register appears at the output whenever the output enable (G) input
signal is high.
SER IN is the serial data input. Data on SER IN loads into the internal register on each rising edge of SRCK.
SER OUT is the serial data output of the 8-bit serial shift register. The purpose of this pin is to cascade several
devices on the serial bus. By connecting the SER OUT pin to the SER IN input of the next device on the serial
bus to cascade, the data transfers to the next device on the falling edge of SRCK. This can improve the cascade
application reliability, as it can avoid the issue that the second device receives SRCK and data input at the same
rising edge of SRCK.
SRCK is the serial clock input. On each rising SRCK edge, data transfers from SER IN to the internal serial shift
registers.
VCC is the power-supply pin voltage for the device. TI recommends adding a 0.1-μF ceramic capacitor close to
the pin.
THERMAL SHUTDOWN
The device implements an internal thermal shutdown to protect itself if the junction temperature exceeds 175°C
(typical). The thermal shutdown forces the device to have an open state when the junction temperature exceeds
the thermal trip threshold. Once the junction temperature decreases below 160°C (typical), the device begins to
operate again.
SPACER
SPACER
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APPLICATION INFORMATION
Figure 5 shows a typical cascade application circuit with two TLC6C598-Q1 chips configured to cascade
topology. The MCU generates all the input signals.
Battery 9 V–40 V
3 V–5.5 V
DRAIN0
DRAIN6
DRAIN1
DRAIN7
VCC
GND
SER IN
SRCK
MCU
G
SER OUT
CLR
RCK
DRAIN0
DRAIN6
DRAIN1
DRAIN7
VCC
SER IN
GND
SRCK
G
SER OUT
CLR
RCK
Figure 5. Typical Application Circuit
PARAMETER MEASUREMENT INFORMATION
Figure 6 and Figure 7 show the resistive-load test circuit and voltage waveforms. One can see from Figure 7 that
with G held low and CLR held high, the status of each drain changes on the rising edge of the register clock,
indicating the transfer of data to the output buffers at that time.
8
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PARAMETER MEASUREMENT INFORMATION (continued)
5V
10 V
VCC
CLR
ID
RL = 200 W
SRCK
Output
MCU
DRAIN
SER IN
CL = 30 pF
(see Note A)
RCK
G
GND
A.
CL includes probe and jig capacitance.
Figure 6. Resistive-Load Test Circuit
8
7
6
5
4
3
2
1
SRCK
SER IN
G
RCK
0
CLR
1
DRAIN0
0
DRAIN1
0
DRAIN6
0
DRAIN7
0
Figure 7. Voltage Waveforms
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PARAMETER MEASUREMENT INFORMATION (continued)
Timing Waveform
Figure 8 shows the SER IN to SER OUT waveform. The output signal appears on the falling edge of the shift
register clock (SRCK) because there is a phase inverter at SER OUT (see Figure 2). As a result, it takes seven
and a half periods of SRCK for data to transfer from SER IN to SER OUT.
8
7
5
6
3
4
2
1
SRCK
SER IN
CLR
1
SER OUT
0
Figure 8. SER IN to SER OUT Waveform
Figure 9 shows the switching times and voltage waveforms. Tests for all these parameters took place using the
test circuit shown in Figure 6.
5V
G
50%
50%
0V
tPHL
tPLH
90%
Output
10 V
90%
10%
10%
0.5 V
tf
tr
5V
SRCK
50%
0V
tsu
th
5V
SER IN
50%
50%
0V
tw
Switching Times, Input Setup and Hold Waveforms
SRCK
50%
50%
tpd
tpd
50%
SER OUT
50%
SER OUT Propagation Delay Waveform
Figure 9. Switching Times and Voltage Waveforms
10
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TYPICAL CHARACTERISTICS
SUPPLY CURRENT
vs
FREQUENCY
500
SUPPLY CURRENT
vs
SUPPLY VOLTAGE
350
T A = ±40ƒC
T A = 25ƒC
T A = 125ƒC
Supply Current ( A)
Supply Current ( A)
400
All Channels Off
All Channels On
300
300
200
250
200
150
100
100
50
VCC = 5V
0
0
0.1
1
10
100
Frequency (MHz)
3.0
3.5
4.0
4.5
5.0
5.5
Supply Voltage (V)
C001
Figure 10.
6.0
C002
Figure 11.
Conditions for Figure 12 and Figure 13: Single channel on
DRAIN-TO-SOURCE ON-STATE RESISTANCE
vs
DRAIN CURRENT
DRAIN-TO-SOURCE ON-STATE RESISTANCE
vs
DRAIN CURRENT
16
Drain-Source On-State Resistance (Ÿ
Drain-Source On-State Resistance (Ÿ
12
10
8
6
4
TA = ±40ƒC
2
TA = 25ƒC
VCC = 5V
TA = 125ƒC
0
0
10
14
12
10
8
6
4
TA = ±40ƒC
TA = 25ƒC
2
20
30
40
50
Drain Current (mA)
60
VCC = 3.3V
TA = 125ƒC
0
0
10
20
30
40
50
Drain Current (mA)
C003
Figure 12.
60
C004
Figure 13.
TYPICAL CHARACTERISTICS
Conditions for Figure 14, Figure 15 and Figure 16: All channels on
DRAIN-TO-SOURCE ON-STATE RESISTANCE
vs
DRAIN CURRENT
DRAIN-TO-SOURCE ON-STATE RESISTANCE
vs
DRAIN CURRENT
18
Drain-Source On-State Resistance (Ÿ
Drain-Source On-State Resistance (Ÿ
14
12
10
8
6
4
TA = ±40ƒC
2
TA = 25ƒC
VCC = 5V
TA = 125ƒC
0
0
10
16
14
12
10
8
6
4
TA = ±40ƒC
2
TA = 25ƒC
20
30
40
Drain Current (mA)
50
60
VCC = 3.3V
TA = 125ƒC
0
0
C005
Figure 14.
10
20
30
40
50
Drain Current (mA)
60
C006
Figure 15.
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TYPICAL CHARACTERISTICS (continued)
Conditions for Figure 14, Figure 15 and Figure 16: All channels on
DRAIN-TO-SOURCE ON-STATE RESISTANCE
vs
DRAIN CURRENT
SWITCHING TIME
vs
AMBIENT TEMPERATURE
350
16
300
tplh
tPLH
tPHL
tphl
250
trtr
tftf
14
Switching Time (ns)
Drain-Source On-State Resistance (Ÿ
18
12
10
8
6
4
TA = ±40ƒC
2
TA = 25ƒC
2.5
3.0
3.5
150
100
50
Ids = 20mA
TA = 125ƒC
0
200
0
4.0
4.5
5.0
Supply Voltage (V)
5.5
6.0
6.5
±60
±40
C007
Figure 16.
12
±20
0
20
40
60
80
Ambient Temperature (ƒC)
100
120
140
C008
Figure 17.
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PACKAGE OPTION ADDENDUM
www.ti.com
31-May-2013
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
(2)
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
TLC6C598QDRQ1
ACTIVE
SOIC
D
16
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
-40 to 125
TLC6C598
TLC6C598QPWRQ1
ACTIVE
TSSOP
PW
16
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
-40 to 125
6C598
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
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TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
TLC6C598QDRQ1
SOIC
D
16
2500
330.0
16.4
6.5
10.3
2.1
8.0
16.0
Q1
TLC6C598QPWRQ1
TSSOP
PW
16
2000
330.0
16.4
6.95
7.1
1.6
8.0
16.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
3-Jun-2013
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
TLC6C598QDRQ1
SOIC
D
16
2500
367.0
367.0
38.0
TLC6C598QPWRQ1
TSSOP
PW
16
2000
367.0
367.0
38.0
Pack Materials-Page 2
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