TI TPS22986

TPS22986
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SLVSBS5 – JANUARY 2013
Thunderbolt™ Supply Selection IC
Check for Samples: TPS22986
FEATURES
1
•
•
•
•
•
•
•
2
2.8 V to 19.8 V Input
Auto Selects 3.3 V supply
>10mA Low Power Switch
>500mA High Power Switch
Reverse Current Blocking from OUT to VDD
Wake on UART Input Activity
UART RX and TX Buffers
APPLICATIONS
•
•
•
•
Thunderbolt™ Cables
Notebook Computers
Desktop Computers
Power Management Systems
VDD1
The TPS22986 is a supply selection device for active
Thunderbolt™ cables. The device selects a 3.3V
input from two available supplies and connects the
chosen input to two outputs, OUTA and OUTB. When
a 3.3V supply is not present, the outputs become
high impedance.
The TPS22986 has two modes of operation, Normal
and Control. In Normal Mode, OUTA is always on
when a valid supply is present. OUTB is connected to
a valid supply when the ENB input is high.
In Control Mode, OUTA behaves the same as Normal
Mode and OUTB is controlled by a combination of
monitored inputs and valid supplies on VDD1 and
VDD2. When a valid VDD is available, the device
waits for a rising input on ENB and then disconnects
OUTB until the next falling RXH transition. Once the
next falling RXH transition occurs, the device
reconnects OUTB.
VDD2
VDD2
VDD1
VDD (Internal)
RPUCFGOE
CPO
DESCRIPTION
Charge
Pump
FET1
CFG/OE
FET3
In either mode, when a valid VDD is not available, the
TPS22986 opens all switches and the outputs OUTA
and OUTB become high impedance. When the
connected VDD exceeds 3.6V, it is disconnected from
the outputs.
ENB
Logic
Core
RESETZ
FET4
The TPS22986 is available in a 1.6mm x 1.6mm
WCSP package.
FET2
RXH
TXH
Level
Shifter
RXH
Level
Shifter
TXH
RXC
TXC
GND
OUTA
OUTB
100k
Load
CDR and Microcontroller
RPDNORMAL
Figure 1. Typical Application
1
2
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Thunderbolt is a trademark of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2013, Texas Instruments Incorporated
TPS22986
SLVSBS5 – JANUARY 2013
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These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
ORDERING INFORMATION
(1)
PART NUMBER
PACKAGE MARKING (1)
PACKAGE
DEVICE SPECIFIC FEATURES
TPS22986YFP
YMDDJS
YFP
WCSP
Y=Year, M=Month, D=Sequence Code, DJ=TPS22986 Device Code, S=Wafer Fab/Assembly Site Code
Top View/Footprint
Bump View
4
3
2
1
D
D4
D3
D2
D1
D
C
C4
C3
C2
C1
B
B4
B3
B2
A
A4
A3
4
3
1
2
3
4
D
D1
D2
D3
D4
D
C
C
C1
C2
C3
C4
C
B1
B
B
B1
B2
B3
B4
B
A2
A1
A
A
A1
A2
A3
A4
A
2
1
1
2
3
4
Die Size: 1.6mm x 1.6mm
Bump Size: 0.25mm
Bump Pitch: 0.4mm
TPS22986 Pin Mapping (Top View)
4
3
2
1
D
VDD1
VDD1
VDD2
VDD2
C
OUTA
OUTB
OUTB
GND
B
RXH
TXH
RESETZ
CPO
A
RXC
TXC
ENB
CFG/OE
DISSIPATION RATINGS
(1)
(2)
2
PACKAGE
THERMAL RESISTANCE
θJA
THERMAL RESISTANCE (1)
θJB
POWER RATING
TA = 25°C
DERATING FACTOR
ABOVE (2) TA = 25°C
YFP
95°C/W
63°C/W
1050 mW
10.5 mW/°C
Simulated with high-K board
Maximum power dissipation is a function of TJ(max), θJA and TA. The maximum allowable power dissipation at any allowable ambient
temperature is PD = (TJ(max) – TA) / θJA.
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ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range (unless otherwise noted) (1) (2)
VALUE
UNIT
(3)
–0.3 to 20
V
Voltage range on OUTA, OUTB (3)
–0.3 to 4.0
V
–0.3 to VDD+0.3
V
Voltage range on CPO (3)
–0.3 to 13
V
Voltage range on RXH, TXC (3)
–0.3 to 4.0
V
Operating ambient temperature range
–40 to 85
°C
125
°C
–65 to 150
°C
500
V
2
kV
4.4
kV
Voltage range on VDD1, VDD2
Voltage range on RXC, TXH, RESETZ, CFG/OE, ENB
(VDD is the active valid 3.3V input at VDD1 or VDD2)
VI
TA
TJ
(MAX)
Tstg
(3) (4)
Maximum operating junction temperature
Storage temperature range
Charge Device Model (JESD 22 C101)
Human Body Model (JESD 22 A114)
Contact discharge on VDD1, VDD2 (IEC 61000-4-2) (5)
(1)
(2)
(3)
(4)
(5)
Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute–maximum–rated conditions for extended periods may affect device reliability.
In applications where high power dissipation and/or poor package thermal resistance is present, the maximum ambient temperature may
have to be derated. Maximum ambient temperature [TA(max)] is dependent on the maximum operating junction temperature [TJ(max)], the
maximum power dissipation of the device in the application [PD(max)], and the junction-to-ambient thermal resistance of the part/package
in the application (θJA), as given by the following equation: TA(max) = TJ(max) – (θJA × PD(max)).
All voltage values are with respect to network ground terminal.
All inputs must be connected to a supply that is less than the max of VDD1 and VDD2
IEC tests are run with 0.1µF on VDD1 and VDD2. IEC rating is non-destructive.
RECOMMENDED OPERATING CONDITIONS
over operating free-air temperature range (unless otherwise noted)
VDD1
VDD2
Supply voltage range
MIN
MAX
UNIT
2.8
19.8
V
2.8
19.8
V
ILIM1/2
FET1 and FET2 Switch current range
10
mA
ILIM3/4
FET3 and FET4 Switch current range
500
mA
VIH
Input logic high
RXH, TXC, CFG/OE, ENB
VIL
Input logic low
RXH, TXC, CFG/OE, ENB
VOH
Output logic high
RXC, TXH, RESETZ
VOL
Output logic low
RXC, TXH, RESETZ
2
V
0.8
2.25
V
V
0.4
V
Output capacitance on OUTA
1
4
Output capacitance on OUTB
4
22
CCPO
Output capacitance on CPO
2
10
nF
TA
Operating temperature range
–40
85
°C
COUT
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ELECTRICAL CHARACTERISTICS
Unless otherwise noted the specification applies over the VDD range and operating junction temp –40°C ≤ TJ ≤ 85°C. Typical
values are for VDD = 3.3V and TJ = 25°C.
PARAMETER
TEST CONDITIONS
MIN
TYP MAX
UNIT
POWER SUPPLIES AND CURRENTS
VDD1/2
Input voltage range
2.8
19.8
VDD1 > VDD2
250
VDD1 < VDD2
20
VDD2 > VDD1
250
VDD2 < VDD1
20
500
V
IDD-1
VDD1 Quiescent current
VDD1 = 2.8 to 15V
IDD-2
VDD2 Quiescent current
VDD2 = 2.8 to 15V
IIN-ENB
ENB Input current
VIN = 1.8V to 3.6V
1
µA
IIN-UART
RXH and TXC input current
VIN = 1.8V to 3.6V
6
µA
IIN-CFGOE
CFG/OE Input current after mode selection
VIN = 1.8V to 3.6V
IIN-RESETZ
RESETZ Input current
VRESETZ = 100 mV
0.8
2
500
µA
µA
3
µA
3
mA
SWITCH AND RESISTANCE CHARACTERISTICS
RF1/2
FET1/2 On resistance
VDD = 3.3V, IOUT = 10mA
RF3/4
FET3/4 On resistance
VDD = 3.3V, IOUT = 350mA
RESETZ Pull-down resistance
RESETZ asserted
RPDRESETZ
RPUCFGOE
(1)
RPDUART
3
175
33
50
100
Ω
15
20
25
kΩ
See the UART RX and TX Section
0.6
1
1.75
MΩ
35
50
CFG/OE Pull-up resistance
TXC and RXH
Ω
1
120
mΩ
Pull-down resistance
RPDNORMAL
Series CFG/OE Resistance to enter normal mode
See Mode Selection Section
RPDCONTROL
CFG/OE Resistance to GND to enter control mode
See Mode Selection Section
kΩ
10
12
kΩ
3.55
3.6
V
mV
VOLTAGE THESHOLDS AND AMPLITUDES
VHVLO
High voltage lockout
3.3V Supply Rising
3.5
20
40
60
3.3V Supply Rising
2.7
2.75
2.8
3.3V Supply Falling
2.4
2.45
2.5
8
9
11
V
Hysteresis
VUVLO
Under voltage lockout
V
VCPO
Charge pump voltage
CCPO = 2nF, ICPO = 0mA
VOS
Voltage overshoot on OUTA/B
COUTB = 4µF, IOUTB = 0mA,
COUTA = 1µF, IOUTA = 0mA,
VDD1 SR3.3→4V = 10mV/µs
200
mV
200
µs
TRANSITION TIMING
td
UVLO To FETn open time
COUTB = 4µF
te
UVLO To FETn closed time
COUTA = 1µF
tdh
HVLO To FETn open time
teh
HVLO To FETn closed time
2
ms
20
µs
ms
See The Supply Switch-Over During
HVLO Section
TRANSITION TIMING (NORMAL MODE)
teb
ENB To FET3/4 closed time
COUTB = 4µF
2
tdb
ENB To FET3/4 open time
COUTA = 1µF
200
µs
tE2R
ENB to RESETZ time
6
ms
(1)
4
CFG/OE is pulled to the internal VDD (VDD1 or VDD2) through the resistance RPUCFGOE only during mode selection at power-up.
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ELECTRICAL CHARACTERISTICS (continued)
Unless otherwise noted the specification applies over the VDD range and operating junction temp –40°C ≤ TJ ≤ 85°C. Typical
values are for VDD = 3.3V and TJ = 25°C.
PARAMETER
TEST CONDITIONS
MIN
TYP MAX
UNIT
TRANSITION TIMING (CONTROL MODE)
tU2R
UVLO to RESETZ time
tE2R
ENB to RESETZ time
5
6
7
ms
2
10
tE2O
ENB to FET3/4 open time
µs
COUTB = 4µF, COUTA = 1µF
100
200
tRX2O
RX to FET3/4 closed time
µs
COUTB = 4µF, COUTA = 1µF
0.8
2
ms
tRX2R
RX to RESETZ time
tOE2TX
OE to TXH valid time
RTXH = 100kΩ to GND
7
ms
20
tOE2TXZ
OE to TXH Hi-Z time
RTXH = 100kΩ to GND
20
µs
µs
5
6
TXC / TXH / RXC / RXH I/O
VIH
TXC, RXH Input logic high
VIL
TXC, RXH Input logic low
2
VOH
TXH, RXC Output logic high
VOL
TXH, RXC Output logic low
TR / TF
TXH, RXC rise/fall time
ZO
TXH Output impedance
45
ZO
RXC Output impedance
29
fMAX
TXC, RXH Signal frequency
DC
TXC, RXH Duty cycle
V
0.8
2.25
10-90% CL = 20pF
V
V
0.4
V
70
ns
70
90
Ω
32
35
Ω
1
Mb/s
5
40%
60%
THERMAL SHUTDOWN
TSD
Shutdown temperature
TSDHYST
Shutdown hysteresis
110
130
15
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°C
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FUNCTIONAL BLOCK DIAGRAM
VDD2
VDD1
VDD (Internal)
RPUCFGOE
CPO
Charge
Pump
FET1
CFG/OE
FET3
ENB
Logic
Core
RESETZ
FET4
FET2
Level
Shifter
RXH
Level
Shifter
TXH
RXC
TXC
GND
OUTA
OUTB
PIN FUNCTIONS
PIN NAME
TYPE
VDD1
Supply
Device Supply 1. 0V to 19.8V Input.
VDD2
Supply
Device Supply 2. 0V to 19.8V Input.
OUTA
Output
Output A. 10mA capable output. Refer to the OUTA Supply Selection section for more information
OUTB
Output
Output B. 500mA capable output. Refer to the OUTB Supply Selection section for more information
CPO
Output
Charge Pump Output. This pin is the output of the internal charge pump. It drives the gates fo the internal FET
switches. Connect a capacitor of at least 2nF between this pin and GND.
CFG/OE
Input
Mode Configuration/Output Enable. When CFG is floating or pulled high, the device is in Normal Mode. When
CFG is ground, the device is in Control Mode (see Application Description section for more information), the
mode is latched at power-up. Refer to the Mode Selection section for more information. After the mode is
latched, this pin becomes the output enable for the UART TXH output. Refer UART RX and TX section for more
information.
RXH
Input
UART RX Input. This input is buffered and level-shifted on RXC. In Control Mode, this pin in monitored for a
high to low transition to enable the outputs. Refer UART RX and TX section for more information.
RXC
Output
UART RX Output. This output is a level shifted version of RXH. RXC is referenced to OUTA. Refer UART RX
and TX section for more information.
TXC
Input
UART TX Input. This input is buffered and level-shifted on TXH. Refer the UART RX and TX section for more
information.
TXH
Output
UART TX Output. This output is a buffered version of TXC. TXH is referenced to OUTA. Refer UART RX and
TX section for more information.
RESETZ
Output
Active Low Reset Output. This pin is a delayed reset signal indicating OUTB is connected to a valid VDD.
RESETZ is low when OUTB is high impedance. RESETZ is an open drain output.
ENB
Input
GND
Supply
6
DESCRIPTION
OUTB Enable. In Normal Mode, this pin is the active-high OUTB enable. In Control Mode, this pin opens OUTB
when asserted high and latches this condition.
Device ground.
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APPLICATION INFORMATION
OUTA Supply Selection
The TPS22986 chooses between two different power supplies, VDD1 or VDD2, and connects these to OUTA.
When a valid VDD (VUVLO < VDD < VHVLO) is present on VDD1 or VDD2, the valid VDD is connected to OUTA.
When VDD1 > VHVLO and a valid VDD is present on VDD2, the TPS22986 connects OUTA to VDD2. VDD1 will
always take priority over VDD2. VDD2 will only be connected to OUTA when VDD1 < VUVLO or VDD1 > VHVLO.
When OUTA is connected to VDD2 and VDD1 becomes valid (VUVLO < VDD < VHVLO), the TPS22986 will
disconnect OUTA from VDD2 and connect it to VDD1. Note, VDD1 and VDD2 may power up in any order.
Figure 2 shows a flow diagram illustrating the selection of VDD1 or VDD2 as the appropriate supply to connect to
OUTA.
OUTA OPEN
VDD1
VALID
yes
Transition
to VDD1
OUTA = VDD1
no
no
VDD2
VALID
yes
yes
no
VDD2
VALID
VDD1
VALID
yes
no
Transition
VDD2
OUTA = VDD2
yes
no
VDD2
VALID
no
VDD1
VALID
yes
Figure 2. OUTA Supply Selection
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OUTB Supply Selection
The TPS22986 chooses between two different power supplies, VDD1 or VDD2, and connects these to OUTB. At
initial power-up, when a valid VDD (VUVLO < VDD < VHVLO) is present on VDD1, VDD1 connects to OUTB. When
VDD1 > VHVLO and a valid VDD is present on VDD2, the TPS22986 will connect OUTB to VDD2. Note, OUTB is
also opened and closed by other digital inputs, ENB and RXH, depending on the mode of the TPS22986. See
the Normal Mode and Control Mode sections for more information on the control of OUTB. VDD1 will always take
priority over VDD2. VDD2 will only be connected to OUTB when VDD1 > VHVLO. When OUTB is connected to
VDD2 and VDD1 drops below VHVLO, the TPS22986 will disconnect OUTB from VDD2 and connect it to VDD1.
Note, VDD1 and VDD2 may power up in any order. Figure 3 shows a flow diagram illustrating the selection of
VDD1 or VDD2 as the appropriate supply to connect to OUTB. Note, this diagram shows only the dependence
on the VDD values and does not show the enabling and disabling of OUTB by the ENB and RXH input signals.
OUTB OPEN
VDD1
VALID
yes
Transition
to VDD1
OUTB = VDD1
no
no
VDD1
HIGH
no
yes
no
VDD2
VALID
yes
VDD1
VALID
yes
yes
yes
VDD2
VALID
VDD1
HIGH
no
no
yes
Transition
VDD2
OUTB = VDD2
no
yes
VDD2
VALID
VDD1
VALID
yes
no
VDD1
HIGH
no
Figure 3. OUTB Supply Selection
8
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Valid VDD at Inputs
A valid VDD on either input occurs when the voltage on VDD1 or VDD2 is between VUVLO and VHVLO (VUVLO <
VDD < VHVLO). The VDD voltage is invalid when outside of this range. A VDD is considered high when VDD >
VHVLO. Table 1 shows the relationship between the output voltages and the input voltages. Note, other factors
also determine whether OUTA and OUTB are open. Table 1 only shows the relationship to the voltage at the
inputs VDD1 and VDD2.
Table 1. Output Voltages vs Input Voltages
VDD1
VDD2
OUTA
OUTB
Invalid
Invalid
Open
Open
VDD1
Valid
Valid or Invalid
VDD1
Invalid
Valid
VDD2
Open
High
Valid
VDD2
VDD2
Mode Selection
The TPS22986 has two modes of operation, Normal and Control. Refer to the Normal Mode and Control Mode
sections for the operational description of each mode. At power-up, the TPS22986 determines which mode the
device will operate in. At power-up, the resistance RPUCFGOE is switched to the CFG/OE pin. The external
resistance connected to the pin determines the mode.
To enter Normal Mode, leave this pin floating or ensure that any external pull-down resistance on this pin is
equal to or greater than RPDNORMAL. When the UART buffers/level-shifters are used in this mode, the CFG/OE pin
will also be the output enable for the TXH output. The RPDNORMAL resistance is recommended in series with the
driver of the CFG/OE pin to prevent this driver from loading CFG/OE during power-up.
To enter Control Mode, the CFG/OE pin must be pulled low during power-up. Connect a resistance less than or
equal to RPDCONTROL between CFG/OE and ground that will pull the pin low during power-up. Again, the CFG/OE
pin is the output enable for the TXH output. The RPDCONTROL resistance should be chosen such that the device
driving CFG/OE can overdrive this resistance.
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Normal Mode
When the CFG/OE pin is floating or pulled high at power-up, the device enters Normal Mode. In Normal Mode,
the TPS22986 provides power through OUTA and OUTB. OUTA is connected whenever a valid VDD is present
on either VDD1 or VDD2. OUTB is connected whenever a valid VDD is present on VDD1 or VDD1 > VHVLO and
VDD2 is a valid VDD, and the GPIO control signal ENB is high. If a valid VDD is not present, the TPS22986
enters into a shutdown mode and blocks current flow through the switches.
After the device is latched into Normal Mode, the CFG/OE pin becomes the output enable for the TX buffer/levelshifter. See the UART RX and TX section for more information.
VDD1
VDD2
VDD2
VDD1
VDD (Internal)
RPUCFGOE
CPO
Charge
Pump
FET1
CFG/OE
FET3
ENB
Logic
Core
RESETZ
FET4
FET2
RXH
RXH
TXH
TXH
Level
Shifter
RXC
Level
Shifter
TXC
GND
OUTA
OUTB
100k
Load
CDR and Microcontroller
RPDNORMAL
Figure 4. Normal Mode Typical Application
10
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VDD1
VHVLO
VUVLO
VHVLO
VDD2
VUVLO
OUTA
VOUTA = VDD2e
VOUTA
= VDD1e
VOUTA = VDD2e
td
te
ENB
OUTB
teb
VOUTB = VDD2e
VOUTB = VDD1e
tdb
Figure 5. Timing During Normal Mode
Control Mode
When CFG/OE is grounded at power-up, the device latches into Control Mode. When a valid VDD connected,
OUTA and OUTB are connected to the VDD. Note, a valid VDD is different for OUTA than OUTB. See Table 1
for the output voltages versus input conditions. OUTB remains connected to VDD until ENB transitions high.
OUTA remains connected to VDD as long as a valid VDD exists. RESETZ indicates that a valid VDD is available
at OUTB. When RESETZ is low, OUTB is high-impedance or is transitioning from high-impedance to an on-state.
During power-up, when a valid supply becomes available, RESETZ remains asserted low for the time tU2R to
allow settling of ENB. ENB is masked during this interval until RESETZ is high. When RESETZ is high, a valid
VDD is available at OUTB and ENB is monitored.
When either VDD is not in UVLO for more than tU2R, the device monitors ENB for a high transition. When ENB
transitions high, RESETZ will assert low after time tE2R, and OUTB will open after time tE2O. After the time tE2O,
the TPS22986 starts monitoring RXH for a falling edge. When a falling RXH is detected, OUTB is connected to
the valid VDD after time tRX2O and RESETZ transitions from low to high after time tRX2R. The device then begins
to monitor ENB again for a low to high transition. When a valid VDD is not available, RESETZ is asserted low
and the TPS22986 blocks current flow through the switches. When both VDDs are in UVLO, the device clears
any wait state and does not monitor ENB or RXH.
After the device is latched into Control Mode, the CFG/OE pin becomes the output enable for the TX buffer/levelshifter. See the UART RX and TX section for more information.
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VDD1
VDD2
VDD2
VDD1
VDD (Internal)
RPUCFGOE
CPO
Charge
Pump
FET1
CFG/OE
FET3
ENB
Logic
Core
RPDCONTROL
RESETZ
FET4
FET2
RXH
RXH
TXH
TXH
Level
Shifter
Level
Shifter
RXC
TXC
GND
OUTA
OUTB
100k
CFG2 (ThunderboltTM)
CDR and Microcontroller
Figure 6. Control Mode Typical Application
12
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VDD1
VHVLO
VUVLO
VHVLO
VDD2
VUVLO
OUTA
VOUTA
= VDD1e
VOUTA = VDD2e
VOUTA = VDD2e
td
te
ENB Falls When OUTB Falls
(Power Removed)
ENB
OUTB
VOUTB
= VDD1e
VOUTB =
VDD2e
RESETZ
te
tE2R
tU2R
tE2O
Figure 7. Timing During Control Mode
RXH
OUTB
ENB
RESETZ
tRX2O
tE2R
tRX2R
tE2O
Figure 8. Timing During Control Mode Continued
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Typical Startup
12V±15V
3.3V
VDD1
3.3V
VDD2
ENB
RXH
OUTA
OUTB
Figure 9. Typical Startup in Normal Mode
14
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12V±15V
3.3V
VDD1
3.3V
VDD2
RXH
OUTA
OUTB
ENB
Figure 10. Typical Startup Timing for Control Mode
Soft Start
To prevent inrush current to the load, the TPS22986 soft starts OUTA and OUTB. When OUTA and OUTB are
first enabled, the resistance of the FET switches (FET1, FET2, FET3, and FET4) starts high and reduces every
250µs in four steps. Figure 11 shows the nominal resistance ramp profile for OUTB. Figure 12 shows the flow
diagram of the transition of the outputs.
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12.7
5.9
1.6
0.17
s
0
250
500
750
Figure 11. OUTB Soft Start Resistance vs Time profile (FET3 and FET4 resistance)
Transition
VDD1
(VDD2 Open)
Transition
VDD2
(VDD1 Open)
VDD1
Open
VDD2
Open
OUT > VDD1
OUT > VDD2
yes
yes
no
no
VDD1
Soft Start
VDD2
Soft Start
OUT < VDD1
yes
OUT < VDD2
yes
no
Exit
no
Exit
Figure 12. Transition of OUTA and OUTB to VDD1 or VDD2
16
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Supply Switch-Over During HVLO
When OUTA and OUTB are connected to VDD1 and VDD1 crosses VHVLO, the TPS22986 opens the FET1/3
switches. Due to the delay tdh, the output will overshoot VHVLO by VOS. When a valid VDD is present on VDD2,
OUTA and OUTB will connect to VDD2 after time teh. Figure 13 illustrates this switch-over event.
The overshoot VOS will occur when the VDD (VDD1 or VDD2) that is connected to the output transitions above
VHVLO. VOS is set by the delay tdh and the slew rate of the connected VDD.
The following equation determines the overshoot VOS.
Equation 1: VOS = SRVDD × tdh
SRVDD is the slew rate of the supply that is transitioning above VHVLO. As an example, when SRVDD is 10mV/µs
and tdh is 20µs, VOS is 200mV.
When switching to VDD2 due to an HVLO event on VDD1, the outputs OUTA and OUTB are discharged by their
respective loads until they reach the VDD2 voltage. This prevents in-rush current when charging the output caps.
The discharge time teh is variable and is determined by the following equation.
Equation 2: teh = tdh + (VHVLO + VOS – VDD2) × CLOAD/ILOAD
In this equation, VOS is determined by Equation 1, CLOAD is the load capacitance at the respective output, and
ILOAD is the load current flowing out of the same output. As an example, when VDD2 is 3.3V, tdh is 20µs, VOS is
200mV, CLOAD is 4µF, and ILOAD is 350mA, the resulting teh is 25.7 µs.
Note, when VDD1 transitions above VHVLO and a valid VDD is not present on VDD2, the outputs will open and
will discharge through each respective load.
VHVLO
VDD1
VOS
OUTA/B
tdh
FET1/3 ENABLE
(Internal)
Connected to VDD1
FET2/4 ENABLE
(Internal)
Connected to VDD2
teh
Figure 13. VDD Switch-over at VDD1 Rising Above VHVLO
When VDD1 drops from a HVLO condition, the TPS22986 may brownout at OUTA and OUTB before switching
the outputs to VDD1.
UART RX and TX
The TPS22986 provides failsafe buffers for digital UART RX and TX lines. The failsafe mechanism prevents the
RX and TX lines from being loaded when power is removed from the device. The RX line is divided into a host
side RXH input and a cable side RXC output. The TX line is divided into host side TXH output and a cable side
TXC input. The inputs RXH and TXC have a weak pull-down resistance RPDUART to allow each to be left floating if
unused in the application.
When the TPS22986 is unpowered or when RESETZ is asserted low, the TXH output is high impedance. This
prevents loading the system TX line and allowing other devices on the UART bus to communicate.
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Figure 14 illustrates the TXH control. When RESETZ is high, CFG/OE controls TXH. When CFG/OE is low, TXH
is high impedance. When CFG/OE is high, TXH is a buffered/level-shifted TXC. The CFG/OE input is ignored
when RESETZ is asserted low. Figure 15 shows the delay from CFG/OE to TXH.
Note, the UART buffers are powered from OUTA. When OUTA is disconnected, the UART buffers are
unpowered. When there are no valid supplies connected or when the device is in Thermal Shutdown, OUTA will
disconnect and the buffers will be unpowered.
RESETZ
CFG/OE
TXH
Hi-Z
TXC
Hi-Z
TXC
Hi-Z
Figure 14. UART RX and TX Buffer Control
CFG/OE
TXH
Hi-Z
Hi-Z
TXC
tOE2TX
tOE2TXZ
Figure 15. CFG/OE to TXH Timing
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Thunderbolt System with TPS22981/TPS22986
EN_HV
Host uC
LSTX
LSTX
RSTX
TBT Connector
(miniDP)
EN
TBT Cable Plug
(miniDP)
TBT Cable Plug
(miniDP)
OUT
VHV
Host uC
RSTX
TBT Connector
(miniDP)
EN_HV
EN
OUT
TPS22980/1
TPS22980/1
V3P3
VHV
V3P3
Cable
Host
VDD1 VDD2
TXH
VDD2 VDD1
TXH
RXH
RXH
TXC
TXC
TPS22986
Device
TPS22986
RXC
OUTA OUTB
RXC
OUTB OUTA
Cable uC
CDR
Cable uC
CDR
Cable Connector
Cable Connector
Figure 16. Thunderbolt System with TPS22981/TPS22986
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PACKAGE OPTION ADDENDUM
www.ti.com
22-Jan-2013
PACKAGING INFORMATION
Orderable Device
Status
(1)
TPS22986YFPR
ACTIVE
Package Type Package Pins Package Qty
Drawing
DSBGA
YFP
16
3000
Eco Plan
Lead/Ball Finish
(2)
Green (RoHS
& no Sb/Br)
SNAGCU
MSL Peak Temp
Samples
(3)
(Requires Login)
Level-1-260C-UNLIM
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
D: Max = 1.606 mm, Min =1.546 mm
E: Max = 1.606 mm, Min =1.546 mm
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